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TARGET_NUCLEO_F103RB/stm32f1xx_hal_dma.h@120:7c328cabac7e, 2016-05-10 (annotated)
- Committer:
- Kojto
- Date:
- Tue May 10 12:23:43 2016 -0500
- Revision:
- 120:7c328cabac7e
- Parent:
- 96:487b796308b0
Release 120 of the mbed library
Changes:
- ST - STMF3XX/F4XX - directories removal
- STMF3 - pwm range fix
- STMF1 - Cube driver update
- Renesas - RZ_A1H - async i2c, serial and spi addition
- Freescale - KSDK2 update
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Kojto | 96:487b796308b0 | 1 | /** |
| Kojto | 96:487b796308b0 | 2 | ****************************************************************************** |
| Kojto | 96:487b796308b0 | 3 | * @file stm32f1xx_hal_dma.h |
| Kojto | 96:487b796308b0 | 4 | * @author MCD Application Team |
| Kojto | 120:7c328cabac7e | 5 | * @version V1.0.4 |
| Kojto | 120:7c328cabac7e | 6 | * @date 29-April-2016 |
| Kojto | 96:487b796308b0 | 7 | * @brief Header file of DMA HAL module. |
| Kojto | 96:487b796308b0 | 8 | ****************************************************************************** |
| Kojto | 96:487b796308b0 | 9 | * @attention |
| Kojto | 96:487b796308b0 | 10 | * |
| Kojto | 120:7c328cabac7e | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| Kojto | 96:487b796308b0 | 12 | * |
| Kojto | 96:487b796308b0 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| Kojto | 96:487b796308b0 | 14 | * are permitted provided that the following conditions are met: |
| Kojto | 96:487b796308b0 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| Kojto | 96:487b796308b0 | 16 | * this list of conditions and the following disclaimer. |
| Kojto | 96:487b796308b0 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| Kojto | 96:487b796308b0 | 18 | * this list of conditions and the following disclaimer in the documentation |
| Kojto | 96:487b796308b0 | 19 | * and/or other materials provided with the distribution. |
| Kojto | 96:487b796308b0 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| Kojto | 96:487b796308b0 | 21 | * may be used to endorse or promote products derived from this software |
| Kojto | 96:487b796308b0 | 22 | * without specific prior written permission. |
| Kojto | 96:487b796308b0 | 23 | * |
| Kojto | 96:487b796308b0 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| Kojto | 96:487b796308b0 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| Kojto | 96:487b796308b0 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| Kojto | 96:487b796308b0 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| Kojto | 96:487b796308b0 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| Kojto | 96:487b796308b0 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| Kojto | 96:487b796308b0 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| Kojto | 96:487b796308b0 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| Kojto | 96:487b796308b0 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| Kojto | 96:487b796308b0 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| Kojto | 96:487b796308b0 | 34 | * |
| Kojto | 96:487b796308b0 | 35 | ****************************************************************************** |
| Kojto | 96:487b796308b0 | 36 | */ |
| Kojto | 96:487b796308b0 | 37 | |
| Kojto | 96:487b796308b0 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| Kojto | 96:487b796308b0 | 39 | #ifndef __STM32F1xx_HAL_DMA_H |
| Kojto | 96:487b796308b0 | 40 | #define __STM32F1xx_HAL_DMA_H |
| Kojto | 96:487b796308b0 | 41 | |
| Kojto | 96:487b796308b0 | 42 | #ifdef __cplusplus |
| Kojto | 96:487b796308b0 | 43 | extern "C" { |
| Kojto | 96:487b796308b0 | 44 | #endif |
| Kojto | 96:487b796308b0 | 45 | |
| Kojto | 96:487b796308b0 | 46 | /* Includes ------------------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 47 | #include "stm32f1xx_hal_def.h" |
| Kojto | 96:487b796308b0 | 48 | |
| Kojto | 96:487b796308b0 | 49 | /** @addtogroup STM32F1xx_HAL_Driver |
| Kojto | 96:487b796308b0 | 50 | * @{ |
| Kojto | 96:487b796308b0 | 51 | */ |
| Kojto | 96:487b796308b0 | 52 | |
| Kojto | 96:487b796308b0 | 53 | /** @addtogroup DMA |
| Kojto | 96:487b796308b0 | 54 | * @{ |
| Kojto | 96:487b796308b0 | 55 | */ |
| Kojto | 96:487b796308b0 | 56 | |
| Kojto | 120:7c328cabac7e | 57 | /* Exported types ------------------------------------------------------------*/ |
| Kojto | 120:7c328cabac7e | 58 | |
| Kojto | 96:487b796308b0 | 59 | /** @defgroup DMA_Exported_Types DMA Exported Types |
| Kojto | 96:487b796308b0 | 60 | * @{ |
| Kojto | 96:487b796308b0 | 61 | */ |
| Kojto | 120:7c328cabac7e | 62 | |
| Kojto | 96:487b796308b0 | 63 | /** |
| Kojto | 120:7c328cabac7e | 64 | * @brief DMA Configuration Structure definition |
| Kojto | 96:487b796308b0 | 65 | */ |
| Kojto | 96:487b796308b0 | 66 | typedef struct |
| Kojto | 96:487b796308b0 | 67 | { |
| Kojto | 96:487b796308b0 | 68 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
| Kojto | 96:487b796308b0 | 69 | from memory to memory or from peripheral to memory. |
| Kojto | 96:487b796308b0 | 70 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
| Kojto | 96:487b796308b0 | 71 | |
| Kojto | 96:487b796308b0 | 72 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
| Kojto | 96:487b796308b0 | 73 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
| Kojto | 96:487b796308b0 | 74 | |
| Kojto | 96:487b796308b0 | 75 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
| Kojto | 96:487b796308b0 | 76 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
| Kojto | 96:487b796308b0 | 77 | |
| Kojto | 96:487b796308b0 | 78 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
| Kojto | 96:487b796308b0 | 79 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
| Kojto | 96:487b796308b0 | 80 | |
| Kojto | 96:487b796308b0 | 81 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
| Kojto | 96:487b796308b0 | 82 | This parameter can be a value of @ref DMA_Memory_data_size */ |
| Kojto | 96:487b796308b0 | 83 | |
| Kojto | 96:487b796308b0 | 84 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. |
| Kojto | 96:487b796308b0 | 85 | This parameter can be a value of @ref DMA_mode |
| Kojto | 96:487b796308b0 | 86 | @note The circular buffer mode cannot be used if the memory-to-memory |
| Kojto | 96:487b796308b0 | 87 | data transfer is configured on the selected Channel */ |
| Kojto | 96:487b796308b0 | 88 | |
| Kojto | 96:487b796308b0 | 89 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. |
| Kojto | 96:487b796308b0 | 90 | This parameter can be a value of @ref DMA_Priority_level */ |
| Kojto | 96:487b796308b0 | 91 | } DMA_InitTypeDef; |
| Kojto | 96:487b796308b0 | 92 | |
| Kojto | 96:487b796308b0 | 93 | /** |
| Kojto | 120:7c328cabac7e | 94 | * @brief DMA Configuration enumeration values definition |
| Kojto | 96:487b796308b0 | 95 | */ |
| Kojto | 96:487b796308b0 | 96 | typedef enum |
| Kojto | 96:487b796308b0 | 97 | { |
| Kojto | 96:487b796308b0 | 98 | DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ |
| Kojto | 96:487b796308b0 | 99 | DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */ |
| Kojto | 96:487b796308b0 | 100 | |
| Kojto | 96:487b796308b0 | 101 | } DMA_ControlTypeDef; |
| Kojto | 96:487b796308b0 | 102 | |
| Kojto | 96:487b796308b0 | 103 | /** |
| Kojto | 96:487b796308b0 | 104 | * @brief HAL DMA State structures definition |
| Kojto | 96:487b796308b0 | 105 | */ |
| Kojto | 96:487b796308b0 | 106 | typedef enum |
| Kojto | 96:487b796308b0 | 107 | { |
| Kojto | 120:7c328cabac7e | 108 | HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ |
| Kojto | 120:7c328cabac7e | 109 | HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ |
| Kojto | 96:487b796308b0 | 110 | HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */ |
| Kojto | 120:7c328cabac7e | 111 | HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ |
| Kojto | 120:7c328cabac7e | 112 | HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ |
| Kojto | 96:487b796308b0 | 113 | HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ |
| Kojto | 96:487b796308b0 | 114 | }HAL_DMA_StateTypeDef; |
| Kojto | 96:487b796308b0 | 115 | |
| Kojto | 96:487b796308b0 | 116 | /** |
| Kojto | 120:7c328cabac7e | 117 | * @brief HAL DMA Error Code structure definition |
| Kojto | 120:7c328cabac7e | 118 | */ |
| Kojto | 96:487b796308b0 | 119 | typedef enum |
| Kojto | 96:487b796308b0 | 120 | { |
| Kojto | 96:487b796308b0 | 121 | HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ |
| Kojto | 96:487b796308b0 | 122 | HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ |
| Kojto | 120:7c328cabac7e | 123 | }HAL_DMA_LevelCompleteTypeDef; |
| Kojto | 96:487b796308b0 | 124 | |
| Kojto | 96:487b796308b0 | 125 | /** |
| Kojto | 120:7c328cabac7e | 126 | * @brief DMA handle Structure definition |
| Kojto | 120:7c328cabac7e | 127 | */ |
| Kojto | 96:487b796308b0 | 128 | typedef struct __DMA_HandleTypeDef |
| Kojto | 120:7c328cabac7e | 129 | { |
| Kojto | 120:7c328cabac7e | 130 | DMA_Channel_TypeDef *Instance; /*!< Register base address */ |
| Kojto | 96:487b796308b0 | 131 | |
| Kojto | 120:7c328cabac7e | 132 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
| Kojto | 96:487b796308b0 | 133 | |
| Kojto | 120:7c328cabac7e | 134 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
| Kojto | 96:487b796308b0 | 135 | |
| Kojto | 120:7c328cabac7e | 136 | HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
| Kojto | 96:487b796308b0 | 137 | |
| Kojto | 96:487b796308b0 | 138 | void *Parent; /*!< Parent object state */ |
| Kojto | 96:487b796308b0 | 139 | |
| Kojto | 96:487b796308b0 | 140 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
| Kojto | 96:487b796308b0 | 141 | |
| Kojto | 96:487b796308b0 | 142 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
| Kojto | 96:487b796308b0 | 143 | |
| Kojto | 96:487b796308b0 | 144 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
| Kojto | 96:487b796308b0 | 145 | |
| Kojto | 96:487b796308b0 | 146 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
| Kojto | 96:487b796308b0 | 147 | } DMA_HandleTypeDef; |
| Kojto | 96:487b796308b0 | 148 | /** |
| Kojto | 96:487b796308b0 | 149 | * @} |
| Kojto | 96:487b796308b0 | 150 | */ |
| Kojto | 96:487b796308b0 | 151 | |
| Kojto | 96:487b796308b0 | 152 | /* Exported constants --------------------------------------------------------*/ |
| Kojto | 120:7c328cabac7e | 153 | |
| Kojto | 96:487b796308b0 | 154 | /** @defgroup DMA_Exported_Constants DMA Exported Constants |
| Kojto | 96:487b796308b0 | 155 | * @{ |
| Kojto | 96:487b796308b0 | 156 | */ |
| Kojto | 96:487b796308b0 | 157 | |
| Kojto | 120:7c328cabac7e | 158 | /** @defgroup DMA_Error_Code DMA Error Code |
| Kojto | 96:487b796308b0 | 159 | * @{ |
| Kojto | 96:487b796308b0 | 160 | */ |
| Kojto | 96:487b796308b0 | 161 | #define HAL_DMA_ERROR_NONE ((uint32_t)0x00) /*!< No error */ |
| Kojto | 96:487b796308b0 | 162 | #define HAL_DMA_ERROR_TE ((uint32_t)0x01) /*!< Transfer error */ |
| Kojto | 96:487b796308b0 | 163 | #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x20) /*!< Timeout error */ |
| Kojto | 96:487b796308b0 | 164 | |
| Kojto | 96:487b796308b0 | 165 | /** |
| Kojto | 96:487b796308b0 | 166 | * @} |
| Kojto | 96:487b796308b0 | 167 | */ |
| Kojto | 96:487b796308b0 | 168 | |
| Kojto | 96:487b796308b0 | 169 | /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction |
| Kojto | 96:487b796308b0 | 170 | * @{ |
| Kojto | 96:487b796308b0 | 171 | */ |
| Kojto | 120:7c328cabac7e | 172 | #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ |
| Kojto | 120:7c328cabac7e | 173 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ |
| Kojto | 120:7c328cabac7e | 174 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ |
| Kojto | 96:487b796308b0 | 175 | |
| Kojto | 96:487b796308b0 | 176 | /** |
| Kojto | 96:487b796308b0 | 177 | * @} |
| Kojto | 96:487b796308b0 | 178 | */ |
| Kojto | 96:487b796308b0 | 179 | |
| Kojto | 96:487b796308b0 | 180 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode |
| Kojto | 96:487b796308b0 | 181 | * @{ |
| Kojto | 96:487b796308b0 | 182 | */ |
| Kojto | 120:7c328cabac7e | 183 | #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ |
| Kojto | 120:7c328cabac7e | 184 | #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ |
| Kojto | 96:487b796308b0 | 185 | /** |
| Kojto | 96:487b796308b0 | 186 | * @} |
| Kojto | 96:487b796308b0 | 187 | */ |
| Kojto | 96:487b796308b0 | 188 | |
| Kojto | 96:487b796308b0 | 189 | /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode |
| Kojto | 96:487b796308b0 | 190 | * @{ |
| Kojto | 96:487b796308b0 | 191 | */ |
| Kojto | 120:7c328cabac7e | 192 | #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ |
| Kojto | 120:7c328cabac7e | 193 | #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ |
| Kojto | 96:487b796308b0 | 194 | /** |
| Kojto | 96:487b796308b0 | 195 | * @} |
| Kojto | 96:487b796308b0 | 196 | */ |
| Kojto | 96:487b796308b0 | 197 | |
| Kojto | 96:487b796308b0 | 198 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size |
| Kojto | 96:487b796308b0 | 199 | * @{ |
| Kojto | 96:487b796308b0 | 200 | */ |
| Kojto | 120:7c328cabac7e | 201 | #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */ |
| Kojto | 120:7c328cabac7e | 202 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ |
| Kojto | 120:7c328cabac7e | 203 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ |
| Kojto | 96:487b796308b0 | 204 | /** |
| Kojto | 96:487b796308b0 | 205 | * @} |
| Kojto | 96:487b796308b0 | 206 | */ |
| Kojto | 96:487b796308b0 | 207 | |
| Kojto | 96:487b796308b0 | 208 | /** @defgroup DMA_Memory_data_size DMA Memory data size |
| Kojto | 96:487b796308b0 | 209 | * @{ |
| Kojto | 96:487b796308b0 | 210 | */ |
| Kojto | 120:7c328cabac7e | 211 | #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */ |
| Kojto | 120:7c328cabac7e | 212 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ |
| Kojto | 120:7c328cabac7e | 213 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ |
| Kojto | 96:487b796308b0 | 214 | /** |
| Kojto | 96:487b796308b0 | 215 | * @} |
| Kojto | 96:487b796308b0 | 216 | */ |
| Kojto | 96:487b796308b0 | 217 | |
| Kojto | 96:487b796308b0 | 218 | /** @defgroup DMA_mode DMA mode |
| Kojto | 96:487b796308b0 | 219 | * @{ |
| Kojto | 96:487b796308b0 | 220 | */ |
| Kojto | 120:7c328cabac7e | 221 | #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ |
| Kojto | 120:7c328cabac7e | 222 | #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ |
| Kojto | 96:487b796308b0 | 223 | /** |
| Kojto | 96:487b796308b0 | 224 | * @} |
| Kojto | 96:487b796308b0 | 225 | */ |
| Kojto | 96:487b796308b0 | 226 | |
| Kojto | 96:487b796308b0 | 227 | /** @defgroup DMA_Priority_level DMA Priority level |
| Kojto | 96:487b796308b0 | 228 | * @{ |
| Kojto | 96:487b796308b0 | 229 | */ |
| Kojto | 120:7c328cabac7e | 230 | #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ |
| Kojto | 120:7c328cabac7e | 231 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ |
| Kojto | 120:7c328cabac7e | 232 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ |
| Kojto | 120:7c328cabac7e | 233 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ |
| Kojto | 96:487b796308b0 | 234 | /** |
| Kojto | 96:487b796308b0 | 235 | * @} |
| Kojto | 96:487b796308b0 | 236 | */ |
| Kojto | 96:487b796308b0 | 237 | |
| Kojto | 96:487b796308b0 | 238 | |
| Kojto | 96:487b796308b0 | 239 | /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions |
| Kojto | 96:487b796308b0 | 240 | * @{ |
| Kojto | 96:487b796308b0 | 241 | */ |
| Kojto | 96:487b796308b0 | 242 | #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) |
| Kojto | 96:487b796308b0 | 243 | #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) |
| Kojto | 96:487b796308b0 | 244 | #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) |
| Kojto | 96:487b796308b0 | 245 | /** |
| Kojto | 96:487b796308b0 | 246 | * @} |
| Kojto | 96:487b796308b0 | 247 | */ |
| Kojto | 96:487b796308b0 | 248 | |
| Kojto | 96:487b796308b0 | 249 | /** @defgroup DMA_flag_definitions DMA flag definitions |
| Kojto | 96:487b796308b0 | 250 | * @{ |
| Kojto | 96:487b796308b0 | 251 | */ |
| Kojto | 96:487b796308b0 | 252 | #define DMA_FLAG_GL1 ((uint32_t)0x00000001) |
| Kojto | 96:487b796308b0 | 253 | #define DMA_FLAG_TC1 ((uint32_t)0x00000002) |
| Kojto | 96:487b796308b0 | 254 | #define DMA_FLAG_HT1 ((uint32_t)0x00000004) |
| Kojto | 96:487b796308b0 | 255 | #define DMA_FLAG_TE1 ((uint32_t)0x00000008) |
| Kojto | 96:487b796308b0 | 256 | #define DMA_FLAG_GL2 ((uint32_t)0x00000010) |
| Kojto | 96:487b796308b0 | 257 | #define DMA_FLAG_TC2 ((uint32_t)0x00000020) |
| Kojto | 96:487b796308b0 | 258 | #define DMA_FLAG_HT2 ((uint32_t)0x00000040) |
| Kojto | 96:487b796308b0 | 259 | #define DMA_FLAG_TE2 ((uint32_t)0x00000080) |
| Kojto | 96:487b796308b0 | 260 | #define DMA_FLAG_GL3 ((uint32_t)0x00000100) |
| Kojto | 96:487b796308b0 | 261 | #define DMA_FLAG_TC3 ((uint32_t)0x00000200) |
| Kojto | 96:487b796308b0 | 262 | #define DMA_FLAG_HT3 ((uint32_t)0x00000400) |
| Kojto | 96:487b796308b0 | 263 | #define DMA_FLAG_TE3 ((uint32_t)0x00000800) |
| Kojto | 96:487b796308b0 | 264 | #define DMA_FLAG_GL4 ((uint32_t)0x00001000) |
| Kojto | 96:487b796308b0 | 265 | #define DMA_FLAG_TC4 ((uint32_t)0x00002000) |
| Kojto | 96:487b796308b0 | 266 | #define DMA_FLAG_HT4 ((uint32_t)0x00004000) |
| Kojto | 96:487b796308b0 | 267 | #define DMA_FLAG_TE4 ((uint32_t)0x00008000) |
| Kojto | 96:487b796308b0 | 268 | #define DMA_FLAG_GL5 ((uint32_t)0x00010000) |
| Kojto | 96:487b796308b0 | 269 | #define DMA_FLAG_TC5 ((uint32_t)0x00020000) |
| Kojto | 96:487b796308b0 | 270 | #define DMA_FLAG_HT5 ((uint32_t)0x00040000) |
| Kojto | 96:487b796308b0 | 271 | #define DMA_FLAG_TE5 ((uint32_t)0x00080000) |
| Kojto | 96:487b796308b0 | 272 | #define DMA_FLAG_GL6 ((uint32_t)0x00100000) |
| Kojto | 96:487b796308b0 | 273 | #define DMA_FLAG_TC6 ((uint32_t)0x00200000) |
| Kojto | 96:487b796308b0 | 274 | #define DMA_FLAG_HT6 ((uint32_t)0x00400000) |
| Kojto | 96:487b796308b0 | 275 | #define DMA_FLAG_TE6 ((uint32_t)0x00800000) |
| Kojto | 96:487b796308b0 | 276 | #define DMA_FLAG_GL7 ((uint32_t)0x01000000) |
| Kojto | 96:487b796308b0 | 277 | #define DMA_FLAG_TC7 ((uint32_t)0x02000000) |
| Kojto | 96:487b796308b0 | 278 | #define DMA_FLAG_HT7 ((uint32_t)0x04000000) |
| Kojto | 96:487b796308b0 | 279 | #define DMA_FLAG_TE7 ((uint32_t)0x08000000) |
| Kojto | 96:487b796308b0 | 280 | /** |
| Kojto | 96:487b796308b0 | 281 | * @} |
| Kojto | 96:487b796308b0 | 282 | */ |
| Kojto | 96:487b796308b0 | 283 | |
| Kojto | 96:487b796308b0 | 284 | /** |
| Kojto | 96:487b796308b0 | 285 | * @} |
| Kojto | 96:487b796308b0 | 286 | */ |
| Kojto | 120:7c328cabac7e | 287 | |
| Kojto | 96:487b796308b0 | 288 | |
| Kojto | 120:7c328cabac7e | 289 | /* Exported macro ------------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 290 | /** @defgroup DMA_Exported_Macros DMA Exported Macros |
| Kojto | 96:487b796308b0 | 291 | * @{ |
| Kojto | 96:487b796308b0 | 292 | */ |
| Kojto | 96:487b796308b0 | 293 | |
| Kojto | 96:487b796308b0 | 294 | /** @brief Reset DMA handle state |
| Kojto | 96:487b796308b0 | 295 | * @param __HANDLE__: DMA handle. |
| Kojto | 96:487b796308b0 | 296 | * @retval None |
| Kojto | 96:487b796308b0 | 297 | */ |
| Kojto | 96:487b796308b0 | 298 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
| Kojto | 96:487b796308b0 | 299 | |
| Kojto | 96:487b796308b0 | 300 | /** |
| Kojto | 96:487b796308b0 | 301 | * @brief Enable the specified DMA Channel. |
| Kojto | 96:487b796308b0 | 302 | * @param __HANDLE__: DMA handle |
| Kojto | 96:487b796308b0 | 303 | * @retval None. |
| Kojto | 96:487b796308b0 | 304 | */ |
| Kojto | 96:487b796308b0 | 305 | #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) |
| Kojto | 96:487b796308b0 | 306 | |
| Kojto | 96:487b796308b0 | 307 | /** |
| Kojto | 96:487b796308b0 | 308 | * @brief Disable the specified DMA Channel. |
| Kojto | 96:487b796308b0 | 309 | * @param __HANDLE__: DMA handle |
| Kojto | 96:487b796308b0 | 310 | * @retval None. |
| Kojto | 96:487b796308b0 | 311 | */ |
| Kojto | 96:487b796308b0 | 312 | #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) |
| Kojto | 96:487b796308b0 | 313 | |
| Kojto | 96:487b796308b0 | 314 | |
| Kojto | 96:487b796308b0 | 315 | /* Interrupt & Flag management */ |
| Kojto | 96:487b796308b0 | 316 | |
| Kojto | 96:487b796308b0 | 317 | /** |
| Kojto | 96:487b796308b0 | 318 | * @brief Enables the specified DMA Channel interrupts. |
| Kojto | 96:487b796308b0 | 319 | * @param __HANDLE__: DMA handle |
| Kojto | 96:487b796308b0 | 320 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| Kojto | 96:487b796308b0 | 321 | * This parameter can be any combination of the following values: |
| Kojto | 96:487b796308b0 | 322 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| Kojto | 96:487b796308b0 | 323 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| Kojto | 96:487b796308b0 | 324 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| Kojto | 96:487b796308b0 | 325 | * @retval None |
| Kojto | 96:487b796308b0 | 326 | */ |
| Kojto | 96:487b796308b0 | 327 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) |
| Kojto | 96:487b796308b0 | 328 | |
| Kojto | 96:487b796308b0 | 329 | /** |
| Kojto | 96:487b796308b0 | 330 | * @brief Disables the specified DMA Channel interrupts. |
| Kojto | 96:487b796308b0 | 331 | * @param __HANDLE__: DMA handle |
| Kojto | 120:7c328cabac7e | 332 | * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. |
| Kojto | 96:487b796308b0 | 333 | * This parameter can be any combination of the following values: |
| Kojto | 96:487b796308b0 | 334 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| Kojto | 96:487b796308b0 | 335 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| Kojto | 96:487b796308b0 | 336 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| Kojto | 96:487b796308b0 | 337 | * @retval None |
| Kojto | 96:487b796308b0 | 338 | */ |
| Kojto | 96:487b796308b0 | 339 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) |
| Kojto | 96:487b796308b0 | 340 | |
| Kojto | 96:487b796308b0 | 341 | /** |
| Kojto | 120:7c328cabac7e | 342 | * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. |
| Kojto | 96:487b796308b0 | 343 | * @param __HANDLE__: DMA handle |
| Kojto | 96:487b796308b0 | 344 | * @param __INTERRUPT__: specifies the DMA interrupt source to check. |
| Kojto | 96:487b796308b0 | 345 | * This parameter can be one of the following values: |
| Kojto | 96:487b796308b0 | 346 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| Kojto | 96:487b796308b0 | 347 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
| Kojto | 96:487b796308b0 | 348 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| Kojto | 96:487b796308b0 | 349 | * @retval The state of DMA_IT (SET or RESET). |
| Kojto | 96:487b796308b0 | 350 | */ |
| Kojto | 96:487b796308b0 | 351 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| Kojto | 96:487b796308b0 | 352 | |
| Kojto | 96:487b796308b0 | 353 | /** |
| Kojto | 120:7c328cabac7e | 354 | * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. |
| Kojto | 120:7c328cabac7e | 355 | * @param __HANDLE__: DMA handle |
| Kojto | 120:7c328cabac7e | 356 | * |
| Kojto | 120:7c328cabac7e | 357 | * @retval The number of remaining data units in the current DMA Channel transfer. |
| Kojto | 120:7c328cabac7e | 358 | */ |
| Kojto | 120:7c328cabac7e | 359 | #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) |
| Kojto | 120:7c328cabac7e | 360 | |
| Kojto | 120:7c328cabac7e | 361 | /** |
| Kojto | 96:487b796308b0 | 362 | * @} |
| Kojto | 96:487b796308b0 | 363 | */ |
| Kojto | 96:487b796308b0 | 364 | |
| Kojto | 96:487b796308b0 | 365 | /* Include DMA HAL Extension module */ |
| Kojto | 96:487b796308b0 | 366 | #include "stm32f1xx_hal_dma_ex.h" |
| Kojto | 96:487b796308b0 | 367 | |
| Kojto | 96:487b796308b0 | 368 | /* Exported functions --------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 369 | /** @addtogroup DMA_Exported_Functions DMA Exported Functions |
| Kojto | 96:487b796308b0 | 370 | * @{ |
| Kojto | 96:487b796308b0 | 371 | */ |
| Kojto | 96:487b796308b0 | 372 | |
| Kojto | 96:487b796308b0 | 373 | /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions |
| Kojto | 96:487b796308b0 | 374 | * @{ |
| Kojto | 96:487b796308b0 | 375 | */ |
| Kojto | 96:487b796308b0 | 376 | /* Initialization and de-initialization functions *****************************/ |
| Kojto | 96:487b796308b0 | 377 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
| Kojto | 96:487b796308b0 | 378 | HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); |
| Kojto | 96:487b796308b0 | 379 | /** |
| Kojto | 96:487b796308b0 | 380 | * @} |
| Kojto | 96:487b796308b0 | 381 | */ |
| Kojto | 96:487b796308b0 | 382 | |
| Kojto | 96:487b796308b0 | 383 | /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions |
| Kojto | 96:487b796308b0 | 384 | * @{ |
| Kojto | 96:487b796308b0 | 385 | */ |
| Kojto | 96:487b796308b0 | 386 | /* IO operation functions *****************************************************/ |
| Kojto | 96:487b796308b0 | 387 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| Kojto | 96:487b796308b0 | 388 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
| Kojto | 96:487b796308b0 | 389 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
| Kojto | 96:487b796308b0 | 390 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
| Kojto | 120:7c328cabac7e | 391 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
| Kojto | 96:487b796308b0 | 392 | /** |
| Kojto | 96:487b796308b0 | 393 | * @} |
| Kojto | 96:487b796308b0 | 394 | */ |
| Kojto | 96:487b796308b0 | 395 | |
| Kojto | 96:487b796308b0 | 396 | /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions |
| Kojto | 96:487b796308b0 | 397 | * @{ |
| Kojto | 96:487b796308b0 | 398 | */ |
| Kojto | 96:487b796308b0 | 399 | /* Peripheral State and Error functions ***************************************/ |
| Kojto | 96:487b796308b0 | 400 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
| Kojto | 96:487b796308b0 | 401 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
| Kojto | 96:487b796308b0 | 402 | /** |
| Kojto | 96:487b796308b0 | 403 | * @} |
| Kojto | 96:487b796308b0 | 404 | */ |
| Kojto | 96:487b796308b0 | 405 | |
| Kojto | 96:487b796308b0 | 406 | /** |
| Kojto | 96:487b796308b0 | 407 | * @} |
| Kojto | 96:487b796308b0 | 408 | */ |
| Kojto | 96:487b796308b0 | 409 | |
| Kojto | 120:7c328cabac7e | 410 | /* Private Constants -------------------------------------------------------------*/ |
| Kojto | 120:7c328cabac7e | 411 | /** @defgroup DMA_Private_Constants DMA Private Constants |
| Kojto | 120:7c328cabac7e | 412 | * @brief DMA private defines and constants |
| Kojto | 120:7c328cabac7e | 413 | * @{ |
| Kojto | 120:7c328cabac7e | 414 | */ |
| Kojto | 120:7c328cabac7e | 415 | /** |
| Kojto | 120:7c328cabac7e | 416 | * @} |
| Kojto | 120:7c328cabac7e | 417 | */ |
| Kojto | 120:7c328cabac7e | 418 | |
| Kojto | 120:7c328cabac7e | 419 | /* Private macros ------------------------------------------------------------*/ |
| Kojto | 120:7c328cabac7e | 420 | /** @defgroup DMA_Private_Macros DMA Private Macros |
| Kojto | 120:7c328cabac7e | 421 | * @brief DMA private macros |
| Kojto | 120:7c328cabac7e | 422 | * @{ |
| Kojto | 120:7c328cabac7e | 423 | */ |
| Kojto | 120:7c328cabac7e | 424 | |
| Kojto | 120:7c328cabac7e | 425 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
| Kojto | 120:7c328cabac7e | 426 | |
| Kojto | 120:7c328cabac7e | 427 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
| Kojto | 120:7c328cabac7e | 428 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
| Kojto | 120:7c328cabac7e | 429 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
| Kojto | 120:7c328cabac7e | 430 | |
| Kojto | 120:7c328cabac7e | 431 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
| Kojto | 120:7c328cabac7e | 432 | ((STATE) == DMA_PINC_DISABLE)) |
| Kojto | 120:7c328cabac7e | 433 | |
| Kojto | 120:7c328cabac7e | 434 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
| Kojto | 120:7c328cabac7e | 435 | ((STATE) == DMA_MINC_DISABLE)) |
| Kojto | 120:7c328cabac7e | 436 | |
| Kojto | 120:7c328cabac7e | 437 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
| Kojto | 120:7c328cabac7e | 438 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
| Kojto | 120:7c328cabac7e | 439 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
| Kojto | 120:7c328cabac7e | 440 | |
| Kojto | 120:7c328cabac7e | 441 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
| Kojto | 120:7c328cabac7e | 442 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
| Kojto | 120:7c328cabac7e | 443 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
| Kojto | 120:7c328cabac7e | 444 | |
| Kojto | 120:7c328cabac7e | 445 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
| Kojto | 120:7c328cabac7e | 446 | ((MODE) == DMA_CIRCULAR)) |
| Kojto | 120:7c328cabac7e | 447 | |
| Kojto | 120:7c328cabac7e | 448 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
| Kojto | 120:7c328cabac7e | 449 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
| Kojto | 120:7c328cabac7e | 450 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
| Kojto | 120:7c328cabac7e | 451 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
| Kojto | 120:7c328cabac7e | 452 | |
| Kojto | 120:7c328cabac7e | 453 | /** |
| Kojto | 120:7c328cabac7e | 454 | * @} |
| Kojto | 120:7c328cabac7e | 455 | */ |
| Kojto | 120:7c328cabac7e | 456 | |
| Kojto | 120:7c328cabac7e | 457 | /* Private functions ---------------------------------------------------------*/ |
| Kojto | 120:7c328cabac7e | 458 | /** @defgroup DMA_Private_Functions DMA Private Functions |
| Kojto | 120:7c328cabac7e | 459 | * @brief DMA private functions |
| Kojto | 120:7c328cabac7e | 460 | * @{ |
| Kojto | 120:7c328cabac7e | 461 | */ |
| Kojto | 120:7c328cabac7e | 462 | /** |
| Kojto | 120:7c328cabac7e | 463 | * @} |
| Kojto | 120:7c328cabac7e | 464 | */ |
| Kojto | 120:7c328cabac7e | 465 | |
| Kojto | 96:487b796308b0 | 466 | /** |
| Kojto | 96:487b796308b0 | 467 | * @} |
| Kojto | 96:487b796308b0 | 468 | */ |
| Kojto | 96:487b796308b0 | 469 | |
| Kojto | 96:487b796308b0 | 470 | /** |
| Kojto | 96:487b796308b0 | 471 | * @} |
| Kojto | 96:487b796308b0 | 472 | */ |
| Kojto | 96:487b796308b0 | 473 | |
| Kojto | 96:487b796308b0 | 474 | #ifdef __cplusplus |
| Kojto | 96:487b796308b0 | 475 | } |
| Kojto | 96:487b796308b0 | 476 | #endif |
| Kojto | 96:487b796308b0 | 477 | |
| Kojto | 96:487b796308b0 | 478 | #endif /* __STM32F1xx_HAL_DMA_H */ |
| Kojto | 96:487b796308b0 | 479 | |
| Kojto | 96:487b796308b0 | 480 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |