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TARGET_NUCLEO_F103RB/stm32f1xx_hal_rcc_ex.h@120:7c328cabac7e, 2016-05-10 (annotated)

Committer:
Kojto
Date:
Tue May 10 12:23:43 2016 -0500
Revision:
120:7c328cabac7e
Parent:
96:487b796308b0 
Release 120 of the mbed library



Changes:

- ST - STMF3XX/F4XX - directories removal

     - STMF3 - pwm range fix

     - STMF1 - Cube driver update

- Renesas - RZ_A1H - async i2c, serial and spi addition

- Freescale - KSDK2 update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 96:487b796308b0 1 /**
Kojto 96:487b796308b0 2 ******************************************************************************
Kojto 96:487b796308b0 3 * @file stm32f1xx_hal_rcc_ex.h
Kojto 96:487b796308b0 4 * @author MCD Application Team
Kojto 120:7c328cabac7e 5 * @version V1.0.4
Kojto 120:7c328cabac7e 6 * @date 29-April-2016
Kojto 96:487b796308b0 7 * @brief Header file of RCC HAL Extension module.
Kojto 96:487b796308b0 8 ******************************************************************************
Kojto 96:487b796308b0 9 * @attention
Kojto 96:487b796308b0 10 *
Kojto 120:7c328cabac7e 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 96:487b796308b0 12 *
Kojto 96:487b796308b0 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 96:487b796308b0 14 * are permitted provided that the following conditions are met:
Kojto 96:487b796308b0 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 96:487b796308b0 16 * this list of conditions and the following disclaimer.
Kojto 96:487b796308b0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 96:487b796308b0 18 * this list of conditions and the following disclaimer in the documentation
Kojto 96:487b796308b0 19 * and/or other materials provided with the distribution.
Kojto 96:487b796308b0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 96:487b796308b0 21 * may be used to endorse or promote products derived from this software
Kojto 96:487b796308b0 22 * without specific prior written permission.
Kojto 96:487b796308b0 23 *
Kojto 96:487b796308b0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 96:487b796308b0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 96:487b796308b0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 96:487b796308b0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 96:487b796308b0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 96:487b796308b0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 96:487b796308b0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 96:487b796308b0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 96:487b796308b0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 96:487b796308b0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 96:487b796308b0 34 *
Kojto 96:487b796308b0 35 ******************************************************************************
Kojto 96:487b796308b0 36 */
Kojto 96:487b796308b0 37
Kojto 96:487b796308b0 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 96:487b796308b0 39 #ifndef __STM32F1xx_HAL_RCC_EX_H
Kojto 96:487b796308b0 40 #define __STM32F1xx_HAL_RCC_EX_H
Kojto 96:487b796308b0 41
Kojto 96:487b796308b0 42 #ifdef __cplusplus
Kojto 96:487b796308b0 43 extern "C" {
Kojto 96:487b796308b0 44 #endif
Kojto 96:487b796308b0 45
Kojto 96:487b796308b0 46 /* Includes ------------------------------------------------------------------*/
Kojto 96:487b796308b0 47 #include "stm32f1xx_hal_def.h"
Kojto 96:487b796308b0 48
Kojto 96:487b796308b0 49 /** @addtogroup STM32F1xx_HAL_Driver
Kojto 96:487b796308b0 50 * @{
Kojto 96:487b796308b0 51 */
Kojto 96:487b796308b0 52
Kojto 96:487b796308b0 53 /** @addtogroup RCCEx
Kojto 96:487b796308b0 54 * @{
Kojto 96:487b796308b0 55 */
Kojto 96:487b796308b0 56
Kojto 96:487b796308b0 57 /** @addtogroup RCCEx_Private_Constants
Kojto 96:487b796308b0 58 * @{
Kojto 96:487b796308b0 59 */
Kojto 96:487b796308b0 60
Kojto 96:487b796308b0 61 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 62
Kojto 96:487b796308b0 63 /* Alias word address of PLLI2SON bit */
Kojto 96:487b796308b0 64 #define PLLI2SON_BITNUMBER POSITION_VAL(RCC_CR_PLL3ON)
Kojto 120:7c328cabac7e 65 #define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLI2SON_BITNUMBER * 4)))
Kojto 120:7c328cabac7e 66 /* Alias word address of PLL2ON bit */
Kojto 120:7c328cabac7e 67 #define PLL2ON_BITNUMBER POSITION_VAL(RCC_CR_PLL2ON)
Kojto 120:7c328cabac7e 68 #define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLL2ON_BITNUMBER * 4)))
Kojto 96:487b796308b0 69
Kojto 96:487b796308b0 70 #define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 120:7c328cabac7e 71 #define PLL2_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 96:487b796308b0 72
Kojto 96:487b796308b0 73 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 74
Kojto 120:7c328cabac7e 75
Kojto 120:7c328cabac7e 76 #define CR_REG_INDEX ((uint8_t)1)
Kojto 96:487b796308b0 77
Kojto 96:487b796308b0 78 /**
Kojto 96:487b796308b0 79 * @}
Kojto 96:487b796308b0 80 */
Kojto 96:487b796308b0 81
Kojto 96:487b796308b0 82 /** @addtogroup RCCEx_Private_Macros
Kojto 96:487b796308b0 83 * @{
Kojto 96:487b796308b0 84 */
Kojto 96:487b796308b0 85
Kojto 96:487b796308b0 86 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 87 #define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \
Kojto 96:487b796308b0 88 ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))
Kojto 96:487b796308b0 89 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 90
Kojto 120:7c328cabac7e 91 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
Kojto 120:7c328cabac7e 92 || defined(STM32F100xE)
Kojto 96:487b796308b0 93 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \
Kojto 96:487b796308b0 94 ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \
Kojto 96:487b796308b0 95 ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \
Kojto 96:487b796308b0 96 ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \
Kojto 96:487b796308b0 97 ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \
Kojto 96:487b796308b0 98 ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \
Kojto 96:487b796308b0 99 ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \
Kojto 96:487b796308b0 100 ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16))
Kojto 96:487b796308b0 101
Kojto 96:487b796308b0 102 #else
Kojto 96:487b796308b0 103 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))
Kojto 96:487b796308b0 104 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
Kojto 96:487b796308b0 105
Kojto 96:487b796308b0 106 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 107 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
Kojto 96:487b796308b0 108 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
Kojto 96:487b796308b0 109 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
Kojto 96:487b796308b0 110 ((__MUL__) == RCC_PLL_MUL6_5))
Kojto 96:487b796308b0 111
Kojto 96:487b796308b0 112 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
Kojto 96:487b796308b0 113 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
Kojto 96:487b796308b0 114 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \
Kojto 96:487b796308b0 115 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \
Kojto 96:487b796308b0 116 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
Kojto 96:487b796308b0 117
Kojto 96:487b796308b0 118 #else
Kojto 96:487b796308b0 119 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
Kojto 96:487b796308b0 120 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
Kojto 96:487b796308b0 121 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
Kojto 96:487b796308b0 122 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
Kojto 96:487b796308b0 123 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
Kojto 96:487b796308b0 124 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
Kojto 96:487b796308b0 125 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
Kojto 96:487b796308b0 126 ((__MUL__) == RCC_PLL_MUL16))
Kojto 96:487b796308b0 127
Kojto 96:487b796308b0 128 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
Kojto 96:487b796308b0 129 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
Kojto 96:487b796308b0 130 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
Kojto 96:487b796308b0 131
Kojto 96:487b796308b0 132 #endif /* STM32F105xC || STM32F107xC*/
Kojto 96:487b796308b0 133
Kojto 96:487b796308b0 134 #define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \
Kojto 96:487b796308b0 135 ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))
Kojto 96:487b796308b0 136
Kojto 96:487b796308b0 137 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 138 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))
Kojto 96:487b796308b0 139
Kojto 96:487b796308b0 140 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))
Kojto 96:487b796308b0 141
Kojto 120:7c328cabac7e 142 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3))
Kojto 96:487b796308b0 143
Kojto 96:487b796308b0 144 #define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \
Kojto 96:487b796308b0 145 ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \
Kojto 96:487b796308b0 146 ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \
Kojto 96:487b796308b0 147 ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \
Kojto 96:487b796308b0 148 ((__MUL__) == RCC_PLLI2S_MUL20))
Kojto 96:487b796308b0 149
Kojto 96:487b796308b0 150 #define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \
Kojto 96:487b796308b0 151 ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \
Kojto 96:487b796308b0 152 ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \
Kojto 96:487b796308b0 153 ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \
Kojto 96:487b796308b0 154 ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \
Kojto 96:487b796308b0 155 ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \
Kojto 96:487b796308b0 156 ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \
Kojto 96:487b796308b0 157 ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16))
Kojto 96:487b796308b0 158
Kojto 96:487b796308b0 159 #define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \
Kojto 96:487b796308b0 160 ((__PLL__) == RCC_PLL2_ON))
Kojto 96:487b796308b0 161
Kojto 96:487b796308b0 162 #define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \
Kojto 96:487b796308b0 163 ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \
Kojto 96:487b796308b0 164 ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \
Kojto 96:487b796308b0 165 ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \
Kojto 96:487b796308b0 166 ((__MUL__) == RCC_PLL2_MUL20))
Kojto 96:487b796308b0 167
Kojto 96:487b796308b0 168 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
Kojto 96:487b796308b0 169 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
Kojto 96:487b796308b0 170 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
Kojto 96:487b796308b0 171 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
Kojto 96:487b796308b0 172 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
Kojto 96:487b796308b0 173 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
Kojto 96:487b796308b0 174
Kojto 96:487b796308b0 175 #elif defined(STM32F103xE) || defined(STM32F103xG)
Kojto 96:487b796308b0 176
Kojto 96:487b796308b0 177 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)
Kojto 96:487b796308b0 178
Kojto 96:487b796308b0 179 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)
Kojto 96:487b796308b0 180
Kojto 96:487b796308b0 181 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
Kojto 96:487b796308b0 182 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
Kojto 96:487b796308b0 183 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
Kojto 96:487b796308b0 184 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
Kojto 96:487b796308b0 185 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
Kojto 96:487b796308b0 186 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
Kojto 96:487b796308b0 187
Kojto 96:487b796308b0 188
Kojto 120:7c328cabac7e 189 #elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
Kojto 120:7c328cabac7e 190 || defined(STM32F103xB)
Kojto 96:487b796308b0 191
Kojto 96:487b796308b0 192 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
Kojto 96:487b796308b0 193 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
Kojto 96:487b796308b0 194 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
Kojto 96:487b796308b0 195 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
Kojto 96:487b796308b0 196
Kojto 96:487b796308b0 197 #else
Kojto 96:487b796308b0 198
Kojto 96:487b796308b0 199 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
Kojto 96:487b796308b0 200 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
Kojto 96:487b796308b0 201 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC))
Kojto 96:487b796308b0 202
Kojto 96:487b796308b0 203 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 204
Kojto 120:7c328cabac7e 205 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
Kojto 120:7c328cabac7e 206 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
Kojto 96:487b796308b0 207
Kojto 120:7c328cabac7e 208 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))
Kojto 96:487b796308b0 209
Kojto 96:487b796308b0 210 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
Kojto 96:487b796308b0 211
Kojto 96:487b796308b0 212 /**
Kojto 96:487b796308b0 213 * @}
Kojto 96:487b796308b0 214 */
Kojto 96:487b796308b0 215
Kojto 96:487b796308b0 216 /* Exported types ------------------------------------------------------------*/
Kojto 96:487b796308b0 217
Kojto 96:487b796308b0 218 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto 96:487b796308b0 219 * @{
Kojto 96:487b796308b0 220 */
Kojto 96:487b796308b0 221
Kojto 96:487b796308b0 222 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 223 /**
Kojto 96:487b796308b0 224 * @brief RCC PLL2 configuration structure definition
Kojto 96:487b796308b0 225 */
Kojto 96:487b796308b0 226 typedef struct
Kojto 96:487b796308b0 227 {
Kojto 96:487b796308b0 228 uint32_t PLL2State; /*!< The new state of the PLL2.
Kojto 96:487b796308b0 229 This parameter can be a value of @ref RCCEx_PLL2_Config */
Kojto 96:487b796308b0 230
Kojto 96:487b796308b0 231 uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock
Kojto 96:487b796308b0 232 This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/
Kojto 96:487b796308b0 233
Kojto 96:487b796308b0 234 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 235 uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
Kojto 96:487b796308b0 236 This parameter can be a value of @ref RCCEx_Prediv2_Factor */
Kojto 96:487b796308b0 237
Kojto 96:487b796308b0 238 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 239 } RCC_PLL2InitTypeDef;
Kojto 96:487b796308b0 240
Kojto 96:487b796308b0 241 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 242
Kojto 96:487b796308b0 243 /**
Kojto 96:487b796308b0 244 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto 96:487b796308b0 245 */
Kojto 96:487b796308b0 246 typedef struct
Kojto 96:487b796308b0 247 {
Kojto 96:487b796308b0 248 uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto 96:487b796308b0 249 This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto 96:487b796308b0 250
Kojto 96:487b796308b0 251 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 252 uint32_t Prediv1Source; /*!< The Prediv1 source value.
Kojto 96:487b796308b0 253 This parameter can be a value of @ref RCCEx_Prediv1_Source */
Kojto 96:487b796308b0 254 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 255
Kojto 96:487b796308b0 256 uint32_t HSEState; /*!< The new state of the HSE.
Kojto 120:7c328cabac7e 257 This parameter can be a value of @ref RCC_HSE_Config */
Kojto 96:487b796308b0 258
Kojto 96:487b796308b0 259 uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)
Kojto 96:487b796308b0 260 This parameter can be a value of @ref RCCEx_Prediv1_Factor */
Kojto 96:487b796308b0 261
Kojto 96:487b796308b0 262 uint32_t LSEState; /*!< The new state of the LSE.
Kojto 120:7c328cabac7e 263 This parameter can be a value of @ref RCC_LSE_Config */
Kojto 96:487b796308b0 264
Kojto 96:487b796308b0 265 uint32_t HSIState; /*!< The new state of the HSI.
Kojto 96:487b796308b0 266 This parameter can be a value of @ref RCC_HSI_Config */
Kojto 96:487b796308b0 267
Kojto 96:487b796308b0 268 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Kojto 96:487b796308b0 269 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto 96:487b796308b0 270
Kojto 96:487b796308b0 271 uint32_t LSIState; /*!< The new state of the LSI.
Kojto 96:487b796308b0 272 This parameter can be a value of @ref RCC_LSI_Config */
Kojto 96:487b796308b0 273
Kojto 96:487b796308b0 274 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
Kojto 96:487b796308b0 275
Kojto 96:487b796308b0 276 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 277 RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */
Kojto 96:487b796308b0 278 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 279 } RCC_OscInitTypeDef;
Kojto 96:487b796308b0 280
Kojto 96:487b796308b0 281 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 282 /**
Kojto 96:487b796308b0 283 * @brief RCC PLLI2S configuration structure definition
Kojto 96:487b796308b0 284 */
Kojto 96:487b796308b0 285 typedef struct
Kojto 96:487b796308b0 286 {
Kojto 96:487b796308b0 287 uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock
Kojto 96:487b796308b0 288 This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/
Kojto 96:487b796308b0 289
Kojto 96:487b796308b0 290 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 291 uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
Kojto 96:487b796308b0 292 This parameter can be a value of @ref RCCEx_Prediv2_Factor */
Kojto 96:487b796308b0 293
Kojto 96:487b796308b0 294 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 295 } RCC_PLLI2SInitTypeDef;
Kojto 96:487b796308b0 296 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 297
Kojto 96:487b796308b0 298 /**
Kojto 96:487b796308b0 299 * @brief RCC extended clocks structure definition
Kojto 96:487b796308b0 300 */
Kojto 96:487b796308b0 301 typedef struct
Kojto 96:487b796308b0 302 {
Kojto 96:487b796308b0 303 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 96:487b796308b0 304 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 96:487b796308b0 305
Kojto 96:487b796308b0 306 uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
Kojto 96:487b796308b0 307 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 96:487b796308b0 308
Kojto 96:487b796308b0 309 uint32_t AdcClockSelection; /*!< ADC clock source
Kojto 96:487b796308b0 310 This parameter can be a value of @ref RCCEx_ADC_Prescaler */
Kojto 96:487b796308b0 311
Kojto 120:7c328cabac7e 312 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
Kojto 120:7c328cabac7e 313 || defined(STM32F107xC)
Kojto 96:487b796308b0 314 uint32_t I2s2ClockSelection; /*!< I2S2 clock source
Kojto 96:487b796308b0 315 This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */
Kojto 96:487b796308b0 316
Kojto 96:487b796308b0 317 uint32_t I2s3ClockSelection; /*!< I2S3 clock source
Kojto 96:487b796308b0 318 This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */
Kojto 96:487b796308b0 319
Kojto 120:7c328cabac7e 320 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 321 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
Kojto 96:487b796308b0 322 This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */
Kojto 96:487b796308b0 323
Kojto 96:487b796308b0 324 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 325 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 326
Kojto 120:7c328cabac7e 327 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
Kojto 120:7c328cabac7e 328 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
Kojto 120:7c328cabac7e 329 || defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 330 uint32_t UsbClockSelection; /*!< USB clock source
Kojto 96:487b796308b0 331 This parameter can be a value of @ref RCCEx_USB_Prescaler */
Kojto 96:487b796308b0 332
Kojto 96:487b796308b0 333 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 334 } RCC_PeriphCLKInitTypeDef;
Kojto 96:487b796308b0 335
Kojto 96:487b796308b0 336 /**
Kojto 96:487b796308b0 337 * @}
Kojto 96:487b796308b0 338 */
Kojto 96:487b796308b0 339
Kojto 96:487b796308b0 340 /* Exported constants --------------------------------------------------------*/
Kojto 96:487b796308b0 341
Kojto 96:487b796308b0 342 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
Kojto 96:487b796308b0 343 * @{
Kojto 96:487b796308b0 344 */
Kojto 96:487b796308b0 345
Kojto 96:487b796308b0 346 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
Kojto 96:487b796308b0 347 * @{
Kojto 96:487b796308b0 348 */
Kojto 96:487b796308b0 349 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001)
Kojto 96:487b796308b0 350 #define RCC_PERIPHCLK_ADC ((uint32_t)0x00000002)
Kojto 120:7c328cabac7e 351 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
Kojto 120:7c328cabac7e 352 || defined(STM32F107xC)
Kojto 96:487b796308b0 353 #define RCC_PERIPHCLK_I2S2 ((uint32_t)0x00000004)
Kojto 96:487b796308b0 354 #define RCC_PERIPHCLK_I2S3 ((uint32_t)0x00000008)
Kojto 96:487b796308b0 355 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
Kojto 120:7c328cabac7e 356 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
Kojto 120:7c328cabac7e 357 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
Kojto 120:7c328cabac7e 358 || defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 359 #define RCC_PERIPHCLK_USB ((uint32_t)0x00000010)
Kojto 96:487b796308b0 360 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 361
Kojto 96:487b796308b0 362 /**
Kojto 96:487b796308b0 363 * @}
Kojto 96:487b796308b0 364 */
Kojto 96:487b796308b0 365
Kojto 96:487b796308b0 366 /** @defgroup RCCEx_ADC_Prescaler ADC Prescaler
Kojto 96:487b796308b0 367 * @{
Kojto 96:487b796308b0 368 */
Kojto 96:487b796308b0 369 #define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
Kojto 96:487b796308b0 370 #define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
Kojto 96:487b796308b0 371 #define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
Kojto 96:487b796308b0 372 #define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
Kojto 96:487b796308b0 373
Kojto 96:487b796308b0 374 /**
Kojto 96:487b796308b0 375 * @}
Kojto 96:487b796308b0 376 */
Kojto 96:487b796308b0 377
Kojto 120:7c328cabac7e 378 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
Kojto 120:7c328cabac7e 379 || defined(STM32F107xC)
Kojto 96:487b796308b0 380 /** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source
Kojto 96:487b796308b0 381 * @{
Kojto 96:487b796308b0 382 */
Kojto 96:487b796308b0 383 #define RCC_I2S2CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
Kojto 96:487b796308b0 384 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 385 #define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC
Kojto 96:487b796308b0 386 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 387
Kojto 96:487b796308b0 388 /**
Kojto 96:487b796308b0 389 * @}
Kojto 96:487b796308b0 390 */
Kojto 96:487b796308b0 391
Kojto 96:487b796308b0 392 /** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source
Kojto 96:487b796308b0 393 * @{
Kojto 96:487b796308b0 394 */
Kojto 96:487b796308b0 395 #define RCC_I2S3CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
Kojto 96:487b796308b0 396 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 397 #define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC
Kojto 96:487b796308b0 398 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 399
Kojto 96:487b796308b0 400 /**
Kojto 96:487b796308b0 401 * @}
Kojto 96:487b796308b0 402 */
Kojto 96:487b796308b0 403
Kojto 96:487b796308b0 404 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 405
Kojto 120:7c328cabac7e 406 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
Kojto 120:7c328cabac7e 407 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
Kojto 96:487b796308b0 408
Kojto 96:487b796308b0 409 /** @defgroup RCCEx_USB_Prescaler USB Prescaler
Kojto 96:487b796308b0 410 * @{
Kojto 96:487b796308b0 411 */
Kojto 120:7c328cabac7e 412 #define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE
Kojto 120:7c328cabac7e 413 #define RCC_USBCLKSOURCE_PLL_DIV1_5 ((uint32_t)0x00000000)
Kojto 96:487b796308b0 414
Kojto 96:487b796308b0 415 /**
Kojto 96:487b796308b0 416 * @}
Kojto 96:487b796308b0 417 */
Kojto 96:487b796308b0 418
Kojto 96:487b796308b0 419 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
Kojto 96:487b796308b0 420
Kojto 96:487b796308b0 421
Kojto 96:487b796308b0 422 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 423 /** @defgroup RCCEx_USB_Prescaler USB Prescaler
Kojto 96:487b796308b0 424 * @{
Kojto 96:487b796308b0 425 */
Kojto 120:7c328cabac7e 426 #define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE
Kojto 120:7c328cabac7e 427 #define RCC_USBCLKSOURCE_PLL_DIV3 ((uint32_t)0x00000000)
Kojto 96:487b796308b0 428
Kojto 96:487b796308b0 429 /**
Kojto 96:487b796308b0 430 * @}
Kojto 96:487b796308b0 431 */
Kojto 96:487b796308b0 432
Kojto 96:487b796308b0 433 /** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor
Kojto 96:487b796308b0 434 * @{
Kojto 96:487b796308b0 435 */
Kojto 96:487b796308b0 436
Kojto 96:487b796308b0 437 #define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */
Kojto 96:487b796308b0 438 #define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */
Kojto 96:487b796308b0 439 #define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
Kojto 96:487b796308b0 440 #define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
Kojto 96:487b796308b0 441 #define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
Kojto 96:487b796308b0 442 #define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
Kojto 96:487b796308b0 443 #define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
Kojto 96:487b796308b0 444 #define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
Kojto 96:487b796308b0 445 #define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */
Kojto 96:487b796308b0 446
Kojto 96:487b796308b0 447 /**
Kojto 96:487b796308b0 448 * @}
Kojto 96:487b796308b0 449 */
Kojto 96:487b796308b0 450 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 451
Kojto 96:487b796308b0 452 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 453 /** @defgroup RCCEx_Prediv1_Source Prediv1 Source
Kojto 96:487b796308b0 454 * @{
Kojto 96:487b796308b0 455 */
Kojto 96:487b796308b0 456
Kojto 96:487b796308b0 457 #define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE
Kojto 96:487b796308b0 458 #define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2
Kojto 96:487b796308b0 459
Kojto 96:487b796308b0 460 /**
Kojto 96:487b796308b0 461 * @}
Kojto 96:487b796308b0 462 */
Kojto 96:487b796308b0 463 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 464
Kojto 96:487b796308b0 465 /** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor
Kojto 96:487b796308b0 466 * @{
Kojto 96:487b796308b0 467 */
Kojto 96:487b796308b0 468
Kojto 96:487b796308b0 469 #define RCC_HSE_PREDIV_DIV1 ((uint32_t)0x00000000)
Kojto 96:487b796308b0 470
Kojto 120:7c328cabac7e 471 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
Kojto 120:7c328cabac7e 472 || defined(STM32F100xE)
Kojto 96:487b796308b0 473 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2
Kojto 96:487b796308b0 474 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3
Kojto 96:487b796308b0 475 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4
Kojto 96:487b796308b0 476 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5
Kojto 96:487b796308b0 477 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6
Kojto 96:487b796308b0 478 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7
Kojto 96:487b796308b0 479 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8
Kojto 96:487b796308b0 480 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9
Kojto 96:487b796308b0 481 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10
Kojto 96:487b796308b0 482 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11
Kojto 96:487b796308b0 483 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12
Kojto 96:487b796308b0 484 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13
Kojto 96:487b796308b0 485 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14
Kojto 96:487b796308b0 486 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15
Kojto 96:487b796308b0 487 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16
Kojto 96:487b796308b0 488 #else
Kojto 96:487b796308b0 489 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE
Kojto 96:487b796308b0 490 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
Kojto 96:487b796308b0 491
Kojto 96:487b796308b0 492 /**
Kojto 96:487b796308b0 493 * @}
Kojto 96:487b796308b0 494 */
Kojto 96:487b796308b0 495
Kojto 96:487b796308b0 496 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 497 /** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor
Kojto 96:487b796308b0 498 * @{
Kojto 96:487b796308b0 499 */
Kojto 96:487b796308b0 500
Kojto 96:487b796308b0 501 #define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */
Kojto 96:487b796308b0 502 #define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */
Kojto 96:487b796308b0 503 #define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */
Kojto 96:487b796308b0 504 #define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */
Kojto 96:487b796308b0 505 #define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */
Kojto 96:487b796308b0 506 #define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */
Kojto 96:487b796308b0 507 #define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */
Kojto 96:487b796308b0 508 #define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */
Kojto 96:487b796308b0 509 #define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */
Kojto 96:487b796308b0 510 #define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */
Kojto 96:487b796308b0 511 #define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */
Kojto 96:487b796308b0 512 #define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */
Kojto 96:487b796308b0 513 #define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */
Kojto 96:487b796308b0 514 #define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */
Kojto 96:487b796308b0 515 #define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */
Kojto 96:487b796308b0 516 #define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */
Kojto 96:487b796308b0 517
Kojto 96:487b796308b0 518 /**
Kojto 96:487b796308b0 519 * @}
Kojto 96:487b796308b0 520 */
Kojto 96:487b796308b0 521
Kojto 96:487b796308b0 522 /** @defgroup RCCEx_PLL2_Config PLL Config
Kojto 96:487b796308b0 523 * @{
Kojto 96:487b796308b0 524 */
Kojto 96:487b796308b0 525 #define RCC_PLL2_NONE ((uint32_t)0x00000000)
Kojto 96:487b796308b0 526 #define RCC_PLL2_OFF ((uint32_t)0x00000001)
Kojto 96:487b796308b0 527 #define RCC_PLL2_ON ((uint32_t)0x00000002)
Kojto 96:487b796308b0 528
Kojto 96:487b796308b0 529 /**
Kojto 96:487b796308b0 530 * @}
Kojto 96:487b796308b0 531 */
Kojto 96:487b796308b0 532
Kojto 96:487b796308b0 533 /** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor
Kojto 96:487b796308b0 534 * @{
Kojto 96:487b796308b0 535 */
Kojto 96:487b796308b0 536
Kojto 96:487b796308b0 537 #define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */
Kojto 96:487b796308b0 538 #define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */
Kojto 96:487b796308b0 539 #define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
Kojto 96:487b796308b0 540 #define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
Kojto 96:487b796308b0 541 #define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
Kojto 96:487b796308b0 542 #define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
Kojto 96:487b796308b0 543 #define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
Kojto 96:487b796308b0 544 #define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
Kojto 96:487b796308b0 545 #define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */
Kojto 96:487b796308b0 546
Kojto 96:487b796308b0 547 /**
Kojto 96:487b796308b0 548 * @}
Kojto 96:487b796308b0 549 */
Kojto 96:487b796308b0 550
Kojto 96:487b796308b0 551 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 552
Kojto 96:487b796308b0 553 /** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor
Kojto 96:487b796308b0 554 * @{
Kojto 96:487b796308b0 555 */
Kojto 96:487b796308b0 556
Kojto 96:487b796308b0 557 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 558 #else
Kojto 96:487b796308b0 559 #define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2
Kojto 96:487b796308b0 560 #define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3
Kojto 96:487b796308b0 561 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 562 #define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4
Kojto 96:487b796308b0 563 #define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5
Kojto 96:487b796308b0 564 #define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6
Kojto 96:487b796308b0 565 #define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7
Kojto 96:487b796308b0 566 #define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8
Kojto 96:487b796308b0 567 #define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9
Kojto 96:487b796308b0 568 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 569 #define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5
Kojto 96:487b796308b0 570 #else
Kojto 96:487b796308b0 571 #define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10
Kojto 96:487b796308b0 572 #define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11
Kojto 96:487b796308b0 573 #define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12
Kojto 96:487b796308b0 574 #define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13
Kojto 96:487b796308b0 575 #define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14
Kojto 96:487b796308b0 576 #define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15
Kojto 96:487b796308b0 577 #define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16
Kojto 96:487b796308b0 578 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 579
Kojto 96:487b796308b0 580 /**
Kojto 96:487b796308b0 581 * @}
Kojto 96:487b796308b0 582 */
Kojto 96:487b796308b0 583
Kojto 96:487b796308b0 584 /** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source
Kojto 96:487b796308b0 585 * @{
Kojto 96:487b796308b0 586 */
Kojto 96:487b796308b0 587 #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
Kojto 96:487b796308b0 588 #define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
Kojto 96:487b796308b0 589 #define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
Kojto 96:487b796308b0 590 #define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
Kojto 96:487b796308b0 591 #define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
Kojto 96:487b796308b0 592 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 593 #define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK)
Kojto 96:487b796308b0 594 #define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
Kojto 96:487b796308b0 595 #define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE)
Kojto 96:487b796308b0 596 #define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK)
Kojto 96:487b796308b0 597 #endif /* STM32F105xC || STM32F107xC*/
Kojto 96:487b796308b0 598 /**
Kojto 96:487b796308b0 599 * @}
Kojto 96:487b796308b0 600 */
Kojto 96:487b796308b0 601
Kojto 96:487b796308b0 602 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 603 /** @defgroup RCCEx_Interrupt RCCEx Interrupt
Kojto 96:487b796308b0 604 * @{
Kojto 96:487b796308b0 605 */
Kojto 96:487b796308b0 606 #define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF)
Kojto 120:7c328cabac7e 607 #define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF)
Kojto 96:487b796308b0 608 /**
Kojto 96:487b796308b0 609 * @}
Kojto 96:487b796308b0 610 */
Kojto 96:487b796308b0 611
Kojto 96:487b796308b0 612 /** @defgroup RCCEx_Flag RCCEx Flag
Kojto 96:487b796308b0 613 * Elements values convention: 0XXYYYYYb
Kojto 96:487b796308b0 614 * - YYYYY : Flag position in the register
Kojto 96:487b796308b0 615 * - XX : Register index
Kojto 96:487b796308b0 616 * - 01: CR register
Kojto 96:487b796308b0 617 * @{
Kojto 96:487b796308b0 618 */
Kojto 96:487b796308b0 619 /* Flags in the CR register */
Kojto 96:487b796308b0 620 #define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL2RDY)))
Kojto 96:487b796308b0 621 #define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL3RDY)))
Kojto 96:487b796308b0 622 /**
Kojto 96:487b796308b0 623 * @}
Kojto 96:487b796308b0 624 */
Kojto 96:487b796308b0 625 #endif /* STM32F105xC || STM32F107xC*/
Kojto 96:487b796308b0 626
Kojto 96:487b796308b0 627 /**
Kojto 96:487b796308b0 628 * @}
Kojto 96:487b796308b0 629 */
Kojto 96:487b796308b0 630
Kojto 96:487b796308b0 631 /* Exported macro ------------------------------------------------------------*/
Kojto 96:487b796308b0 632 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto 96:487b796308b0 633 * @{
Kojto 96:487b796308b0 634 */
Kojto 96:487b796308b0 635
Kojto 96:487b796308b0 636 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
Kojto 96:487b796308b0 637 * @brief Enable or disable the AHB1 peripheral clock.
Kojto 96:487b796308b0 638 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 96:487b796308b0 639 * is disabled and the application software has to enable this clock before
Kojto 96:487b796308b0 640 * using it.
Kojto 96:487b796308b0 641 * @{
Kojto 96:487b796308b0 642 */
Kojto 96:487b796308b0 643
Kojto 120:7c328cabac7e 644 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
Kojto 120:7c328cabac7e 645 || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\
Kojto 120:7c328cabac7e 646 || defined (STM32F100xE)
Kojto 96:487b796308b0 647 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto 96:487b796308b0 648 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 649 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
Kojto 96:487b796308b0 650 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 651 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
Kojto 96:487b796308b0 652 UNUSED(tmpreg); \
Kojto 96:487b796308b0 653 } while(0)
Kojto 96:487b796308b0 654
Kojto 96:487b796308b0 655 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
Kojto 96:487b796308b0 656 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
Kojto 96:487b796308b0 657
Kojto 120:7c328cabac7e 658 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
Kojto 120:7c328cabac7e 659 || defined(STM32F103xG) || defined (STM32F100xE)
Kojto 96:487b796308b0 660 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \
Kojto 96:487b796308b0 661 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 662 SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
Kojto 96:487b796308b0 663 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 664 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
Kojto 96:487b796308b0 665 UNUSED(tmpreg); \
Kojto 96:487b796308b0 666 } while(0)
Kojto 96:487b796308b0 667
Kojto 96:487b796308b0 668 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
Kojto 96:487b796308b0 669 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
Kojto 96:487b796308b0 670
Kojto 120:7c328cabac7e 671 #if defined(STM32F103xE) || defined(STM32F103xG)
Kojto 96:487b796308b0 672 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto 96:487b796308b0 673 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 674 SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
Kojto 96:487b796308b0 675 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 676 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
Kojto 96:487b796308b0 677 UNUSED(tmpreg); \
Kojto 96:487b796308b0 678 } while(0)
Kojto 96:487b796308b0 679
Kojto 96:487b796308b0 680
Kojto 96:487b796308b0 681 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
Kojto 96:487b796308b0 682 #endif /* STM32F103xE || STM32F103xG */
Kojto 96:487b796308b0 683
Kojto 96:487b796308b0 684 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 685 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
Kojto 96:487b796308b0 686 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 687 SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
Kojto 96:487b796308b0 688 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 689 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
Kojto 96:487b796308b0 690 UNUSED(tmpreg); \
Kojto 96:487b796308b0 691 } while(0)
Kojto 96:487b796308b0 692
Kojto 96:487b796308b0 693
Kojto 96:487b796308b0 694 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
Kojto 96:487b796308b0 695 #endif /* STM32F105xC || STM32F107xC*/
Kojto 96:487b796308b0 696
Kojto 96:487b796308b0 697 #if defined(STM32F107xC)
Kojto 96:487b796308b0 698 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto 96:487b796308b0 699 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 700 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
Kojto 96:487b796308b0 701 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 702 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
Kojto 96:487b796308b0 703 UNUSED(tmpreg); \
Kojto 96:487b796308b0 704 } while(0)
Kojto 96:487b796308b0 705
Kojto 96:487b796308b0 706 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto 96:487b796308b0 707 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 708 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
Kojto 96:487b796308b0 709 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 710 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
Kojto 96:487b796308b0 711 UNUSED(tmpreg); \
Kojto 96:487b796308b0 712 } while(0)
Kojto 96:487b796308b0 713
Kojto 96:487b796308b0 714 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto 96:487b796308b0 715 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 716 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
Kojto 96:487b796308b0 717 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 718 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
Kojto 96:487b796308b0 719 UNUSED(tmpreg); \
Kojto 96:487b796308b0 720 } while(0)
Kojto 96:487b796308b0 721
Kojto 96:487b796308b0 722 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
Kojto 96:487b796308b0 723 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
Kojto 96:487b796308b0 724 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))
Kojto 96:487b796308b0 725
Kojto 96:487b796308b0 726 /**
Kojto 96:487b796308b0 727 * @brief Enable ETHERNET clock.
Kojto 96:487b796308b0 728 */
Kojto 96:487b796308b0 729 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto 96:487b796308b0 730 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto 96:487b796308b0 731 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto 96:487b796308b0 732 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
Kojto 96:487b796308b0 733 } while(0)
Kojto 96:487b796308b0 734 /**
Kojto 96:487b796308b0 735 * @brief Disable ETHERNET clock.
Kojto 96:487b796308b0 736 */
Kojto 96:487b796308b0 737 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto 96:487b796308b0 738 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto 96:487b796308b0 739 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto 96:487b796308b0 740 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
Kojto 96:487b796308b0 741 } while(0)
Kojto 96:487b796308b0 742
Kojto 96:487b796308b0 743 #endif /* STM32F107xC*/
Kojto 96:487b796308b0 744
Kojto 96:487b796308b0 745 /**
Kojto 96:487b796308b0 746 * @}
Kojto 96:487b796308b0 747 */
Kojto 96:487b796308b0 748
Kojto 96:487b796308b0 749 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto 96:487b796308b0 750 * @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto 96:487b796308b0 751 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 96:487b796308b0 752 * is disabled and the application software has to enable this clock before
Kojto 96:487b796308b0 753 * using it.
Kojto 96:487b796308b0 754 * @{
Kojto 96:487b796308b0 755 */
Kojto 96:487b796308b0 756
Kojto 120:7c328cabac7e 757 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
Kojto 120:7c328cabac7e 758 || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\
Kojto 120:7c328cabac7e 759 || defined (STM32F100xE)
Kojto 96:487b796308b0 760 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
Kojto 96:487b796308b0 761 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
Kojto 96:487b796308b0 762 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
Kojto 120:7c328cabac7e 763 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
Kojto 120:7c328cabac7e 764 || defined(STM32F103xG) || defined (STM32F100xE)
Kojto 96:487b796308b0 765 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
Kojto 96:487b796308b0 766 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
Kojto 96:487b796308b0 767 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
Kojto 120:7c328cabac7e 768 #if defined(STM32F103xE) || defined(STM32F103xG)
Kojto 96:487b796308b0 769 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)
Kojto 96:487b796308b0 770 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)
Kojto 96:487b796308b0 771 #endif /* STM32F103xE || STM32F103xG */
Kojto 96:487b796308b0 772 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 773 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)
Kojto 96:487b796308b0 774 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)
Kojto 96:487b796308b0 775 #endif /* STM32F105xC || STM32F107xC*/
Kojto 96:487b796308b0 776 #if defined(STM32F107xC)
Kojto 96:487b796308b0 777 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)
Kojto 96:487b796308b0 778 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)
Kojto 96:487b796308b0 779 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)
Kojto 96:487b796308b0 780 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)
Kojto 96:487b796308b0 781 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)
Kojto 96:487b796308b0 782 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)
Kojto 96:487b796308b0 783 #endif /* STM32F107xC*/
Kojto 96:487b796308b0 784
Kojto 96:487b796308b0 785 /**
Kojto 96:487b796308b0 786 * @}
Kojto 96:487b796308b0 787 */
Kojto 96:487b796308b0 788
Kojto 96:487b796308b0 789 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
Kojto 96:487b796308b0 790 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 96:487b796308b0 791 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 96:487b796308b0 792 * is disabled and the application software has to enable this clock before
Kojto 96:487b796308b0 793 * using it.
Kojto 96:487b796308b0 794 * @{
Kojto 96:487b796308b0 795 */
Kojto 96:487b796308b0 796
Kojto 120:7c328cabac7e 797 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
Kojto 120:7c328cabac7e 798 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
Kojto 96:487b796308b0 799 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto 96:487b796308b0 800 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 801 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto 96:487b796308b0 802 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 803 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto 96:487b796308b0 804 UNUSED(tmpreg); \
Kojto 96:487b796308b0 805 } while(0)
Kojto 96:487b796308b0 806
Kojto 96:487b796308b0 807 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto 96:487b796308b0 808 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 809
Kojto 120:7c328cabac7e 810 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
Kojto 120:7c328cabac7e 811 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
Kojto 120:7c328cabac7e 812 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
Kojto 120:7c328cabac7e 813 || defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 814 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto 96:487b796308b0 815 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 816 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto 96:487b796308b0 817 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 818 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto 96:487b796308b0 819 UNUSED(tmpreg); \
Kojto 96:487b796308b0 820 } while(0)
Kojto 96:487b796308b0 821
Kojto 96:487b796308b0 822 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto 96:487b796308b0 823 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 824 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 96:487b796308b0 825 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 826 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 96:487b796308b0 827 UNUSED(tmpreg); \
Kojto 96:487b796308b0 828 } while(0)
Kojto 96:487b796308b0 829
Kojto 96:487b796308b0 830 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto 96:487b796308b0 831 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 832 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto 96:487b796308b0 833 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 834 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto 96:487b796308b0 835 UNUSED(tmpreg); \
Kojto 96:487b796308b0 836 } while(0)
Kojto 96:487b796308b0 837
Kojto 96:487b796308b0 838 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto 96:487b796308b0 839 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 840 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 96:487b796308b0 841 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 842 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 96:487b796308b0 843 UNUSED(tmpreg); \
Kojto 96:487b796308b0 844 } while(0)
Kojto 96:487b796308b0 845
Kojto 96:487b796308b0 846 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto 96:487b796308b0 847 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 96:487b796308b0 848 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto 96:487b796308b0 849 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 96:487b796308b0 850 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 851
Kojto 120:7c328cabac7e 852 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
Kojto 120:7c328cabac7e 853 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
Kojto 96:487b796308b0 854 #define __HAL_RCC_USB_CLK_ENABLE() do { \
Kojto 96:487b796308b0 855 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 856 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
Kojto 96:487b796308b0 857 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 858 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
Kojto 96:487b796308b0 859 UNUSED(tmpreg); \
Kojto 96:487b796308b0 860 } while(0)
Kojto 96:487b796308b0 861
Kojto 96:487b796308b0 862 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
Kojto 96:487b796308b0 863 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
Kojto 96:487b796308b0 864
Kojto 120:7c328cabac7e 865 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
Kojto 120:7c328cabac7e 866 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 867 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto 96:487b796308b0 868 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 869 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 96:487b796308b0 870 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 871 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 96:487b796308b0 872 UNUSED(tmpreg); \
Kojto 96:487b796308b0 873 } while(0)
Kojto 96:487b796308b0 874
Kojto 96:487b796308b0 875 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto 96:487b796308b0 876 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 877 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto 96:487b796308b0 878 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 879 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto 96:487b796308b0 880 UNUSED(tmpreg); \
Kojto 96:487b796308b0 881 } while(0)
Kojto 96:487b796308b0 882
Kojto 96:487b796308b0 883 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto 96:487b796308b0 884 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 885 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto 96:487b796308b0 886 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 887 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto 96:487b796308b0 888 UNUSED(tmpreg); \
Kojto 96:487b796308b0 889 } while(0)
Kojto 96:487b796308b0 890
Kojto 96:487b796308b0 891 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto 96:487b796308b0 892 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 893 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 96:487b796308b0 894 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 895 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 96:487b796308b0 896 UNUSED(tmpreg); \
Kojto 96:487b796308b0 897 } while(0)
Kojto 96:487b796308b0 898
Kojto 96:487b796308b0 899 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto 96:487b796308b0 900 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 901 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 96:487b796308b0 902 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 903 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 96:487b796308b0 904 UNUSED(tmpreg); \
Kojto 96:487b796308b0 905 } while(0)
Kojto 96:487b796308b0 906
Kojto 96:487b796308b0 907 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto 96:487b796308b0 908 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 909 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 96:487b796308b0 910 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 911 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 96:487b796308b0 912 UNUSED(tmpreg); \
Kojto 96:487b796308b0 913 } while(0)
Kojto 96:487b796308b0 914
Kojto 96:487b796308b0 915 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto 96:487b796308b0 916 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 917 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto 96:487b796308b0 918 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 919 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto 96:487b796308b0 920 UNUSED(tmpreg); \
Kojto 96:487b796308b0 921 } while(0)
Kojto 96:487b796308b0 922
Kojto 96:487b796308b0 923 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto 96:487b796308b0 924 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto 96:487b796308b0 925 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto 96:487b796308b0 926 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto 96:487b796308b0 927 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto 96:487b796308b0 928 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto 96:487b796308b0 929 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto 96:487b796308b0 930 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 931
Kojto 96:487b796308b0 932 #if defined(STM32F100xB) || defined (STM32F100xE)
Kojto 96:487b796308b0 933 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto 96:487b796308b0 934 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 935 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto 96:487b796308b0 936 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 937 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto 96:487b796308b0 938 UNUSED(tmpreg); \
Kojto 96:487b796308b0 939 } while(0)
Kojto 96:487b796308b0 940
Kojto 96:487b796308b0 941 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto 96:487b796308b0 942 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 943 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto 96:487b796308b0 944 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 945 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto 96:487b796308b0 946 UNUSED(tmpreg); \
Kojto 96:487b796308b0 947 } while(0)
Kojto 96:487b796308b0 948
Kojto 96:487b796308b0 949 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto 96:487b796308b0 950 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 951 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto 96:487b796308b0 952 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 953 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto 96:487b796308b0 954 UNUSED(tmpreg); \
Kojto 96:487b796308b0 955 } while(0)
Kojto 96:487b796308b0 956
Kojto 96:487b796308b0 957 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
Kojto 96:487b796308b0 958 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 959 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto 96:487b796308b0 960 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 961 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto 96:487b796308b0 962 UNUSED(tmpreg); \
Kojto 96:487b796308b0 963 } while(0)
Kojto 96:487b796308b0 964
Kojto 96:487b796308b0 965 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto 96:487b796308b0 966 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto 96:487b796308b0 967 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto 96:487b796308b0 968 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto 96:487b796308b0 969 #endif /* STM32F100xB || STM32F100xE */
Kojto 96:487b796308b0 970
Kojto 96:487b796308b0 971 #ifdef STM32F100xE
Kojto 96:487b796308b0 972 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto 96:487b796308b0 973 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 974 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 96:487b796308b0 975 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 976 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 96:487b796308b0 977 UNUSED(tmpreg); \
Kojto 96:487b796308b0 978 } while(0)
Kojto 96:487b796308b0 979
Kojto 96:487b796308b0 980 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto 96:487b796308b0 981 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 982 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto 96:487b796308b0 983 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 984 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto 96:487b796308b0 985 UNUSED(tmpreg); \
Kojto 96:487b796308b0 986 } while(0)
Kojto 96:487b796308b0 987
Kojto 96:487b796308b0 988 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto 96:487b796308b0 989 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 990 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto 96:487b796308b0 991 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 992 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto 96:487b796308b0 993 UNUSED(tmpreg); \
Kojto 96:487b796308b0 994 } while(0)
Kojto 96:487b796308b0 995
Kojto 96:487b796308b0 996 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto 96:487b796308b0 997 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 998 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 96:487b796308b0 999 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1000 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 96:487b796308b0 1001 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1002 } while(0)
Kojto 96:487b796308b0 1003
Kojto 96:487b796308b0 1004 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1005 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1006 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 96:487b796308b0 1007 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1008 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 96:487b796308b0 1009 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1010 } while(0)
Kojto 96:487b796308b0 1011
Kojto 96:487b796308b0 1012 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1013 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1014 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 96:487b796308b0 1015 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1016 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 96:487b796308b0 1017 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1018 } while(0)
Kojto 96:487b796308b0 1019
Kojto 96:487b796308b0 1020 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1021 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1022 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 96:487b796308b0 1023 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1024 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 96:487b796308b0 1025 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1026 } while(0)
Kojto 96:487b796308b0 1027
Kojto 96:487b796308b0 1028 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto 96:487b796308b0 1029 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto 96:487b796308b0 1030 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto 96:487b796308b0 1031 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto 96:487b796308b0 1032 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto 96:487b796308b0 1033 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto 96:487b796308b0 1034 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto 96:487b796308b0 1035 #endif /* STM32F100xE */
Kojto 96:487b796308b0 1036
Kojto 96:487b796308b0 1037 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 1038 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1039 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1040 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto 96:487b796308b0 1041 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1042 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto 96:487b796308b0 1043 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1044 } while(0)
Kojto 96:487b796308b0 1045
Kojto 96:487b796308b0 1046 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto 96:487b796308b0 1047 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 1048
Kojto 96:487b796308b0 1049 #if defined(STM32F101xG) || defined(STM32F103xG)
Kojto 96:487b796308b0 1050 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1051 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1052 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto 96:487b796308b0 1053 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1054 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto 96:487b796308b0 1055 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1056 } while(0)
Kojto 96:487b796308b0 1057
Kojto 96:487b796308b0 1058 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1059 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1060 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto 96:487b796308b0 1061 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1062 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto 96:487b796308b0 1063 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1064 } while(0)
Kojto 96:487b796308b0 1065
Kojto 96:487b796308b0 1066 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1067 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1068 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 96:487b796308b0 1069 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1070 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 96:487b796308b0 1071 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1072 } while(0)
Kojto 96:487b796308b0 1073
Kojto 96:487b796308b0 1074 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto 96:487b796308b0 1075 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto 96:487b796308b0 1076 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto 96:487b796308b0 1077 #endif /* STM32F101xG || STM32F103xG*/
Kojto 96:487b796308b0 1078
Kojto 96:487b796308b0 1079 /**
Kojto 96:487b796308b0 1080 * @}
Kojto 96:487b796308b0 1081 */
Kojto 96:487b796308b0 1082
Kojto 96:487b796308b0 1083 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto 96:487b796308b0 1084 * @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto 96:487b796308b0 1085 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 96:487b796308b0 1086 * is disabled and the application software has to enable this clock before
Kojto 96:487b796308b0 1087 * using it.
Kojto 96:487b796308b0 1088 * @{
Kojto 96:487b796308b0 1089 */
Kojto 96:487b796308b0 1090
Kojto 120:7c328cabac7e 1091 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
Kojto 120:7c328cabac7e 1092 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
Kojto 96:487b796308b0 1093 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
Kojto 96:487b796308b0 1094 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
Kojto 96:487b796308b0 1095 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
Kojto 120:7c328cabac7e 1096 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
Kojto 120:7c328cabac7e 1097 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
Kojto 120:7c328cabac7e 1098 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
Kojto 120:7c328cabac7e 1099 || defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 1100 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto 96:487b796308b0 1101 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto 96:487b796308b0 1102 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
Kojto 96:487b796308b0 1103 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
Kojto 96:487b796308b0 1104 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
Kojto 96:487b796308b0 1105 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
Kojto 96:487b796308b0 1106 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
Kojto 96:487b796308b0 1107 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Kojto 96:487b796308b0 1108 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
Kojto 120:7c328cabac7e 1109 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
Kojto 120:7c328cabac7e 1110 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
Kojto 96:487b796308b0 1111 #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
Kojto 96:487b796308b0 1112 #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
Kojto 96:487b796308b0 1113 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
Kojto 120:7c328cabac7e 1114 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
Kojto 120:7c328cabac7e 1115 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 1116 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
Kojto 96:487b796308b0 1117 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
Kojto 96:487b796308b0 1118 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto 96:487b796308b0 1119 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto 96:487b796308b0 1120 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto 96:487b796308b0 1121 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto 96:487b796308b0 1122 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto 96:487b796308b0 1123 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto 96:487b796308b0 1124 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
Kojto 96:487b796308b0 1125 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
Kojto 96:487b796308b0 1126 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
Kojto 96:487b796308b0 1127 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
Kojto 96:487b796308b0 1128 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
Kojto 96:487b796308b0 1129 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
Kojto 96:487b796308b0 1130 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 1131 #if defined(STM32F100xB) || defined (STM32F100xE)
Kojto 96:487b796308b0 1132 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto 96:487b796308b0 1133 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto 96:487b796308b0 1134 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto 96:487b796308b0 1135 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto 96:487b796308b0 1136 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
Kojto 96:487b796308b0 1137 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
Kojto 96:487b796308b0 1138 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
Kojto 96:487b796308b0 1139 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
Kojto 96:487b796308b0 1140 #endif /* STM32F100xB || STM32F100xE */
Kojto 96:487b796308b0 1141 #ifdef STM32F100xE
Kojto 96:487b796308b0 1142 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
Kojto 96:487b796308b0 1143 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
Kojto 96:487b796308b0 1144 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
Kojto 96:487b796308b0 1145 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
Kojto 96:487b796308b0 1146 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
Kojto 96:487b796308b0 1147 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
Kojto 96:487b796308b0 1148 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
Kojto 96:487b796308b0 1149 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
Kojto 96:487b796308b0 1150 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto 96:487b796308b0 1151 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto 96:487b796308b0 1152 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
Kojto 96:487b796308b0 1153 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
Kojto 96:487b796308b0 1154 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
Kojto 96:487b796308b0 1155 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
Kojto 96:487b796308b0 1156 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
Kojto 96:487b796308b0 1157 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
Kojto 96:487b796308b0 1158 #endif /* STM32F100xE */
Kojto 96:487b796308b0 1159 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 1160 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
Kojto 96:487b796308b0 1161 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
Kojto 96:487b796308b0 1162 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 1163 #if defined(STM32F101xG) || defined(STM32F103xG)
Kojto 96:487b796308b0 1164 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
Kojto 96:487b796308b0 1165 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
Kojto 96:487b796308b0 1166 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
Kojto 96:487b796308b0 1167 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
Kojto 96:487b796308b0 1168 #endif /* STM32F101xG || STM32F103xG*/
Kojto 96:487b796308b0 1169
Kojto 96:487b796308b0 1170 /**
Kojto 96:487b796308b0 1171 * @}
Kojto 96:487b796308b0 1172 */
Kojto 96:487b796308b0 1173
Kojto 96:487b796308b0 1174 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
Kojto 96:487b796308b0 1175 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 96:487b796308b0 1176 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 96:487b796308b0 1177 * is disabled and the application software has to enable this clock before
Kojto 96:487b796308b0 1178 * using it.
Kojto 96:487b796308b0 1179 * @{
Kojto 96:487b796308b0 1180 */
Kojto 96:487b796308b0 1181
Kojto 120:7c328cabac7e 1182 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
Kojto 120:7c328cabac7e 1183 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
Kojto 120:7c328cabac7e 1184 || defined(STM32F103xG)
Kojto 96:487b796308b0 1185 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1186 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1187 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto 96:487b796308b0 1188 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1189 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto 96:487b796308b0 1190 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1191 } while(0)
Kojto 96:487b796308b0 1192
Kojto 96:487b796308b0 1193 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto 96:487b796308b0 1194 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
Kojto 96:487b796308b0 1195
Kojto 120:7c328cabac7e 1196 #if defined(STM32F100xB) || defined(STM32F100xE)
Kojto 96:487b796308b0 1197 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1198 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1199 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
Kojto 96:487b796308b0 1200 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1201 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
Kojto 96:487b796308b0 1202 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1203 } while(0)
Kojto 96:487b796308b0 1204
Kojto 96:487b796308b0 1205 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1206 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1207 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
Kojto 96:487b796308b0 1208 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1209 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
Kojto 96:487b796308b0 1210 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1211 } while(0)
Kojto 96:487b796308b0 1212
Kojto 96:487b796308b0 1213 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1214 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1215 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
Kojto 96:487b796308b0 1216 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1217 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
Kojto 96:487b796308b0 1218 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1219 } while(0)
Kojto 96:487b796308b0 1220
Kojto 96:487b796308b0 1221 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
Kojto 96:487b796308b0 1222 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
Kojto 96:487b796308b0 1223 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
Kojto 96:487b796308b0 1224 #endif /* STM32F100xB || STM32F100xE */
Kojto 96:487b796308b0 1225
Kojto 120:7c328cabac7e 1226 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
Kojto 120:7c328cabac7e 1227 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
Kojto 120:7c328cabac7e 1228 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
Kojto 120:7c328cabac7e 1229 || defined(STM32F107xC)
Kojto 96:487b796308b0 1230 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1231 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1232 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
Kojto 96:487b796308b0 1233 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1234 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
Kojto 96:487b796308b0 1235 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1236 } while(0)
Kojto 96:487b796308b0 1237
Kojto 96:487b796308b0 1238 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
Kojto 96:487b796308b0 1239 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 1240
Kojto 120:7c328cabac7e 1241 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
Kojto 120:7c328cabac7e 1242 || defined(STM32F103xG)
Kojto 96:487b796308b0 1243 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1244 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1245 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
Kojto 96:487b796308b0 1246 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1247 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
Kojto 96:487b796308b0 1248 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1249 } while(0)
Kojto 96:487b796308b0 1250
Kojto 96:487b796308b0 1251 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1252 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1253 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
Kojto 96:487b796308b0 1254 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1255 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
Kojto 96:487b796308b0 1256 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1257 } while(0)
Kojto 96:487b796308b0 1258
Kojto 96:487b796308b0 1259 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
Kojto 96:487b796308b0 1260 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
Kojto 96:487b796308b0 1261 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
Kojto 96:487b796308b0 1262
Kojto 120:7c328cabac7e 1263 #if defined(STM32F103xE) || defined(STM32F103xG)
Kojto 96:487b796308b0 1264 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1265 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1266 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto 96:487b796308b0 1267 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1268 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto 96:487b796308b0 1269 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1270 } while(0)
Kojto 96:487b796308b0 1271
Kojto 96:487b796308b0 1272 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1273 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1274 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto 96:487b796308b0 1275 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1276 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto 96:487b796308b0 1277 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1278 } while(0)
Kojto 96:487b796308b0 1279
Kojto 96:487b796308b0 1280 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto 96:487b796308b0 1281 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto 96:487b796308b0 1282 #endif /* STM32F103xE || STM32F103xG */
Kojto 96:487b796308b0 1283
Kojto 120:7c328cabac7e 1284 #if defined(STM32F100xE)
Kojto 96:487b796308b0 1285 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1286 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1287 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
Kojto 96:487b796308b0 1288 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1289 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
Kojto 96:487b796308b0 1290 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1291 } while(0)
Kojto 96:487b796308b0 1292
Kojto 96:487b796308b0 1293 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1294 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1295 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
Kojto 96:487b796308b0 1296 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1297 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
Kojto 96:487b796308b0 1298 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1299 } while(0)
Kojto 96:487b796308b0 1300
Kojto 96:487b796308b0 1301 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
Kojto 96:487b796308b0 1302 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
Kojto 96:487b796308b0 1303 #endif /* STM32F100xE */
Kojto 96:487b796308b0 1304
Kojto 96:487b796308b0 1305 #if defined(STM32F101xG) || defined(STM32F103xG)
Kojto 96:487b796308b0 1306 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1307 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1308 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 96:487b796308b0 1309 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1310 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 96:487b796308b0 1311 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1312 } while(0)
Kojto 96:487b796308b0 1313
Kojto 96:487b796308b0 1314 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1315 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1316 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto 96:487b796308b0 1317 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1318 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto 96:487b796308b0 1319 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1320 } while(0)
Kojto 96:487b796308b0 1321
Kojto 96:487b796308b0 1322 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
Kojto 96:487b796308b0 1323 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1324 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 96:487b796308b0 1325 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 1326 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 96:487b796308b0 1327 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1328 } while(0)
Kojto 96:487b796308b0 1329
Kojto 96:487b796308b0 1330 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Kojto 96:487b796308b0 1331 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto 96:487b796308b0 1332 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Kojto 96:487b796308b0 1333 #endif /* STM32F101xG || STM32F103xG */
Kojto 96:487b796308b0 1334
Kojto 96:487b796308b0 1335 /**
Kojto 96:487b796308b0 1336 * @}
Kojto 96:487b796308b0 1337 */
Kojto 96:487b796308b0 1338
Kojto 96:487b796308b0 1339 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto 96:487b796308b0 1340 * @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto 96:487b796308b0 1341 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 96:487b796308b0 1342 * is disabled and the application software has to enable this clock before
Kojto 96:487b796308b0 1343 * using it.
Kojto 96:487b796308b0 1344 * @{
Kojto 96:487b796308b0 1345 */
Kojto 96:487b796308b0 1346
Kojto 120:7c328cabac7e 1347 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
Kojto 120:7c328cabac7e 1348 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
Kojto 120:7c328cabac7e 1349 || defined(STM32F103xG)
Kojto 96:487b796308b0 1350 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
Kojto 96:487b796308b0 1351 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
Kojto 96:487b796308b0 1352 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
Kojto 120:7c328cabac7e 1353 #if defined(STM32F100xB) || defined(STM32F100xE)
Kojto 96:487b796308b0 1354 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
Kojto 96:487b796308b0 1355 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
Kojto 96:487b796308b0 1356 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
Kojto 96:487b796308b0 1357 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
Kojto 96:487b796308b0 1358 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
Kojto 96:487b796308b0 1359 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
Kojto 96:487b796308b0 1360 #endif /* STM32F100xB || STM32F100xE */
Kojto 120:7c328cabac7e 1361 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
Kojto 120:7c328cabac7e 1362 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
Kojto 120:7c328cabac7e 1363 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
Kojto 120:7c328cabac7e 1364 || defined(STM32F107xC)
Kojto 96:487b796308b0 1365 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
Kojto 96:487b796308b0 1366 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
Kojto 96:487b796308b0 1367 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
Kojto 120:7c328cabac7e 1368 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
Kojto 120:7c328cabac7e 1369 || defined(STM32F103xG)
Kojto 96:487b796308b0 1370 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
Kojto 96:487b796308b0 1371 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
Kojto 96:487b796308b0 1372 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
Kojto 96:487b796308b0 1373 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
Kojto 96:487b796308b0 1374 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
Kojto 120:7c328cabac7e 1375 #if defined(STM32F103xE) || defined(STM32F103xG)
Kojto 96:487b796308b0 1376 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
Kojto 96:487b796308b0 1377 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
Kojto 96:487b796308b0 1378 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
Kojto 96:487b796308b0 1379 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
Kojto 96:487b796308b0 1380 #endif /* STM32F103xE || STM32F103xG */
Kojto 120:7c328cabac7e 1381 #if defined(STM32F100xE)
Kojto 96:487b796308b0 1382 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
Kojto 96:487b796308b0 1383 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
Kojto 96:487b796308b0 1384 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
Kojto 96:487b796308b0 1385 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
Kojto 96:487b796308b0 1386 #endif /* STM32F100xE */
Kojto 96:487b796308b0 1387 #if defined(STM32F101xG) || defined(STM32F103xG)
Kojto 96:487b796308b0 1388 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
Kojto 96:487b796308b0 1389 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
Kojto 96:487b796308b0 1390 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
Kojto 96:487b796308b0 1391 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
Kojto 96:487b796308b0 1392 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
Kojto 96:487b796308b0 1393 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
Kojto 96:487b796308b0 1394 #endif /* STM32F101xG || STM32F103xG */
Kojto 96:487b796308b0 1395
Kojto 96:487b796308b0 1396 /**
Kojto 96:487b796308b0 1397 * @}
Kojto 96:487b796308b0 1398 */
Kojto 96:487b796308b0 1399
Kojto 96:487b796308b0 1400 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 1401 /** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release
Kojto 96:487b796308b0 1402 * @brief Force or release AHB peripheral reset.
Kojto 96:487b796308b0 1403 * @{
Kojto 96:487b796308b0 1404 */
Kojto 120:7c328cabac7e 1405 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
Kojto 96:487b796308b0 1406 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST))
Kojto 96:487b796308b0 1407 #if defined(STM32F107xC)
Kojto 96:487b796308b0 1408 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST))
Kojto 96:487b796308b0 1409 #endif /* STM32F107xC */
Kojto 96:487b796308b0 1410
Kojto 96:487b796308b0 1411 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
Kojto 96:487b796308b0 1412 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))
Kojto 96:487b796308b0 1413 #if defined(STM32F107xC)
Kojto 96:487b796308b0 1414 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))
Kojto 96:487b796308b0 1415 #endif /* STM32F107xC */
Kojto 96:487b796308b0 1416
Kojto 96:487b796308b0 1417 /**
Kojto 96:487b796308b0 1418 * @}
Kojto 96:487b796308b0 1419 */
Kojto 96:487b796308b0 1420 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 1421
Kojto 96:487b796308b0 1422 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto 96:487b796308b0 1423 * @brief Force or release APB1 peripheral reset.
Kojto 96:487b796308b0 1424 * @{
Kojto 96:487b796308b0 1425 */
Kojto 96:487b796308b0 1426
Kojto 120:7c328cabac7e 1427 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
Kojto 120:7c328cabac7e 1428 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
Kojto 96:487b796308b0 1429 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
Kojto 96:487b796308b0 1430
Kojto 96:487b796308b0 1431 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto 96:487b796308b0 1432 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 1433
Kojto 120:7c328cabac7e 1434 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
Kojto 120:7c328cabac7e 1435 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
Kojto 120:7c328cabac7e 1436 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
Kojto 120:7c328cabac7e 1437 || defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 1438 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
Kojto 96:487b796308b0 1439 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 96:487b796308b0 1440 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
Kojto 96:487b796308b0 1441 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 96:487b796308b0 1442
Kojto 96:487b796308b0 1443 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto 96:487b796308b0 1444 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 96:487b796308b0 1445 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto 96:487b796308b0 1446 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 96:487b796308b0 1447 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 1448
Kojto 120:7c328cabac7e 1449 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
Kojto 120:7c328cabac7e 1450 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
Kojto 96:487b796308b0 1451 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
Kojto 96:487b796308b0 1452 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
Kojto 96:487b796308b0 1453 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
Kojto 96:487b796308b0 1454
Kojto 120:7c328cabac7e 1455 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
Kojto 120:7c328cabac7e 1456 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 1457 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
Kojto 96:487b796308b0 1458 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
Kojto 96:487b796308b0 1459 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
Kojto 96:487b796308b0 1460 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
Kojto 96:487b796308b0 1461 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
Kojto 96:487b796308b0 1462 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
Kojto 96:487b796308b0 1463 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
Kojto 96:487b796308b0 1464
Kojto 96:487b796308b0 1465 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto 96:487b796308b0 1466 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto 96:487b796308b0 1467 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto 96:487b796308b0 1468 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto 96:487b796308b0 1469 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto 96:487b796308b0 1470 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto 96:487b796308b0 1471 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto 96:487b796308b0 1472 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 1473
Kojto 96:487b796308b0 1474 #if defined(STM32F100xB) || defined (STM32F100xE)
Kojto 96:487b796308b0 1475 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
Kojto 96:487b796308b0 1476 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
Kojto 96:487b796308b0 1477 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
Kojto 96:487b796308b0 1478 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
Kojto 96:487b796308b0 1479
Kojto 96:487b796308b0 1480 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto 96:487b796308b0 1481 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto 96:487b796308b0 1482 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto 96:487b796308b0 1483 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto 96:487b796308b0 1484 #endif /* STM32F100xB || STM32F100xE */
Kojto 96:487b796308b0 1485
Kojto 96:487b796308b0 1486 #if defined (STM32F100xE)
Kojto 96:487b796308b0 1487 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
Kojto 96:487b796308b0 1488 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
Kojto 96:487b796308b0 1489 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
Kojto 96:487b796308b0 1490 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
Kojto 96:487b796308b0 1491 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
Kojto 96:487b796308b0 1492 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
Kojto 96:487b796308b0 1493 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
Kojto 96:487b796308b0 1494
Kojto 96:487b796308b0 1495 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto 96:487b796308b0 1496 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto 96:487b796308b0 1497 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto 96:487b796308b0 1498 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto 96:487b796308b0 1499 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto 96:487b796308b0 1500 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto 96:487b796308b0 1501 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto 96:487b796308b0 1502 #endif /* STM32F100xE */
Kojto 96:487b796308b0 1503
Kojto 96:487b796308b0 1504 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 1505 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
Kojto 96:487b796308b0 1506
Kojto 96:487b796308b0 1507 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto 96:487b796308b0 1508 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 1509
Kojto 96:487b796308b0 1510 #if defined(STM32F101xG) || defined(STM32F103xG)
Kojto 96:487b796308b0 1511 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
Kojto 96:487b796308b0 1512 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
Kojto 96:487b796308b0 1513 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
Kojto 96:487b796308b0 1514
Kojto 96:487b796308b0 1515 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto 96:487b796308b0 1516 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto 96:487b796308b0 1517 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto 96:487b796308b0 1518 #endif /* STM32F101xG || STM32F103xG */
Kojto 96:487b796308b0 1519
Kojto 96:487b796308b0 1520 /**
Kojto 96:487b796308b0 1521 * @}
Kojto 96:487b796308b0 1522 */
Kojto 96:487b796308b0 1523
Kojto 96:487b796308b0 1524 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto 96:487b796308b0 1525 * @brief Force or release APB2 peripheral reset.
Kojto 96:487b796308b0 1526 * @{
Kojto 96:487b796308b0 1527 */
Kojto 96:487b796308b0 1528
Kojto 120:7c328cabac7e 1529 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
Kojto 120:7c328cabac7e 1530 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
Kojto 120:7c328cabac7e 1531 || defined(STM32F103xG)
Kojto 96:487b796308b0 1532 #define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
Kojto 96:487b796308b0 1533
Kojto 96:487b796308b0 1534 #define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
Kojto 96:487b796308b0 1535 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
Kojto 96:487b796308b0 1536
Kojto 120:7c328cabac7e 1537 #if defined(STM32F100xB) || defined(STM32F100xE)
Kojto 96:487b796308b0 1538 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
Kojto 96:487b796308b0 1539 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
Kojto 96:487b796308b0 1540 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
Kojto 96:487b796308b0 1541
Kojto 96:487b796308b0 1542 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
Kojto 96:487b796308b0 1543 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
Kojto 96:487b796308b0 1544 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
Kojto 96:487b796308b0 1545 #endif /* STM32F100xB || STM32F100xE */
Kojto 96:487b796308b0 1546
Kojto 120:7c328cabac7e 1547 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
Kojto 120:7c328cabac7e 1548 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
Kojto 120:7c328cabac7e 1549 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
Kojto 120:7c328cabac7e 1550 || defined(STM32F107xC)
Kojto 96:487b796308b0 1551 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
Kojto 96:487b796308b0 1552
Kojto 96:487b796308b0 1553 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
Kojto 96:487b796308b0 1554 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 1555
Kojto 120:7c328cabac7e 1556 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
Kojto 120:7c328cabac7e 1557 || defined(STM32F103xG)
Kojto 96:487b796308b0 1558 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
Kojto 96:487b796308b0 1559 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
Kojto 96:487b796308b0 1560
Kojto 96:487b796308b0 1561 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
Kojto 96:487b796308b0 1562 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
Kojto 96:487b796308b0 1563 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
Kojto 96:487b796308b0 1564
Kojto 120:7c328cabac7e 1565 #if defined(STM32F103xE) || defined(STM32F103xG)
Kojto 96:487b796308b0 1566 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
Kojto 96:487b796308b0 1567 #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))
Kojto 96:487b796308b0 1568
Kojto 96:487b796308b0 1569 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto 96:487b796308b0 1570 #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
Kojto 96:487b796308b0 1571 #endif /* STM32F103xE || STM32F103xG */
Kojto 96:487b796308b0 1572
Kojto 120:7c328cabac7e 1573 #if defined(STM32F100xE)
Kojto 96:487b796308b0 1574 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
Kojto 96:487b796308b0 1575 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
Kojto 96:487b796308b0 1576
Kojto 96:487b796308b0 1577 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
Kojto 96:487b796308b0 1578 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
Kojto 96:487b796308b0 1579 #endif /* STM32F100xE */
Kojto 96:487b796308b0 1580
Kojto 96:487b796308b0 1581 #if defined(STM32F101xG) || defined(STM32F103xG)
Kojto 96:487b796308b0 1582 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
Kojto 96:487b796308b0 1583 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
Kojto 96:487b796308b0 1584 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
Kojto 96:487b796308b0 1585
Kojto 96:487b796308b0 1586 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Kojto 96:487b796308b0 1587 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto 96:487b796308b0 1588 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Kojto 96:487b796308b0 1589 #endif /* STM32F101xG || STM32F103xG*/
Kojto 96:487b796308b0 1590
Kojto 96:487b796308b0 1591 /**
Kojto 96:487b796308b0 1592 * @}
Kojto 96:487b796308b0 1593 */
Kojto 96:487b796308b0 1594
Kojto 96:487b796308b0 1595 /** @defgroup RCCEx_HSE_Configuration HSE Configuration
Kojto 96:487b796308b0 1596 * @{
Kojto 96:487b796308b0 1597 */
Kojto 96:487b796308b0 1598
Kojto 120:7c328cabac7e 1599 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
Kojto 120:7c328cabac7e 1600 || defined(STM32F100xE)
Kojto 96:487b796308b0 1601 /**
Kojto 96:487b796308b0 1602 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
Kojto 96:487b796308b0 1603 * @note Predivision factor can not be changed if PLL is used as system clock
Kojto 96:487b796308b0 1604 * In this case, you have to select another source of the system clock, disable the PLL and
Kojto 96:487b796308b0 1605 * then change the HSE predivision factor.
Kojto 120:7c328cabac7e 1606 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
Kojto 96:487b796308b0 1607 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
Kojto 96:487b796308b0 1608 */
Kojto 96:487b796308b0 1609 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))
Kojto 96:487b796308b0 1610 #else
Kojto 96:487b796308b0 1611 /**
Kojto 96:487b796308b0 1612 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
Kojto 96:487b796308b0 1613 * @note Predivision factor can not be changed if PLL is used as system clock
Kojto 96:487b796308b0 1614 * In this case, you have to select another source of the system clock, disable the PLL and
Kojto 96:487b796308b0 1615 * then change the HSE predivision factor.
Kojto 120:7c328cabac7e 1616 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
Kojto 96:487b796308b0 1617 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.
Kojto 96:487b796308b0 1618 */
Kojto 96:487b796308b0 1619 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
Kojto 96:487b796308b0 1620 MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
Kojto 96:487b796308b0 1621
Kojto 96:487b796308b0 1622 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 1623
Kojto 120:7c328cabac7e 1624 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
Kojto 120:7c328cabac7e 1625 || defined(STM32F100xE)
Kojto 96:487b796308b0 1626 /**
Kojto 96:487b796308b0 1627 * @brief Macro to get prediv1 factor for PLL.
Kojto 96:487b796308b0 1628 */
Kojto 96:487b796308b0 1629 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
Kojto 96:487b796308b0 1630
Kojto 96:487b796308b0 1631 #else
Kojto 96:487b796308b0 1632 /**
Kojto 96:487b796308b0 1633 * @brief Macro to get prediv1 factor for PLL.
Kojto 96:487b796308b0 1634 */
Kojto 96:487b796308b0 1635 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
Kojto 96:487b796308b0 1636
Kojto 96:487b796308b0 1637 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
Kojto 96:487b796308b0 1638
Kojto 96:487b796308b0 1639 /**
Kojto 96:487b796308b0 1640 * @}
Kojto 96:487b796308b0 1641 */
Kojto 96:487b796308b0 1642
Kojto 96:487b796308b0 1643 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 1644 /** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration
Kojto 96:487b796308b0 1645 * @{
Kojto 96:487b796308b0 1646 */
Kojto 96:487b796308b0 1647
Kojto 96:487b796308b0 1648 /** @brief Macros to enable the main PLLI2S.
Kojto 96:487b796308b0 1649 * @note After enabling the main PLLI2S, the application software should wait on
Kojto 96:487b796308b0 1650 * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can
Kojto 96:487b796308b0 1651 * be used as system clock source.
Kojto 96:487b796308b0 1652 * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
Kojto 96:487b796308b0 1653 */
Kojto 96:487b796308b0 1654 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
Kojto 96:487b796308b0 1655
Kojto 96:487b796308b0 1656 /** @brief Macros to disable the main PLLI2S.
Kojto 96:487b796308b0 1657 * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
Kojto 96:487b796308b0 1658 */
Kojto 96:487b796308b0 1659 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
Kojto 96:487b796308b0 1660
Kojto 96:487b796308b0 1661 /** @brief macros to configure the main PLLI2S multiplication factor.
Kojto 96:487b796308b0 1662 * @note This function must be used only when the main PLLI2S is disabled.
Kojto 96:487b796308b0 1663 *
Kojto 120:7c328cabac7e 1664 * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock
Kojto 96:487b796308b0 1665 * This parameter can be one of the following values:
Kojto 120:7c328cabac7e 1666 * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8
Kojto 120:7c328cabac7e 1667 * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9
Kojto 120:7c328cabac7e 1668 * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10
Kojto 120:7c328cabac7e 1669 * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11
Kojto 120:7c328cabac7e 1670 * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12
Kojto 120:7c328cabac7e 1671 * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13
Kojto 120:7c328cabac7e 1672 * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14
Kojto 120:7c328cabac7e 1673 * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16
Kojto 120:7c328cabac7e 1674 * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20
Kojto 96:487b796308b0 1675 *
Kojto 96:487b796308b0 1676 */
Kojto 96:487b796308b0 1677 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\
Kojto 96:487b796308b0 1678 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))
Kojto 96:487b796308b0 1679
Kojto 96:487b796308b0 1680 /**
Kojto 96:487b796308b0 1681 * @}
Kojto 96:487b796308b0 1682 */
Kojto 96:487b796308b0 1683
Kojto 96:487b796308b0 1684 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 1685
Kojto 96:487b796308b0 1686 /** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration
Kojto 96:487b796308b0 1687 * @brief Macros to configure clock source of different peripherals.
Kojto 96:487b796308b0 1688 * @{
Kojto 96:487b796308b0 1689 */
Kojto 96:487b796308b0 1690
Kojto 120:7c328cabac7e 1691 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
Kojto 120:7c328cabac7e 1692 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
Kojto 96:487b796308b0 1693 /** @brief Macro to configure the USB clock.
Kojto 120:7c328cabac7e 1694 * @param __USBCLKSOURCE__ specifies the USB clock source.
Kojto 96:487b796308b0 1695 * This parameter can be one of the following values:
Kojto 120:7c328cabac7e 1696 * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
Kojto 120:7c328cabac7e 1697 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
Kojto 96:487b796308b0 1698 */
Kojto 96:487b796308b0 1699 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
Kojto 96:487b796308b0 1700 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
Kojto 96:487b796308b0 1701
Kojto 96:487b796308b0 1702 /** @brief Macro to get the USB clock (USBCLK).
Kojto 96:487b796308b0 1703 * @retval The clock source can be one of the following values:
Kojto 120:7c328cabac7e 1704 * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
Kojto 120:7c328cabac7e 1705 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
Kojto 96:487b796308b0 1706 */
Kojto 96:487b796308b0 1707 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
Kojto 96:487b796308b0 1708
Kojto 96:487b796308b0 1709 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
Kojto 96:487b796308b0 1710
Kojto 96:487b796308b0 1711 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 1712
Kojto 96:487b796308b0 1713 /** @brief Macro to configure the USB OTSclock.
Kojto 120:7c328cabac7e 1714 * @param __USBCLKSOURCE__ specifies the USB clock source.
Kojto 96:487b796308b0 1715 * This parameter can be one of the following values:
Kojto 120:7c328cabac7e 1716 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
Kojto 120:7c328cabac7e 1717 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
Kojto 96:487b796308b0 1718 */
Kojto 96:487b796308b0 1719 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
Kojto 96:487b796308b0 1720 MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))
Kojto 96:487b796308b0 1721
Kojto 96:487b796308b0 1722 /** @brief Macro to get the USB clock (USBCLK).
Kojto 96:487b796308b0 1723 * @retval The clock source can be one of the following values:
Kojto 120:7c328cabac7e 1724 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
Kojto 120:7c328cabac7e 1725 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
Kojto 96:487b796308b0 1726 */
Kojto 96:487b796308b0 1727 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))
Kojto 96:487b796308b0 1728
Kojto 96:487b796308b0 1729 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 1730
Kojto 96:487b796308b0 1731 /** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices).
Kojto 120:7c328cabac7e 1732 * @param __ADCCLKSOURCE__ specifies the ADC clock source.
Kojto 96:487b796308b0 1733 * This parameter can be one of the following values:
Kojto 120:7c328cabac7e 1734 * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
Kojto 120:7c328cabac7e 1735 * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
Kojto 120:7c328cabac7e 1736 * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
Kojto 120:7c328cabac7e 1737 * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
Kojto 96:487b796308b0 1738 */
Kojto 96:487b796308b0 1739 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \
Kojto 96:487b796308b0 1740 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
Kojto 96:487b796308b0 1741
Kojto 96:487b796308b0 1742 /** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).
Kojto 96:487b796308b0 1743 * @retval The clock source can be one of the following values:
Kojto 120:7c328cabac7e 1744 * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
Kojto 120:7c328cabac7e 1745 * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
Kojto 120:7c328cabac7e 1746 * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
Kojto 120:7c328cabac7e 1747 * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
Kojto 96:487b796308b0 1748 */
Kojto 96:487b796308b0 1749 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
Kojto 96:487b796308b0 1750
Kojto 96:487b796308b0 1751 /**
Kojto 96:487b796308b0 1752 * @}
Kojto 96:487b796308b0 1753 */
Kojto 96:487b796308b0 1754
Kojto 96:487b796308b0 1755 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 1756
Kojto 96:487b796308b0 1757 /** @addtogroup RCCEx_HSE_Configuration
Kojto 96:487b796308b0 1758 * @{
Kojto 96:487b796308b0 1759 */
Kojto 96:487b796308b0 1760
Kojto 96:487b796308b0 1761 /**
Kojto 96:487b796308b0 1762 * @brief Macro to configure the PLL2 & PLLI2S Predivision factor.
Kojto 96:487b796308b0 1763 * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock
Kojto 96:487b796308b0 1764 * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and
Kojto 96:487b796308b0 1765 * then change the PREDIV2 factor.
Kojto 120:7c328cabac7e 1766 * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S.
Kojto 96:487b796308b0 1767 * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16.
Kojto 96:487b796308b0 1768 */
Kojto 96:487b796308b0 1769 #define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \
Kojto 96:487b796308b0 1770 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))
Kojto 96:487b796308b0 1771
Kojto 96:487b796308b0 1772 /**
Kojto 96:487b796308b0 1773 * @brief Macro to get prediv2 factor for PLL2 & PLL3.
Kojto 96:487b796308b0 1774 */
Kojto 96:487b796308b0 1775 #define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)
Kojto 96:487b796308b0 1776
Kojto 96:487b796308b0 1777 /**
Kojto 96:487b796308b0 1778 * @}
Kojto 96:487b796308b0 1779 */
Kojto 96:487b796308b0 1780
Kojto 96:487b796308b0 1781 /** @addtogroup RCCEx_PLLI2S_Configuration
Kojto 96:487b796308b0 1782 * @{
Kojto 96:487b796308b0 1783 */
Kojto 96:487b796308b0 1784
Kojto 96:487b796308b0 1785 /** @brief Macros to enable the main PLL2.
Kojto 96:487b796308b0 1786 * @note After enabling the main PLL2, the application software should wait on
Kojto 96:487b796308b0 1787 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can
Kojto 96:487b796308b0 1788 * be used as system clock source.
Kojto 96:487b796308b0 1789 * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
Kojto 96:487b796308b0 1790 */
Kojto 120:7c328cabac7e 1791 #define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE)
Kojto 96:487b796308b0 1792
Kojto 96:487b796308b0 1793 /** @brief Macros to disable the main PLL2.
Kojto 96:487b796308b0 1794 * @note The main PLL2 can not be disabled if it is used indirectly as system clock source
Kojto 96:487b796308b0 1795 * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
Kojto 96:487b796308b0 1796 */
Kojto 120:7c328cabac7e 1797 #define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE)
Kojto 96:487b796308b0 1798
Kojto 96:487b796308b0 1799 /** @brief macros to configure the main PLL2 multiplication factor.
Kojto 96:487b796308b0 1800 * @note This function must be used only when the main PLL2 is disabled.
Kojto 96:487b796308b0 1801 *
Kojto 120:7c328cabac7e 1802 * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock
Kojto 96:487b796308b0 1803 * This parameter can be one of the following values:
Kojto 120:7c328cabac7e 1804 * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8
Kojto 120:7c328cabac7e 1805 * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9
Kojto 120:7c328cabac7e 1806 * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10
Kojto 120:7c328cabac7e 1807 * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11
Kojto 120:7c328cabac7e 1808 * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12
Kojto 120:7c328cabac7e 1809 * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13
Kojto 120:7c328cabac7e 1810 * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14
Kojto 120:7c328cabac7e 1811 * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16
Kojto 120:7c328cabac7e 1812 * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20
Kojto 96:487b796308b0 1813 *
Kojto 96:487b796308b0 1814 */
Kojto 96:487b796308b0 1815 #define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\
Kojto 96:487b796308b0 1816 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))
Kojto 96:487b796308b0 1817
Kojto 96:487b796308b0 1818 /**
Kojto 96:487b796308b0 1819 * @}
Kojto 96:487b796308b0 1820 */
Kojto 96:487b796308b0 1821
Kojto 96:487b796308b0 1822 /** @defgroup RCCEx_I2S_Configuration I2S Configuration
Kojto 96:487b796308b0 1823 * @brief Macros to configure clock source of I2S peripherals.
Kojto 96:487b796308b0 1824 * @{
Kojto 96:487b796308b0 1825 */
Kojto 96:487b796308b0 1826
Kojto 96:487b796308b0 1827 /** @brief Macro to configure the I2S2 clock.
Kojto 120:7c328cabac7e 1828 * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source.
Kojto 96:487b796308b0 1829 * This parameter can be one of the following values:
Kojto 120:7c328cabac7e 1830 * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
Kojto 120:7c328cabac7e 1831 * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
Kojto 96:487b796308b0 1832 */
Kojto 96:487b796308b0 1833 #define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \
Kojto 96:487b796308b0 1834 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))
Kojto 96:487b796308b0 1835
Kojto 96:487b796308b0 1836 /** @brief Macro to get the I2S2 clock (I2S2CLK).
Kojto 96:487b796308b0 1837 * @retval The clock source can be one of the following values:
Kojto 120:7c328cabac7e 1838 * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
Kojto 120:7c328cabac7e 1839 * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
Kojto 96:487b796308b0 1840 */
Kojto 96:487b796308b0 1841 #define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))
Kojto 96:487b796308b0 1842
Kojto 96:487b796308b0 1843 /** @brief Macro to configure the I2S3 clock.
Kojto 120:7c328cabac7e 1844 * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source.
Kojto 96:487b796308b0 1845 * This parameter can be one of the following values:
Kojto 120:7c328cabac7e 1846 * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
Kojto 120:7c328cabac7e 1847 * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
Kojto 96:487b796308b0 1848 */
Kojto 96:487b796308b0 1849 #define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \
Kojto 96:487b796308b0 1850 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))
Kojto 96:487b796308b0 1851
Kojto 96:487b796308b0 1852 /** @brief Macro to get the I2S3 clock (I2S3CLK).
Kojto 96:487b796308b0 1853 * @retval The clock source can be one of the following values:
Kojto 120:7c328cabac7e 1854 * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
Kojto 120:7c328cabac7e 1855 * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
Kojto 96:487b796308b0 1856 */
Kojto 96:487b796308b0 1857 #define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))
Kojto 96:487b796308b0 1858
Kojto 96:487b796308b0 1859 /**
Kojto 96:487b796308b0 1860 * @}
Kojto 96:487b796308b0 1861 */
Kojto 96:487b796308b0 1862
Kojto 96:487b796308b0 1863 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 1864 /**
Kojto 96:487b796308b0 1865 * @}
Kojto 96:487b796308b0 1866 */
Kojto 96:487b796308b0 1867
Kojto 96:487b796308b0 1868 /* Exported functions --------------------------------------------------------*/
Kojto 96:487b796308b0 1869 /** @addtogroup RCCEx_Exported_Functions
Kojto 96:487b796308b0 1870 * @{
Kojto 96:487b796308b0 1871 */
Kojto 96:487b796308b0 1872
Kojto 96:487b796308b0 1873 /** @addtogroup RCCEx_Exported_Functions_Group1
Kojto 96:487b796308b0 1874 * @{
Kojto 96:487b796308b0 1875 */
Kojto 96:487b796308b0 1876
Kojto 96:487b796308b0 1877 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 96:487b796308b0 1878 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 96:487b796308b0 1879 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto 96:487b796308b0 1880
Kojto 96:487b796308b0 1881 /**
Kojto 96:487b796308b0 1882 * @}
Kojto 96:487b796308b0 1883 */
Kojto 96:487b796308b0 1884
Kojto 96:487b796308b0 1885 #if defined(STM32F105xC) || defined(STM32F107xC)
Kojto 96:487b796308b0 1886 /** @addtogroup RCCEx_Exported_Functions_Group2
Kojto 96:487b796308b0 1887 * @{
Kojto 96:487b796308b0 1888 */
Kojto 96:487b796308b0 1889 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
Kojto 96:487b796308b0 1890 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
Kojto 96:487b796308b0 1891
Kojto 96:487b796308b0 1892 /**
Kojto 96:487b796308b0 1893 * @}
Kojto 96:487b796308b0 1894 */
Kojto 96:487b796308b0 1895
Kojto 96:487b796308b0 1896 /** @addtogroup RCCEx_Exported_Functions_Group3
Kojto 96:487b796308b0 1897 * @{
Kojto 96:487b796308b0 1898 */
Kojto 96:487b796308b0 1899 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);
Kojto 96:487b796308b0 1900 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
Kojto 96:487b796308b0 1901
Kojto 96:487b796308b0 1902 /**
Kojto 96:487b796308b0 1903 * @}
Kojto 96:487b796308b0 1904 */
Kojto 96:487b796308b0 1905 #endif /* STM32F105xC || STM32F107xC */
Kojto 96:487b796308b0 1906
Kojto 96:487b796308b0 1907 /**
Kojto 96:487b796308b0 1908 * @}
Kojto 96:487b796308b0 1909 */
Kojto 96:487b796308b0 1910
Kojto 96:487b796308b0 1911 /**
Kojto 96:487b796308b0 1912 * @}
Kojto 96:487b796308b0 1913 */
Kojto 96:487b796308b0 1914
Kojto 96:487b796308b0 1915 /**
Kojto 96:487b796308b0 1916 * @}
Kojto 96:487b796308b0 1917 */
Kojto 96:487b796308b0 1918
Kojto 96:487b796308b0 1919 #ifdef __cplusplus
Kojto 96:487b796308b0 1920 }
Kojto 96:487b796308b0 1921 #endif
Kojto 96:487b796308b0 1922
Kojto 96:487b796308b0 1923 #endif /* __STM32F1xx_HAL_RCC_EX_H */
Kojto 96:487b796308b0 1924
Kojto 96:487b796308b0 1925 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 96:487b796308b0 1926