Graham Cantin / MODDMA

trying to make telnetserver repo public

Fork of MODDMA by Andy K

DATALUTS.cpp@16:cb10aec6feb1, 2011-03-14 (annotated)

Committer:
AjK
Date:
Mon Mar 14 13:51:38 2011 +0000
Revision:
16:cb10aec6feb1
Parent:
8:cb4d323ce6fd 
1.12 See ChangeLoc.c

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AjK 8:cb4d323ce6fd 1 /*
AjK 8:cb4d323ce6fd 2 Copyright (c) 2010 Andy Kirkham
AjK 8:cb4d323ce6fd 3
AjK 8:cb4d323ce6fd 4 Permission is hereby granted, free of charge, to any person obtaining a copy
AjK 8:cb4d323ce6fd 5 of this software and associated documentation files (the "Software"), to deal
AjK 8:cb4d323ce6fd 6 in the Software without restriction, including without limitation the rights
AjK 8:cb4d323ce6fd 7 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
AjK 8:cb4d323ce6fd 8 copies of the Software, and to permit persons to whom the Software is
AjK 8:cb4d323ce6fd 9 furnished to do so, subject to the following conditions:
AjK 8:cb4d323ce6fd 10
AjK 8:cb4d323ce6fd 11 The above copyright notice and this permission notice shall be included in
AjK 8:cb4d323ce6fd 12 all copies or substantial portions of the Software.
AjK 8:cb4d323ce6fd 13
AjK 8:cb4d323ce6fd 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
AjK 8:cb4d323ce6fd 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
AjK 8:cb4d323ce6fd 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AjK 8:cb4d323ce6fd 17 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
AjK 8:cb4d323ce6fd 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
AjK 8:cb4d323ce6fd 19 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
AjK 8:cb4d323ce6fd 20 THE SOFTWARE.
AjK 8:cb4d323ce6fd 21 */
AjK 8:cb4d323ce6fd 22
AjK 8:cb4d323ce6fd 23 #include "MODDMA.h"
AjK 8:cb4d323ce6fd 24
AjK 8:cb4d323ce6fd 25 #ifndef MBED_H
AjK 8:cb4d323ce6fd 26 #include "mbed.h"
AjK 8:cb4d323ce6fd 27 #endif
AjK 8:cb4d323ce6fd 28
AjK 8:cb4d323ce6fd 29 #ifndef MODDMA_CONFIG_H
AjK 8:cb4d323ce6fd 30 #include "CONFIG.h"
AjK 8:cb4d323ce6fd 31 #endif
AjK 8:cb4d323ce6fd 32
AjK 8:cb4d323ce6fd 33 namespace AjK {
AjK 8:cb4d323ce6fd 34
AjK 8:cb4d323ce6fd 35 uint32_t
AjK 8:cb4d323ce6fd 36 MODDMA::LUTPerAddr(int n)
AjK 8:cb4d323ce6fd 37 {
AjK 8:cb4d323ce6fd 38 const uint32_t lut[] = {
AjK 8:cb4d323ce6fd 39 (uint32_t)&LPC_SSP0->DR // SSP0 Tx
AjK 8:cb4d323ce6fd 40 , (uint32_t)&LPC_SSP0->DR // SSP0 Rx
AjK 8:cb4d323ce6fd 41 , (uint32_t)&LPC_SSP1->DR // SSP1 Tx
AjK 8:cb4d323ce6fd 42 , (uint32_t)&LPC_SSP1->DR // SSP1 Rx
AjK 8:cb4d323ce6fd 43 , (uint32_t)&LPC_ADC->ADGDR // ADC
AjK 8:cb4d323ce6fd 44 , (uint32_t)&LPC_I2S->I2STXFIFO // I2S Tx
AjK 8:cb4d323ce6fd 45 , (uint32_t)&LPC_I2S->I2SRXFIFO // I2S Rx
AjK 8:cb4d323ce6fd 46 , (uint32_t)&LPC_DAC->DACR // DAC
AjK 8:cb4d323ce6fd 47 , (uint32_t)&LPC_UART0->THR // UART0 Tx
AjK 8:cb4d323ce6fd 48 , (uint32_t)&LPC_UART0->RBR // UART0 Rx
AjK 8:cb4d323ce6fd 49 , (uint32_t)&LPC_UART1->THR // UART1 Tx
AjK 8:cb4d323ce6fd 50 , (uint32_t)&LPC_UART1->RBR // UART1 Rx
AjK 8:cb4d323ce6fd 51 , (uint32_t)&LPC_UART2->THR // UART2 Tx
AjK 8:cb4d323ce6fd 52 , (uint32_t)&LPC_UART2->RBR // UART2 Rx
AjK 8:cb4d323ce6fd 53 , (uint32_t)&LPC_UART3->THR // UART3 Tx
AjK 8:cb4d323ce6fd 54 , (uint32_t)&LPC_UART3->RBR // UART3 Rx
AjK 8:cb4d323ce6fd 55 , (uint32_t)&LPC_TIM0->MR0 // MAT0.0
AjK 8:cb4d323ce6fd 56 , (uint32_t)&LPC_TIM0->MR1 // MAT0.1
AjK 8:cb4d323ce6fd 57 , (uint32_t)&LPC_TIM1->MR0 // MAT1.0
AjK 8:cb4d323ce6fd 58 , (uint32_t)&LPC_TIM1->MR1 // MAT1.1
AjK 8:cb4d323ce6fd 59 , (uint32_t)&LPC_TIM2->MR0 // MAT2.0
AjK 8:cb4d323ce6fd 60 , (uint32_t)&LPC_TIM2->MR1 // MAT2.1
AjK 8:cb4d323ce6fd 61 , (uint32_t)&LPC_TIM3->MR0 // MAT3.0
AjK 8:cb4d323ce6fd 62 , (uint32_t)&LPC_TIM3->MR1 // MAT3.1
AjK 8:cb4d323ce6fd 63 };
AjK 8:cb4d323ce6fd 64 return lut[n & 0xFF];
AjK 8:cb4d323ce6fd 65 }
AjK 8:cb4d323ce6fd 66
AjK 8:cb4d323ce6fd 67 uint32_t
AjK 8:cb4d323ce6fd 68 MODDMA::Channel_p(int channel)
AjK 8:cb4d323ce6fd 69 {
AjK 8:cb4d323ce6fd 70 const uint32_t lut[] = {
AjK 8:cb4d323ce6fd 71 (uint32_t)LPC_GPDMACH0
AjK 8:cb4d323ce6fd 72 , (uint32_t)LPC_GPDMACH1
AjK 8:cb4d323ce6fd 73 , (uint32_t)LPC_GPDMACH2
AjK 8:cb4d323ce6fd 74 , (uint32_t)LPC_GPDMACH3
AjK 8:cb4d323ce6fd 75 , (uint32_t)LPC_GPDMACH4
AjK 8:cb4d323ce6fd 76 , (uint32_t)LPC_GPDMACH5
AjK 8:cb4d323ce6fd 77 , (uint32_t)LPC_GPDMACH6
AjK 8:cb4d323ce6fd 78 , (uint32_t)LPC_GPDMACH7
AjK 8:cb4d323ce6fd 79 };
AjK 8:cb4d323ce6fd 80 return lut[channel & 0xFF];
AjK 8:cb4d323ce6fd 81 }
AjK 8:cb4d323ce6fd 82
AjK 8:cb4d323ce6fd 83 uint8_t
AjK 8:cb4d323ce6fd 84 MODDMA::LUTPerBurst(int n)
AjK 8:cb4d323ce6fd 85 {
AjK 8:cb4d323ce6fd 86 const uint8_t lut[] = {
AjK 8:cb4d323ce6fd 87 (uint8_t)_4 // SSP0 Tx
AjK 8:cb4d323ce6fd 88 , (uint8_t)_4 // SSP0 Rx
AjK 8:cb4d323ce6fd 89 , (uint8_t)_4 // SSP1 Tx
AjK 8:cb4d323ce6fd 90 , (uint8_t)_4 // SSP1 Rx
AjK 8:cb4d323ce6fd 91 , (uint8_t)_1 // ADC
AjK 8:cb4d323ce6fd 92 , (uint8_t)_32 // I2S channel 0
AjK 8:cb4d323ce6fd 93 , (uint8_t)_32 // I2S channel 1
AjK 8:cb4d323ce6fd 94 , (uint8_t)_1 // DAC
AjK 8:cb4d323ce6fd 95 , (uint8_t)_1 // UART0 Tx
AjK 8:cb4d323ce6fd 96 , (uint8_t)_1 // UART0 Rx
AjK 8:cb4d323ce6fd 97 , (uint8_t)_1 // UART1 Tx
AjK 8:cb4d323ce6fd 98 , (uint8_t)_1 // UART1 Rx
AjK 8:cb4d323ce6fd 99 , (uint8_t)_1 // UART2 Tx
AjK 8:cb4d323ce6fd 100 , (uint8_t)_1 // UART2 Rx
AjK 8:cb4d323ce6fd 101 , (uint8_t)_1 // UART3 Tx
AjK 8:cb4d323ce6fd 102 , (uint8_t)_1 // UART3 Rx
AjK 8:cb4d323ce6fd 103 , (uint8_t)_1 // MAT0.0
AjK 8:cb4d323ce6fd 104 , (uint8_t)_1 // MAT0.1
AjK 8:cb4d323ce6fd 105 , (uint8_t)_1 // MAT1.0
AjK 8:cb4d323ce6fd 106 , (uint8_t)_1 // MAT1.1
AjK 8:cb4d323ce6fd 107 , (uint8_t)_1 // MAT2.0
AjK 8:cb4d323ce6fd 108 , (uint8_t)_1 // MAT2.1
AjK 8:cb4d323ce6fd 109 , (uint8_t)_1 // MAT3.0
AjK 8:cb4d323ce6fd 110 , (uint8_t)_1 // MAT3.1
AjK 8:cb4d323ce6fd 111 };
AjK 8:cb4d323ce6fd 112 return lut[n & 0xFFF];
AjK 8:cb4d323ce6fd 113 }
AjK 8:cb4d323ce6fd 114
AjK 8:cb4d323ce6fd 115 uint8_t
AjK 8:cb4d323ce6fd 116 MODDMA::LUTPerWid(int n)
AjK 8:cb4d323ce6fd 117 {
AjK 8:cb4d323ce6fd 118 const uint8_t lut[] = {
AjK 8:cb4d323ce6fd 119 (uint8_t)byte // SSP0 Tx
AjK 8:cb4d323ce6fd 120 , (uint8_t)byte // SSP0 Rx
AjK 8:cb4d323ce6fd 121 , (uint8_t)byte // SSP1 Tx
AjK 8:cb4d323ce6fd 122 , (uint8_t)byte // SSP1 Rx
AjK 8:cb4d323ce6fd 123 , (uint8_t)word // ADC
AjK 8:cb4d323ce6fd 124 , (uint8_t)word // I2S channel 0
AjK 8:cb4d323ce6fd 125 , (uint8_t)word // I2S channel 1
AjK 16:cb10aec6feb1 126 , (uint8_t)word // DAC
AjK 8:cb4d323ce6fd 127 , (uint8_t)byte // UART0 Tx
AjK 8:cb4d323ce6fd 128 , (uint8_t)byte // UART0 Rx
AjK 8:cb4d323ce6fd 129 , (uint8_t)byte // UART1 Tx
AjK 8:cb4d323ce6fd 130 , (uint8_t)byte // UART1 Rx
AjK 8:cb4d323ce6fd 131 , (uint8_t)byte // UART2 Tx
AjK 8:cb4d323ce6fd 132 , (uint8_t)byte // UART2 Rx
AjK 8:cb4d323ce6fd 133 , (uint8_t)byte // UART3 Tx
AjK 8:cb4d323ce6fd 134 , (uint8_t)byte // UART3 Rx
AjK 8:cb4d323ce6fd 135 , (uint8_t)word // MAT0.0
AjK 8:cb4d323ce6fd 136 , (uint8_t)word // MAT0.1
AjK 8:cb4d323ce6fd 137 , (uint8_t)word // MAT1.0
AjK 8:cb4d323ce6fd 138 , (uint8_t)word // MAT1.1
AjK 8:cb4d323ce6fd 139 , (uint8_t)word // MAT2.0
AjK 8:cb4d323ce6fd 140 , (uint8_t)word // MAT2.1
AjK 8:cb4d323ce6fd 141 , (uint8_t)word // MAT3.0
AjK 8:cb4d323ce6fd 142 , (uint8_t)word // MAT3.1
AjK 8:cb4d323ce6fd 143 };
AjK 8:cb4d323ce6fd 144 return lut[n & 0xFFF];
AjK 8:cb4d323ce6fd 145 }
AjK 8:cb4d323ce6fd 146
AjK 8:cb4d323ce6fd 147 }; // namespace AjK ends