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mbed-os/cmsis/TARGET_CORTEX_A/cmsis_gcc.h@3:f3764f852aa8, 2018-10-11 (annotated)
- Committer:
- kadonotakashi
- Date:
- Thu Oct 11 02:27:46 2018 +0000
- Revision:
- 3:f3764f852aa8
- Parent:
- 0:8fdf9a60065b
Nucreo 446 + SSD1331 test version;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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kadonotakashi | 0:8fdf9a60065b | 1 | /**************************************************************************//** |
kadonotakashi | 0:8fdf9a60065b | 2 | * @file cmsis_gcc.h |
kadonotakashi | 0:8fdf9a60065b | 3 | * @brief CMSIS compiler specific macros, functions, instructions |
kadonotakashi | 0:8fdf9a60065b | 4 | * @version V1.0.2 |
kadonotakashi | 0:8fdf9a60065b | 5 | * @date 09. April 2018 |
kadonotakashi | 0:8fdf9a60065b | 6 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 7 | /* |
kadonotakashi | 0:8fdf9a60065b | 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 9 | * |
kadonotakashi | 0:8fdf9a60065b | 10 | * SPDX-License-Identifier: Apache-2.0 |
kadonotakashi | 0:8fdf9a60065b | 11 | * |
kadonotakashi | 0:8fdf9a60065b | 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
kadonotakashi | 0:8fdf9a60065b | 13 | * not use this file except in compliance with the License. |
kadonotakashi | 0:8fdf9a60065b | 14 | * You may obtain a copy of the License at |
kadonotakashi | 0:8fdf9a60065b | 15 | * |
kadonotakashi | 0:8fdf9a60065b | 16 | * www.apache.org/licenses/LICENSE-2.0 |
kadonotakashi | 0:8fdf9a60065b | 17 | * |
kadonotakashi | 0:8fdf9a60065b | 18 | * Unless required by applicable law or agreed to in writing, software |
kadonotakashi | 0:8fdf9a60065b | 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
kadonotakashi | 0:8fdf9a60065b | 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
kadonotakashi | 0:8fdf9a60065b | 21 | * See the License for the specific language governing permissions and |
kadonotakashi | 0:8fdf9a60065b | 22 | * limitations under the License. |
kadonotakashi | 0:8fdf9a60065b | 23 | */ |
kadonotakashi | 0:8fdf9a60065b | 24 | |
kadonotakashi | 0:8fdf9a60065b | 25 | #ifndef __CMSIS_GCC_H |
kadonotakashi | 0:8fdf9a60065b | 26 | #define __CMSIS_GCC_H |
kadonotakashi | 0:8fdf9a60065b | 27 | |
kadonotakashi | 0:8fdf9a60065b | 28 | /* ignore some GCC warnings */ |
kadonotakashi | 0:8fdf9a60065b | 29 | #pragma GCC diagnostic push |
kadonotakashi | 0:8fdf9a60065b | 30 | #pragma GCC diagnostic ignored "-Wsign-conversion" |
kadonotakashi | 0:8fdf9a60065b | 31 | #pragma GCC diagnostic ignored "-Wconversion" |
kadonotakashi | 0:8fdf9a60065b | 32 | #pragma GCC diagnostic ignored "-Wunused-parameter" |
kadonotakashi | 0:8fdf9a60065b | 33 | |
kadonotakashi | 0:8fdf9a60065b | 34 | /* Fallback for __has_builtin */ |
kadonotakashi | 0:8fdf9a60065b | 35 | #ifndef __has_builtin |
kadonotakashi | 0:8fdf9a60065b | 36 | #define __has_builtin(x) (0) |
kadonotakashi | 0:8fdf9a60065b | 37 | #endif |
kadonotakashi | 0:8fdf9a60065b | 38 | |
kadonotakashi | 0:8fdf9a60065b | 39 | /* CMSIS compiler specific defines */ |
kadonotakashi | 0:8fdf9a60065b | 40 | #ifndef __ASM |
kadonotakashi | 0:8fdf9a60065b | 41 | #define __ASM asm |
kadonotakashi | 0:8fdf9a60065b | 42 | #endif |
kadonotakashi | 0:8fdf9a60065b | 43 | #ifndef __INLINE |
kadonotakashi | 0:8fdf9a60065b | 44 | #define __INLINE inline |
kadonotakashi | 0:8fdf9a60065b | 45 | #endif |
kadonotakashi | 0:8fdf9a60065b | 46 | #ifndef __FORCEINLINE |
kadonotakashi | 0:8fdf9a60065b | 47 | #define __FORCEINLINE __attribute__((always_inline)) |
kadonotakashi | 0:8fdf9a60065b | 48 | #endif |
kadonotakashi | 0:8fdf9a60065b | 49 | #ifndef __STATIC_INLINE |
kadonotakashi | 0:8fdf9a60065b | 50 | #define __STATIC_INLINE static inline |
kadonotakashi | 0:8fdf9a60065b | 51 | #endif |
kadonotakashi | 0:8fdf9a60065b | 52 | #ifndef __STATIC_FORCEINLINE |
kadonotakashi | 0:8fdf9a60065b | 53 | #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline |
kadonotakashi | 0:8fdf9a60065b | 54 | #endif |
kadonotakashi | 0:8fdf9a60065b | 55 | #ifndef __NO_RETURN |
kadonotakashi | 0:8fdf9a60065b | 56 | #define __NO_RETURN __attribute__((__noreturn__)) |
kadonotakashi | 0:8fdf9a60065b | 57 | #endif |
kadonotakashi | 0:8fdf9a60065b | 58 | #ifndef CMSIS_DEPRECATED |
kadonotakashi | 0:8fdf9a60065b | 59 | #define CMSIS_DEPRECATED __attribute__((deprecated)) |
kadonotakashi | 0:8fdf9a60065b | 60 | #endif |
kadonotakashi | 0:8fdf9a60065b | 61 | #ifndef __USED |
kadonotakashi | 0:8fdf9a60065b | 62 | #define __USED __attribute__((used)) |
kadonotakashi | 0:8fdf9a60065b | 63 | #endif |
kadonotakashi | 0:8fdf9a60065b | 64 | #ifndef __WEAK |
kadonotakashi | 0:8fdf9a60065b | 65 | #define __WEAK __attribute__((weak)) |
kadonotakashi | 0:8fdf9a60065b | 66 | #endif |
kadonotakashi | 0:8fdf9a60065b | 67 | #ifndef __PACKED |
kadonotakashi | 0:8fdf9a60065b | 68 | #define __PACKED __attribute__((packed, aligned(1))) |
kadonotakashi | 0:8fdf9a60065b | 69 | #endif |
kadonotakashi | 0:8fdf9a60065b | 70 | #ifndef __PACKED_STRUCT |
kadonotakashi | 0:8fdf9a60065b | 71 | #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) |
kadonotakashi | 0:8fdf9a60065b | 72 | #endif |
kadonotakashi | 0:8fdf9a60065b | 73 | #ifndef __UNALIGNED_UINT16_WRITE |
kadonotakashi | 0:8fdf9a60065b | 74 | #pragma GCC diagnostic push |
kadonotakashi | 0:8fdf9a60065b | 75 | #pragma GCC diagnostic ignored "-Wpacked" |
kadonotakashi | 0:8fdf9a60065b | 76 | /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ |
kadonotakashi | 0:8fdf9a60065b | 77 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; |
kadonotakashi | 0:8fdf9a60065b | 78 | #pragma GCC diagnostic pop |
kadonotakashi | 0:8fdf9a60065b | 79 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) |
kadonotakashi | 0:8fdf9a60065b | 80 | #endif |
kadonotakashi | 0:8fdf9a60065b | 81 | #ifndef __UNALIGNED_UINT16_READ |
kadonotakashi | 0:8fdf9a60065b | 82 | #pragma GCC diagnostic push |
kadonotakashi | 0:8fdf9a60065b | 83 | #pragma GCC diagnostic ignored "-Wpacked" |
kadonotakashi | 0:8fdf9a60065b | 84 | /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ |
kadonotakashi | 0:8fdf9a60065b | 85 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; |
kadonotakashi | 0:8fdf9a60065b | 86 | #pragma GCC diagnostic pop |
kadonotakashi | 0:8fdf9a60065b | 87 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) |
kadonotakashi | 0:8fdf9a60065b | 88 | #endif |
kadonotakashi | 0:8fdf9a60065b | 89 | #ifndef __UNALIGNED_UINT32_WRITE |
kadonotakashi | 0:8fdf9a60065b | 90 | #pragma GCC diagnostic push |
kadonotakashi | 0:8fdf9a60065b | 91 | #pragma GCC diagnostic ignored "-Wpacked" |
kadonotakashi | 0:8fdf9a60065b | 92 | /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ |
kadonotakashi | 0:8fdf9a60065b | 93 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; |
kadonotakashi | 0:8fdf9a60065b | 94 | #pragma GCC diagnostic pop |
kadonotakashi | 0:8fdf9a60065b | 95 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) |
kadonotakashi | 0:8fdf9a60065b | 96 | #endif |
kadonotakashi | 0:8fdf9a60065b | 97 | #ifndef __UNALIGNED_UINT32_READ |
kadonotakashi | 0:8fdf9a60065b | 98 | #pragma GCC diagnostic push |
kadonotakashi | 0:8fdf9a60065b | 99 | #pragma GCC diagnostic ignored "-Wpacked" |
kadonotakashi | 0:8fdf9a60065b | 100 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; |
kadonotakashi | 0:8fdf9a60065b | 101 | #pragma GCC diagnostic pop |
kadonotakashi | 0:8fdf9a60065b | 102 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) |
kadonotakashi | 0:8fdf9a60065b | 103 | #endif |
kadonotakashi | 0:8fdf9a60065b | 104 | #ifndef __ALIGNED |
kadonotakashi | 0:8fdf9a60065b | 105 | #define __ALIGNED(x) __attribute__((aligned(x))) |
kadonotakashi | 0:8fdf9a60065b | 106 | #endif |
kadonotakashi | 0:8fdf9a60065b | 107 | |
kadonotakashi | 0:8fdf9a60065b | 108 | /* ########################## Core Instruction Access ######################### */ |
kadonotakashi | 0:8fdf9a60065b | 109 | /** |
kadonotakashi | 0:8fdf9a60065b | 110 | \brief No Operation |
kadonotakashi | 0:8fdf9a60065b | 111 | */ |
kadonotakashi | 0:8fdf9a60065b | 112 | #define __NOP() __ASM volatile ("nop") |
kadonotakashi | 0:8fdf9a60065b | 113 | |
kadonotakashi | 0:8fdf9a60065b | 114 | /** |
kadonotakashi | 0:8fdf9a60065b | 115 | \brief Wait For Interrupt |
kadonotakashi | 0:8fdf9a60065b | 116 | */ |
kadonotakashi | 0:8fdf9a60065b | 117 | #define __WFI() __ASM volatile ("wfi") |
kadonotakashi | 0:8fdf9a60065b | 118 | |
kadonotakashi | 0:8fdf9a60065b | 119 | /** |
kadonotakashi | 0:8fdf9a60065b | 120 | \brief Wait For Event |
kadonotakashi | 0:8fdf9a60065b | 121 | */ |
kadonotakashi | 0:8fdf9a60065b | 122 | #define __WFE() __ASM volatile ("wfe") |
kadonotakashi | 0:8fdf9a60065b | 123 | |
kadonotakashi | 0:8fdf9a60065b | 124 | /** |
kadonotakashi | 0:8fdf9a60065b | 125 | \brief Send Event |
kadonotakashi | 0:8fdf9a60065b | 126 | */ |
kadonotakashi | 0:8fdf9a60065b | 127 | #define __SEV() __ASM volatile ("sev") |
kadonotakashi | 0:8fdf9a60065b | 128 | |
kadonotakashi | 0:8fdf9a60065b | 129 | /** |
kadonotakashi | 0:8fdf9a60065b | 130 | \brief Instruction Synchronization Barrier |
kadonotakashi | 0:8fdf9a60065b | 131 | \details Instruction Synchronization Barrier flushes the pipeline in the processor, |
kadonotakashi | 0:8fdf9a60065b | 132 | so that all instructions following the ISB are fetched from cache or memory, |
kadonotakashi | 0:8fdf9a60065b | 133 | after the instruction has been completed. |
kadonotakashi | 0:8fdf9a60065b | 134 | */ |
kadonotakashi | 0:8fdf9a60065b | 135 | __STATIC_FORCEINLINE void __ISB(void) |
kadonotakashi | 0:8fdf9a60065b | 136 | { |
kadonotakashi | 0:8fdf9a60065b | 137 | __ASM volatile ("isb 0xF":::"memory"); |
kadonotakashi | 0:8fdf9a60065b | 138 | } |
kadonotakashi | 0:8fdf9a60065b | 139 | |
kadonotakashi | 0:8fdf9a60065b | 140 | |
kadonotakashi | 0:8fdf9a60065b | 141 | /** |
kadonotakashi | 0:8fdf9a60065b | 142 | \brief Data Synchronization Barrier |
kadonotakashi | 0:8fdf9a60065b | 143 | \details Acts as a special kind of Data Memory Barrier. |
kadonotakashi | 0:8fdf9a60065b | 144 | It completes when all explicit memory accesses before this instruction complete. |
kadonotakashi | 0:8fdf9a60065b | 145 | */ |
kadonotakashi | 0:8fdf9a60065b | 146 | __STATIC_FORCEINLINE void __DSB(void) |
kadonotakashi | 0:8fdf9a60065b | 147 | { |
kadonotakashi | 0:8fdf9a60065b | 148 | __ASM volatile ("dsb 0xF":::"memory"); |
kadonotakashi | 0:8fdf9a60065b | 149 | } |
kadonotakashi | 0:8fdf9a60065b | 150 | |
kadonotakashi | 0:8fdf9a60065b | 151 | /** |
kadonotakashi | 0:8fdf9a60065b | 152 | \brief Data Memory Barrier |
kadonotakashi | 0:8fdf9a60065b | 153 | \details Ensures the apparent order of the explicit memory operations before |
kadonotakashi | 0:8fdf9a60065b | 154 | and after the instruction, without ensuring their completion. |
kadonotakashi | 0:8fdf9a60065b | 155 | */ |
kadonotakashi | 0:8fdf9a60065b | 156 | __STATIC_FORCEINLINE void __DMB(void) |
kadonotakashi | 0:8fdf9a60065b | 157 | { |
kadonotakashi | 0:8fdf9a60065b | 158 | __ASM volatile ("dmb 0xF":::"memory"); |
kadonotakashi | 0:8fdf9a60065b | 159 | } |
kadonotakashi | 0:8fdf9a60065b | 160 | |
kadonotakashi | 0:8fdf9a60065b | 161 | /** |
kadonotakashi | 0:8fdf9a60065b | 162 | \brief Reverse byte order (32 bit) |
kadonotakashi | 0:8fdf9a60065b | 163 | \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. |
kadonotakashi | 0:8fdf9a60065b | 164 | \param [in] value Value to reverse |
kadonotakashi | 0:8fdf9a60065b | 165 | \return Reversed value |
kadonotakashi | 0:8fdf9a60065b | 166 | */ |
kadonotakashi | 0:8fdf9a60065b | 167 | __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) |
kadonotakashi | 0:8fdf9a60065b | 168 | { |
kadonotakashi | 0:8fdf9a60065b | 169 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) |
kadonotakashi | 0:8fdf9a60065b | 170 | return __builtin_bswap32(value); |
kadonotakashi | 0:8fdf9a60065b | 171 | #else |
kadonotakashi | 0:8fdf9a60065b | 172 | uint32_t result; |
kadonotakashi | 0:8fdf9a60065b | 173 | |
kadonotakashi | 0:8fdf9a60065b | 174 | __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); |
kadonotakashi | 0:8fdf9a60065b | 175 | return result; |
kadonotakashi | 0:8fdf9a60065b | 176 | #endif |
kadonotakashi | 0:8fdf9a60065b | 177 | } |
kadonotakashi | 0:8fdf9a60065b | 178 | |
kadonotakashi | 0:8fdf9a60065b | 179 | /** |
kadonotakashi | 0:8fdf9a60065b | 180 | \brief Reverse byte order (16 bit) |
kadonotakashi | 0:8fdf9a60065b | 181 | \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. |
kadonotakashi | 0:8fdf9a60065b | 182 | \param [in] value Value to reverse |
kadonotakashi | 0:8fdf9a60065b | 183 | \return Reversed value |
kadonotakashi | 0:8fdf9a60065b | 184 | */ |
kadonotakashi | 0:8fdf9a60065b | 185 | #ifndef __NO_EMBEDDED_ASM |
kadonotakashi | 0:8fdf9a60065b | 186 | __attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value) |
kadonotakashi | 0:8fdf9a60065b | 187 | { |
kadonotakashi | 0:8fdf9a60065b | 188 | uint32_t result; |
kadonotakashi | 0:8fdf9a60065b | 189 | __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value)); |
kadonotakashi | 0:8fdf9a60065b | 190 | return result; |
kadonotakashi | 0:8fdf9a60065b | 191 | } |
kadonotakashi | 0:8fdf9a60065b | 192 | #endif |
kadonotakashi | 0:8fdf9a60065b | 193 | |
kadonotakashi | 0:8fdf9a60065b | 194 | /** |
kadonotakashi | 0:8fdf9a60065b | 195 | \brief Reverse byte order (16 bit) |
kadonotakashi | 0:8fdf9a60065b | 196 | \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. |
kadonotakashi | 0:8fdf9a60065b | 197 | \param [in] value Value to reverse |
kadonotakashi | 0:8fdf9a60065b | 198 | \return Reversed value |
kadonotakashi | 0:8fdf9a60065b | 199 | */ |
kadonotakashi | 0:8fdf9a60065b | 200 | __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) |
kadonotakashi | 0:8fdf9a60065b | 201 | { |
kadonotakashi | 0:8fdf9a60065b | 202 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) |
kadonotakashi | 0:8fdf9a60065b | 203 | return (int16_t)__builtin_bswap16(value); |
kadonotakashi | 0:8fdf9a60065b | 204 | #else |
kadonotakashi | 0:8fdf9a60065b | 205 | int16_t result; |
kadonotakashi | 0:8fdf9a60065b | 206 | |
kadonotakashi | 0:8fdf9a60065b | 207 | __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); |
kadonotakashi | 0:8fdf9a60065b | 208 | return result; |
kadonotakashi | 0:8fdf9a60065b | 209 | #endif |
kadonotakashi | 0:8fdf9a60065b | 210 | } |
kadonotakashi | 0:8fdf9a60065b | 211 | |
kadonotakashi | 0:8fdf9a60065b | 212 | /** |
kadonotakashi | 0:8fdf9a60065b | 213 | \brief Rotate Right in unsigned value (32 bit) |
kadonotakashi | 0:8fdf9a60065b | 214 | \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. |
kadonotakashi | 0:8fdf9a60065b | 215 | \param [in] op1 Value to rotate |
kadonotakashi | 0:8fdf9a60065b | 216 | \param [in] op2 Number of Bits to rotate |
kadonotakashi | 0:8fdf9a60065b | 217 | \return Rotated value |
kadonotakashi | 0:8fdf9a60065b | 218 | */ |
kadonotakashi | 0:8fdf9a60065b | 219 | __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) |
kadonotakashi | 0:8fdf9a60065b | 220 | { |
kadonotakashi | 0:8fdf9a60065b | 221 | op2 %= 32U; |
kadonotakashi | 0:8fdf9a60065b | 222 | if (op2 == 0U) { |
kadonotakashi | 0:8fdf9a60065b | 223 | return op1; |
kadonotakashi | 0:8fdf9a60065b | 224 | } |
kadonotakashi | 0:8fdf9a60065b | 225 | return (op1 >> op2) | (op1 << (32U - op2)); |
kadonotakashi | 0:8fdf9a60065b | 226 | } |
kadonotakashi | 0:8fdf9a60065b | 227 | |
kadonotakashi | 0:8fdf9a60065b | 228 | |
kadonotakashi | 0:8fdf9a60065b | 229 | /** |
kadonotakashi | 0:8fdf9a60065b | 230 | \brief Breakpoint |
kadonotakashi | 0:8fdf9a60065b | 231 | \param [in] value is ignored by the processor. |
kadonotakashi | 0:8fdf9a60065b | 232 | If required, a debugger can use it to store additional information about the breakpoint. |
kadonotakashi | 0:8fdf9a60065b | 233 | */ |
kadonotakashi | 0:8fdf9a60065b | 234 | #define __BKPT(value) __ASM volatile ("bkpt "#value) |
kadonotakashi | 0:8fdf9a60065b | 235 | |
kadonotakashi | 0:8fdf9a60065b | 236 | /** |
kadonotakashi | 0:8fdf9a60065b | 237 | \brief Reverse bit order of value |
kadonotakashi | 0:8fdf9a60065b | 238 | \details Reverses the bit order of the given value. |
kadonotakashi | 0:8fdf9a60065b | 239 | \param [in] value Value to reverse |
kadonotakashi | 0:8fdf9a60065b | 240 | \return Reversed value |
kadonotakashi | 0:8fdf9a60065b | 241 | */ |
kadonotakashi | 0:8fdf9a60065b | 242 | __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) |
kadonotakashi | 0:8fdf9a60065b | 243 | { |
kadonotakashi | 0:8fdf9a60065b | 244 | uint32_t result; |
kadonotakashi | 0:8fdf9a60065b | 245 | |
kadonotakashi | 0:8fdf9a60065b | 246 | #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ |
kadonotakashi | 0:8fdf9a60065b | 247 | (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ |
kadonotakashi | 0:8fdf9a60065b | 248 | (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) |
kadonotakashi | 0:8fdf9a60065b | 249 | __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); |
kadonotakashi | 0:8fdf9a60065b | 250 | #else |
kadonotakashi | 0:8fdf9a60065b | 251 | int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ |
kadonotakashi | 0:8fdf9a60065b | 252 | |
kadonotakashi | 0:8fdf9a60065b | 253 | result = value; /* r will be reversed bits of v; first get LSB of v */ |
kadonotakashi | 0:8fdf9a60065b | 254 | for (value >>= 1U; value; value >>= 1U) |
kadonotakashi | 0:8fdf9a60065b | 255 | { |
kadonotakashi | 0:8fdf9a60065b | 256 | result <<= 1U; |
kadonotakashi | 0:8fdf9a60065b | 257 | result |= value & 1U; |
kadonotakashi | 0:8fdf9a60065b | 258 | s--; |
kadonotakashi | 0:8fdf9a60065b | 259 | } |
kadonotakashi | 0:8fdf9a60065b | 260 | result <<= s; /* shift when v's highest bits are zero */ |
kadonotakashi | 0:8fdf9a60065b | 261 | #endif |
kadonotakashi | 0:8fdf9a60065b | 262 | return result; |
kadonotakashi | 0:8fdf9a60065b | 263 | } |
kadonotakashi | 0:8fdf9a60065b | 264 | |
kadonotakashi | 0:8fdf9a60065b | 265 | /** |
kadonotakashi | 0:8fdf9a60065b | 266 | \brief Count leading zeros |
kadonotakashi | 0:8fdf9a60065b | 267 | \param [in] value Value to count the leading zeros |
kadonotakashi | 0:8fdf9a60065b | 268 | \return number of leading zeros in value |
kadonotakashi | 0:8fdf9a60065b | 269 | */ |
kadonotakashi | 0:8fdf9a60065b | 270 | #define __CLZ (uint8_t)__builtin_clz |
kadonotakashi | 0:8fdf9a60065b | 271 | |
kadonotakashi | 0:8fdf9a60065b | 272 | /** |
kadonotakashi | 0:8fdf9a60065b | 273 | \brief LDR Exclusive (8 bit) |
kadonotakashi | 0:8fdf9a60065b | 274 | \details Executes a exclusive LDR instruction for 8 bit value. |
kadonotakashi | 0:8fdf9a60065b | 275 | \param [in] ptr Pointer to data |
kadonotakashi | 0:8fdf9a60065b | 276 | \return value of type uint8_t at (*ptr) |
kadonotakashi | 0:8fdf9a60065b | 277 | */ |
kadonotakashi | 0:8fdf9a60065b | 278 | __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) |
kadonotakashi | 0:8fdf9a60065b | 279 | { |
kadonotakashi | 0:8fdf9a60065b | 280 | uint32_t result; |
kadonotakashi | 0:8fdf9a60065b | 281 | |
kadonotakashi | 0:8fdf9a60065b | 282 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) |
kadonotakashi | 0:8fdf9a60065b | 283 | __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); |
kadonotakashi | 0:8fdf9a60065b | 284 | #else |
kadonotakashi | 0:8fdf9a60065b | 285 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not |
kadonotakashi | 0:8fdf9a60065b | 286 | accepted by assembler. So has to use following less efficient pattern. |
kadonotakashi | 0:8fdf9a60065b | 287 | */ |
kadonotakashi | 0:8fdf9a60065b | 288 | __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); |
kadonotakashi | 0:8fdf9a60065b | 289 | #endif |
kadonotakashi | 0:8fdf9a60065b | 290 | return ((uint8_t) result); /* Add explicit type cast here */ |
kadonotakashi | 0:8fdf9a60065b | 291 | } |
kadonotakashi | 0:8fdf9a60065b | 292 | |
kadonotakashi | 0:8fdf9a60065b | 293 | |
kadonotakashi | 0:8fdf9a60065b | 294 | /** |
kadonotakashi | 0:8fdf9a60065b | 295 | \brief LDR Exclusive (16 bit) |
kadonotakashi | 0:8fdf9a60065b | 296 | \details Executes a exclusive LDR instruction for 16 bit values. |
kadonotakashi | 0:8fdf9a60065b | 297 | \param [in] ptr Pointer to data |
kadonotakashi | 0:8fdf9a60065b | 298 | \return value of type uint16_t at (*ptr) |
kadonotakashi | 0:8fdf9a60065b | 299 | */ |
kadonotakashi | 0:8fdf9a60065b | 300 | __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) |
kadonotakashi | 0:8fdf9a60065b | 301 | { |
kadonotakashi | 0:8fdf9a60065b | 302 | uint32_t result; |
kadonotakashi | 0:8fdf9a60065b | 303 | |
kadonotakashi | 0:8fdf9a60065b | 304 | #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) |
kadonotakashi | 0:8fdf9a60065b | 305 | __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); |
kadonotakashi | 0:8fdf9a60065b | 306 | #else |
kadonotakashi | 0:8fdf9a60065b | 307 | /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not |
kadonotakashi | 0:8fdf9a60065b | 308 | accepted by assembler. So has to use following less efficient pattern. |
kadonotakashi | 0:8fdf9a60065b | 309 | */ |
kadonotakashi | 0:8fdf9a60065b | 310 | __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); |
kadonotakashi | 0:8fdf9a60065b | 311 | #endif |
kadonotakashi | 0:8fdf9a60065b | 312 | return ((uint16_t) result); /* Add explicit type cast here */ |
kadonotakashi | 0:8fdf9a60065b | 313 | } |
kadonotakashi | 0:8fdf9a60065b | 314 | |
kadonotakashi | 0:8fdf9a60065b | 315 | |
kadonotakashi | 0:8fdf9a60065b | 316 | /** |
kadonotakashi | 0:8fdf9a60065b | 317 | \brief LDR Exclusive (32 bit) |
kadonotakashi | 0:8fdf9a60065b | 318 | \details Executes a exclusive LDR instruction for 32 bit values. |
kadonotakashi | 0:8fdf9a60065b | 319 | \param [in] ptr Pointer to data |
kadonotakashi | 0:8fdf9a60065b | 320 | \return value of type uint32_t at (*ptr) |
kadonotakashi | 0:8fdf9a60065b | 321 | */ |
kadonotakashi | 0:8fdf9a60065b | 322 | __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) |
kadonotakashi | 0:8fdf9a60065b | 323 | { |
kadonotakashi | 0:8fdf9a60065b | 324 | uint32_t result; |
kadonotakashi | 0:8fdf9a60065b | 325 | |
kadonotakashi | 0:8fdf9a60065b | 326 | __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); |
kadonotakashi | 0:8fdf9a60065b | 327 | return(result); |
kadonotakashi | 0:8fdf9a60065b | 328 | } |
kadonotakashi | 0:8fdf9a60065b | 329 | |
kadonotakashi | 0:8fdf9a60065b | 330 | |
kadonotakashi | 0:8fdf9a60065b | 331 | /** |
kadonotakashi | 0:8fdf9a60065b | 332 | \brief STR Exclusive (8 bit) |
kadonotakashi | 0:8fdf9a60065b | 333 | \details Executes a exclusive STR instruction for 8 bit values. |
kadonotakashi | 0:8fdf9a60065b | 334 | \param [in] value Value to store |
kadonotakashi | 0:8fdf9a60065b | 335 | \param [in] ptr Pointer to location |
kadonotakashi | 0:8fdf9a60065b | 336 | \return 0 Function succeeded |
kadonotakashi | 0:8fdf9a60065b | 337 | \return 1 Function failed |
kadonotakashi | 0:8fdf9a60065b | 338 | */ |
kadonotakashi | 0:8fdf9a60065b | 339 | __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) |
kadonotakashi | 0:8fdf9a60065b | 340 | { |
kadonotakashi | 0:8fdf9a60065b | 341 | uint32_t result; |
kadonotakashi | 0:8fdf9a60065b | 342 | |
kadonotakashi | 0:8fdf9a60065b | 343 | __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); |
kadonotakashi | 0:8fdf9a60065b | 344 | return(result); |
kadonotakashi | 0:8fdf9a60065b | 345 | } |
kadonotakashi | 0:8fdf9a60065b | 346 | |
kadonotakashi | 0:8fdf9a60065b | 347 | |
kadonotakashi | 0:8fdf9a60065b | 348 | /** |
kadonotakashi | 0:8fdf9a60065b | 349 | \brief STR Exclusive (16 bit) |
kadonotakashi | 0:8fdf9a60065b | 350 | \details Executes a exclusive STR instruction for 16 bit values. |
kadonotakashi | 0:8fdf9a60065b | 351 | \param [in] value Value to store |
kadonotakashi | 0:8fdf9a60065b | 352 | \param [in] ptr Pointer to location |
kadonotakashi | 0:8fdf9a60065b | 353 | \return 0 Function succeeded |
kadonotakashi | 0:8fdf9a60065b | 354 | \return 1 Function failed |
kadonotakashi | 0:8fdf9a60065b | 355 | */ |
kadonotakashi | 0:8fdf9a60065b | 356 | __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) |
kadonotakashi | 0:8fdf9a60065b | 357 | { |
kadonotakashi | 0:8fdf9a60065b | 358 | uint32_t result; |
kadonotakashi | 0:8fdf9a60065b | 359 | |
kadonotakashi | 0:8fdf9a60065b | 360 | __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); |
kadonotakashi | 0:8fdf9a60065b | 361 | return(result); |
kadonotakashi | 0:8fdf9a60065b | 362 | } |
kadonotakashi | 0:8fdf9a60065b | 363 | |
kadonotakashi | 0:8fdf9a60065b | 364 | |
kadonotakashi | 0:8fdf9a60065b | 365 | /** |
kadonotakashi | 0:8fdf9a60065b | 366 | \brief STR Exclusive (32 bit) |
kadonotakashi | 0:8fdf9a60065b | 367 | \details Executes a exclusive STR instruction for 32 bit values. |
kadonotakashi | 0:8fdf9a60065b | 368 | \param [in] value Value to store |
kadonotakashi | 0:8fdf9a60065b | 369 | \param [in] ptr Pointer to location |
kadonotakashi | 0:8fdf9a60065b | 370 | \return 0 Function succeeded |
kadonotakashi | 0:8fdf9a60065b | 371 | \return 1 Function failed |
kadonotakashi | 0:8fdf9a60065b | 372 | */ |
kadonotakashi | 0:8fdf9a60065b | 373 | __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) |
kadonotakashi | 0:8fdf9a60065b | 374 | { |
kadonotakashi | 0:8fdf9a60065b | 375 | uint32_t result; |
kadonotakashi | 0:8fdf9a60065b | 376 | |
kadonotakashi | 0:8fdf9a60065b | 377 | __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); |
kadonotakashi | 0:8fdf9a60065b | 378 | return(result); |
kadonotakashi | 0:8fdf9a60065b | 379 | } |
kadonotakashi | 0:8fdf9a60065b | 380 | |
kadonotakashi | 0:8fdf9a60065b | 381 | |
kadonotakashi | 0:8fdf9a60065b | 382 | /** |
kadonotakashi | 0:8fdf9a60065b | 383 | \brief Remove the exclusive lock |
kadonotakashi | 0:8fdf9a60065b | 384 | \details Removes the exclusive lock which is created by LDREX. |
kadonotakashi | 0:8fdf9a60065b | 385 | */ |
kadonotakashi | 0:8fdf9a60065b | 386 | __STATIC_FORCEINLINE void __CLREX(void) |
kadonotakashi | 0:8fdf9a60065b | 387 | { |
kadonotakashi | 0:8fdf9a60065b | 388 | __ASM volatile ("clrex" ::: "memory"); |
kadonotakashi | 0:8fdf9a60065b | 389 | } |
kadonotakashi | 0:8fdf9a60065b | 390 | |
kadonotakashi | 0:8fdf9a60065b | 391 | /** |
kadonotakashi | 0:8fdf9a60065b | 392 | \brief Signed Saturate |
kadonotakashi | 0:8fdf9a60065b | 393 | \details Saturates a signed value. |
kadonotakashi | 0:8fdf9a60065b | 394 | \param [in] value Value to be saturated |
kadonotakashi | 0:8fdf9a60065b | 395 | \param [in] sat Bit position to saturate to (1..32) |
kadonotakashi | 0:8fdf9a60065b | 396 | \return Saturated value |
kadonotakashi | 0:8fdf9a60065b | 397 | */ |
kadonotakashi | 0:8fdf9a60065b | 398 | #define __SSAT(ARG1,ARG2) \ |
kadonotakashi | 0:8fdf9a60065b | 399 | __extension__ \ |
kadonotakashi | 0:8fdf9a60065b | 400 | ({ \ |
kadonotakashi | 0:8fdf9a60065b | 401 | int32_t __RES, __ARG1 = (ARG1); \ |
kadonotakashi | 0:8fdf9a60065b | 402 | __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ |
kadonotakashi | 0:8fdf9a60065b | 403 | __RES; \ |
kadonotakashi | 0:8fdf9a60065b | 404 | }) |
kadonotakashi | 0:8fdf9a60065b | 405 | |
kadonotakashi | 0:8fdf9a60065b | 406 | |
kadonotakashi | 0:8fdf9a60065b | 407 | /** |
kadonotakashi | 0:8fdf9a60065b | 408 | \brief Unsigned Saturate |
kadonotakashi | 0:8fdf9a60065b | 409 | \details Saturates an unsigned value. |
kadonotakashi | 0:8fdf9a60065b | 410 | \param [in] value Value to be saturated |
kadonotakashi | 0:8fdf9a60065b | 411 | \param [in] sat Bit position to saturate to (0..31) |
kadonotakashi | 0:8fdf9a60065b | 412 | \return Saturated value |
kadonotakashi | 0:8fdf9a60065b | 413 | */ |
kadonotakashi | 0:8fdf9a60065b | 414 | #define __USAT(ARG1,ARG2) \ |
kadonotakashi | 0:8fdf9a60065b | 415 | __extension__ \ |
kadonotakashi | 0:8fdf9a60065b | 416 | ({ \ |
kadonotakashi | 0:8fdf9a60065b | 417 | uint32_t __RES, __ARG1 = (ARG1); \ |
kadonotakashi | 0:8fdf9a60065b | 418 | __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ |
kadonotakashi | 0:8fdf9a60065b | 419 | __RES; \ |
kadonotakashi | 0:8fdf9a60065b | 420 | }) |
kadonotakashi | 0:8fdf9a60065b | 421 | |
kadonotakashi | 0:8fdf9a60065b | 422 | /* ########################### Core Function Access ########################### */ |
kadonotakashi | 0:8fdf9a60065b | 423 | |
kadonotakashi | 0:8fdf9a60065b | 424 | /** |
kadonotakashi | 0:8fdf9a60065b | 425 | \brief Enable IRQ Interrupts |
kadonotakashi | 0:8fdf9a60065b | 426 | \details Enables IRQ interrupts by clearing the I-bit in the CPSR. |
kadonotakashi | 0:8fdf9a60065b | 427 | Can only be executed in Privileged modes. |
kadonotakashi | 0:8fdf9a60065b | 428 | */ |
kadonotakashi | 0:8fdf9a60065b | 429 | __STATIC_FORCEINLINE void __enable_irq(void) |
kadonotakashi | 0:8fdf9a60065b | 430 | { |
kadonotakashi | 0:8fdf9a60065b | 431 | __ASM volatile ("cpsie i" : : : "memory"); |
kadonotakashi | 0:8fdf9a60065b | 432 | } |
kadonotakashi | 0:8fdf9a60065b | 433 | |
kadonotakashi | 0:8fdf9a60065b | 434 | /** |
kadonotakashi | 0:8fdf9a60065b | 435 | \brief Disable IRQ Interrupts |
kadonotakashi | 0:8fdf9a60065b | 436 | \details Disables IRQ interrupts by setting the I-bit in the CPSR. |
kadonotakashi | 0:8fdf9a60065b | 437 | Can only be executed in Privileged modes. |
kadonotakashi | 0:8fdf9a60065b | 438 | */ |
kadonotakashi | 0:8fdf9a60065b | 439 | __STATIC_FORCEINLINE void __disable_irq(void) |
kadonotakashi | 0:8fdf9a60065b | 440 | { |
kadonotakashi | 0:8fdf9a60065b | 441 | __ASM volatile ("cpsid i" : : : "memory"); |
kadonotakashi | 0:8fdf9a60065b | 442 | } |
kadonotakashi | 0:8fdf9a60065b | 443 | |
kadonotakashi | 0:8fdf9a60065b | 444 | /** |
kadonotakashi | 0:8fdf9a60065b | 445 | \brief Get FPSCR |
kadonotakashi | 0:8fdf9a60065b | 446 | \details Returns the current value of the Floating Point Status/Control register. |
kadonotakashi | 0:8fdf9a60065b | 447 | \return Floating Point Status/Control register value |
kadonotakashi | 0:8fdf9a60065b | 448 | */ |
kadonotakashi | 0:8fdf9a60065b | 449 | __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) |
kadonotakashi | 0:8fdf9a60065b | 450 | { |
kadonotakashi | 0:8fdf9a60065b | 451 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
kadonotakashi | 0:8fdf9a60065b | 452 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
kadonotakashi | 0:8fdf9a60065b | 453 | #if __has_builtin(__builtin_arm_get_fpscr) |
kadonotakashi | 0:8fdf9a60065b | 454 | // Re-enable using built-in when GCC has been fixed |
kadonotakashi | 0:8fdf9a60065b | 455 | // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) |
kadonotakashi | 0:8fdf9a60065b | 456 | /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ |
kadonotakashi | 0:8fdf9a60065b | 457 | return __builtin_arm_get_fpscr(); |
kadonotakashi | 0:8fdf9a60065b | 458 | #else |
kadonotakashi | 0:8fdf9a60065b | 459 | uint32_t result; |
kadonotakashi | 0:8fdf9a60065b | 460 | |
kadonotakashi | 0:8fdf9a60065b | 461 | __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); |
kadonotakashi | 0:8fdf9a60065b | 462 | return(result); |
kadonotakashi | 0:8fdf9a60065b | 463 | #endif |
kadonotakashi | 0:8fdf9a60065b | 464 | #else |
kadonotakashi | 0:8fdf9a60065b | 465 | return(0U); |
kadonotakashi | 0:8fdf9a60065b | 466 | #endif |
kadonotakashi | 0:8fdf9a60065b | 467 | } |
kadonotakashi | 0:8fdf9a60065b | 468 | |
kadonotakashi | 0:8fdf9a60065b | 469 | /** |
kadonotakashi | 0:8fdf9a60065b | 470 | \brief Set FPSCR |
kadonotakashi | 0:8fdf9a60065b | 471 | \details Assigns the given value to the Floating Point Status/Control register. |
kadonotakashi | 0:8fdf9a60065b | 472 | \param [in] fpscr Floating Point Status/Control value to set |
kadonotakashi | 0:8fdf9a60065b | 473 | */ |
kadonotakashi | 0:8fdf9a60065b | 474 | __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) |
kadonotakashi | 0:8fdf9a60065b | 475 | { |
kadonotakashi | 0:8fdf9a60065b | 476 | #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ |
kadonotakashi | 0:8fdf9a60065b | 477 | (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) |
kadonotakashi | 0:8fdf9a60065b | 478 | #if __has_builtin(__builtin_arm_set_fpscr) |
kadonotakashi | 0:8fdf9a60065b | 479 | // Re-enable using built-in when GCC has been fixed |
kadonotakashi | 0:8fdf9a60065b | 480 | // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) |
kadonotakashi | 0:8fdf9a60065b | 481 | /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ |
kadonotakashi | 0:8fdf9a60065b | 482 | __builtin_arm_set_fpscr(fpscr); |
kadonotakashi | 0:8fdf9a60065b | 483 | #else |
kadonotakashi | 0:8fdf9a60065b | 484 | __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); |
kadonotakashi | 0:8fdf9a60065b | 485 | #endif |
kadonotakashi | 0:8fdf9a60065b | 486 | #else |
kadonotakashi | 0:8fdf9a60065b | 487 | (void)fpscr; |
kadonotakashi | 0:8fdf9a60065b | 488 | #endif |
kadonotakashi | 0:8fdf9a60065b | 489 | } |
kadonotakashi | 0:8fdf9a60065b | 490 | |
kadonotakashi | 0:8fdf9a60065b | 491 | /** \brief Get CPSR Register |
kadonotakashi | 0:8fdf9a60065b | 492 | \return CPSR Register value |
kadonotakashi | 0:8fdf9a60065b | 493 | */ |
kadonotakashi | 0:8fdf9a60065b | 494 | __STATIC_FORCEINLINE uint32_t __get_CPSR(void) |
kadonotakashi | 0:8fdf9a60065b | 495 | { |
kadonotakashi | 0:8fdf9a60065b | 496 | uint32_t result; |
kadonotakashi | 0:8fdf9a60065b | 497 | __ASM volatile("MRS %0, cpsr" : "=r" (result) ); |
kadonotakashi | 0:8fdf9a60065b | 498 | return(result); |
kadonotakashi | 0:8fdf9a60065b | 499 | } |
kadonotakashi | 0:8fdf9a60065b | 500 | |
kadonotakashi | 0:8fdf9a60065b | 501 | /** \brief Set CPSR Register |
kadonotakashi | 0:8fdf9a60065b | 502 | \param [in] cpsr CPSR value to set |
kadonotakashi | 0:8fdf9a60065b | 503 | */ |
kadonotakashi | 0:8fdf9a60065b | 504 | __STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) |
kadonotakashi | 0:8fdf9a60065b | 505 | { |
kadonotakashi | 0:8fdf9a60065b | 506 | __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); |
kadonotakashi | 0:8fdf9a60065b | 507 | } |
kadonotakashi | 0:8fdf9a60065b | 508 | |
kadonotakashi | 0:8fdf9a60065b | 509 | /** \brief Get Mode |
kadonotakashi | 0:8fdf9a60065b | 510 | \return Processor Mode |
kadonotakashi | 0:8fdf9a60065b | 511 | */ |
kadonotakashi | 0:8fdf9a60065b | 512 | __STATIC_FORCEINLINE uint32_t __get_mode(void) |
kadonotakashi | 0:8fdf9a60065b | 513 | { |
kadonotakashi | 0:8fdf9a60065b | 514 | return (__get_CPSR() & 0x1FU); |
kadonotakashi | 0:8fdf9a60065b | 515 | } |
kadonotakashi | 0:8fdf9a60065b | 516 | |
kadonotakashi | 0:8fdf9a60065b | 517 | /** \brief Set Mode |
kadonotakashi | 0:8fdf9a60065b | 518 | \param [in] mode Mode value to set |
kadonotakashi | 0:8fdf9a60065b | 519 | */ |
kadonotakashi | 0:8fdf9a60065b | 520 | __STATIC_FORCEINLINE void __set_mode(uint32_t mode) |
kadonotakashi | 0:8fdf9a60065b | 521 | { |
kadonotakashi | 0:8fdf9a60065b | 522 | __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); |
kadonotakashi | 0:8fdf9a60065b | 523 | } |
kadonotakashi | 0:8fdf9a60065b | 524 | |
kadonotakashi | 0:8fdf9a60065b | 525 | /** \brief Get Stack Pointer |
kadonotakashi | 0:8fdf9a60065b | 526 | \return Stack Pointer value |
kadonotakashi | 0:8fdf9a60065b | 527 | */ |
kadonotakashi | 0:8fdf9a60065b | 528 | __STATIC_FORCEINLINE uint32_t __get_SP(void) |
kadonotakashi | 0:8fdf9a60065b | 529 | { |
kadonotakashi | 0:8fdf9a60065b | 530 | uint32_t result; |
kadonotakashi | 0:8fdf9a60065b | 531 | __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); |
kadonotakashi | 0:8fdf9a60065b | 532 | return result; |
kadonotakashi | 0:8fdf9a60065b | 533 | } |
kadonotakashi | 0:8fdf9a60065b | 534 | |
kadonotakashi | 0:8fdf9a60065b | 535 | /** \brief Set Stack Pointer |
kadonotakashi | 0:8fdf9a60065b | 536 | \param [in] stack Stack Pointer value to set |
kadonotakashi | 0:8fdf9a60065b | 537 | */ |
kadonotakashi | 0:8fdf9a60065b | 538 | __STATIC_FORCEINLINE void __set_SP(uint32_t stack) |
kadonotakashi | 0:8fdf9a60065b | 539 | { |
kadonotakashi | 0:8fdf9a60065b | 540 | __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); |
kadonotakashi | 0:8fdf9a60065b | 541 | } |
kadonotakashi | 0:8fdf9a60065b | 542 | |
kadonotakashi | 0:8fdf9a60065b | 543 | /** \brief Get USR/SYS Stack Pointer |
kadonotakashi | 0:8fdf9a60065b | 544 | \return USR/SYS Stack Pointer value |
kadonotakashi | 0:8fdf9a60065b | 545 | */ |
kadonotakashi | 0:8fdf9a60065b | 546 | __STATIC_FORCEINLINE uint32_t __get_SP_usr(void) |
kadonotakashi | 0:8fdf9a60065b | 547 | { |
kadonotakashi | 0:8fdf9a60065b | 548 | uint32_t cpsr = __get_CPSR(); |
kadonotakashi | 0:8fdf9a60065b | 549 | uint32_t result; |
kadonotakashi | 0:8fdf9a60065b | 550 | __ASM volatile( |
kadonotakashi | 0:8fdf9a60065b | 551 | "CPS #0x1F \n" |
kadonotakashi | 0:8fdf9a60065b | 552 | "MOV %0, sp " : "=r"(result) : : "memory" |
kadonotakashi | 0:8fdf9a60065b | 553 | ); |
kadonotakashi | 0:8fdf9a60065b | 554 | __set_CPSR(cpsr); |
kadonotakashi | 0:8fdf9a60065b | 555 | __ISB(); |
kadonotakashi | 0:8fdf9a60065b | 556 | return result; |
kadonotakashi | 0:8fdf9a60065b | 557 | } |
kadonotakashi | 0:8fdf9a60065b | 558 | |
kadonotakashi | 0:8fdf9a60065b | 559 | /** \brief Set USR/SYS Stack Pointer |
kadonotakashi | 0:8fdf9a60065b | 560 | \param [in] topOfProcStack USR/SYS Stack Pointer value to set |
kadonotakashi | 0:8fdf9a60065b | 561 | */ |
kadonotakashi | 0:8fdf9a60065b | 562 | __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) |
kadonotakashi | 0:8fdf9a60065b | 563 | { |
kadonotakashi | 0:8fdf9a60065b | 564 | uint32_t cpsr = __get_CPSR(); |
kadonotakashi | 0:8fdf9a60065b | 565 | __ASM volatile( |
kadonotakashi | 0:8fdf9a60065b | 566 | "CPS #0x1F \n" |
kadonotakashi | 0:8fdf9a60065b | 567 | "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" |
kadonotakashi | 0:8fdf9a60065b | 568 | ); |
kadonotakashi | 0:8fdf9a60065b | 569 | __set_CPSR(cpsr); |
kadonotakashi | 0:8fdf9a60065b | 570 | __ISB(); |
kadonotakashi | 0:8fdf9a60065b | 571 | } |
kadonotakashi | 0:8fdf9a60065b | 572 | |
kadonotakashi | 0:8fdf9a60065b | 573 | /** \brief Get FPEXC |
kadonotakashi | 0:8fdf9a60065b | 574 | \return Floating Point Exception Control register value |
kadonotakashi | 0:8fdf9a60065b | 575 | */ |
kadonotakashi | 0:8fdf9a60065b | 576 | __STATIC_FORCEINLINE uint32_t __get_FPEXC(void) |
kadonotakashi | 0:8fdf9a60065b | 577 | { |
kadonotakashi | 0:8fdf9a60065b | 578 | #if (__FPU_PRESENT == 1) |
kadonotakashi | 0:8fdf9a60065b | 579 | uint32_t result; |
kadonotakashi | 0:8fdf9a60065b | 580 | __ASM volatile("VMRS %0, fpexc" : "=r" (result) ); |
kadonotakashi | 0:8fdf9a60065b | 581 | return(result); |
kadonotakashi | 0:8fdf9a60065b | 582 | #else |
kadonotakashi | 0:8fdf9a60065b | 583 | return(0); |
kadonotakashi | 0:8fdf9a60065b | 584 | #endif |
kadonotakashi | 0:8fdf9a60065b | 585 | } |
kadonotakashi | 0:8fdf9a60065b | 586 | |
kadonotakashi | 0:8fdf9a60065b | 587 | /** \brief Set FPEXC |
kadonotakashi | 0:8fdf9a60065b | 588 | \param [in] fpexc Floating Point Exception Control value to set |
kadonotakashi | 0:8fdf9a60065b | 589 | */ |
kadonotakashi | 0:8fdf9a60065b | 590 | __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) |
kadonotakashi | 0:8fdf9a60065b | 591 | { |
kadonotakashi | 0:8fdf9a60065b | 592 | #if (__FPU_PRESENT == 1) |
kadonotakashi | 0:8fdf9a60065b | 593 | __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); |
kadonotakashi | 0:8fdf9a60065b | 594 | #endif |
kadonotakashi | 0:8fdf9a60065b | 595 | } |
kadonotakashi | 0:8fdf9a60065b | 596 | |
kadonotakashi | 0:8fdf9a60065b | 597 | /* |
kadonotakashi | 0:8fdf9a60065b | 598 | * Include common core functions to access Coprocessor 15 registers |
kadonotakashi | 0:8fdf9a60065b | 599 | */ |
kadonotakashi | 0:8fdf9a60065b | 600 | |
kadonotakashi | 0:8fdf9a60065b | 601 | #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) |
kadonotakashi | 0:8fdf9a60065b | 602 | #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) |
kadonotakashi | 0:8fdf9a60065b | 603 | #define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) |
kadonotakashi | 0:8fdf9a60065b | 604 | #define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) |
kadonotakashi | 0:8fdf9a60065b | 605 | |
kadonotakashi | 0:8fdf9a60065b | 606 | #include "cmsis_cp15.h" |
kadonotakashi | 0:8fdf9a60065b | 607 | |
kadonotakashi | 0:8fdf9a60065b | 608 | /** \brief Enable Floating Point Unit |
kadonotakashi | 0:8fdf9a60065b | 609 | |
kadonotakashi | 0:8fdf9a60065b | 610 | Critical section, called from undef handler, so systick is disabled |
kadonotakashi | 0:8fdf9a60065b | 611 | */ |
kadonotakashi | 0:8fdf9a60065b | 612 | __STATIC_INLINE void __FPU_Enable(void) |
kadonotakashi | 0:8fdf9a60065b | 613 | { |
kadonotakashi | 0:8fdf9a60065b | 614 | __ASM volatile( |
kadonotakashi | 0:8fdf9a60065b | 615 | //Permit access to VFP/NEON, registers by modifying CPACR |
kadonotakashi | 0:8fdf9a60065b | 616 | " MRC p15,0,R1,c1,c0,2 \n" |
kadonotakashi | 0:8fdf9a60065b | 617 | " ORR R1,R1,#0x00F00000 \n" |
kadonotakashi | 0:8fdf9a60065b | 618 | " MCR p15,0,R1,c1,c0,2 \n" |
kadonotakashi | 0:8fdf9a60065b | 619 | |
kadonotakashi | 0:8fdf9a60065b | 620 | //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted |
kadonotakashi | 0:8fdf9a60065b | 621 | " ISB \n" |
kadonotakashi | 0:8fdf9a60065b | 622 | |
kadonotakashi | 0:8fdf9a60065b | 623 | //Enable VFP/NEON |
kadonotakashi | 0:8fdf9a60065b | 624 | " VMRS R1,FPEXC \n" |
kadonotakashi | 0:8fdf9a60065b | 625 | " ORR R1,R1,#0x40000000 \n" |
kadonotakashi | 0:8fdf9a60065b | 626 | " VMSR FPEXC,R1 \n" |
kadonotakashi | 0:8fdf9a60065b | 627 | |
kadonotakashi | 0:8fdf9a60065b | 628 | //Initialise VFP/NEON registers to 0 |
kadonotakashi | 0:8fdf9a60065b | 629 | " MOV R2,#0 \n" |
kadonotakashi | 0:8fdf9a60065b | 630 | |
kadonotakashi | 0:8fdf9a60065b | 631 | //Initialise D16 registers to 0 |
kadonotakashi | 0:8fdf9a60065b | 632 | " VMOV D0, R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 633 | " VMOV D1, R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 634 | " VMOV D2, R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 635 | " VMOV D3, R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 636 | " VMOV D4, R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 637 | " VMOV D5, R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 638 | " VMOV D6, R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 639 | " VMOV D7, R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 640 | " VMOV D8, R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 641 | " VMOV D9, R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 642 | " VMOV D10,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 643 | " VMOV D11,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 644 | " VMOV D12,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 645 | " VMOV D13,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 646 | " VMOV D14,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 647 | " VMOV D15,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 648 | |
kadonotakashi | 0:8fdf9a60065b | 649 | #if (defined(__ARM_NEON) && (__ARM_NEON == 1)) |
kadonotakashi | 0:8fdf9a60065b | 650 | //Initialise D32 registers to 0 |
kadonotakashi | 0:8fdf9a60065b | 651 | " VMOV D16,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 652 | " VMOV D17,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 653 | " VMOV D18,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 654 | " VMOV D19,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 655 | " VMOV D20,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 656 | " VMOV D21,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 657 | " VMOV D22,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 658 | " VMOV D23,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 659 | " VMOV D24,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 660 | " VMOV D25,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 661 | " VMOV D26,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 662 | " VMOV D27,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 663 | " VMOV D28,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 664 | " VMOV D29,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 665 | " VMOV D30,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 666 | " VMOV D31,R2,R2 \n" |
kadonotakashi | 0:8fdf9a60065b | 667 | #endif |
kadonotakashi | 0:8fdf9a60065b | 668 | |
kadonotakashi | 0:8fdf9a60065b | 669 | //Initialise FPSCR to a known state |
kadonotakashi | 0:8fdf9a60065b | 670 | " VMRS R2,FPSCR \n" |
kadonotakashi | 0:8fdf9a60065b | 671 | " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. |
kadonotakashi | 0:8fdf9a60065b | 672 | " AND R2,R2,R3 \n" |
kadonotakashi | 0:8fdf9a60065b | 673 | " VMSR FPSCR,R2 " |
kadonotakashi | 0:8fdf9a60065b | 674 | ); |
kadonotakashi | 0:8fdf9a60065b | 675 | } |
kadonotakashi | 0:8fdf9a60065b | 676 | |
kadonotakashi | 0:8fdf9a60065b | 677 | #pragma GCC diagnostic pop |
kadonotakashi | 0:8fdf9a60065b | 678 | |
kadonotakashi | 0:8fdf9a60065b | 679 | #endif /* __CMSIS_GCC_H */ |