takashi kadono
Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/ecap_reg.h@3:f3764f852aa8, 2018-10-11 (annotated)
- Committer:
- kadonotakashi
- Date:
- Thu Oct 11 02:27:46 2018 +0000
- Revision:
- 3:f3764f852aa8
- Parent:
- 0:8fdf9a60065b
Nucreo 446 + SSD1331 test version;
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| kadonotakashi | 0:8fdf9a60065b | 1 | /**************************************************************************//** |
| kadonotakashi | 0:8fdf9a60065b | 2 | * @file ecap_reg.h |
| kadonotakashi | 0:8fdf9a60065b | 3 | * @version V1.00 |
| kadonotakashi | 0:8fdf9a60065b | 4 | * @brief ECAP register definition header file |
| kadonotakashi | 0:8fdf9a60065b | 5 | * |
| kadonotakashi | 0:8fdf9a60065b | 6 | * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. |
| kadonotakashi | 0:8fdf9a60065b | 7 | *****************************************************************************/ |
| kadonotakashi | 0:8fdf9a60065b | 8 | #ifndef __ECAP_REG_H__ |
| kadonotakashi | 0:8fdf9a60065b | 9 | #define __ECAP_REG_H__ |
| kadonotakashi | 0:8fdf9a60065b | 10 | |
| kadonotakashi | 0:8fdf9a60065b | 11 | /*---------------------- Enhanced Input Capture Timer -------------------------*/ |
| kadonotakashi | 0:8fdf9a60065b | 12 | /** |
| kadonotakashi | 0:8fdf9a60065b | 13 | @addtogroup ECAP Enhanced Input Capture Timer(ECAP) |
| kadonotakashi | 0:8fdf9a60065b | 14 | Memory Mapped Structure for ECAP Controller |
| kadonotakashi | 0:8fdf9a60065b | 15 | @{ */ |
| kadonotakashi | 0:8fdf9a60065b | 16 | |
| kadonotakashi | 0:8fdf9a60065b | 17 | typedef struct |
| kadonotakashi | 0:8fdf9a60065b | 18 | { |
| kadonotakashi | 0:8fdf9a60065b | 19 | |
| kadonotakashi | 0:8fdf9a60065b | 20 | /** |
| kadonotakashi | 0:8fdf9a60065b | 21 | * @var ECAP_T::CNT |
| kadonotakashi | 0:8fdf9a60065b | 22 | * Offset: 0x00 Input Capture Counter (24-bit up counter) |
| kadonotakashi | 0:8fdf9a60065b | 23 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 24 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 25 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 26 | * |[23:0] |CNT |Input Capture Timer/Counter |
| kadonotakashi | 0:8fdf9a60065b | 27 | * | | |The input Capture Timer/Counter is a 24-bit up-counting counter |
| kadonotakashi | 0:8fdf9a60065b | 28 | * | | |The clock source for the counter is from the clock divider |
| kadonotakashi | 0:8fdf9a60065b | 29 | * @var ECAP_T::HLD0 |
| kadonotakashi | 0:8fdf9a60065b | 30 | * Offset: 0x04 Input Capture Hold Register 0 |
| kadonotakashi | 0:8fdf9a60065b | 31 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 32 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 33 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 34 | * |[23:0] |HOLD |Input Capture Counter Hold Register |
| kadonotakashi | 0:8fdf9a60065b | 35 | * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register |
| kadonotakashi | 0:8fdf9a60065b | 36 | * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. |
| kadonotakashi | 0:8fdf9a60065b | 37 | * @var ECAP_T::HLD1 |
| kadonotakashi | 0:8fdf9a60065b | 38 | * Offset: 0x08 Input Capture Hold Register 1 |
| kadonotakashi | 0:8fdf9a60065b | 39 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 40 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 41 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 42 | * |[23:0] |HOLD |Input Capture Counter Hold Register |
| kadonotakashi | 0:8fdf9a60065b | 43 | * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register |
| kadonotakashi | 0:8fdf9a60065b | 44 | * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. |
| kadonotakashi | 0:8fdf9a60065b | 45 | * @var ECAP_T::HLD2 |
| kadonotakashi | 0:8fdf9a60065b | 46 | * Offset: 0x0C Input Capture Hold Register 2 |
| kadonotakashi | 0:8fdf9a60065b | 47 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 48 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 49 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 50 | * |[23:0] |HOLD |Input Capture Counter Hold Register |
| kadonotakashi | 0:8fdf9a60065b | 51 | * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register |
| kadonotakashi | 0:8fdf9a60065b | 52 | * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. |
| kadonotakashi | 0:8fdf9a60065b | 53 | * @var ECAP_T::CNTCMP |
| kadonotakashi | 0:8fdf9a60065b | 54 | * Offset: 0x10 Input Capture Compare Register |
| kadonotakashi | 0:8fdf9a60065b | 55 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 56 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 57 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 58 | * |[23:0] |CNTCMP |Input Capture Counter Compare Register |
| kadonotakashi | 0:8fdf9a60065b | 59 | * | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT). |
| kadonotakashi | 0:8fdf9a60065b | 60 | * | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT. |
| kadonotakashi | 0:8fdf9a60065b | 61 | * @var ECAP_T::CTL0 |
| kadonotakashi | 0:8fdf9a60065b | 62 | * Offset: 0x14 Input Capture Control Register 0 |
| kadonotakashi | 0:8fdf9a60065b | 63 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 64 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 65 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 66 | * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection |
| kadonotakashi | 0:8fdf9a60065b | 67 | * | | |To determine the sampling frequency of the Noise Filter clock |
| kadonotakashi | 0:8fdf9a60065b | 68 | * | | |000 = CAP_CLK. |
| kadonotakashi | 0:8fdf9a60065b | 69 | * | | |001 = CAP_CLK/2. |
| kadonotakashi | 0:8fdf9a60065b | 70 | * | | |010 = CAP_CLK/4. |
| kadonotakashi | 0:8fdf9a60065b | 71 | * | | |011 = CAP_CLK/16. |
| kadonotakashi | 0:8fdf9a60065b | 72 | * | | |100 = CAP_CLK/32. |
| kadonotakashi | 0:8fdf9a60065b | 73 | * | | |101 = CAP_CLK/64. |
| kadonotakashi | 0:8fdf9a60065b | 74 | * |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control |
| kadonotakashi | 0:8fdf9a60065b | 75 | * | | |0 = Noise filter of Input Capture Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 76 | * | | |1 = Noise filter of Input Capture Disabled (Bypass). |
| kadonotakashi | 0:8fdf9a60065b | 77 | * |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 78 | * | | |0 = IC0 input to Input Capture Unit Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 79 | * | | |1 = IC0 input to Input Capture Unit Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 80 | * |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 81 | * | | |0 = IC1 input to Input Capture Unit Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 82 | * | | |1 = IC1 input to Input Capture Unit Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 83 | * |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 84 | * | | |0 = IC2 input to Input Capture Unit Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 85 | * | | |1 = IC2 input to Input Capture Unit Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 86 | * |[9:8] |CAPSEL0 |CAP0 Input Source Selection |
| kadonotakashi | 0:8fdf9a60065b | 87 | * | | |00 = CAP0 input is from port pin ICAP0. |
| kadonotakashi | 0:8fdf9a60065b | 88 | * | | |01 = Reserved. |
| kadonotakashi | 0:8fdf9a60065b | 89 | * | | |10 = CAP0 input is from signal CHA of QEI controller unit n. |
| kadonotakashi | 0:8fdf9a60065b | 90 | * | | |11 = Reserved. |
| kadonotakashi | 0:8fdf9a60065b | 91 | * | | |Note: Input capture unit n matches QEIn, where n = 0~1. |
| kadonotakashi | 0:8fdf9a60065b | 92 | * |[11:10] |CAPSEL1 |CAP1 Input Source Selection |
| kadonotakashi | 0:8fdf9a60065b | 93 | * | | |00 = CAP1 input is from port pin ICAP1. |
| kadonotakashi | 0:8fdf9a60065b | 94 | * | | |01 = Reserved. |
| kadonotakashi | 0:8fdf9a60065b | 95 | * | | |10 = CAP1 input is from signal CHB of QEI controller unit n. |
| kadonotakashi | 0:8fdf9a60065b | 96 | * | | |11 = Reserved. |
| kadonotakashi | 0:8fdf9a60065b | 97 | * | | |Note: Input capture unit n matches QEIn, where n = 0~1. |
| kadonotakashi | 0:8fdf9a60065b | 98 | * |[13:12] |CAPSEL2 |CAP2 Input Source Selection |
| kadonotakashi | 0:8fdf9a60065b | 99 | * | | |00 = CAP2 input is from port pin ICAP2. |
| kadonotakashi | 0:8fdf9a60065b | 100 | * | | |01 = Reserved. |
| kadonotakashi | 0:8fdf9a60065b | 101 | * | | |10 = CAP2 input is from signal CHX of QEI controller unit n. |
| kadonotakashi | 0:8fdf9a60065b | 102 | * | | |11 = Reserved. |
| kadonotakashi | 0:8fdf9a60065b | 103 | * | | |Note: Input capture unit n matches QEIn, where n = 0~1. |
| kadonotakashi | 0:8fdf9a60065b | 104 | * |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 105 | * | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 106 | * | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 107 | * |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 108 | * | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 109 | * | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 110 | * |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 111 | * | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 112 | * | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 113 | * |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 114 | * | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 115 | * | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 116 | * |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 117 | * | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 118 | * | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 119 | * |[24] |CNTEN |Input Capture Counter Start Counting Control |
| kadonotakashi | 0:8fdf9a60065b | 120 | * | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the . |
| kadonotakashi | 0:8fdf9a60065b | 121 | * | | |0 = ECAP_CNT stop counting. |
| kadonotakashi | 0:8fdf9a60065b | 122 | * | | |1 = ECAP_CNT starts up-counting. |
| kadonotakashi | 0:8fdf9a60065b | 123 | * |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control |
| kadonotakashi | 0:8fdf9a60065b | 124 | * | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs. |
| kadonotakashi | 0:8fdf9a60065b | 125 | * | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 126 | * | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 127 | * |[28] |CMPEN |Compare Function Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 128 | * | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set. |
| kadonotakashi | 0:8fdf9a60065b | 129 | * | | |0 = The compare function Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 130 | * | | |1 = The compare function Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 131 | * |[29] |CAPEN |Input Capture Timer/Counter Enable Control |
| kadonotakashi | 0:8fdf9a60065b | 132 | * | | |0 = Input Capture function Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 133 | * | | |1 = Input Capture function Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 134 | * @var ECAP_T::CTL1 |
| kadonotakashi | 0:8fdf9a60065b | 135 | * Offset: 0x18 Input Capture Control Register 1 |
| kadonotakashi | 0:8fdf9a60065b | 136 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 137 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 138 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 139 | * |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection |
| kadonotakashi | 0:8fdf9a60065b | 140 | * | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change |
| kadonotakashi | 0:8fdf9a60065b | 141 | * | | |00 = Detect rising edge only. |
| kadonotakashi | 0:8fdf9a60065b | 142 | * | | |01 = Detect falling edge only. |
| kadonotakashi | 0:8fdf9a60065b | 143 | * | | |1x = Detect both rising and falling edge. |
| kadonotakashi | 0:8fdf9a60065b | 144 | * |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection |
| kadonotakashi | 0:8fdf9a60065b | 145 | * | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change |
| kadonotakashi | 0:8fdf9a60065b | 146 | * | | |00 = Detect rising edge only. |
| kadonotakashi | 0:8fdf9a60065b | 147 | * | | |01 = Detect falling edge only. |
| kadonotakashi | 0:8fdf9a60065b | 148 | * | | |1x = Detect both rising and falling edge. |
| kadonotakashi | 0:8fdf9a60065b | 149 | * |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection |
| kadonotakashi | 0:8fdf9a60065b | 150 | * | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes |
| kadonotakashi | 0:8fdf9a60065b | 151 | * | | |00 = Detect rising edge only. |
| kadonotakashi | 0:8fdf9a60065b | 152 | * | | |01 = Detect falling edge only. |
| kadonotakashi | 0:8fdf9a60065b | 153 | * | | |1x = Detect both rising and falling edge. |
| kadonotakashi | 0:8fdf9a60065b | 154 | * |[8] |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 155 | * | | |0 = The reload triggered by Event CAPTE0 Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 156 | * | | |1 = The reload triggered by Event CAPTE0 Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 157 | * |[9] |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 158 | * | | |0 = The reload triggered by Event CAPTE1 Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 159 | * | | |1 = The reload triggered by Event CAPTE1 Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 160 | * |[10] |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 161 | * | | |0 = The reload triggered by Event CAPTE2 Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 162 | * | | |1 = The reload triggered by Event CAPTE2 Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 163 | * |[11] |OVRLDEN |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit |
| kadonotakashi | 0:8fdf9a60065b | 164 | * | | |0 = The reload triggered by CAPOV Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 165 | * | | |1 = The reload triggered by CAPOV Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 166 | * |[14:12] |CLKSEL |Capture Timer Clock Divide Selection |
| kadonotakashi | 0:8fdf9a60065b | 167 | * | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]. |
| kadonotakashi | 0:8fdf9a60065b | 168 | * | | |000 = CAP_CLK/1. |
| kadonotakashi | 0:8fdf9a60065b | 169 | * | | |001 = CAP_CLK/4. |
| kadonotakashi | 0:8fdf9a60065b | 170 | * | | |010 = CAP_CLK/16. |
| kadonotakashi | 0:8fdf9a60065b | 171 | * | | |011 = CAP_CLK/32. |
| kadonotakashi | 0:8fdf9a60065b | 172 | * | | |100 = CAP_CLK/64. |
| kadonotakashi | 0:8fdf9a60065b | 173 | * | | |101 = CAP_CLK/96. |
| kadonotakashi | 0:8fdf9a60065b | 174 | * | | |110 = CAP_CLK/112. |
| kadonotakashi | 0:8fdf9a60065b | 175 | * | | |111 = CAP_CLK/128. |
| kadonotakashi | 0:8fdf9a60065b | 176 | * |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection |
| kadonotakashi | 0:8fdf9a60065b | 177 | * | | |Select the capture timer/counter clock source. |
| kadonotakashi | 0:8fdf9a60065b | 178 | * | | |00 = CAP_CLK (default). |
| kadonotakashi | 0:8fdf9a60065b | 179 | * | | |01 = CAP0. |
| kadonotakashi | 0:8fdf9a60065b | 180 | * | | |10 = CAP1. |
| kadonotakashi | 0:8fdf9a60065b | 181 | * | | |11 = CAP2. |
| kadonotakashi | 0:8fdf9a60065b | 182 | * |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control |
| kadonotakashi | 0:8fdf9a60065b | 183 | * | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 184 | * | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 185 | * |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control |
| kadonotakashi | 0:8fdf9a60065b | 186 | * | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 187 | * | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 188 | * |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control |
| kadonotakashi | 0:8fdf9a60065b | 189 | * | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled. |
| kadonotakashi | 0:8fdf9a60065b | 190 | * | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled. |
| kadonotakashi | 0:8fdf9a60065b | 191 | * @var ECAP_T::STATUS |
| kadonotakashi | 0:8fdf9a60065b | 192 | * Offset: 0x1C Input Capture Status Register |
| kadonotakashi | 0:8fdf9a60065b | 193 | * --------------------------------------------------------------------------------------------------- |
| kadonotakashi | 0:8fdf9a60065b | 194 | * |Bits |Field |Descriptions |
| kadonotakashi | 0:8fdf9a60065b | 195 | * | :----: | :----: | :---- | |
| kadonotakashi | 0:8fdf9a60065b | 196 | * |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag |
| kadonotakashi | 0:8fdf9a60065b | 197 | * | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. |
| kadonotakashi | 0:8fdf9a60065b | 198 | * | | |0 = No valid edge change has been detected at CAP0 input since last clear. |
| kadonotakashi | 0:8fdf9a60065b | 199 | * | | |1 = At least a valid edge change has been detected at CAP0 input since last clear. |
| kadonotakashi | 0:8fdf9a60065b | 200 | * | | |Note: This bit is only cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 201 | * |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag |
| kadonotakashi | 0:8fdf9a60065b | 202 | * | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. |
| kadonotakashi | 0:8fdf9a60065b | 203 | * | | |0 = No valid edge change has been detected at CAP1 input since last clear. |
| kadonotakashi | 0:8fdf9a60065b | 204 | * | | |1 = At least a valid edge change has been detected at CAP1 input since last clear. |
| kadonotakashi | 0:8fdf9a60065b | 205 | * | | |Note: This bit is only cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 206 | * |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag |
| kadonotakashi | 0:8fdf9a60065b | 207 | * | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. |
| kadonotakashi | 0:8fdf9a60065b | 208 | * | | |0 = No valid edge change has been detected at CAP2 input since last clear. |
| kadonotakashi | 0:8fdf9a60065b | 209 | * | | |1 = At least a valid edge change has been detected at CAP2 input since last clear. |
| kadonotakashi | 0:8fdf9a60065b | 210 | * | | |Note: This bit is only cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 211 | * |[4] |CAPCMPF |Input Capture Compare-match Flag |
| kadonotakashi | 0:8fdf9a60065b | 212 | * | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value. |
| kadonotakashi | 0:8fdf9a60065b | 213 | * | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear. |
| kadonotakashi | 0:8fdf9a60065b | 214 | * | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear. |
| kadonotakashi | 0:8fdf9a60065b | 215 | * | | |Note: This bit is only cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 216 | * |[5] |CAPOVF |Input Capture Counter Overflow Flag |
| kadonotakashi | 0:8fdf9a60065b | 217 | * | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero. |
| kadonotakashi | 0:8fdf9a60065b | 218 | * | | |0 = No overflow event has occurred since last clear. |
| kadonotakashi | 0:8fdf9a60065b | 219 | * | | |1 = Overflow event(s) has/have occurred since last clear. |
| kadonotakashi | 0:8fdf9a60065b | 220 | * | | |Note: This bit is only cleared by writing 1 to it. |
| kadonotakashi | 0:8fdf9a60065b | 221 | * |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 222 | * | | |Reflecting the value of input channel 0, CAP0 |
| kadonotakashi | 0:8fdf9a60065b | 223 | * | | |(The bit is read only and write is ignored) |
| kadonotakashi | 0:8fdf9a60065b | 224 | * |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 225 | * | | |Reflecting the value of input channel 1, CAP1 |
| kadonotakashi | 0:8fdf9a60065b | 226 | * | | |(The bit is read only and write is ignored) |
| kadonotakashi | 0:8fdf9a60065b | 227 | * |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only) |
| kadonotakashi | 0:8fdf9a60065b | 228 | * | | |Reflecting the value of input channel 2, CAP2. |
| kadonotakashi | 0:8fdf9a60065b | 229 | * | | |(The bit is read only and write is ignored) |
| kadonotakashi | 0:8fdf9a60065b | 230 | */ |
| kadonotakashi | 0:8fdf9a60065b | 231 | __IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */ |
| kadonotakashi | 0:8fdf9a60065b | 232 | __IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */ |
| kadonotakashi | 0:8fdf9a60065b | 233 | __IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */ |
| kadonotakashi | 0:8fdf9a60065b | 234 | __IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */ |
| kadonotakashi | 0:8fdf9a60065b | 235 | __IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */ |
| kadonotakashi | 0:8fdf9a60065b | 236 | __IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */ |
| kadonotakashi | 0:8fdf9a60065b | 237 | __IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */ |
| kadonotakashi | 0:8fdf9a60065b | 238 | __IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */ |
| kadonotakashi | 0:8fdf9a60065b | 239 | |
| kadonotakashi | 0:8fdf9a60065b | 240 | } ECAP_T; |
| kadonotakashi | 0:8fdf9a60065b | 241 | |
| kadonotakashi | 0:8fdf9a60065b | 242 | /** |
| kadonotakashi | 0:8fdf9a60065b | 243 | @addtogroup ECAP_CONST ECAP Bit Field Definition |
| kadonotakashi | 0:8fdf9a60065b | 244 | Constant Definitions for ECAP Controller |
| kadonotakashi | 0:8fdf9a60065b | 245 | @{ */ |
| kadonotakashi | 0:8fdf9a60065b | 246 | |
| kadonotakashi | 0:8fdf9a60065b | 247 | #define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */ |
| kadonotakashi | 0:8fdf9a60065b | 248 | #define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 249 | |
| kadonotakashi | 0:8fdf9a60065b | 250 | #define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */ |
| kadonotakashi | 0:8fdf9a60065b | 251 | #define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 252 | |
| kadonotakashi | 0:8fdf9a60065b | 253 | #define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */ |
| kadonotakashi | 0:8fdf9a60065b | 254 | #define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 255 | |
| kadonotakashi | 0:8fdf9a60065b | 256 | #define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */ |
| kadonotakashi | 0:8fdf9a60065b | 257 | #define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 258 | |
| kadonotakashi | 0:8fdf9a60065b | 259 | #define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */ |
| kadonotakashi | 0:8fdf9a60065b | 260 | #define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 261 | |
| kadonotakashi | 0:8fdf9a60065b | 262 | #define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 263 | #define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 264 | |
| kadonotakashi | 0:8fdf9a60065b | 265 | #define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */ |
| kadonotakashi | 0:8fdf9a60065b | 266 | #define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 267 | |
| kadonotakashi | 0:8fdf9a60065b | 268 | #define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 269 | #define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 270 | |
| kadonotakashi | 0:8fdf9a60065b | 271 | #define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 272 | #define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 273 | |
| kadonotakashi | 0:8fdf9a60065b | 274 | #define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 275 | #define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 276 | |
| kadonotakashi | 0:8fdf9a60065b | 277 | #define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 278 | #define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 279 | |
| kadonotakashi | 0:8fdf9a60065b | 280 | #define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 281 | #define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 282 | |
| kadonotakashi | 0:8fdf9a60065b | 283 | #define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 284 | #define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 285 | |
| kadonotakashi | 0:8fdf9a60065b | 286 | #define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 287 | #define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 288 | |
| kadonotakashi | 0:8fdf9a60065b | 289 | #define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 290 | #define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 291 | |
| kadonotakashi | 0:8fdf9a60065b | 292 | #define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 293 | #define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 294 | |
| kadonotakashi | 0:8fdf9a60065b | 295 | #define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 296 | #define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 297 | |
| kadonotakashi | 0:8fdf9a60065b | 298 | #define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 299 | #define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 300 | |
| kadonotakashi | 0:8fdf9a60065b | 301 | #define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 302 | #define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 303 | |
| kadonotakashi | 0:8fdf9a60065b | 304 | #define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 305 | #define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 306 | |
| kadonotakashi | 0:8fdf9a60065b | 307 | #define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 308 | #define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 309 | |
| kadonotakashi | 0:8fdf9a60065b | 310 | #define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 311 | #define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 312 | |
| kadonotakashi | 0:8fdf9a60065b | 313 | #define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 314 | #define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 315 | |
| kadonotakashi | 0:8fdf9a60065b | 316 | #define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 317 | #define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 318 | |
| kadonotakashi | 0:8fdf9a60065b | 319 | #define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 320 | #define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 321 | |
| kadonotakashi | 0:8fdf9a60065b | 322 | #define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 323 | #define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 324 | |
| kadonotakashi | 0:8fdf9a60065b | 325 | #define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 326 | #define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 327 | |
| kadonotakashi | 0:8fdf9a60065b | 328 | #define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 329 | #define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 330 | |
| kadonotakashi | 0:8fdf9a60065b | 331 | #define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 332 | #define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 333 | |
| kadonotakashi | 0:8fdf9a60065b | 334 | #define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 335 | #define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 336 | |
| kadonotakashi | 0:8fdf9a60065b | 337 | #define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */ |
| kadonotakashi | 0:8fdf9a60065b | 338 | #define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 339 | |
| kadonotakashi | 0:8fdf9a60065b | 340 | #define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 341 | #define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 342 | |
| kadonotakashi | 0:8fdf9a60065b | 343 | #define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 344 | #define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 345 | |
| kadonotakashi | 0:8fdf9a60065b | 346 | #define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */ |
| kadonotakashi | 0:8fdf9a60065b | 347 | #define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 348 | |
| kadonotakashi | 0:8fdf9a60065b | 349 | #define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 350 | #define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 351 | |
| kadonotakashi | 0:8fdf9a60065b | 352 | #define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 353 | #define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 354 | |
| kadonotakashi | 0:8fdf9a60065b | 355 | #define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 356 | #define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 357 | |
| kadonotakashi | 0:8fdf9a60065b | 358 | #define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 359 | #define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 360 | |
| kadonotakashi | 0:8fdf9a60065b | 361 | #define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */ |
| kadonotakashi | 0:8fdf9a60065b | 362 | #define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 363 | |
| kadonotakashi | 0:8fdf9a60065b | 364 | #define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 365 | #define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 366 | |
| kadonotakashi | 0:8fdf9a60065b | 367 | #define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 368 | #define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 369 | |
| kadonotakashi | 0:8fdf9a60065b | 370 | #define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */ |
| kadonotakashi | 0:8fdf9a60065b | 371 | #define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */ |
| kadonotakashi | 0:8fdf9a60065b | 372 | |
| kadonotakashi | 0:8fdf9a60065b | 373 | /**@}*/ /* ECAP_CONST */ |
| kadonotakashi | 0:8fdf9a60065b | 374 | /**@}*/ /* end of ECAP register group */ |
| kadonotakashi | 0:8fdf9a60065b | 375 | |
| kadonotakashi | 0:8fdf9a60065b | 376 | |
| kadonotakashi | 0:8fdf9a60065b | 377 | #endif /* __ECAP_REG_H__ */ |