takashi kadono / Mbed OS Nucleo446_SSD1331

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_sdhc.h@0:8fdf9a60065b, 2018-10-10 (annotated)

Committer:
kadonotakashi
Date:
Wed Oct 10 00:33:53 2018 +0000
Revision:
0:8fdf9a60065b
how to make mbed librry

Who changed what in which revision?

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kadonotakashi 0:8fdf9a60065b 1 /*
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
kadonotakashi 0:8fdf9a60065b 3 * All rights reserved.
kadonotakashi 0:8fdf9a60065b 4 *
kadonotakashi 0:8fdf9a60065b 5 * Redistribution and use in source and binary forms, with or without modification,
kadonotakashi 0:8fdf9a60065b 6 * are permitted provided that the following conditions are met:
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * o Redistributions of source code must retain the above copyright notice, this list
kadonotakashi 0:8fdf9a60065b 9 * of conditions and the following disclaimer.
kadonotakashi 0:8fdf9a60065b 10 *
kadonotakashi 0:8fdf9a60065b 11 * o Redistributions in binary form must reproduce the above copyright notice, this
kadonotakashi 0:8fdf9a60065b 12 * list of conditions and the following disclaimer in the documentation and/or
kadonotakashi 0:8fdf9a60065b 13 * other materials provided with the distribution.
kadonotakashi 0:8fdf9a60065b 14 *
kadonotakashi 0:8fdf9a60065b 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
kadonotakashi 0:8fdf9a60065b 16 * contributors may be used to endorse or promote products derived from this
kadonotakashi 0:8fdf9a60065b 17 * software without specific prior written permission.
kadonotakashi 0:8fdf9a60065b 18 *
kadonotakashi 0:8fdf9a60065b 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
kadonotakashi 0:8fdf9a60065b 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
kadonotakashi 0:8fdf9a60065b 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
kadonotakashi 0:8fdf9a60065b 22 * DISCLAIMED. IN NO EVENT SL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
kadonotakashi 0:8fdf9a60065b 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
kadonotakashi 0:8fdf9a60065b 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
kadonotakashi 0:8fdf9a60065b 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
kadonotakashi 0:8fdf9a60065b 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
kadonotakashi 0:8fdf9a60065b 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
kadonotakashi 0:8fdf9a60065b 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
kadonotakashi 0:8fdf9a60065b 29 */
kadonotakashi 0:8fdf9a60065b 30 #ifndef _FSL_SDHC_H_
kadonotakashi 0:8fdf9a60065b 31 #define _FSL_SDHC_H_
kadonotakashi 0:8fdf9a60065b 32
kadonotakashi 0:8fdf9a60065b 33 #include "fsl_common.h"
kadonotakashi 0:8fdf9a60065b 34
kadonotakashi 0:8fdf9a60065b 35 /*!
kadonotakashi 0:8fdf9a60065b 36 * @addtogroup sdhc
kadonotakashi 0:8fdf9a60065b 37 * @{
kadonotakashi 0:8fdf9a60065b 38 */
kadonotakashi 0:8fdf9a60065b 39
kadonotakashi 0:8fdf9a60065b 40 /******************************************************************************
kadonotakashi 0:8fdf9a60065b 41 * Definitions.
kadonotakashi 0:8fdf9a60065b 42 *****************************************************************************/
kadonotakashi 0:8fdf9a60065b 43
kadonotakashi 0:8fdf9a60065b 44 /*! @name Driver version */
kadonotakashi 0:8fdf9a60065b 45 /*@{*/
kadonotakashi 0:8fdf9a60065b 46 /*! @brief Driver version 2.1.2. */
kadonotakashi 0:8fdf9a60065b 47 #define FSL_SDHC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 2U))
kadonotakashi 0:8fdf9a60065b 48 /*@}*/
kadonotakashi 0:8fdf9a60065b 49
kadonotakashi 0:8fdf9a60065b 50 /*! @brief Maximum block count can be set one time */
kadonotakashi 0:8fdf9a60065b 51 #define SDHC_MAX_BLOCK_COUNT (SDHC_BLKATTR_BLKCNT_MASK >> SDHC_BLKATTR_BLKCNT_SHIFT)
kadonotakashi 0:8fdf9a60065b 52
kadonotakashi 0:8fdf9a60065b 53 /*! @brief SDHC status */
kadonotakashi 0:8fdf9a60065b 54 enum _sdhc_status
kadonotakashi 0:8fdf9a60065b 55 {
kadonotakashi 0:8fdf9a60065b 56 kStatus_SDHC_BusyTransferring = MAKE_STATUS(kStatusGroup_SDHC, 0U), /*!< Transfer is on-going */
kadonotakashi 0:8fdf9a60065b 57 kStatus_SDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_SDHC, 1U), /*!< Set DMA descriptor failed */
kadonotakashi 0:8fdf9a60065b 58 kStatus_SDHC_SendCommandFailed = MAKE_STATUS(kStatusGroup_SDHC, 2U), /*!< Send command failed */
kadonotakashi 0:8fdf9a60065b 59 kStatus_SDHC_TransferDataFailed = MAKE_STATUS(kStatusGroup_SDHC, 3U), /*!< Transfer data failed */
kadonotakashi 0:8fdf9a60065b 60 };
kadonotakashi 0:8fdf9a60065b 61
kadonotakashi 0:8fdf9a60065b 62 /*! @brief Host controller capabilities flag mask */
kadonotakashi 0:8fdf9a60065b 63 enum _sdhc_capability_flag
kadonotakashi 0:8fdf9a60065b 64 {
kadonotakashi 0:8fdf9a60065b 65 kSDHC_SupportAdmaFlag = SDHC_HTCAPBLT_ADMAS_MASK, /*!< Support ADMA */
kadonotakashi 0:8fdf9a60065b 66 kSDHC_SupportHighSpeedFlag = SDHC_HTCAPBLT_HSS_MASK, /*!< Support high-speed */
kadonotakashi 0:8fdf9a60065b 67 kSDHC_SupportDmaFlag = SDHC_HTCAPBLT_DMAS_MASK, /*!< Support DMA */
kadonotakashi 0:8fdf9a60065b 68 kSDHC_SupportSuspendResumeFlag = SDHC_HTCAPBLT_SRS_MASK, /*!< Support suspend/resume */
kadonotakashi 0:8fdf9a60065b 69 kSDHC_SupportV330Flag = SDHC_HTCAPBLT_VS33_MASK, /*!< Support voltage 3.3V */
kadonotakashi 0:8fdf9a60065b 70 #if defined FSL_FEATURE_SDHC_HAS_V300_SUPPORT && FSL_FEATURE_SDHC_HAS_V300_SUPPORT
kadonotakashi 0:8fdf9a60065b 71 kSDHC_SupportV300Flag = SDHC_HTCAPBLT_VS30_MASK, /*!< Support voltage 3.0V */
kadonotakashi 0:8fdf9a60065b 72 #endif
kadonotakashi 0:8fdf9a60065b 73 #if defined FSL_FEATURE_SDHC_HAS_V180_SUPPORT && FSL_FEATURE_SDHC_HAS_V180_SUPPORT
kadonotakashi 0:8fdf9a60065b 74 kSDHC_SupportV180Flag = SDHC_HTCAPBLT_VS18_MASK, /*!< Support voltage 1.8V */
kadonotakashi 0:8fdf9a60065b 75 #endif
kadonotakashi 0:8fdf9a60065b 76 /* Put additional two flags in HTCAPBLT_MBL's position. */
kadonotakashi 0:8fdf9a60065b 77 kSDHC_Support4BitFlag = (SDHC_HTCAPBLT_MBL_SHIFT << 0U), /*!< Support 4 bit mode */
kadonotakashi 0:8fdf9a60065b 78 kSDHC_Support8BitFlag = (SDHC_HTCAPBLT_MBL_SHIFT << 1U), /*!< Support 8 bit mode */
kadonotakashi 0:8fdf9a60065b 79 };
kadonotakashi 0:8fdf9a60065b 80
kadonotakashi 0:8fdf9a60065b 81 /*! @brief Wakeup event mask */
kadonotakashi 0:8fdf9a60065b 82 enum _sdhc_wakeup_event
kadonotakashi 0:8fdf9a60065b 83 {
kadonotakashi 0:8fdf9a60065b 84 kSDHC_WakeupEventOnCardInt = SDHC_PROCTL_WECINT_MASK, /*!< Wakeup on card interrupt */
kadonotakashi 0:8fdf9a60065b 85 kSDHC_WakeupEventOnCardInsert = SDHC_PROCTL_WECINS_MASK, /*!< Wakeup on card insertion */
kadonotakashi 0:8fdf9a60065b 86 kSDHC_WakeupEventOnCardRemove = SDHC_PROCTL_WECRM_MASK, /*!< Wakeup on card removal */
kadonotakashi 0:8fdf9a60065b 87
kadonotakashi 0:8fdf9a60065b 88 kSDHC_WakeupEventsAll = (kSDHC_WakeupEventOnCardInt | kSDHC_WakeupEventOnCardInsert |
kadonotakashi 0:8fdf9a60065b 89 kSDHC_WakeupEventOnCardRemove), /*!< All wakeup events */
kadonotakashi 0:8fdf9a60065b 90 };
kadonotakashi 0:8fdf9a60065b 91
kadonotakashi 0:8fdf9a60065b 92 /*! @brief Reset type mask */
kadonotakashi 0:8fdf9a60065b 93 enum _sdhc_reset
kadonotakashi 0:8fdf9a60065b 94 {
kadonotakashi 0:8fdf9a60065b 95 kSDHC_ResetAll = SDHC_SYSCTL_RSTA_MASK, /*!< Reset all except card detection */
kadonotakashi 0:8fdf9a60065b 96 kSDHC_ResetCommand = SDHC_SYSCTL_RSTC_MASK, /*!< Reset command line */
kadonotakashi 0:8fdf9a60065b 97 kSDHC_ResetData = SDHC_SYSCTL_RSTD_MASK, /*!< Reset data line */
kadonotakashi 0:8fdf9a60065b 98
kadonotakashi 0:8fdf9a60065b 99 kSDHC_ResetsAll = (kSDHC_ResetAll | kSDHC_ResetCommand | kSDHC_ResetData), /*!< All reset types */
kadonotakashi 0:8fdf9a60065b 100 };
kadonotakashi 0:8fdf9a60065b 101
kadonotakashi 0:8fdf9a60065b 102 /*! @brief Transfer flag mask */
kadonotakashi 0:8fdf9a60065b 103 enum _sdhc_transfer_flag
kadonotakashi 0:8fdf9a60065b 104 {
kadonotakashi 0:8fdf9a60065b 105 kSDHC_EnableDmaFlag = SDHC_XFERTYP_DMAEN_MASK, /*!< Enable DMA */
kadonotakashi 0:8fdf9a60065b 106
kadonotakashi 0:8fdf9a60065b 107 kSDHC_CommandTypeSuspendFlag = (SDHC_XFERTYP_CMDTYP(1U)), /*!< Suspend command */
kadonotakashi 0:8fdf9a60065b 108 kSDHC_CommandTypeResumeFlag = (SDHC_XFERTYP_CMDTYP(2U)), /*!< Resume command */
kadonotakashi 0:8fdf9a60065b 109 kSDHC_CommandTypeAbortFlag = (SDHC_XFERTYP_CMDTYP(3U)), /*!< Abort command */
kadonotakashi 0:8fdf9a60065b 110
kadonotakashi 0:8fdf9a60065b 111 kSDHC_EnableBlockCountFlag = SDHC_XFERTYP_BCEN_MASK, /*!< Enable block count */
kadonotakashi 0:8fdf9a60065b 112 kSDHC_EnableAutoCommand12Flag = SDHC_XFERTYP_AC12EN_MASK, /*!< Enable auto CMD12 */
kadonotakashi 0:8fdf9a60065b 113 kSDHC_DataReadFlag = SDHC_XFERTYP_DTDSEL_MASK, /*!< Enable data read */
kadonotakashi 0:8fdf9a60065b 114 kSDHC_MultipleBlockFlag = SDHC_XFERTYP_MSBSEL_MASK, /*!< Multiple block data read/write */
kadonotakashi 0:8fdf9a60065b 115
kadonotakashi 0:8fdf9a60065b 116 kSDHC_ResponseLength136Flag = SDHC_XFERTYP_RSPTYP(1U), /*!< 136 bit response length */
kadonotakashi 0:8fdf9a60065b 117 kSDHC_ResponseLength48Flag = SDHC_XFERTYP_RSPTYP(2U), /*!< 48 bit response length */
kadonotakashi 0:8fdf9a60065b 118 kSDHC_ResponseLength48BusyFlag = SDHC_XFERTYP_RSPTYP(3U), /*!< 48 bit response length with busy status */
kadonotakashi 0:8fdf9a60065b 119
kadonotakashi 0:8fdf9a60065b 120 kSDHC_EnableCrcCheckFlag = SDHC_XFERTYP_CCCEN_MASK, /*!< Enable CRC check */
kadonotakashi 0:8fdf9a60065b 121 kSDHC_EnableIndexCheckFlag = SDHC_XFERTYP_CICEN_MASK, /*!< Enable index check */
kadonotakashi 0:8fdf9a60065b 122 kSDHC_DataPresentFlag = SDHC_XFERTYP_DPSEL_MASK, /*!< Data present flag */
kadonotakashi 0:8fdf9a60065b 123 };
kadonotakashi 0:8fdf9a60065b 124
kadonotakashi 0:8fdf9a60065b 125 /*! @brief Present status flag mask */
kadonotakashi 0:8fdf9a60065b 126 enum _sdhc_present_status_flag
kadonotakashi 0:8fdf9a60065b 127 {
kadonotakashi 0:8fdf9a60065b 128 kSDHC_CommandInhibitFlag = SDHC_PRSSTAT_CIHB_MASK, /*!< Command inhibit */
kadonotakashi 0:8fdf9a60065b 129 kSDHC_DataInhibitFlag = SDHC_PRSSTAT_CDIHB_MASK, /*!< Data inhibit */
kadonotakashi 0:8fdf9a60065b 130 kSDHC_DataLineActiveFlag = SDHC_PRSSTAT_DLA_MASK, /*!< Data line active */
kadonotakashi 0:8fdf9a60065b 131 kSDHC_SdClockStableFlag = SDHC_PRSSTAT_SDSTB_MASK, /*!< SD bus clock stable */
kadonotakashi 0:8fdf9a60065b 132 kSDHC_WriteTransferActiveFlag = SDHC_PRSSTAT_WTA_MASK, /*!< Write transfer active */
kadonotakashi 0:8fdf9a60065b 133 kSDHC_ReadTransferActiveFlag = SDHC_PRSSTAT_RTA_MASK, /*!< Read transfer active */
kadonotakashi 0:8fdf9a60065b 134 kSDHC_BufferWriteEnableFlag = SDHC_PRSSTAT_BWEN_MASK, /*!< Buffer write enable */
kadonotakashi 0:8fdf9a60065b 135 kSDHC_BufferReadEnableFlag = SDHC_PRSSTAT_BREN_MASK, /*!< Buffer read enable */
kadonotakashi 0:8fdf9a60065b 136 kSDHC_CardInsertedFlag = SDHC_PRSSTAT_CINS_MASK, /*!< Card inserted */
kadonotakashi 0:8fdf9a60065b 137 kSDHC_CommandLineLevelFlag = SDHC_PRSSTAT_CLSL_MASK, /*!< Command line signal level */
kadonotakashi 0:8fdf9a60065b 138 kSDHC_Data0LineLevelFlag = (1U << 24U), /*!< Data0 line signal level */
kadonotakashi 0:8fdf9a60065b 139 kSDHC_Data1LineLevelFlag = (1U << 25U), /*!< Data1 line signal level */
kadonotakashi 0:8fdf9a60065b 140 kSDHC_Data2LineLevelFlag = (1U << 26U), /*!< Data2 line signal level */
kadonotakashi 0:8fdf9a60065b 141 kSDHC_Data3LineLevelFlag = (1U << 27U), /*!< Data3 line signal level */
kadonotakashi 0:8fdf9a60065b 142 kSDHC_Data4LineLevelFlag = (1U << 28U), /*!< Data4 line signal level */
kadonotakashi 0:8fdf9a60065b 143 kSDHC_Data5LineLevelFlag = (1U << 29U), /*!< Data5 line signal level */
kadonotakashi 0:8fdf9a60065b 144 kSDHC_Data6LineLevelFlag = (1U << 30U), /*!< Data6 line signal level */
kadonotakashi 0:8fdf9a60065b 145 kSDHC_Data7LineLevelFlag = (1U << 31U), /*!< Data7 line signal level */
kadonotakashi 0:8fdf9a60065b 146 };
kadonotakashi 0:8fdf9a60065b 147
kadonotakashi 0:8fdf9a60065b 148 /*! @brief Interrupt status flag mask */
kadonotakashi 0:8fdf9a60065b 149 enum _sdhc_interrupt_status_flag
kadonotakashi 0:8fdf9a60065b 150 {
kadonotakashi 0:8fdf9a60065b 151 kSDHC_CommandCompleteFlag = SDHC_IRQSTAT_CC_MASK, /*!< Command complete */
kadonotakashi 0:8fdf9a60065b 152 kSDHC_DataCompleteFlag = SDHC_IRQSTAT_TC_MASK, /*!< Data complete */
kadonotakashi 0:8fdf9a60065b 153 kSDHC_BlockGapEventFlag = SDHC_IRQSTAT_BGE_MASK, /*!< Block gap event */
kadonotakashi 0:8fdf9a60065b 154 kSDHC_DmaCompleteFlag = SDHC_IRQSTAT_DINT_MASK, /*!< DMA interrupt */
kadonotakashi 0:8fdf9a60065b 155 kSDHC_BufferWriteReadyFlag = SDHC_IRQSTAT_BWR_MASK, /*!< Buffer write ready */
kadonotakashi 0:8fdf9a60065b 156 kSDHC_BufferReadReadyFlag = SDHC_IRQSTAT_BRR_MASK, /*!< Buffer read ready */
kadonotakashi 0:8fdf9a60065b 157 kSDHC_CardInsertionFlag = SDHC_IRQSTAT_CINS_MASK, /*!< Card inserted */
kadonotakashi 0:8fdf9a60065b 158 kSDHC_CardRemovalFlag = SDHC_IRQSTAT_CRM_MASK, /*!< Card removed */
kadonotakashi 0:8fdf9a60065b 159 kSDHC_CardInterruptFlag = SDHC_IRQSTAT_CINT_MASK, /*!< Card interrupt */
kadonotakashi 0:8fdf9a60065b 160 kSDHC_CommandTimeoutFlag = SDHC_IRQSTAT_CTOE_MASK, /*!< Command timeout error */
kadonotakashi 0:8fdf9a60065b 161 kSDHC_CommandCrcErrorFlag = SDHC_IRQSTAT_CCE_MASK, /*!< Command CRC error */
kadonotakashi 0:8fdf9a60065b 162 kSDHC_CommandEndBitErrorFlag = SDHC_IRQSTAT_CEBE_MASK, /*!< Command end bit error */
kadonotakashi 0:8fdf9a60065b 163 kSDHC_CommandIndexErrorFlag = SDHC_IRQSTAT_CIE_MASK, /*!< Command index error */
kadonotakashi 0:8fdf9a60065b 164 kSDHC_DataTimeoutFlag = SDHC_IRQSTAT_DTOE_MASK, /*!< Data timeout error */
kadonotakashi 0:8fdf9a60065b 165 kSDHC_DataCrcErrorFlag = SDHC_IRQSTAT_DCE_MASK, /*!< Data CRC error */
kadonotakashi 0:8fdf9a60065b 166 kSDHC_DataEndBitErrorFlag = SDHC_IRQSTAT_DEBE_MASK, /*!< Data end bit error */
kadonotakashi 0:8fdf9a60065b 167 kSDHC_AutoCommand12ErrorFlag = SDHC_IRQSTAT_AC12E_MASK, /*!< Auto CMD12 error */
kadonotakashi 0:8fdf9a60065b 168 kSDHC_DmaErrorFlag = SDHC_IRQSTAT_DMAE_MASK, /*!< DMA error */
kadonotakashi 0:8fdf9a60065b 169
kadonotakashi 0:8fdf9a60065b 170 kSDHC_CommandErrorFlag = (kSDHC_CommandTimeoutFlag | kSDHC_CommandCrcErrorFlag | kSDHC_CommandEndBitErrorFlag |
kadonotakashi 0:8fdf9a60065b 171 kSDHC_CommandIndexErrorFlag), /*!< Command error */
kadonotakashi 0:8fdf9a60065b 172 kSDHC_DataErrorFlag = (kSDHC_DataTimeoutFlag | kSDHC_DataCrcErrorFlag | kSDHC_DataEndBitErrorFlag |
kadonotakashi 0:8fdf9a60065b 173 kSDHC_AutoCommand12ErrorFlag), /*!< Data error */
kadonotakashi 0:8fdf9a60065b 174 kSDHC_ErrorFlag = (kSDHC_CommandErrorFlag | kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag), /*!< All error */
kadonotakashi 0:8fdf9a60065b 175 kSDHC_DataFlag = (kSDHC_DataCompleteFlag | kSDHC_DmaCompleteFlag | kSDHC_BufferWriteReadyFlag |
kadonotakashi 0:8fdf9a60065b 176 kSDHC_BufferReadReadyFlag | kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag), /*!< Data interrupts */
kadonotakashi 0:8fdf9a60065b 177 kSDHC_CommandFlag = (kSDHC_CommandErrorFlag | kSDHC_CommandCompleteFlag), /*!< Command interrupts */
kadonotakashi 0:8fdf9a60065b 178 kSDHC_CardDetectFlag = (kSDHC_CardInsertionFlag | kSDHC_CardRemovalFlag), /*!< Card detection interrupts */
kadonotakashi 0:8fdf9a60065b 179
kadonotakashi 0:8fdf9a60065b 180 kSDHC_AllInterruptFlags = (kSDHC_BlockGapEventFlag | kSDHC_CardInterruptFlag | kSDHC_CommandFlag | kSDHC_DataFlag |
kadonotakashi 0:8fdf9a60065b 181 kSDHC_ErrorFlag), /*!< All flags mask */
kadonotakashi 0:8fdf9a60065b 182 };
kadonotakashi 0:8fdf9a60065b 183
kadonotakashi 0:8fdf9a60065b 184 /*! @brief Auto CMD12 error status flag mask */
kadonotakashi 0:8fdf9a60065b 185 enum _sdhc_auto_command12_error_status_flag
kadonotakashi 0:8fdf9a60065b 186 {
kadonotakashi 0:8fdf9a60065b 187 kSDHC_AutoCommand12NotExecutedFlag = SDHC_AC12ERR_AC12NE_MASK, /*!< Not executed error */
kadonotakashi 0:8fdf9a60065b 188 kSDHC_AutoCommand12TimeoutFlag = SDHC_AC12ERR_AC12TOE_MASK, /*!< Timeout error */
kadonotakashi 0:8fdf9a60065b 189 kSDHC_AutoCommand12EndBitErrorFlag = SDHC_AC12ERR_AC12EBE_MASK, /*!< End bit error */
kadonotakashi 0:8fdf9a60065b 190 kSDHC_AutoCommand12CrcErrorFlag = SDHC_AC12ERR_AC12CE_MASK, /*!< CRC error */
kadonotakashi 0:8fdf9a60065b 191 kSDHC_AutoCommand12IndexErrorFlag = SDHC_AC12ERR_AC12IE_MASK, /*!< Index error */
kadonotakashi 0:8fdf9a60065b 192 kSDHC_AutoCommand12NotIssuedFlag = SDHC_AC12ERR_CNIBAC12E_MASK, /*!< Not issued error */
kadonotakashi 0:8fdf9a60065b 193 };
kadonotakashi 0:8fdf9a60065b 194
kadonotakashi 0:8fdf9a60065b 195 /*! @brief ADMA error status flag mask */
kadonotakashi 0:8fdf9a60065b 196 enum _sdhc_adma_error_status_flag
kadonotakashi 0:8fdf9a60065b 197 {
kadonotakashi 0:8fdf9a60065b 198 kSDHC_AdmaLenghMismatchFlag = SDHC_ADMAES_ADMALME_MASK, /*!< Length mismatch error */
kadonotakashi 0:8fdf9a60065b 199 kSDHC_AdmaDescriptorErrorFlag = SDHC_ADMAES_ADMADCE_MASK, /*!< Descriptor error */
kadonotakashi 0:8fdf9a60065b 200 };
kadonotakashi 0:8fdf9a60065b 201
kadonotakashi 0:8fdf9a60065b 202 /*!
kadonotakashi 0:8fdf9a60065b 203 * @brief ADMA error state
kadonotakashi 0:8fdf9a60065b 204 *
kadonotakashi 0:8fdf9a60065b 205 * This state is the detail state when ADMA error has occurred.
kadonotakashi 0:8fdf9a60065b 206 */
kadonotakashi 0:8fdf9a60065b 207 typedef enum _sdhc_adma_error_state
kadonotakashi 0:8fdf9a60065b 208 {
kadonotakashi 0:8fdf9a60065b 209 kSDHC_AdmaErrorStateStopDma = 0x00U, /*!< Stop DMA */
kadonotakashi 0:8fdf9a60065b 210 kSDHC_AdmaErrorStateFetchDescriptor = 0x01U, /*!< Fetch descriptor */
kadonotakashi 0:8fdf9a60065b 211 kSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address */
kadonotakashi 0:8fdf9a60065b 212 kSDHC_AdmaErrorStateTransferData = 0x03U, /*!< Transfer data */
kadonotakashi 0:8fdf9a60065b 213 } sdhc_adma_error_state_t;
kadonotakashi 0:8fdf9a60065b 214
kadonotakashi 0:8fdf9a60065b 215 /*! @brief Force event mask */
kadonotakashi 0:8fdf9a60065b 216 enum _sdhc_force_event
kadonotakashi 0:8fdf9a60065b 217 {
kadonotakashi 0:8fdf9a60065b 218 kSDHC_ForceEventAutoCommand12NotExecuted = SDHC_FEVT_AC12NE_MASK, /*!< Auto CMD12 not executed error */
kadonotakashi 0:8fdf9a60065b 219 kSDHC_ForceEventAutoCommand12Timeout = SDHC_FEVT_AC12TOE_MASK, /*!< Auto CMD12 timeout error */
kadonotakashi 0:8fdf9a60065b 220 kSDHC_ForceEventAutoCommand12CrcError = SDHC_FEVT_AC12CE_MASK, /*!< Auto CMD12 CRC error */
kadonotakashi 0:8fdf9a60065b 221 kSDHC_ForceEventEndBitError = SDHC_FEVT_AC12EBE_MASK, /*!< Auto CMD12 end bit error */
kadonotakashi 0:8fdf9a60065b 222 kSDHC_ForceEventAutoCommand12IndexError = SDHC_FEVT_AC12IE_MASK, /*!< Auto CMD12 index error */
kadonotakashi 0:8fdf9a60065b 223 kSDHC_ForceEventAutoCommand12NotIssued = SDHC_FEVT_CNIBAC12E_MASK, /*!< Auto CMD12 not issued error */
kadonotakashi 0:8fdf9a60065b 224 kSDHC_ForceEventCommandTimeout = SDHC_FEVT_CTOE_MASK, /*!< Command timeout error */
kadonotakashi 0:8fdf9a60065b 225 kSDHC_ForceEventCommandCrcError = SDHC_FEVT_CCE_MASK, /*!< Command CRC error */
kadonotakashi 0:8fdf9a60065b 226 kSDHC_ForceEventCommandEndBitError = SDHC_FEVT_CEBE_MASK, /*!< Command end bit error */
kadonotakashi 0:8fdf9a60065b 227 kSDHC_ForceEventCommandIndexError = SDHC_FEVT_CIE_MASK, /*!< Command index error */
kadonotakashi 0:8fdf9a60065b 228 kSDHC_ForceEventDataTimeout = SDHC_FEVT_DTOE_MASK, /*!< Data timeout error */
kadonotakashi 0:8fdf9a60065b 229 kSDHC_ForceEventDataCrcError = SDHC_FEVT_DCE_MASK, /*!< Data CRC error */
kadonotakashi 0:8fdf9a60065b 230 kSDHC_ForceEventDataEndBitError = SDHC_FEVT_DEBE_MASK, /*!< Data end bit error */
kadonotakashi 0:8fdf9a60065b 231 kSDHC_ForceEventAutoCommand12Error = SDHC_FEVT_AC12E_MASK, /*!< Auto CMD12 error */
kadonotakashi 0:8fdf9a60065b 232 kSDHC_ForceEventCardInt = SDHC_FEVT_CINT_MASK, /*!< Card interrupt */
kadonotakashi 0:8fdf9a60065b 233 kSDHC_ForceEventDmaError = SDHC_FEVT_DMAE_MASK, /*!< Dma error */
kadonotakashi 0:8fdf9a60065b 234
kadonotakashi 0:8fdf9a60065b 235 kSDHC_ForceEventsAll =
kadonotakashi 0:8fdf9a60065b 236 (kSDHC_ForceEventAutoCommand12NotExecuted | kSDHC_ForceEventAutoCommand12Timeout |
kadonotakashi 0:8fdf9a60065b 237 kSDHC_ForceEventAutoCommand12CrcError | kSDHC_ForceEventEndBitError | kSDHC_ForceEventAutoCommand12IndexError |
kadonotakashi 0:8fdf9a60065b 238 kSDHC_ForceEventAutoCommand12NotIssued | kSDHC_ForceEventCommandTimeout | kSDHC_ForceEventCommandCrcError |
kadonotakashi 0:8fdf9a60065b 239 kSDHC_ForceEventCommandEndBitError | kSDHC_ForceEventCommandIndexError | kSDHC_ForceEventDataTimeout |
kadonotakashi 0:8fdf9a60065b 240 kSDHC_ForceEventDataCrcError | kSDHC_ForceEventDataEndBitError | kSDHC_ForceEventAutoCommand12Error |
kadonotakashi 0:8fdf9a60065b 241 kSDHC_ForceEventCardInt | kSDHC_ForceEventDmaError), /*!< All force event flags mask */
kadonotakashi 0:8fdf9a60065b 242 };
kadonotakashi 0:8fdf9a60065b 243
kadonotakashi 0:8fdf9a60065b 244 /*! @brief Data transfer width */
kadonotakashi 0:8fdf9a60065b 245 typedef enum _sdhc_data_bus_width
kadonotakashi 0:8fdf9a60065b 246 {
kadonotakashi 0:8fdf9a60065b 247 kSDHC_DataBusWidth1Bit = 0U, /*!< 1-bit mode */
kadonotakashi 0:8fdf9a60065b 248 kSDHC_DataBusWidth4Bit = 1U, /*!< 4-bit mode */
kadonotakashi 0:8fdf9a60065b 249 kSDHC_DataBusWidth8Bit = 2U, /*!< 8-bit mode */
kadonotakashi 0:8fdf9a60065b 250 } sdhc_data_bus_width_t;
kadonotakashi 0:8fdf9a60065b 251
kadonotakashi 0:8fdf9a60065b 252 /*! @brief Endian mode */
kadonotakashi 0:8fdf9a60065b 253 typedef enum _sdhc_endian_mode
kadonotakashi 0:8fdf9a60065b 254 {
kadonotakashi 0:8fdf9a60065b 255 kSDHC_EndianModeBig = 0U, /*!< Big endian mode */
kadonotakashi 0:8fdf9a60065b 256 kSDHC_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */
kadonotakashi 0:8fdf9a60065b 257 kSDHC_EndianModeLittle = 2U, /*!< Little endian mode */
kadonotakashi 0:8fdf9a60065b 258 } sdhc_endian_mode_t;
kadonotakashi 0:8fdf9a60065b 259
kadonotakashi 0:8fdf9a60065b 260 /*! @brief DMA mode */
kadonotakashi 0:8fdf9a60065b 261 typedef enum _sdhc_dma_mode
kadonotakashi 0:8fdf9a60065b 262 {
kadonotakashi 0:8fdf9a60065b 263 kSDHC_DmaModeNo = 0U, /*!< No DMA */
kadonotakashi 0:8fdf9a60065b 264 kSDHC_DmaModeAdma1 = 1U, /*!< ADMA1 is selected */
kadonotakashi 0:8fdf9a60065b 265 kSDHC_DmaModeAdma2 = 2U, /*!< ADMA2 is selected */
kadonotakashi 0:8fdf9a60065b 266 } sdhc_dma_mode_t;
kadonotakashi 0:8fdf9a60065b 267
kadonotakashi 0:8fdf9a60065b 268 /*! @brief SDIO control flag mask */
kadonotakashi 0:8fdf9a60065b 269 enum _sdhc_sdio_control_flag
kadonotakashi 0:8fdf9a60065b 270 {
kadonotakashi 0:8fdf9a60065b 271 kSDHC_StopAtBlockGapFlag = 0x01, /*!< Stop at block gap */
kadonotakashi 0:8fdf9a60065b 272 kSDHC_ReadWaitControlFlag = 0x02, /*!< Read wait control */
kadonotakashi 0:8fdf9a60065b 273 kSDHC_InterruptAtBlockGapFlag = 0x04, /*!< Interrupt at block gap */
kadonotakashi 0:8fdf9a60065b 274 kSDHC_ExactBlockNumberReadFlag = 0x08, /*!< Exact block number read */
kadonotakashi 0:8fdf9a60065b 275 };
kadonotakashi 0:8fdf9a60065b 276
kadonotakashi 0:8fdf9a60065b 277 /*! @brief MMC card boot mode */
kadonotakashi 0:8fdf9a60065b 278 typedef enum _sdhc_boot_mode
kadonotakashi 0:8fdf9a60065b 279 {
kadonotakashi 0:8fdf9a60065b 280 kSDHC_BootModeNormal = 0U, /*!< Normal boot */
kadonotakashi 0:8fdf9a60065b 281 kSDHC_BootModeAlternative = 1U, /*!< Alternative boot */
kadonotakashi 0:8fdf9a60065b 282 } sdhc_boot_mode_t;
kadonotakashi 0:8fdf9a60065b 283
kadonotakashi 0:8fdf9a60065b 284 /*! @brief The command type */
kadonotakashi 0:8fdf9a60065b 285 typedef enum _sdhc_command_type
kadonotakashi 0:8fdf9a60065b 286 {
kadonotakashi 0:8fdf9a60065b 287 kSDHC_CommandTypeNormal = 0U, /*!< Normal command */
kadonotakashi 0:8fdf9a60065b 288 kSDHC_CommandTypeSuspend = 1U, /*!< Suspend command */
kadonotakashi 0:8fdf9a60065b 289 kSDHC_CommandTypeResume = 2U, /*!< Resume command */
kadonotakashi 0:8fdf9a60065b 290 kSDHC_CommandTypeAbort = 3U, /*!< Abort command */
kadonotakashi 0:8fdf9a60065b 291 } sdhc_command_type_t;
kadonotakashi 0:8fdf9a60065b 292
kadonotakashi 0:8fdf9a60065b 293 /*!
kadonotakashi 0:8fdf9a60065b 294 * @brief The command response type.
kadonotakashi 0:8fdf9a60065b 295 *
kadonotakashi 0:8fdf9a60065b 296 * Define the command response type from card to host controller.
kadonotakashi 0:8fdf9a60065b 297 */
kadonotakashi 0:8fdf9a60065b 298 typedef enum _sdhc_response_type
kadonotakashi 0:8fdf9a60065b 299 {
kadonotakashi 0:8fdf9a60065b 300 kSDHC_ResponseTypeNone = 0U, /*!< Response type: none */
kadonotakashi 0:8fdf9a60065b 301 kSDHC_ResponseTypeR1 = 1U, /*!< Response type: R1 */
kadonotakashi 0:8fdf9a60065b 302 kSDHC_ResponseTypeR1b = 2U, /*!< Response type: R1b */
kadonotakashi 0:8fdf9a60065b 303 kSDHC_ResponseTypeR2 = 3U, /*!< Response type: R2 */
kadonotakashi 0:8fdf9a60065b 304 kSDHC_ResponseTypeR3 = 4U, /*!< Response type: R3 */
kadonotakashi 0:8fdf9a60065b 305 kSDHC_ResponseTypeR4 = 5U, /*!< Response type: R4 */
kadonotakashi 0:8fdf9a60065b 306 kSDHC_ResponseTypeR5 = 6U, /*!< Response type: R5 */
kadonotakashi 0:8fdf9a60065b 307 kSDHC_ResponseTypeR5b = 7U, /*!< Response type: R5b */
kadonotakashi 0:8fdf9a60065b 308 kSDHC_ResponseTypeR6 = 8U, /*!< Response type: R6 */
kadonotakashi 0:8fdf9a60065b 309 kSDHC_ResponseTypeR7 = 9U, /*!< Response type: R7 */
kadonotakashi 0:8fdf9a60065b 310 } sdhc_response_type_t;
kadonotakashi 0:8fdf9a60065b 311
kadonotakashi 0:8fdf9a60065b 312 /*! @brief The alignment size for ADDRESS filed in ADMA1's descriptor */
kadonotakashi 0:8fdf9a60065b 313 #define SDHC_ADMA1_ADDRESS_ALIGN (4096U)
kadonotakashi 0:8fdf9a60065b 314 /*! @brief The alignment size for LENGTH field in ADMA1's descriptor */
kadonotakashi 0:8fdf9a60065b 315 #define SDHC_ADMA1_LENGTH_ALIGN (4096U)
kadonotakashi 0:8fdf9a60065b 316 /*! @brief The alignment size for ADDRESS field in ADMA2's descriptor */
kadonotakashi 0:8fdf9a60065b 317 #define SDHC_ADMA2_ADDRESS_ALIGN (4U)
kadonotakashi 0:8fdf9a60065b 318 /*! @brief The alignment size for LENGTH filed in ADMA2's descriptor */
kadonotakashi 0:8fdf9a60065b 319 #define SDHC_ADMA2_LENGTH_ALIGN (4U)
kadonotakashi 0:8fdf9a60065b 320
kadonotakashi 0:8fdf9a60065b 321 /* ADMA1 descriptor table
kadonotakashi 0:8fdf9a60065b 322 * |------------------------|---------|--------------------------|
kadonotakashi 0:8fdf9a60065b 323 * | Address/page field |Reserved | Attribute |
kadonotakashi 0:8fdf9a60065b 324 * |------------------------|---------|--------------------------|
kadonotakashi 0:8fdf9a60065b 325 * |31 12|11 6|05 |04 |03|02 |01 |00 |
kadonotakashi 0:8fdf9a60065b 326 * |------------------------|---------|----|----|--|---|---|-----|
kadonotakashi 0:8fdf9a60065b 327 * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid|
kadonotakashi 0:8fdf9a60065b 328 * |------------------------|---------|----|----|--|---|---|-----|
kadonotakashi 0:8fdf9a60065b 329 *
kadonotakashi 0:8fdf9a60065b 330 *
kadonotakashi 0:8fdf9a60065b 331 * |------|------|-----------------|-------|-------------|
kadonotakashi 0:8fdf9a60065b 332 * | Act2 | Act1 | Comment | 31-28 | 27 - 12 |
kadonotakashi 0:8fdf9a60065b 333 * |------|------|-----------------|---------------------|
kadonotakashi 0:8fdf9a60065b 334 * | 0 | 0 | No op | Don't care |
kadonotakashi 0:8fdf9a60065b 335 * |------|------|-----------------|-------|-------------|
kadonotakashi 0:8fdf9a60065b 336 * | 0 | 1 | Set data length | 0000 | Data Length |
kadonotakashi 0:8fdf9a60065b 337 * |------|------|-----------------|-------|-------------|
kadonotakashi 0:8fdf9a60065b 338 * | 1 | 0 | Transfer data | Data address |
kadonotakashi 0:8fdf9a60065b 339 * |------|------|-----------------|---------------------|
kadonotakashi 0:8fdf9a60065b 340 * | 1 | 1 | Link descriptor | Descriptor address |
kadonotakashi 0:8fdf9a60065b 341 * |------|------|-----------------|---------------------|
kadonotakashi 0:8fdf9a60065b 342 */
kadonotakashi 0:8fdf9a60065b 343 /*! @brief The bit shift for ADDRESS filed in ADMA1's descriptor */
kadonotakashi 0:8fdf9a60065b 344 #define SDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 345 /*! @brief The bit mask for ADDRESS field in ADMA1's descriptor */
kadonotakashi 0:8fdf9a60065b 346 #define SDHC_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU)
kadonotakashi 0:8fdf9a60065b 347 /*! @brief The bit shift for LENGTH filed in ADMA1's descriptor */
kadonotakashi 0:8fdf9a60065b 348 #define SDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT (12U)
kadonotakashi 0:8fdf9a60065b 349 /*! @brief The mask for LENGTH field in ADMA1's descriptor */
kadonotakashi 0:8fdf9a60065b 350 #define SDHC_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 351 /*! @brief The maximum value of LENGTH filed in ADMA1's descriptor */
kadonotakashi 0:8fdf9a60065b 352 #define SDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDHC_ADMA1_DESCRIPTOR_LENGTH_MASK + 1U)
kadonotakashi 0:8fdf9a60065b 353
kadonotakashi 0:8fdf9a60065b 354 /*! @brief The mask for the control/status field in ADMA1 descriptor */
kadonotakashi 0:8fdf9a60065b 355 enum _sdhc_adma1_descriptor_flag
kadonotakashi 0:8fdf9a60065b 356 {
kadonotakashi 0:8fdf9a60065b 357 kSDHC_Adma1DescriptorValidFlag = (1U << 0U), /*!< Valid flag */
kadonotakashi 0:8fdf9a60065b 358 kSDHC_Adma1DescriptorEndFlag = (1U << 1U), /*!< End flag */
kadonotakashi 0:8fdf9a60065b 359 kSDHC_Adma1DescriptorInterrupFlag = (1U << 2U), /*!< Interrupt flag */
kadonotakashi 0:8fdf9a60065b 360 kSDHC_Adma1DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 flag */
kadonotakashi 0:8fdf9a60065b 361 kSDHC_Adma1DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 flag */
kadonotakashi 0:8fdf9a60065b 362 kSDHC_Adma1DescriptorTypeNop = (kSDHC_Adma1DescriptorValidFlag), /*!< No operation */
kadonotakashi 0:8fdf9a60065b 363 kSDHC_Adma1DescriptorTypeTransfer =
kadonotakashi 0:8fdf9a60065b 364 (kSDHC_Adma1DescriptorActivity2Flag | kSDHC_Adma1DescriptorValidFlag), /*!< Transfer data */
kadonotakashi 0:8fdf9a60065b 365 kSDHC_Adma1DescriptorTypeLink = (kSDHC_Adma1DescriptorActivity1Flag | kSDHC_Adma1DescriptorActivity2Flag |
kadonotakashi 0:8fdf9a60065b 366 kSDHC_Adma1DescriptorValidFlag), /*!< Link descriptor */
kadonotakashi 0:8fdf9a60065b 367 kSDHC_Adma1DescriptorTypeSetLength =
kadonotakashi 0:8fdf9a60065b 368 (kSDHC_Adma1DescriptorActivity1Flag | kSDHC_Adma1DescriptorValidFlag), /*!< Set data length */
kadonotakashi 0:8fdf9a60065b 369 };
kadonotakashi 0:8fdf9a60065b 370
kadonotakashi 0:8fdf9a60065b 371 /* ADMA2 descriptor table
kadonotakashi 0:8fdf9a60065b 372 * |----------------|---------------|-------------|--------------------------|
kadonotakashi 0:8fdf9a60065b 373 * | Address field | Length | Reserved | Attribute |
kadonotakashi 0:8fdf9a60065b 374 * |----------------|---------------|-------------|--------------------------|
kadonotakashi 0:8fdf9a60065b 375 * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 |
kadonotakashi 0:8fdf9a60065b 376 * |----------------|---------------|-------------|----|----|--|---|---|-----|
kadonotakashi 0:8fdf9a60065b 377 * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid|
kadonotakashi 0:8fdf9a60065b 378 * |----------------|---------------|-------------|----|----|--|---|---|-----|
kadonotakashi 0:8fdf9a60065b 379 *
kadonotakashi 0:8fdf9a60065b 380 *
kadonotakashi 0:8fdf9a60065b 381 * | Act2 | Act1 | Comment | Operation |
kadonotakashi 0:8fdf9a60065b 382 * |------|------|-----------------|-------------------------------------------------------------------|
kadonotakashi 0:8fdf9a60065b 383 * | 0 | 0 | No op | Don't care |
kadonotakashi 0:8fdf9a60065b 384 * |------|------|-----------------|-------------------------------------------------------------------|
kadonotakashi 0:8fdf9a60065b 385 * | 0 | 1 | Reserved | Read this line and go to next one |
kadonotakashi 0:8fdf9a60065b 386 * |------|------|-----------------|-------------------------------------------------------------------|
kadonotakashi 0:8fdf9a60065b 387 * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line |
kadonotakashi 0:8fdf9a60065b 388 * |------|------|-----------------|-------------------------------------------------------------------|
kadonotakashi 0:8fdf9a60065b 389 * | 1 | 1 | Link descriptor | Link to another descriptor |
kadonotakashi 0:8fdf9a60065b 390 * |------|------|-----------------|-------------------------------------------------------------------|
kadonotakashi 0:8fdf9a60065b 391 */
kadonotakashi 0:8fdf9a60065b 392 /*! @brief The bit shift for LENGTH field in ADMA2's descriptor */
kadonotakashi 0:8fdf9a60065b 393 #define SDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT (16U)
kadonotakashi 0:8fdf9a60065b 394 /*! @brief The bit mask for LENGTH field in ADMA2's descriptor */
kadonotakashi 0:8fdf9a60065b 395 #define SDHC_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU)
kadonotakashi 0:8fdf9a60065b 396 /*! @brief The maximum value of LENGTH field in ADMA2's descriptor */
kadonotakashi 0:8fdf9a60065b 397 #define SDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDHC_ADMA2_DESCRIPTOR_LENGTH_MASK)
kadonotakashi 0:8fdf9a60065b 398
kadonotakashi 0:8fdf9a60065b 399 /*! @brief ADMA1 descriptor control and status mask */
kadonotakashi 0:8fdf9a60065b 400 enum _sdhc_adma2_descriptor_flag
kadonotakashi 0:8fdf9a60065b 401 {
kadonotakashi 0:8fdf9a60065b 402 kSDHC_Adma2DescriptorValidFlag = (1U << 0U), /*!< Valid flag */
kadonotakashi 0:8fdf9a60065b 403 kSDHC_Adma2DescriptorEndFlag = (1U << 1U), /*!< End flag */
kadonotakashi 0:8fdf9a60065b 404 kSDHC_Adma2DescriptorInterruptFlag = (1U << 2U), /*!< Interrupt flag */
kadonotakashi 0:8fdf9a60065b 405 kSDHC_Adma2DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 mask */
kadonotakashi 0:8fdf9a60065b 406 kSDHC_Adma2DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 mask */
kadonotakashi 0:8fdf9a60065b 407
kadonotakashi 0:8fdf9a60065b 408 kSDHC_Adma2DescriptorTypeNop = (kSDHC_Adma2DescriptorValidFlag), /*!< No operation */
kadonotakashi 0:8fdf9a60065b 409 kSDHC_Adma2DescriptorTypeReserved =
kadonotakashi 0:8fdf9a60065b 410 (kSDHC_Adma2DescriptorActivity1Flag | kSDHC_Adma2DescriptorValidFlag), /*!< Reserved */
kadonotakashi 0:8fdf9a60065b 411 kSDHC_Adma2DescriptorTypeTransfer =
kadonotakashi 0:8fdf9a60065b 412 (kSDHC_Adma2DescriptorActivity2Flag | kSDHC_Adma2DescriptorValidFlag), /*!< Transfer type */
kadonotakashi 0:8fdf9a60065b 413 kSDHC_Adma2DescriptorTypeLink = (kSDHC_Adma2DescriptorActivity1Flag | kSDHC_Adma2DescriptorActivity2Flag |
kadonotakashi 0:8fdf9a60065b 414 kSDHC_Adma2DescriptorValidFlag), /*!< Link type */
kadonotakashi 0:8fdf9a60065b 415 };
kadonotakashi 0:8fdf9a60065b 416
kadonotakashi 0:8fdf9a60065b 417 /*! @brief Defines the adma1 descriptor structure. */
kadonotakashi 0:8fdf9a60065b 418 typedef uint32_t sdhc_adma1_descriptor_t;
kadonotakashi 0:8fdf9a60065b 419
kadonotakashi 0:8fdf9a60065b 420 /*! @brief Defines the ADMA2 descriptor structure. */
kadonotakashi 0:8fdf9a60065b 421 typedef struct _sdhc_adma2_descriptor
kadonotakashi 0:8fdf9a60065b 422 {
kadonotakashi 0:8fdf9a60065b 423 uint32_t attribute; /*!< The control and status field */
kadonotakashi 0:8fdf9a60065b 424 const uint32_t *address; /*!< The address field */
kadonotakashi 0:8fdf9a60065b 425 } sdhc_adma2_descriptor_t;
kadonotakashi 0:8fdf9a60065b 426
kadonotakashi 0:8fdf9a60065b 427 /*!
kadonotakashi 0:8fdf9a60065b 428 * @brief SDHC capability information.
kadonotakashi 0:8fdf9a60065b 429 *
kadonotakashi 0:8fdf9a60065b 430 * Defines a structure to save the capability information of SDHC.
kadonotakashi 0:8fdf9a60065b 431 */
kadonotakashi 0:8fdf9a60065b 432 typedef struct _sdhc_capability
kadonotakashi 0:8fdf9a60065b 433 {
kadonotakashi 0:8fdf9a60065b 434 uint32_t specVersion; /*!< Specification version */
kadonotakashi 0:8fdf9a60065b 435 uint32_t vendorVersion; /*!< Vendor version */
kadonotakashi 0:8fdf9a60065b 436 uint32_t maxBlockLength; /*!< Maximum block length united as byte */
kadonotakashi 0:8fdf9a60065b 437 uint32_t maxBlockCount; /*!< Maximum block count can be set one time */
kadonotakashi 0:8fdf9a60065b 438 uint32_t flags; /*!< Capability flags to indicate the support information(_sdhc_capability_flag) */
kadonotakashi 0:8fdf9a60065b 439 } sdhc_capability_t;
kadonotakashi 0:8fdf9a60065b 440
kadonotakashi 0:8fdf9a60065b 441 /*! @brief Card transfer configuration.
kadonotakashi 0:8fdf9a60065b 442 *
kadonotakashi 0:8fdf9a60065b 443 * Define structure to configure the transfer-related command index/argument/flags and data block
kadonotakashi 0:8fdf9a60065b 444 * size/data block numbers. This structure needs to be filled each time a command is sent to the card.
kadonotakashi 0:8fdf9a60065b 445 */
kadonotakashi 0:8fdf9a60065b 446 typedef struct _sdhc_transfer_config
kadonotakashi 0:8fdf9a60065b 447 {
kadonotakashi 0:8fdf9a60065b 448 size_t dataBlockSize; /*!< Data block size */
kadonotakashi 0:8fdf9a60065b 449 uint32_t dataBlockCount; /*!< Data block count */
kadonotakashi 0:8fdf9a60065b 450 uint32_t commandArgument; /*!< Command argument */
kadonotakashi 0:8fdf9a60065b 451 uint32_t commandIndex; /*!< Command index */
kadonotakashi 0:8fdf9a60065b 452 uint32_t flags; /*!< Transfer flags(_sdhc_transfer_flag) */
kadonotakashi 0:8fdf9a60065b 453 } sdhc_transfer_config_t;
kadonotakashi 0:8fdf9a60065b 454
kadonotakashi 0:8fdf9a60065b 455 /*! @brief Data structure to configure the MMC boot feature */
kadonotakashi 0:8fdf9a60065b 456 typedef struct _sdhc_boot_config
kadonotakashi 0:8fdf9a60065b 457 {
kadonotakashi 0:8fdf9a60065b 458 uint32_t ackTimeoutCount; /*!< Timeout value for the boot ACK. The available range is 0 ~ 15. */
kadonotakashi 0:8fdf9a60065b 459 sdhc_boot_mode_t bootMode; /*!< Boot mode selection. */
kadonotakashi 0:8fdf9a60065b 460 uint32_t blockCount; /*!< Stop at block gap value of automatic mode. Available range is 0 ~ 65535. */
kadonotakashi 0:8fdf9a60065b 461 bool enableBootAck; /*!< Enable or disable boot ACK */
kadonotakashi 0:8fdf9a60065b 462 bool enableBoot; /*!< Enable or disable fast boot */
kadonotakashi 0:8fdf9a60065b 463 bool enableAutoStopAtBlockGap; /*!< Enable or disable auto stop at block gap function in boot period */
kadonotakashi 0:8fdf9a60065b 464 } sdhc_boot_config_t;
kadonotakashi 0:8fdf9a60065b 465
kadonotakashi 0:8fdf9a60065b 466 /*! @brief Data structure to initialize the SDHC */
kadonotakashi 0:8fdf9a60065b 467 typedef struct _sdhc_config
kadonotakashi 0:8fdf9a60065b 468 {
kadonotakashi 0:8fdf9a60065b 469 bool cardDetectDat3; /*!< Enable DAT3 as card detection pin */
kadonotakashi 0:8fdf9a60065b 470 sdhc_endian_mode_t endianMode; /*!< Endian mode */
kadonotakashi 0:8fdf9a60065b 471 sdhc_dma_mode_t dmaMode; /*!< DMA mode */
kadonotakashi 0:8fdf9a60065b 472 uint32_t readWatermarkLevel; /*!< Watermark level for DMA read operation. Available range is 1 ~ 128. */
kadonotakashi 0:8fdf9a60065b 473 uint32_t writeWatermarkLevel; /*!< Watermark level for DMA write operation. Available range is 1 ~ 128. */
kadonotakashi 0:8fdf9a60065b 474 } sdhc_config_t;
kadonotakashi 0:8fdf9a60065b 475
kadonotakashi 0:8fdf9a60065b 476 /*!
kadonotakashi 0:8fdf9a60065b 477 * @brief Card data descriptor
kadonotakashi 0:8fdf9a60065b 478 *
kadonotakashi 0:8fdf9a60065b 479 * Defines a structure to contain data-related attribute. 'enableIgnoreError' is used for the case that upper card
kadonotakashi 0:8fdf9a60065b 480 * driver
kadonotakashi 0:8fdf9a60065b 481 * want to ignore the error event to read/write all the data not to stop read/write immediately when error event
kadonotakashi 0:8fdf9a60065b 482 * happen for example bus testing procedure for MMC card.
kadonotakashi 0:8fdf9a60065b 483 */
kadonotakashi 0:8fdf9a60065b 484 typedef struct _sdhc_data
kadonotakashi 0:8fdf9a60065b 485 {
kadonotakashi 0:8fdf9a60065b 486 bool enableAutoCommand12; /*!< Enable auto CMD12 */
kadonotakashi 0:8fdf9a60065b 487 bool enableIgnoreError; /*!< Enable to ignore error event to read/write all the data */
kadonotakashi 0:8fdf9a60065b 488 size_t blockSize; /*!< Block size */
kadonotakashi 0:8fdf9a60065b 489 uint32_t blockCount; /*!< Block count */
kadonotakashi 0:8fdf9a60065b 490 uint32_t *rxData; /*!< Buffer to save data read */
kadonotakashi 0:8fdf9a60065b 491 const uint32_t *txData; /*!< Data buffer to write */
kadonotakashi 0:8fdf9a60065b 492 } sdhc_data_t;
kadonotakashi 0:8fdf9a60065b 493
kadonotakashi 0:8fdf9a60065b 494 /*!
kadonotakashi 0:8fdf9a60065b 495 * @brief Card command descriptor
kadonotakashi 0:8fdf9a60065b 496 *
kadonotakashi 0:8fdf9a60065b 497 * Define card command-related attribute.
kadonotakashi 0:8fdf9a60065b 498 */
kadonotakashi 0:8fdf9a60065b 499 typedef struct _sdhc_command
kadonotakashi 0:8fdf9a60065b 500 {
kadonotakashi 0:8fdf9a60065b 501 uint32_t index; /*!< Command index */
kadonotakashi 0:8fdf9a60065b 502 uint32_t argument; /*!< Command argument */
kadonotakashi 0:8fdf9a60065b 503 sdhc_command_type_t type; /*!< Command type */
kadonotakashi 0:8fdf9a60065b 504 sdhc_response_type_t responseType; /*!< Command response type */
kadonotakashi 0:8fdf9a60065b 505 uint32_t response[4U]; /*!< Response for this command */
kadonotakashi 0:8fdf9a60065b 506 } sdhc_command_t;
kadonotakashi 0:8fdf9a60065b 507
kadonotakashi 0:8fdf9a60065b 508 /*! @brief Transfer state */
kadonotakashi 0:8fdf9a60065b 509 typedef struct _sdhc_transfer
kadonotakashi 0:8fdf9a60065b 510 {
kadonotakashi 0:8fdf9a60065b 511 sdhc_data_t *data; /*!< Data to transfer */
kadonotakashi 0:8fdf9a60065b 512 sdhc_command_t *command; /*!< Command to send */
kadonotakashi 0:8fdf9a60065b 513 } sdhc_transfer_t;
kadonotakashi 0:8fdf9a60065b 514
kadonotakashi 0:8fdf9a60065b 515 /*! @brief SDHC handle typedef */
kadonotakashi 0:8fdf9a60065b 516 typedef struct _sdhc_handle sdhc_handle_t;
kadonotakashi 0:8fdf9a60065b 517
kadonotakashi 0:8fdf9a60065b 518 /*! @brief SDHC callback functions. */
kadonotakashi 0:8fdf9a60065b 519 typedef struct _sdhc_transfer_callback
kadonotakashi 0:8fdf9a60065b 520 {
kadonotakashi 0:8fdf9a60065b 521 void (*CardInserted)(void); /*!< Card inserted occurs when DAT3/CD pin is for card detect */
kadonotakashi 0:8fdf9a60065b 522 void (*CardRemoved)(void); /*!< Card removed occurs */
kadonotakashi 0:8fdf9a60065b 523 void (*SdioInterrupt)(void); /*!< SDIO card interrupt occurs */
kadonotakashi 0:8fdf9a60065b 524 void (*SdioBlockGap)(void); /*!< SDIO card stopped at block gap occurs */
kadonotakashi 0:8fdf9a60065b 525 void (*TransferComplete)(SDHC_Type *base,
kadonotakashi 0:8fdf9a60065b 526 sdhc_handle_t *handle,
kadonotakashi 0:8fdf9a60065b 527 status_t status,
kadonotakashi 0:8fdf9a60065b 528 void *userData); /*!< Transfer complete callback */
kadonotakashi 0:8fdf9a60065b 529 } sdhc_transfer_callback_t;
kadonotakashi 0:8fdf9a60065b 530
kadonotakashi 0:8fdf9a60065b 531 /*!
kadonotakashi 0:8fdf9a60065b 532 * @brief SDHC handle
kadonotakashi 0:8fdf9a60065b 533 *
kadonotakashi 0:8fdf9a60065b 534 * Defines the structure to save the SDHC state information and callback function. The detailed interrupt status when
kadonotakashi 0:8fdf9a60065b 535 * sending a command or transfering data can be obtained from the interruptFlags field by using the mask defined in
kadonotakashi 0:8fdf9a60065b 536 * sdhc_interrupt_flag_t.
kadonotakashi 0:8fdf9a60065b 537 *
kadonotakashi 0:8fdf9a60065b 538 * @note All the fields except interruptFlags and transferredWords must be allocated by the user.
kadonotakashi 0:8fdf9a60065b 539 */
kadonotakashi 0:8fdf9a60065b 540 struct _sdhc_handle
kadonotakashi 0:8fdf9a60065b 541 {
kadonotakashi 0:8fdf9a60065b 542 /* Transfer parameter */
kadonotakashi 0:8fdf9a60065b 543 sdhc_data_t *volatile data; /*!< Data to transfer */
kadonotakashi 0:8fdf9a60065b 544 sdhc_command_t *volatile command; /*!< Command to send */
kadonotakashi 0:8fdf9a60065b 545
kadonotakashi 0:8fdf9a60065b 546 /* Transfer status */
kadonotakashi 0:8fdf9a60065b 547 volatile uint32_t interruptFlags; /*!< Interrupt flags of last transaction */
kadonotakashi 0:8fdf9a60065b 548 volatile uint32_t transferredWords; /*!< Words transferred by DATAPORT way */
kadonotakashi 0:8fdf9a60065b 549
kadonotakashi 0:8fdf9a60065b 550 /* Callback functions */
kadonotakashi 0:8fdf9a60065b 551 sdhc_transfer_callback_t callback; /*!< Callback function */
kadonotakashi 0:8fdf9a60065b 552 void *userData; /*!< Parameter for transfer complete callback */
kadonotakashi 0:8fdf9a60065b 553 };
kadonotakashi 0:8fdf9a60065b 554
kadonotakashi 0:8fdf9a60065b 555 /*! @brief SDHC transfer function. */
kadonotakashi 0:8fdf9a60065b 556 typedef status_t (*sdhc_transfer_function_t)(SDHC_Type *base, sdhc_transfer_t *content);
kadonotakashi 0:8fdf9a60065b 557
kadonotakashi 0:8fdf9a60065b 558 /*! @brief SDHC host descriptor */
kadonotakashi 0:8fdf9a60065b 559 typedef struct _sdhc_host
kadonotakashi 0:8fdf9a60065b 560 {
kadonotakashi 0:8fdf9a60065b 561 SDHC_Type *base; /*!< SDHC peripheral base address */
kadonotakashi 0:8fdf9a60065b 562 uint32_t sourceClock_Hz; /*!< SDHC source clock frequency united in Hz */
kadonotakashi 0:8fdf9a60065b 563 sdhc_config_t config; /*!< SDHC configuration */
kadonotakashi 0:8fdf9a60065b 564 sdhc_capability_t capability; /*!< SDHC capability information */
kadonotakashi 0:8fdf9a60065b 565 sdhc_transfer_function_t transfer; /*!< SDHC transfer function */
kadonotakashi 0:8fdf9a60065b 566 } sdhc_host_t;
kadonotakashi 0:8fdf9a60065b 567
kadonotakashi 0:8fdf9a60065b 568 /*************************************************************************************************
kadonotakashi 0:8fdf9a60065b 569 * API
kadonotakashi 0:8fdf9a60065b 570 ************************************************************************************************/
kadonotakashi 0:8fdf9a60065b 571 #if defined(__cplusplus)
kadonotakashi 0:8fdf9a60065b 572 extern "C" {
kadonotakashi 0:8fdf9a60065b 573 #endif
kadonotakashi 0:8fdf9a60065b 574
kadonotakashi 0:8fdf9a60065b 575 /*!
kadonotakashi 0:8fdf9a60065b 576 * @name Initialization and deinitialization
kadonotakashi 0:8fdf9a60065b 577 * @{
kadonotakashi 0:8fdf9a60065b 578 */
kadonotakashi 0:8fdf9a60065b 579
kadonotakashi 0:8fdf9a60065b 580 /*!
kadonotakashi 0:8fdf9a60065b 581 * @brief SDHC module initialization function.
kadonotakashi 0:8fdf9a60065b 582 *
kadonotakashi 0:8fdf9a60065b 583 * Configures the SDHC according to the user configuration.
kadonotakashi 0:8fdf9a60065b 584 *
kadonotakashi 0:8fdf9a60065b 585 * Example:
kadonotakashi 0:8fdf9a60065b 586 @code
kadonotakashi 0:8fdf9a60065b 587 sdhc_config_t config;
kadonotakashi 0:8fdf9a60065b 588 config.cardDetectDat3 = false;
kadonotakashi 0:8fdf9a60065b 589 config.endianMode = kSDHC_EndianModeLittle;
kadonotakashi 0:8fdf9a60065b 590 config.dmaMode = kSDHC_DmaModeAdma2;
kadonotakashi 0:8fdf9a60065b 591 config.readWatermarkLevel = 128U;
kadonotakashi 0:8fdf9a60065b 592 config.writeWatermarkLevel = 128U;
kadonotakashi 0:8fdf9a60065b 593 SDHC_Init(SDHC, &config);
kadonotakashi 0:8fdf9a60065b 594 @endcode
kadonotakashi 0:8fdf9a60065b 595 *
kadonotakashi 0:8fdf9a60065b 596 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 597 * @param config SDHC configuration information.
kadonotakashi 0:8fdf9a60065b 598 * @retval kStatus_Success Operate successfully.
kadonotakashi 0:8fdf9a60065b 599 */
kadonotakashi 0:8fdf9a60065b 600 void SDHC_Init(SDHC_Type *base, const sdhc_config_t *config);
kadonotakashi 0:8fdf9a60065b 601
kadonotakashi 0:8fdf9a60065b 602 /*!
kadonotakashi 0:8fdf9a60065b 603 * @brief Deinitializes the SDHC.
kadonotakashi 0:8fdf9a60065b 604 *
kadonotakashi 0:8fdf9a60065b 605 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 606 */
kadonotakashi 0:8fdf9a60065b 607 void SDHC_Deinit(SDHC_Type *base);
kadonotakashi 0:8fdf9a60065b 608
kadonotakashi 0:8fdf9a60065b 609 /*!
kadonotakashi 0:8fdf9a60065b 610 * @brief Resets the SDHC.
kadonotakashi 0:8fdf9a60065b 611 *
kadonotakashi 0:8fdf9a60065b 612 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 613 * @param mask The reset type mask(_sdhc_reset).
kadonotakashi 0:8fdf9a60065b 614 * @param timeout Timeout for reset.
kadonotakashi 0:8fdf9a60065b 615 * @retval true Reset successfully.
kadonotakashi 0:8fdf9a60065b 616 * @retval false Reset failed.
kadonotakashi 0:8fdf9a60065b 617 */
kadonotakashi 0:8fdf9a60065b 618 bool SDHC_Reset(SDHC_Type *base, uint32_t mask, uint32_t timeout);
kadonotakashi 0:8fdf9a60065b 619
kadonotakashi 0:8fdf9a60065b 620 /* @} */
kadonotakashi 0:8fdf9a60065b 621
kadonotakashi 0:8fdf9a60065b 622 /*!
kadonotakashi 0:8fdf9a60065b 623 * @name DMA Control
kadonotakashi 0:8fdf9a60065b 624 * @{
kadonotakashi 0:8fdf9a60065b 625 */
kadonotakashi 0:8fdf9a60065b 626
kadonotakashi 0:8fdf9a60065b 627 /*!
kadonotakashi 0:8fdf9a60065b 628 * @brief Sets the ADMA descriptor table configuration.
kadonotakashi 0:8fdf9a60065b 629 *
kadonotakashi 0:8fdf9a60065b 630 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 631 * @param dmaMode DMA mode.
kadonotakashi 0:8fdf9a60065b 632 * @param table ADMA table address.
kadonotakashi 0:8fdf9a60065b 633 * @param tableWords ADMA table buffer length united as Words.
kadonotakashi 0:8fdf9a60065b 634 * @param data Data buffer address.
kadonotakashi 0:8fdf9a60065b 635 * @param dataBytes Data length united as bytes.
kadonotakashi 0:8fdf9a60065b 636 * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data.
kadonotakashi 0:8fdf9a60065b 637 * @retval kStatus_Success Operate successfully.
kadonotakashi 0:8fdf9a60065b 638 */
kadonotakashi 0:8fdf9a60065b 639 status_t SDHC_SetAdmaTableConfig(SDHC_Type *base,
kadonotakashi 0:8fdf9a60065b 640 sdhc_dma_mode_t dmaMode,
kadonotakashi 0:8fdf9a60065b 641 uint32_t *table,
kadonotakashi 0:8fdf9a60065b 642 uint32_t tableWords,
kadonotakashi 0:8fdf9a60065b 643 const uint32_t *data,
kadonotakashi 0:8fdf9a60065b 644 uint32_t dataBytes);
kadonotakashi 0:8fdf9a60065b 645
kadonotakashi 0:8fdf9a60065b 646 /* @} */
kadonotakashi 0:8fdf9a60065b 647
kadonotakashi 0:8fdf9a60065b 648 /*!
kadonotakashi 0:8fdf9a60065b 649 * @name Interrupts
kadonotakashi 0:8fdf9a60065b 650 * @{
kadonotakashi 0:8fdf9a60065b 651 */
kadonotakashi 0:8fdf9a60065b 652
kadonotakashi 0:8fdf9a60065b 653 /*!
kadonotakashi 0:8fdf9a60065b 654 * @brief Enables the interrupt status.
kadonotakashi 0:8fdf9a60065b 655 *
kadonotakashi 0:8fdf9a60065b 656 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 657 * @param mask Interrupt status flags mask(_sdhc_interrupt_status_flag).
kadonotakashi 0:8fdf9a60065b 658 */
kadonotakashi 0:8fdf9a60065b 659 static inline void SDHC_EnableInterruptStatus(SDHC_Type *base, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 660 {
kadonotakashi 0:8fdf9a60065b 661 base->IRQSTATEN |= mask;
kadonotakashi 0:8fdf9a60065b 662 }
kadonotakashi 0:8fdf9a60065b 663
kadonotakashi 0:8fdf9a60065b 664 /*!
kadonotakashi 0:8fdf9a60065b 665 * @brief Disables the interrupt status.
kadonotakashi 0:8fdf9a60065b 666 *
kadonotakashi 0:8fdf9a60065b 667 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 668 * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag).
kadonotakashi 0:8fdf9a60065b 669 */
kadonotakashi 0:8fdf9a60065b 670 static inline void SDHC_DisableInterruptStatus(SDHC_Type *base, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 671 {
kadonotakashi 0:8fdf9a60065b 672 base->IRQSTATEN &= ~mask;
kadonotakashi 0:8fdf9a60065b 673 }
kadonotakashi 0:8fdf9a60065b 674
kadonotakashi 0:8fdf9a60065b 675 /*!
kadonotakashi 0:8fdf9a60065b 676 * @brief Enables the interrupt signal corresponding to the interrupt status flag.
kadonotakashi 0:8fdf9a60065b 677 *
kadonotakashi 0:8fdf9a60065b 678 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 679 * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag).
kadonotakashi 0:8fdf9a60065b 680 */
kadonotakashi 0:8fdf9a60065b 681 static inline void SDHC_EnableInterruptSignal(SDHC_Type *base, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 682 {
kadonotakashi 0:8fdf9a60065b 683 base->IRQSIGEN |= mask;
kadonotakashi 0:8fdf9a60065b 684 }
kadonotakashi 0:8fdf9a60065b 685
kadonotakashi 0:8fdf9a60065b 686 /*!
kadonotakashi 0:8fdf9a60065b 687 * @brief Disables the interrupt signal corresponding to the interrupt status flag.
kadonotakashi 0:8fdf9a60065b 688 *
kadonotakashi 0:8fdf9a60065b 689 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 690 * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag).
kadonotakashi 0:8fdf9a60065b 691 */
kadonotakashi 0:8fdf9a60065b 692 static inline void SDHC_DisableInterruptSignal(SDHC_Type *base, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 693 {
kadonotakashi 0:8fdf9a60065b 694 base->IRQSIGEN &= ~mask;
kadonotakashi 0:8fdf9a60065b 695 }
kadonotakashi 0:8fdf9a60065b 696
kadonotakashi 0:8fdf9a60065b 697 /* @} */
kadonotakashi 0:8fdf9a60065b 698
kadonotakashi 0:8fdf9a60065b 699 /*!
kadonotakashi 0:8fdf9a60065b 700 * @name Status
kadonotakashi 0:8fdf9a60065b 701 * @{
kadonotakashi 0:8fdf9a60065b 702 */
kadonotakashi 0:8fdf9a60065b 703
kadonotakashi 0:8fdf9a60065b 704 /*!
kadonotakashi 0:8fdf9a60065b 705 * @brief Gets the current interrupt status.
kadonotakashi 0:8fdf9a60065b 706 *
kadonotakashi 0:8fdf9a60065b 707 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 708 * @return Current interrupt status flags mask(_sdhc_interrupt_status_flag).
kadonotakashi 0:8fdf9a60065b 709 */
kadonotakashi 0:8fdf9a60065b 710 static inline uint32_t SDHC_GetInterruptStatusFlags(SDHC_Type *base)
kadonotakashi 0:8fdf9a60065b 711 {
kadonotakashi 0:8fdf9a60065b 712 return base->IRQSTAT;
kadonotakashi 0:8fdf9a60065b 713 }
kadonotakashi 0:8fdf9a60065b 714
kadonotakashi 0:8fdf9a60065b 715 /*!
kadonotakashi 0:8fdf9a60065b 716 * @brief Clears a specified interrupt status.
kadonotakashi 0:8fdf9a60065b 717 *
kadonotakashi 0:8fdf9a60065b 718 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 719 * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag).
kadonotakashi 0:8fdf9a60065b 720 */
kadonotakashi 0:8fdf9a60065b 721 static inline void SDHC_ClearInterruptStatusFlags(SDHC_Type *base, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 722 {
kadonotakashi 0:8fdf9a60065b 723 base->IRQSTAT = mask;
kadonotakashi 0:8fdf9a60065b 724 }
kadonotakashi 0:8fdf9a60065b 725
kadonotakashi 0:8fdf9a60065b 726 /*!
kadonotakashi 0:8fdf9a60065b 727 * @brief Gets the status of auto command 12 error.
kadonotakashi 0:8fdf9a60065b 728 *
kadonotakashi 0:8fdf9a60065b 729 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 730 * @return Auto command 12 error status flags mask(_sdhc_auto_command12_error_status_flag).
kadonotakashi 0:8fdf9a60065b 731 */
kadonotakashi 0:8fdf9a60065b 732 static inline uint32_t SDHC_GetAutoCommand12ErrorStatusFlags(SDHC_Type *base)
kadonotakashi 0:8fdf9a60065b 733 {
kadonotakashi 0:8fdf9a60065b 734 return base->AC12ERR;
kadonotakashi 0:8fdf9a60065b 735 }
kadonotakashi 0:8fdf9a60065b 736
kadonotakashi 0:8fdf9a60065b 737 /*!
kadonotakashi 0:8fdf9a60065b 738 * @brief Gets the status of the ADMA error.
kadonotakashi 0:8fdf9a60065b 739 *
kadonotakashi 0:8fdf9a60065b 740 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 741 * @return ADMA error status flags mask(_sdhc_adma_error_status_flag).
kadonotakashi 0:8fdf9a60065b 742 */
kadonotakashi 0:8fdf9a60065b 743 static inline uint32_t SDHC_GetAdmaErrorStatusFlags(SDHC_Type *base)
kadonotakashi 0:8fdf9a60065b 744 {
kadonotakashi 0:8fdf9a60065b 745 return base->ADMAES;
kadonotakashi 0:8fdf9a60065b 746 }
kadonotakashi 0:8fdf9a60065b 747
kadonotakashi 0:8fdf9a60065b 748 /*!
kadonotakashi 0:8fdf9a60065b 749 * @brief Gets a present status.
kadonotakashi 0:8fdf9a60065b 750 *
kadonotakashi 0:8fdf9a60065b 751 * This function gets the present SDHC's status except for an interrupt status and an error status.
kadonotakashi 0:8fdf9a60065b 752 *
kadonotakashi 0:8fdf9a60065b 753 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 754 * @return Present SDHC's status flags mask(_sdhc_present_status_flag).
kadonotakashi 0:8fdf9a60065b 755 */
kadonotakashi 0:8fdf9a60065b 756 static inline uint32_t SDHC_GetPresentStatusFlags(SDHC_Type *base)
kadonotakashi 0:8fdf9a60065b 757 {
kadonotakashi 0:8fdf9a60065b 758 return base->PRSSTAT;
kadonotakashi 0:8fdf9a60065b 759 }
kadonotakashi 0:8fdf9a60065b 760
kadonotakashi 0:8fdf9a60065b 761 /* @} */
kadonotakashi 0:8fdf9a60065b 762
kadonotakashi 0:8fdf9a60065b 763 /*!
kadonotakashi 0:8fdf9a60065b 764 * @name Bus Operations
kadonotakashi 0:8fdf9a60065b 765 * @{
kadonotakashi 0:8fdf9a60065b 766 */
kadonotakashi 0:8fdf9a60065b 767
kadonotakashi 0:8fdf9a60065b 768 /*!
kadonotakashi 0:8fdf9a60065b 769 * @brief Gets the capability information.
kadonotakashi 0:8fdf9a60065b 770 *
kadonotakashi 0:8fdf9a60065b 771 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 772 * @param capability Structure to save capability information.
kadonotakashi 0:8fdf9a60065b 773 */
kadonotakashi 0:8fdf9a60065b 774 void SDHC_GetCapability(SDHC_Type *base, sdhc_capability_t *capability);
kadonotakashi 0:8fdf9a60065b 775
kadonotakashi 0:8fdf9a60065b 776 /*!
kadonotakashi 0:8fdf9a60065b 777 * @brief Enables or disables the SD bus clock.
kadonotakashi 0:8fdf9a60065b 778 *
kadonotakashi 0:8fdf9a60065b 779 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 780 * @param enable True to enable, false to disable.
kadonotakashi 0:8fdf9a60065b 781 */
kadonotakashi 0:8fdf9a60065b 782 static inline void SDHC_EnableSdClock(SDHC_Type *base, bool enable)
kadonotakashi 0:8fdf9a60065b 783 {
kadonotakashi 0:8fdf9a60065b 784 if (enable)
kadonotakashi 0:8fdf9a60065b 785 {
kadonotakashi 0:8fdf9a60065b 786 base->SYSCTL |= SDHC_SYSCTL_SDCLKEN_MASK;
kadonotakashi 0:8fdf9a60065b 787 }
kadonotakashi 0:8fdf9a60065b 788 else
kadonotakashi 0:8fdf9a60065b 789 {
kadonotakashi 0:8fdf9a60065b 790 base->SYSCTL &= ~SDHC_SYSCTL_SDCLKEN_MASK;
kadonotakashi 0:8fdf9a60065b 791 }
kadonotakashi 0:8fdf9a60065b 792 }
kadonotakashi 0:8fdf9a60065b 793
kadonotakashi 0:8fdf9a60065b 794 /*!
kadonotakashi 0:8fdf9a60065b 795 * @brief Sets the SD bus clock frequency.
kadonotakashi 0:8fdf9a60065b 796 *
kadonotakashi 0:8fdf9a60065b 797 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 798 * @param srcClock_Hz SDHC source clock frequency united in Hz.
kadonotakashi 0:8fdf9a60065b 799 * @param busClock_Hz SD bus clock frequency united in Hz.
kadonotakashi 0:8fdf9a60065b 800 *
kadonotakashi 0:8fdf9a60065b 801 * @return The nearest frequency of busClock_Hz configured to SD bus.
kadonotakashi 0:8fdf9a60065b 802 */
kadonotakashi 0:8fdf9a60065b 803 uint32_t SDHC_SetSdClock(SDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz);
kadonotakashi 0:8fdf9a60065b 804
kadonotakashi 0:8fdf9a60065b 805 /*!
kadonotakashi 0:8fdf9a60065b 806 * @brief Sends 80 clocks to the card to set it to the active state.
kadonotakashi 0:8fdf9a60065b 807 *
kadonotakashi 0:8fdf9a60065b 808 * This function must be called each time the card is inserted to ensure that the card can receive the command
kadonotakashi 0:8fdf9a60065b 809 * correctly.
kadonotakashi 0:8fdf9a60065b 810 *
kadonotakashi 0:8fdf9a60065b 811 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 812 * @param timeout Timeout to initialize card.
kadonotakashi 0:8fdf9a60065b 813 * @retval true Set card active successfully.
kadonotakashi 0:8fdf9a60065b 814 * @retval false Set card active failed.
kadonotakashi 0:8fdf9a60065b 815 */
kadonotakashi 0:8fdf9a60065b 816 bool SDHC_SetCardActive(SDHC_Type *base, uint32_t timeout);
kadonotakashi 0:8fdf9a60065b 817
kadonotakashi 0:8fdf9a60065b 818 /*!
kadonotakashi 0:8fdf9a60065b 819 * @brief Sets the data transfer width.
kadonotakashi 0:8fdf9a60065b 820 *
kadonotakashi 0:8fdf9a60065b 821 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 822 * @param width Data transfer width.
kadonotakashi 0:8fdf9a60065b 823 */
kadonotakashi 0:8fdf9a60065b 824 static inline void SDHC_SetDataBusWidth(SDHC_Type *base, sdhc_data_bus_width_t width)
kadonotakashi 0:8fdf9a60065b 825 {
kadonotakashi 0:8fdf9a60065b 826 base->PROCTL = ((base->PROCTL & ~SDHC_PROCTL_DTW_MASK) | SDHC_PROCTL_DTW(width));
kadonotakashi 0:8fdf9a60065b 827 }
kadonotakashi 0:8fdf9a60065b 828
kadonotakashi 0:8fdf9a60065b 829 /*!
kadonotakashi 0:8fdf9a60065b 830 * @brief Sets the card transfer-related configuration.
kadonotakashi 0:8fdf9a60065b 831 *
kadonotakashi 0:8fdf9a60065b 832 * This function fills the card transfer-related command argument/transfer flag/data size. The command and data are sent
kadonotakashi 0:8fdf9a60065b 833 by
kadonotakashi 0:8fdf9a60065b 834 * SDHC after calling this function.
kadonotakashi 0:8fdf9a60065b 835 *
kadonotakashi 0:8fdf9a60065b 836 * Example:
kadonotakashi 0:8fdf9a60065b 837 @code
kadonotakashi 0:8fdf9a60065b 838 sdhc_transfer_config_t transferConfig;
kadonotakashi 0:8fdf9a60065b 839 transferConfig.dataBlockSize = 512U;
kadonotakashi 0:8fdf9a60065b 840 transferConfig.dataBlockCount = 2U;
kadonotakashi 0:8fdf9a60065b 841 transferConfig.commandArgument = 0x01AAU;
kadonotakashi 0:8fdf9a60065b 842 transferConfig.commandIndex = 8U;
kadonotakashi 0:8fdf9a60065b 843 transferConfig.flags |= (kSDHC_EnableDmaFlag | kSDHC_EnableAutoCommand12Flag | kSDHC_MultipleBlockFlag);
kadonotakashi 0:8fdf9a60065b 844 SDHC_SetTransferConfig(SDHC, &transferConfig);
kadonotakashi 0:8fdf9a60065b 845 @endcode
kadonotakashi 0:8fdf9a60065b 846 *
kadonotakashi 0:8fdf9a60065b 847 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 848 * @param config Command configuration structure.
kadonotakashi 0:8fdf9a60065b 849 */
kadonotakashi 0:8fdf9a60065b 850 void SDHC_SetTransferConfig(SDHC_Type *base, const sdhc_transfer_config_t *config);
kadonotakashi 0:8fdf9a60065b 851
kadonotakashi 0:8fdf9a60065b 852 /*!
kadonotakashi 0:8fdf9a60065b 853 * @brief Gets the command response.
kadonotakashi 0:8fdf9a60065b 854 *
kadonotakashi 0:8fdf9a60065b 855 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 856 * @param index The index of response register, range from 0 to 3.
kadonotakashi 0:8fdf9a60065b 857 * @return Response register transfer.
kadonotakashi 0:8fdf9a60065b 858 */
kadonotakashi 0:8fdf9a60065b 859 static inline uint32_t SDHC_GetCommandResponse(SDHC_Type *base, uint32_t index)
kadonotakashi 0:8fdf9a60065b 860 {
kadonotakashi 0:8fdf9a60065b 861 assert(index < 4U);
kadonotakashi 0:8fdf9a60065b 862
kadonotakashi 0:8fdf9a60065b 863 return base->CMDRSP[index];
kadonotakashi 0:8fdf9a60065b 864 }
kadonotakashi 0:8fdf9a60065b 865
kadonotakashi 0:8fdf9a60065b 866 /*!
kadonotakashi 0:8fdf9a60065b 867 * @brief Fills the the data port.
kadonotakashi 0:8fdf9a60065b 868 *
kadonotakashi 0:8fdf9a60065b 869 * This function is used to implement the data transfer by Data Port instead of DMA.
kadonotakashi 0:8fdf9a60065b 870 *
kadonotakashi 0:8fdf9a60065b 871 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 872 * @param data The data about to be sent.
kadonotakashi 0:8fdf9a60065b 873 */
kadonotakashi 0:8fdf9a60065b 874 static inline void SDHC_WriteData(SDHC_Type *base, uint32_t data)
kadonotakashi 0:8fdf9a60065b 875 {
kadonotakashi 0:8fdf9a60065b 876 base->DATPORT = data;
kadonotakashi 0:8fdf9a60065b 877 }
kadonotakashi 0:8fdf9a60065b 878
kadonotakashi 0:8fdf9a60065b 879 /*!
kadonotakashi 0:8fdf9a60065b 880 * @brief Retrieves the data from the data port.
kadonotakashi 0:8fdf9a60065b 881 *
kadonotakashi 0:8fdf9a60065b 882 * This function is used to implement the data transfer by Data Port instead of DMA.
kadonotakashi 0:8fdf9a60065b 883 *
kadonotakashi 0:8fdf9a60065b 884 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 885 * @return The data has been read.
kadonotakashi 0:8fdf9a60065b 886 */
kadonotakashi 0:8fdf9a60065b 887 static inline uint32_t SDHC_ReadData(SDHC_Type *base)
kadonotakashi 0:8fdf9a60065b 888 {
kadonotakashi 0:8fdf9a60065b 889 return base->DATPORT;
kadonotakashi 0:8fdf9a60065b 890 }
kadonotakashi 0:8fdf9a60065b 891
kadonotakashi 0:8fdf9a60065b 892 /*!
kadonotakashi 0:8fdf9a60065b 893 * @brief Enables or disables a wakeup event in low-power mode.
kadonotakashi 0:8fdf9a60065b 894 *
kadonotakashi 0:8fdf9a60065b 895 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 896 * @param mask Wakeup events mask(_sdhc_wakeup_event).
kadonotakashi 0:8fdf9a60065b 897 * @param enable True to enable, false to disable.
kadonotakashi 0:8fdf9a60065b 898 */
kadonotakashi 0:8fdf9a60065b 899 static inline void SDHC_EnableWakeupEvent(SDHC_Type *base, uint32_t mask, bool enable)
kadonotakashi 0:8fdf9a60065b 900 {
kadonotakashi 0:8fdf9a60065b 901 if (enable)
kadonotakashi 0:8fdf9a60065b 902 {
kadonotakashi 0:8fdf9a60065b 903 base->PROCTL |= mask;
kadonotakashi 0:8fdf9a60065b 904 }
kadonotakashi 0:8fdf9a60065b 905 else
kadonotakashi 0:8fdf9a60065b 906 {
kadonotakashi 0:8fdf9a60065b 907 base->PROCTL &= ~mask;
kadonotakashi 0:8fdf9a60065b 908 }
kadonotakashi 0:8fdf9a60065b 909 }
kadonotakashi 0:8fdf9a60065b 910
kadonotakashi 0:8fdf9a60065b 911 /*!
kadonotakashi 0:8fdf9a60065b 912 * @brief Enables or disables the card detection level for testing.
kadonotakashi 0:8fdf9a60065b 913 *
kadonotakashi 0:8fdf9a60065b 914 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 915 * @param enable True to enable, false to disable.
kadonotakashi 0:8fdf9a60065b 916 */
kadonotakashi 0:8fdf9a60065b 917 static inline void SDHC_EnableCardDetectTest(SDHC_Type *base, bool enable)
kadonotakashi 0:8fdf9a60065b 918 {
kadonotakashi 0:8fdf9a60065b 919 if (enable)
kadonotakashi 0:8fdf9a60065b 920 {
kadonotakashi 0:8fdf9a60065b 921 base->PROCTL |= SDHC_PROCTL_CDSS_MASK;
kadonotakashi 0:8fdf9a60065b 922 }
kadonotakashi 0:8fdf9a60065b 923 else
kadonotakashi 0:8fdf9a60065b 924 {
kadonotakashi 0:8fdf9a60065b 925 base->PROCTL &= ~SDHC_PROCTL_CDSS_MASK;
kadonotakashi 0:8fdf9a60065b 926 }
kadonotakashi 0:8fdf9a60065b 927 }
kadonotakashi 0:8fdf9a60065b 928
kadonotakashi 0:8fdf9a60065b 929 /*!
kadonotakashi 0:8fdf9a60065b 930 * @brief Sets the card detection test level.
kadonotakashi 0:8fdf9a60065b 931 *
kadonotakashi 0:8fdf9a60065b 932 * This function sets the card detection test level to indicate whether the card is inserted into the SDHC when DAT[3]/
kadonotakashi 0:8fdf9a60065b 933 * CD pin is selected as a card detection pin. This function can also assert the pin logic when DAT[3]/CD pin is
kadonotakashi 0:8fdf9a60065b 934 * selected
kadonotakashi 0:8fdf9a60065b 935 * as the card detection pin.
kadonotakashi 0:8fdf9a60065b 936 *
kadonotakashi 0:8fdf9a60065b 937 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 938 * @param high True to set the card detect level to high.
kadonotakashi 0:8fdf9a60065b 939 */
kadonotakashi 0:8fdf9a60065b 940 static inline void SDHC_SetCardDetectTestLevel(SDHC_Type *base, bool high)
kadonotakashi 0:8fdf9a60065b 941 {
kadonotakashi 0:8fdf9a60065b 942 if (high)
kadonotakashi 0:8fdf9a60065b 943 {
kadonotakashi 0:8fdf9a60065b 944 base->PROCTL |= SDHC_PROCTL_CDTL_MASK;
kadonotakashi 0:8fdf9a60065b 945 }
kadonotakashi 0:8fdf9a60065b 946 else
kadonotakashi 0:8fdf9a60065b 947 {
kadonotakashi 0:8fdf9a60065b 948 base->PROCTL &= ~SDHC_PROCTL_CDTL_MASK;
kadonotakashi 0:8fdf9a60065b 949 }
kadonotakashi 0:8fdf9a60065b 950 }
kadonotakashi 0:8fdf9a60065b 951
kadonotakashi 0:8fdf9a60065b 952 /*!
kadonotakashi 0:8fdf9a60065b 953 * @brief Enables or disables the SDIO card control.
kadonotakashi 0:8fdf9a60065b 954 *
kadonotakashi 0:8fdf9a60065b 955 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 956 * @param mask SDIO card control flags mask(_sdhc_sdio_control_flag).
kadonotakashi 0:8fdf9a60065b 957 * @param enable True to enable, false to disable.
kadonotakashi 0:8fdf9a60065b 958 */
kadonotakashi 0:8fdf9a60065b 959 void SDHC_EnableSdioControl(SDHC_Type *base, uint32_t mask, bool enable);
kadonotakashi 0:8fdf9a60065b 960
kadonotakashi 0:8fdf9a60065b 961 /*!
kadonotakashi 0:8fdf9a60065b 962 * @brief Restarts a transaction which has stopped at the block GAP for the SDIO card.
kadonotakashi 0:8fdf9a60065b 963 *
kadonotakashi 0:8fdf9a60065b 964 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 965 */
kadonotakashi 0:8fdf9a60065b 966 static inline void SDHC_SetContinueRequest(SDHC_Type *base)
kadonotakashi 0:8fdf9a60065b 967 {
kadonotakashi 0:8fdf9a60065b 968 base->PROCTL |= SDHC_PROCTL_CREQ_MASK;
kadonotakashi 0:8fdf9a60065b 969 }
kadonotakashi 0:8fdf9a60065b 970
kadonotakashi 0:8fdf9a60065b 971 /*!
kadonotakashi 0:8fdf9a60065b 972 * @brief Configures the MMC boot feature.
kadonotakashi 0:8fdf9a60065b 973 *
kadonotakashi 0:8fdf9a60065b 974 * Example:
kadonotakashi 0:8fdf9a60065b 975 @code
kadonotakashi 0:8fdf9a60065b 976 sdhc_boot_config_t config;
kadonotakashi 0:8fdf9a60065b 977 config.ackTimeoutCount = 4;
kadonotakashi 0:8fdf9a60065b 978 config.bootMode = kSDHC_BootModeNormal;
kadonotakashi 0:8fdf9a60065b 979 config.blockCount = 5;
kadonotakashi 0:8fdf9a60065b 980 config.enableBootAck = true;
kadonotakashi 0:8fdf9a60065b 981 config.enableBoot = true;
kadonotakashi 0:8fdf9a60065b 982 config.enableAutoStopAtBlockGap = true;
kadonotakashi 0:8fdf9a60065b 983 SDHC_SetMmcBootConfig(SDHC, &config);
kadonotakashi 0:8fdf9a60065b 984 @endcode
kadonotakashi 0:8fdf9a60065b 985 *
kadonotakashi 0:8fdf9a60065b 986 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 987 * @param config The MMC boot configuration information.
kadonotakashi 0:8fdf9a60065b 988 */
kadonotakashi 0:8fdf9a60065b 989 void SDHC_SetMmcBootConfig(SDHC_Type *base, const sdhc_boot_config_t *config);
kadonotakashi 0:8fdf9a60065b 990
kadonotakashi 0:8fdf9a60065b 991 /*!
kadonotakashi 0:8fdf9a60065b 992 * @brief Forces generating events according to the given mask.
kadonotakashi 0:8fdf9a60065b 993 *
kadonotakashi 0:8fdf9a60065b 994 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 995 * @param mask The force events mask(_sdhc_force_event).
kadonotakashi 0:8fdf9a60065b 996 */
kadonotakashi 0:8fdf9a60065b 997 static inline void SDHC_SetForceEvent(SDHC_Type *base, uint32_t mask)
kadonotakashi 0:8fdf9a60065b 998 {
kadonotakashi 0:8fdf9a60065b 999 base->FEVT = mask;
kadonotakashi 0:8fdf9a60065b 1000 }
kadonotakashi 0:8fdf9a60065b 1001
kadonotakashi 0:8fdf9a60065b 1002 /* @} */
kadonotakashi 0:8fdf9a60065b 1003
kadonotakashi 0:8fdf9a60065b 1004 /*!
kadonotakashi 0:8fdf9a60065b 1005 * @name Transactional
kadonotakashi 0:8fdf9a60065b 1006 * @{
kadonotakashi 0:8fdf9a60065b 1007 */
kadonotakashi 0:8fdf9a60065b 1008
kadonotakashi 0:8fdf9a60065b 1009 /*!
kadonotakashi 0:8fdf9a60065b 1010 * @brief Transfers the command/data using a blocking method.
kadonotakashi 0:8fdf9a60065b 1011 *
kadonotakashi 0:8fdf9a60065b 1012 * This function waits until the command response/data is received or the SDHC encounters an error by polling the status
kadonotakashi 0:8fdf9a60065b 1013 * flag.
kadonotakashi 0:8fdf9a60065b 1014 * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
kadonotakashi 0:8fdf9a60065b 1015 * the re-entry mechanism.
kadonotakashi 0:8fdf9a60065b 1016 *
kadonotakashi 0:8fdf9a60065b 1017 * @note There is no need to call the API 'SDHC_TransferCreateHandle' when calling this API.
kadonotakashi 0:8fdf9a60065b 1018 *
kadonotakashi 0:8fdf9a60065b 1019 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 1020 * @param admaTable ADMA table address, can't be null if transfer way is ADMA1/ADMA2.
kadonotakashi 0:8fdf9a60065b 1021 * @param admaTableWords ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2.
kadonotakashi 0:8fdf9a60065b 1022 * @param transfer Transfer content.
kadonotakashi 0:8fdf9a60065b 1023 * @retval kStatus_InvalidArgument Argument is invalid.
kadonotakashi 0:8fdf9a60065b 1024 * @retval kStatus_SDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed.
kadonotakashi 0:8fdf9a60065b 1025 * @retval kStatus_SDHC_SendCommandFailed Send command failed.
kadonotakashi 0:8fdf9a60065b 1026 * @retval kStatus_SDHC_TransferDataFailed Transfer data failed.
kadonotakashi 0:8fdf9a60065b 1027 * @retval kStatus_Success Operate successfully.
kadonotakashi 0:8fdf9a60065b 1028 */
kadonotakashi 0:8fdf9a60065b 1029 status_t SDHC_TransferBlocking(SDHC_Type *base,
kadonotakashi 0:8fdf9a60065b 1030 uint32_t *admaTable,
kadonotakashi 0:8fdf9a60065b 1031 uint32_t admaTableWords,
kadonotakashi 0:8fdf9a60065b 1032 sdhc_transfer_t *transfer);
kadonotakashi 0:8fdf9a60065b 1033
kadonotakashi 0:8fdf9a60065b 1034 /*!
kadonotakashi 0:8fdf9a60065b 1035 * @brief Creates the SDHC handle.
kadonotakashi 0:8fdf9a60065b 1036 *
kadonotakashi 0:8fdf9a60065b 1037 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 1038 * @param handle SDHC handle pointer.
kadonotakashi 0:8fdf9a60065b 1039 * @param callback Structure pointer to contain all callback functions.
kadonotakashi 0:8fdf9a60065b 1040 * @param userData Callback function parameter.
kadonotakashi 0:8fdf9a60065b 1041 */
kadonotakashi 0:8fdf9a60065b 1042 void SDHC_TransferCreateHandle(SDHC_Type *base,
kadonotakashi 0:8fdf9a60065b 1043 sdhc_handle_t *handle,
kadonotakashi 0:8fdf9a60065b 1044 const sdhc_transfer_callback_t *callback,
kadonotakashi 0:8fdf9a60065b 1045 void *userData);
kadonotakashi 0:8fdf9a60065b 1046
kadonotakashi 0:8fdf9a60065b 1047 /*!
kadonotakashi 0:8fdf9a60065b 1048 * @brief Transfers the command/data using an interrupt and an asynchronous method.
kadonotakashi 0:8fdf9a60065b 1049 *
kadonotakashi 0:8fdf9a60065b 1050 * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or encounter an
kadonotakashi 0:8fdf9a60065b 1051 * error.
kadonotakashi 0:8fdf9a60065b 1052 * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
kadonotakashi 0:8fdf9a60065b 1053 * the re-entry mechanism.
kadonotakashi 0:8fdf9a60065b 1054 *
kadonotakashi 0:8fdf9a60065b 1055 * @note Call the API 'SDHC_TransferCreateHandle' when calling this API.
kadonotakashi 0:8fdf9a60065b 1056 *
kadonotakashi 0:8fdf9a60065b 1057 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 1058 * @param handle SDHC handle.
kadonotakashi 0:8fdf9a60065b 1059 * @param admaTable ADMA table address, can't be null if transfer way is ADMA1/ADMA2.
kadonotakashi 0:8fdf9a60065b 1060 * @param admaTableWords ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2.
kadonotakashi 0:8fdf9a60065b 1061 * @param transfer Transfer content.
kadonotakashi 0:8fdf9a60065b 1062 * @retval kStatus_InvalidArgument Argument is invalid.
kadonotakashi 0:8fdf9a60065b 1063 * @retval kStatus_SDHC_BusyTransferring Busy transferring.
kadonotakashi 0:8fdf9a60065b 1064 * @retval kStatus_SDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed.
kadonotakashi 0:8fdf9a60065b 1065 * @retval kStatus_Success Operate successfully.
kadonotakashi 0:8fdf9a60065b 1066 */
kadonotakashi 0:8fdf9a60065b 1067 status_t SDHC_TransferNonBlocking(
kadonotakashi 0:8fdf9a60065b 1068 SDHC_Type *base, sdhc_handle_t *handle, uint32_t *admaTable, uint32_t admaTableWords, sdhc_transfer_t *transfer);
kadonotakashi 0:8fdf9a60065b 1069
kadonotakashi 0:8fdf9a60065b 1070 /*!
kadonotakashi 0:8fdf9a60065b 1071 * @brief IRQ handler for the SDHC.
kadonotakashi 0:8fdf9a60065b 1072 *
kadonotakashi 0:8fdf9a60065b 1073 * This function deals with the IRQs on the given host controller.
kadonotakashi 0:8fdf9a60065b 1074 *
kadonotakashi 0:8fdf9a60065b 1075 * @param base SDHC peripheral base address.
kadonotakashi 0:8fdf9a60065b 1076 * @param handle SDHC handle.
kadonotakashi 0:8fdf9a60065b 1077 */
kadonotakashi 0:8fdf9a60065b 1078 void SDHC_TransferHandleIRQ(SDHC_Type *base, sdhc_handle_t *handle);
kadonotakashi 0:8fdf9a60065b 1079
kadonotakashi 0:8fdf9a60065b 1080 /* @} */
kadonotakashi 0:8fdf9a60065b 1081
kadonotakashi 0:8fdf9a60065b 1082 #if defined(__cplusplus)
kadonotakashi 0:8fdf9a60065b 1083 }
kadonotakashi 0:8fdf9a60065b 1084 #endif
kadonotakashi 0:8fdf9a60065b 1085 /*! @} */
kadonotakashi 0:8fdf9a60065b 1086
kadonotakashi 0:8fdf9a60065b 1087 #endif /* _FSL_SDHC_H_*/