Kazuki Yamamoto / Mbed 2 deprecated uart_i2c_conv

UART to I2C master(s) converter, targetting to emulate SC18IM700(NXP) chip

Dependencies:   mbed

UART to I2C master(s) converter, targetting to emulate SC18IM700(NXP) chip

Features

up to 4x I2C master

  • for LPC824 implement, we can use up to 4 channels of I2C masters
    • 1x Fm+ and 3x Fm I2C channels
  • for LPC1768 implement, we can use up to 2 channels of I2C masters
    • 2x Fm I2C channels
  • for LPC11U35 implement, only one channel for I2C master, but program uses USB CDC class for UART communication (means no external USB-Serial converter chip)
    • 1x Fm+ I2C channels

1x SPI master

up to 2x 8bit GPIO

Tested Platforms

LPC824

LPC1768

LPC11U35

Quote:

LPC11U35 implement requires importing USBDevice library to use USBSerial class

visit https://github.com/K4zuki/tinyI2C for more information

main.cpp@78:434514b8d383, 2016-09-03 (annotated)

Committer:
K4zuki
Date:
Sat Sep 03 00:47:37 2016 +0900
Revision:
78:434514b8d383
Parent:
36:ffbd9829c8d1
Child:
80:3cbe7972872b
remove force-LF attribute

Who changed what in which revision?

UserRevisionLine numberNew contents of line
K4zuki 78:434514b8d383 1 /** uart_i2c_conv for LPC824
K4zuki 78:434514b8d383 2 */
K4zuki 78:434514b8d383 3
K4zuki 78:434514b8d383 4 #include "mbed.h"
K4zuki 78:434514b8d383 5 #include "settings.h"
K4zuki 78:434514b8d383 6 //Table 3. ASCII commands supported by SC18IM700
K4zuki 78:434514b8d383 7 //ASCII command Hex value Command function
K4zuki 78:434514b8d383 8 //[X] S 0x53 I2C-bus START
K4zuki 78:434514b8d383 9 //[X] P 0x50 I2C/SPI-bus STOP
K4zuki 78:434514b8d383 10 //[X] R 0x52 read SC18IM700 internal register
K4zuki 78:434514b8d383 11 //[X] W 0x57 write to SC18IM700 internal register
K4zuki 78:434514b8d383 12 //[?] I 0x49 read GPIO port
K4zuki 78:434514b8d383 13 //[?] O 0x4F write to GPIO port
K4zuki 78:434514b8d383 14 //[_] Z 0x5A power down
K4zuki 78:434514b8d383 15 //[X] C 0x43 change channel
K4zuki 78:434514b8d383 16 //[_] E 0x45 SPI transfer start
K4zuki 78:434514b8d383 17 //[_] V 0x__ enable VDDIO output to chip
K4zuki 78:434514b8d383 18
K4zuki 78:434514b8d383 19 /**
K4zuki 78:434514b8d383 20 "C| '0'| P"
K4zuki 78:434514b8d383 21 "C| '1'| P"
K4zuki 78:434514b8d383 22 "C| '2'| P"
K4zuki 78:434514b8d383 23 "C| '3'| P"
K4zuki 78:434514b8d383 24 "S| 0x_8 _0| 0x_0 _4| 0x_D _E _A _D _B _E _A _F| P"
K4zuki 78:434514b8d383 25 "S| 0x_8 _0| 0x_0 _4| 0x_D _E _A _D _B _E _A _F| S| 0x_8 _1| 0x_0 _4| P"
K4zuki 78:434514b8d383 26 "S| 0x_8 _1| 0x_0 _4| P"
K4zuki 78:434514b8d383 27 "R| '0'| P"
K4zuki 78:434514b8d383 28 "R| '0'| '1'| ...| P"
K4zuki 78:434514b8d383 29 "W| '0' 0x_a _a| P"
K4zuki 78:434514b8d383 30 "W| '0' 0x_a _a| '1' 0x_b _b| ...| P"
K4zuki 78:434514b8d383 31 "I| '0'| P"
K4zuki 78:434514b8d383 32 "O| '0'| 0x_a _a| P"
K4zuki 78:434514b8d383 33 "E| 0x_0 _4| 0x_0 _0| 0x_D _E _A _D _B _E _A _F| P" //write
K4zuki 78:434514b8d383 34 "E| 0x_0 _4| 0x_0 _4| 0x_D _E _A _D _B _E _A _F| P" //write and read
K4zuki 78:434514b8d383 35 */
K4zuki 78:434514b8d383 36 int main()
K4zuki 78:434514b8d383 37 {
K4zuki 78:434514b8d383 38 I2C* dev = &dev1;
K4zuki 78:434514b8d383 39
K4zuki 78:434514b8d383 40 #ifdef isUART
K4zuki 78:434514b8d383 41 pc.baud(115200);
K4zuki 78:434514b8d383 42 #endif
K4zuki 78:434514b8d383 43 _spi.frequency(8000000);
K4zuki 78:434514b8d383 44
K4zuki 78:434514b8d383 45 bool s = false;
K4zuki 78:434514b8d383 46 dev1.frequency(400000);//800k; works around 940kHz with 200ohm pullups/ not work at 1M?
K4zuki 78:434514b8d383 47 #if defined(TARGET_SSCI824) || defined(TARGET_LP824MAX)
K4zuki 78:434514b8d383 48 dev1.frequency(800000);//800k; works around 940kHz with 200ohm pullups/ not work at 1M?
K4zuki 78:434514b8d383 49 LPC_IOCON->PIO0_11 &= ~(0x03<<8);
K4zuki 78:434514b8d383 50 LPC_IOCON->PIO0_11 |= (0x02<<8);
K4zuki 78:434514b8d383 51 LPC_IOCON->PIO0_10 &= ~(0x03<<8);
K4zuki 78:434514b8d383 52 LPC_IOCON->PIO0_10 |= (0x02<<8);
K4zuki 78:434514b8d383 53 #elif defined(TARGET_MCU_LPC11U35_501) || defined(TARGET_LPC11U35_401)
K4zuki 78:434514b8d383 54 dev1.frequency(800000);//800k; works around 940kHz with 200ohm pullups/ not work at 1M?
K4zuki 78:434514b8d383 55 LPC_IOCON->PIO0_4 &= ~(0x03<<8);
K4zuki 78:434514b8d383 56 LPC_IOCON->PIO0_4 |= (0x02<<8);
K4zuki 78:434514b8d383 57 LPC_IOCON->PIO0_5 &= ~(0x03<<8);
K4zuki 78:434514b8d383 58 LPC_IOCON->PIO0_5 |= (0x02<<8);
K4zuki 78:434514b8d383 59 #endif
K4zuki 78:434514b8d383 60
K4zuki 78:434514b8d383 61 #ifdef isI2C2
K4zuki 78:434514b8d383 62 dev2.frequency(400000);//400k
K4zuki 78:434514b8d383 63 #endif
K4zuki 78:434514b8d383 64 #ifdef isI2C3
K4zuki 78:434514b8d383 65 dev3.frequency(400000);//400k
K4zuki 78:434514b8d383 66 #endif
K4zuki 78:434514b8d383 67 #ifdef isI2C4
K4zuki 78:434514b8d383 68 dev4.frequency(400000);//400k
K4zuki 78:434514b8d383 69 #endif
K4zuki 78:434514b8d383 70 #ifdef isGPIO1
K4zuki 78:434514b8d383 71 DigitalInOut* gpio1[] = {
K4zuki 78:434514b8d383 72 &_GPIO10,
K4zuki 78:434514b8d383 73 &_GPIO11,
K4zuki 78:434514b8d383 74 &_GPIO12,
K4zuki 78:434514b8d383 75 &_GPIO13,
K4zuki 78:434514b8d383 76 &_GPIO14,
K4zuki 78:434514b8d383 77 &_GPIO15,
K4zuki 78:434514b8d383 78 &_GPIO16,
K4zuki 78:434514b8d383 79 &_GPIO17,
K4zuki 78:434514b8d383 80 };
K4zuki 78:434514b8d383 81 for(int k = 0; k < 8; k++){
K4zuki 78:434514b8d383 82 gpio1[k]->input();
K4zuki 78:434514b8d383 83 gpio1[k]->mode( PullUp );
K4zuki 78:434514b8d383 84 }
K4zuki 78:434514b8d383 85 #endif
K4zuki 78:434514b8d383 86
K4zuki 78:434514b8d383 87 DigitalInOut* gpio0[] = {
K4zuki 78:434514b8d383 88 &_GPIO00,
K4zuki 78:434514b8d383 89 &_GPIO01,
K4zuki 78:434514b8d383 90 &_GPIO02,
K4zuki 78:434514b8d383 91 &_GPIO03,
K4zuki 78:434514b8d383 92 &_GPIO04,
K4zuki 78:434514b8d383 93 &_GPIO05,
K4zuki 78:434514b8d383 94 &_GPIO06,
K4zuki 78:434514b8d383 95 &_GPIO07,
K4zuki 78:434514b8d383 96 };
K4zuki 78:434514b8d383 97 for(int k = 0; k < 8; k++){
K4zuki 78:434514b8d383 98 gpio0[k]->input();
K4zuki 78:434514b8d383 99 gpio0[k]->mode( PullUp );
K4zuki 78:434514b8d383 100 }
K4zuki 78:434514b8d383 101
K4zuki 78:434514b8d383 102 int ack = 0;
K4zuki 78:434514b8d383 103 int plength = 0;
K4zuki 78:434514b8d383 104 int recieve[256];
K4zuki 78:434514b8d383 105 char send[256];
K4zuki 78:434514b8d383 106 for(int k = 0; k < 256; k+=4){
K4zuki 78:434514b8d383 107 // cafe moca
K4zuki 78:434514b8d383 108 recieve[k+0] = send[k+0] = 0xC4;
K4zuki 78:434514b8d383 109 recieve[k+1] = send[k+1] = 0xFE;
K4zuki 78:434514b8d383 110 recieve[k+2] = send[k+2] = 0xE0;
K4zuki 78:434514b8d383 111 recieve[k+3] = send[k+3] = 0xCA;
K4zuki 78:434514b8d383 112 }
K4zuki 78:434514b8d383 113
K4zuki 78:434514b8d383 114 int read = 0;
K4zuki 78:434514b8d383 115 int address = 0;
K4zuki 78:434514b8d383 116 int data = 0;
K4zuki 78:434514b8d383 117 int _data = 0;
K4zuki 78:434514b8d383 118 int length = 0;
K4zuki 78:434514b8d383 119 int channel = 0;
K4zuki 78:434514b8d383 120 int format = 8;
K4zuki 78:434514b8d383 121 int enabled = 0;
K4zuki 78:434514b8d383 122 int disabled = 0;
K4zuki 78:434514b8d383 123 enum command_e {
K4zuki 78:434514b8d383 124 CMD_S='S',
K4zuki 78:434514b8d383 125 CMD_P='P',
K4zuki 78:434514b8d383 126 CMD_C='C',
K4zuki 78:434514b8d383 127 CMD_R='R',
K4zuki 78:434514b8d383 128 CMD_W='W',
K4zuki 78:434514b8d383 129 CMD_I='I',
K4zuki 78:434514b8d383 130 CMD_O='O',
K4zuki 78:434514b8d383 131 CMD_E='E',
K4zuki 78:434514b8d383 132 };
K4zuki 78:434514b8d383 133 enum channel_e {
K4zuki 78:434514b8d383 134 CH0 = '0',
K4zuki 78:434514b8d383 135 CH1 = '1',
K4zuki 78:434514b8d383 136 CH2 = '2',
K4zuki 78:434514b8d383 137 CH3 = '3',
K4zuki 78:434514b8d383 138 };
K4zuki 78:434514b8d383 139 enum register_e {
K4zuki 78:434514b8d383 140 CHIP_ID = '0',
K4zuki 78:434514b8d383 141 GPIO0_STAT = '1',
K4zuki 78:434514b8d383 142 GPIO1_STAT = '2',
K4zuki 78:434514b8d383 143 GPIO0_CONF = '3',
K4zuki 78:434514b8d383 144 GPIO1_CONF = '4',
K4zuki 78:434514b8d383 145 I2C_CONF = '5',
K4zuki 78:434514b8d383 146 SPI_CONF = '6',
K4zuki 78:434514b8d383 147 REG7,
K4zuki 78:434514b8d383 148 REG8,
K4zuki 78:434514b8d383 149 REG9,
K4zuki 78:434514b8d383 150 };
K4zuki 78:434514b8d383 151 // enum chipID_e {
K4zuki 78:434514b8d383 152 // ID_LPC824 = '0',
K4zuki 78:434514b8d383 153 // ID_LPC1768 = '1',
K4zuki 78:434514b8d383 154 // ID_LPC11UXX = '2',
K4zuki 78:434514b8d383 155 // };
K4zuki 78:434514b8d383 156 // static const uint8_t chip_id=ID_LPC824;
K4zuki 78:434514b8d383 157 static uint8_t registers[]={
K4zuki 78:434514b8d383 158 chip_id,
K4zuki 78:434514b8d383 159 0x00,
K4zuki 78:434514b8d383 160 0x00,
K4zuki 78:434514b8d383 161 0x00,
K4zuki 78:434514b8d383 162 0x00,
K4zuki 78:434514b8d383 163 0xFF,
K4zuki 78:434514b8d383 164 0x70,
K4zuki 78:434514b8d383 165 REG7,
K4zuki 78:434514b8d383 166 REG8,
K4zuki 78:434514b8d383 167 REG9,
K4zuki 78:434514b8d383 168 };
K4zuki 78:434514b8d383 169
K4zuki 78:434514b8d383 170 int i=0;
K4zuki 78:434514b8d383 171 while(1) {
K4zuki 78:434514b8d383 172 i=0;
K4zuki 78:434514b8d383 173 length=0;
K4zuki 78:434514b8d383 174 while(true) {
K4zuki 78:434514b8d383 175 read = pc.getc();
K4zuki 78:434514b8d383 176 recieve[i] = read;
K4zuki 78:434514b8d383 177 i++;
K4zuki 78:434514b8d383 178 if(read == 'P') {
K4zuki 78:434514b8d383 179 plength = i;
K4zuki 78:434514b8d383 180 break;
K4zuki 78:434514b8d383 181 }
K4zuki 78:434514b8d383 182 }
K4zuki 78:434514b8d383 183 i=0;
K4zuki 78:434514b8d383 184 while(i < plength) {
K4zuki 78:434514b8d383 185 switch(recieve[i]) {
K4zuki 78:434514b8d383 186 case CMD_C:
K4zuki 78:434514b8d383 187 {
K4zuki 78:434514b8d383 188 s = false;
K4zuki 78:434514b8d383 189 channel=recieve[i+1];
K4zuki 78:434514b8d383 190 switch(channel) {
K4zuki 78:434514b8d383 191 case CH0:
K4zuki 78:434514b8d383 192 {
K4zuki 78:434514b8d383 193 channel = CH0;
K4zuki 78:434514b8d383 194 dev = &dev1;
K4zuki 78:434514b8d383 195 break;
K4zuki 78:434514b8d383 196 }
K4zuki 78:434514b8d383 197 #ifdef isI2C2
K4zuki 78:434514b8d383 198 case CH1:
K4zuki 78:434514b8d383 199 {
K4zuki 78:434514b8d383 200 channel = CH1;
K4zuki 78:434514b8d383 201 dev = &dev2;
K4zuki 78:434514b8d383 202 break;
K4zuki 78:434514b8d383 203 }
K4zuki 78:434514b8d383 204 #endif
K4zuki 78:434514b8d383 205 #ifdef isI2C3
K4zuki 78:434514b8d383 206 case CH2:
K4zuki 78:434514b8d383 207 {
K4zuki 78:434514b8d383 208 channel = CH2;
K4zuki 78:434514b8d383 209 dev = &dev3;
K4zuki 78:434514b8d383 210 break;
K4zuki 78:434514b8d383 211 }
K4zuki 78:434514b8d383 212 #endif
K4zuki 78:434514b8d383 213 #ifdef isI2C4
K4zuki 78:434514b8d383 214 case CH3:
K4zuki 78:434514b8d383 215 {
K4zuki 78:434514b8d383 216 channel = CH3;
K4zuki 78:434514b8d383 217 dev = &dev4;
K4zuki 78:434514b8d383 218 break;
K4zuki 78:434514b8d383 219 }
K4zuki 78:434514b8d383 220 #endif
K4zuki 78:434514b8d383 221 default:
K4zuki 78:434514b8d383 222 {
K4zuki 78:434514b8d383 223 channel = CH0;
K4zuki 78:434514b8d383 224 dev = &dev1;
K4zuki 78:434514b8d383 225 break;
K4zuki 78:434514b8d383 226 }
K4zuki 78:434514b8d383 227 }
K4zuki 78:434514b8d383 228 i += 2;
K4zuki 78:434514b8d383 229 break;
K4zuki 78:434514b8d383 230 }
K4zuki 78:434514b8d383 231 case CMD_S:
K4zuki 78:434514b8d383 232 {
K4zuki 78:434514b8d383 233 s = true;
K4zuki 78:434514b8d383 234 ack = plength - 2 - (i+1) + (recieve[i+2] & 0x01);
K4zuki 78:434514b8d383 235 if(ack >= 4){ //valid packet
K4zuki 78:434514b8d383 236 address = 0xff & (recieve[i+1] << 4 | (recieve[i+2] & 0x0F));
K4zuki 78:434514b8d383 237 length = 0xff & (recieve[i+3] << 4 | (recieve[i+4] & 0x0F));
K4zuki 78:434514b8d383 238
K4zuki 78:434514b8d383 239 if(address & 0x01) { //read
K4zuki 78:434514b8d383 240 ack = dev->read(address, send, length, false); //added
K4zuki 78:434514b8d383 241 send[length] = ack;
K4zuki 78:434514b8d383 242 length += 1;
K4zuki 78:434514b8d383 243 i += 5;
K4zuki 78:434514b8d383 244 } else { // write
K4zuki 78:434514b8d383 245 for(int j = 0; j < (length * 2); j+=2) {
K4zuki 78:434514b8d383 246 ack = 0xff&((recieve[5+j] << 4) | (recieve[6+j] & 0x0F));
K4zuki 78:434514b8d383 247 *(send+(j/2)) = ack; //added
K4zuki 78:434514b8d383 248 }
K4zuki 78:434514b8d383 249 ack = dev->write(address, send, length, true); //added
K4zuki 78:434514b8d383 250 i += (5 + length * 2);
K4zuki 78:434514b8d383 251 send[0] = ack;
K4zuki 78:434514b8d383 252 length = 1;
K4zuki 78:434514b8d383 253 }
K4zuki 78:434514b8d383 254 }else{
K4zuki 78:434514b8d383 255 pc.printf("bad packet! %d, %d, %02X, %d\n\r",plength,i,recieve[(i+2)]&0x0F,ack);
K4zuki 78:434514b8d383 256 s = false;
K4zuki 78:434514b8d383 257 i = plength;
K4zuki 78:434514b8d383 258 }
K4zuki 78:434514b8d383 259 break;
K4zuki 78:434514b8d383 260 }
K4zuki 78:434514b8d383 261 case CMD_P:
K4zuki 78:434514b8d383 262 {
K4zuki 78:434514b8d383 263 if(s){
K4zuki 78:434514b8d383 264 dev->stop();
K4zuki 78:434514b8d383 265 s = false;
K4zuki 78:434514b8d383 266 if(send[length-1] == 0){
K4zuki 78:434514b8d383 267 pc.printf("ACK,");
K4zuki 78:434514b8d383 268 }else{
K4zuki 78:434514b8d383 269 pc.printf("NAK,");
K4zuki 78:434514b8d383 270 }
K4zuki 78:434514b8d383 271 length--;
K4zuki 78:434514b8d383 272 }
K4zuki 78:434514b8d383 273 i = plength;
K4zuki 78:434514b8d383 274 for(int j=0; j<length; j++) {
K4zuki 78:434514b8d383 275 pc.printf("%02X,",send[j]);
K4zuki 78:434514b8d383 276 }
K4zuki 78:434514b8d383 277 pc.printf("ok\n\r");
K4zuki 78:434514b8d383 278 break;
K4zuki 78:434514b8d383 279 }
K4zuki 78:434514b8d383 280 case CMD_R:
K4zuki 78:434514b8d383 281 {
K4zuki 78:434514b8d383 282 s = false;
K4zuki 78:434514b8d383 283 length = plength - 2;
K4zuki 78:434514b8d383 284 if(length < 1){
K4zuki 78:434514b8d383 285 pc.printf("bad packet! %d\n\r",length);
K4zuki 78:434514b8d383 286 i = plength + 1;
K4zuki 78:434514b8d383 287 length = 0;
K4zuki 78:434514b8d383 288 }else{
K4zuki 78:434514b8d383 289 for(int j = 0; j < length; j++){
K4zuki 78:434514b8d383 290 address = recieve[i+1+j];
K4zuki 78:434514b8d383 291 switch(address){
K4zuki 78:434514b8d383 292 case CHIP_ID:
K4zuki 78:434514b8d383 293 {
K4zuki 78:434514b8d383 294 data = chip_id;
K4zuki 78:434514b8d383 295 break;
K4zuki 78:434514b8d383 296 }
K4zuki 78:434514b8d383 297 case GPIO0_STAT:
K4zuki 78:434514b8d383 298 {
K4zuki 78:434514b8d383 299 for(int k = 0; k < 8; k++){
K4zuki 78:434514b8d383 300 _data = gpio0[k]->read();
K4zuki 78:434514b8d383 301 data |= (_data << k);
K4zuki 78:434514b8d383 302 }
K4zuki 78:434514b8d383 303 registers[GPIO0_STAT-'0'] = data;
K4zuki 78:434514b8d383 304 break;
K4zuki 78:434514b8d383 305 }
K4zuki 78:434514b8d383 306 case GPIO0_CONF:
K4zuki 78:434514b8d383 307 {
K4zuki 78:434514b8d383 308 data = registers[GPIO0_CONF-'0'];
K4zuki 78:434514b8d383 309 break;
K4zuki 78:434514b8d383 310 }
K4zuki 78:434514b8d383 311 #ifdef isGPIO1
K4zuki 78:434514b8d383 312 case GPIO1_STAT:
K4zuki 78:434514b8d383 313 {
K4zuki 78:434514b8d383 314 for(int k = 0; k < 8; k++){
K4zuki 78:434514b8d383 315 _data = gpio1[k]->read();
K4zuki 78:434514b8d383 316 data |= (_data << k);
K4zuki 78:434514b8d383 317 }
K4zuki 78:434514b8d383 318 registers[GPIO1_STAT-'0'] = data;
K4zuki 78:434514b8d383 319 break;
K4zuki 78:434514b8d383 320 }
K4zuki 78:434514b8d383 321 case GPIO1_CONF:
K4zuki 78:434514b8d383 322 {
K4zuki 78:434514b8d383 323 data = registers[GPIO1_CONF-'0'];
K4zuki 78:434514b8d383 324 break;
K4zuki 78:434514b8d383 325 }
K4zuki 78:434514b8d383 326 #endif
K4zuki 78:434514b8d383 327 case I2C_CONF:
K4zuki 78:434514b8d383 328 {
K4zuki 78:434514b8d383 329 data = registers[I2C_CONF-'0'];
K4zuki 78:434514b8d383 330 break;
K4zuki 78:434514b8d383 331 }
K4zuki 78:434514b8d383 332 case SPI_CONF:
K4zuki 78:434514b8d383 333 {
K4zuki 78:434514b8d383 334 data = registers[SPI_CONF-'0'];
K4zuki 78:434514b8d383 335 break;
K4zuki 78:434514b8d383 336 }
K4zuki 78:434514b8d383 337 default:
K4zuki 78:434514b8d383 338 {
K4zuki 78:434514b8d383 339 data = 0xAA;
K4zuki 78:434514b8d383 340 break;
K4zuki 78:434514b8d383 341 }
K4zuki 78:434514b8d383 342 }
K4zuki 78:434514b8d383 343 send[j] = (char)data;
K4zuki 78:434514b8d383 344 data = 0;
K4zuki 78:434514b8d383 345 }
K4zuki 78:434514b8d383 346 i += (length+1);
K4zuki 78:434514b8d383 347 }
K4zuki 78:434514b8d383 348 break;
K4zuki 78:434514b8d383 349 }
K4zuki 78:434514b8d383 350 case CMD_W:
K4zuki 78:434514b8d383 351 {
K4zuki 78:434514b8d383 352 s = false;
K4zuki 78:434514b8d383 353 length = plength - 2;
K4zuki 78:434514b8d383 354 if(length < 3){
K4zuki 78:434514b8d383 355 pc.printf("bad packet! %d\n\r",length);
K4zuki 78:434514b8d383 356 i = plength + 1;
K4zuki 78:434514b8d383 357 length = 0;
K4zuki 78:434514b8d383 358 }else{
K4zuki 78:434514b8d383 359 for(int j = 0; j < length; j +=3){
K4zuki 78:434514b8d383 360 address = recieve[i+1+j];
K4zuki 78:434514b8d383 361 data = 0xff & (recieve[i+2+j] << 4 | (recieve[i+3+j] & 0x0F));
K4zuki 78:434514b8d383 362 _data = 0;
K4zuki 78:434514b8d383 363 switch(address){
K4zuki 78:434514b8d383 364 case CHIP_ID:
K4zuki 78:434514b8d383 365 {
K4zuki 78:434514b8d383 366 //READ ONLY: do nothing
K4zuki 78:434514b8d383 367 data = registers[CHIP_ID-'0'];
K4zuki 78:434514b8d383 368 break;
K4zuki 78:434514b8d383 369 }
K4zuki 78:434514b8d383 370 case GPIO0_STAT:
K4zuki 78:434514b8d383 371 {
K4zuki 78:434514b8d383 372 _data = registers[GPIO0_CONF-'0'];
K4zuki 78:434514b8d383 373 for(int k=0; k<8; k++){
K4zuki 78:434514b8d383 374 if(_data&0x01){ // output
K4zuki 78:434514b8d383 375 gpio0[k]->write((data>>k)&0x01);
K4zuki 78:434514b8d383 376 }else{ // input
K4zuki 78:434514b8d383 377 ; // do nothing
K4zuki 78:434514b8d383 378 }
K4zuki 78:434514b8d383 379 _data >>= 1;
K4zuki 78:434514b8d383 380 }
K4zuki 78:434514b8d383 381 break;
K4zuki 78:434514b8d383 382 }
K4zuki 78:434514b8d383 383 case GPIO0_CONF:
K4zuki 78:434514b8d383 384 {
K4zuki 78:434514b8d383 385 registers[GPIO0_CONF-'0'] = data;
K4zuki 78:434514b8d383 386 for(int k = 0; k < 8; k++){
K4zuki 78:434514b8d383 387 if(data & 0x01){//output
K4zuki 78:434514b8d383 388 gpio0[k]->output();
K4zuki 78:434514b8d383 389 }else{//input
K4zuki 78:434514b8d383 390 gpio0[k]->input();
K4zuki 78:434514b8d383 391 gpio0[k]->mode(PullUp);
K4zuki 78:434514b8d383 392 }
K4zuki 78:434514b8d383 393 data >>= 1;
K4zuki 78:434514b8d383 394 }
K4zuki 78:434514b8d383 395 data = registers[GPIO0_CONF-'0'];
K4zuki 78:434514b8d383 396 break;
K4zuki 78:434514b8d383 397 }
K4zuki 78:434514b8d383 398 #ifdef isGPIO1
K4zuki 78:434514b8d383 399 case GPIO1_STAT:
K4zuki 78:434514b8d383 400 {
K4zuki 78:434514b8d383 401 _data = registers[GPIO1_CONF-'0'];
K4zuki 78:434514b8d383 402 for(int k = 0; k < 8; k++){
K4zuki 78:434514b8d383 403 if(_data & 0x01){ // output
K4zuki 78:434514b8d383 404 gpio1[k]->write((data>>k)&0x01);
K4zuki 78:434514b8d383 405 }else{ // input
K4zuki 78:434514b8d383 406 ; // do nothing
K4zuki 78:434514b8d383 407 }
K4zuki 78:434514b8d383 408 _data >>= 1;
K4zuki 78:434514b8d383 409 }
K4zuki 78:434514b8d383 410 break;
K4zuki 78:434514b8d383 411 }
K4zuki 78:434514b8d383 412 case GPIO1_CONF:
K4zuki 78:434514b8d383 413 {
K4zuki 78:434514b8d383 414 registers[GPIO1_CONF-'0'] = data;
K4zuki 78:434514b8d383 415 for(int k = 0; k < 6; k++){
K4zuki 78:434514b8d383 416 if(data & 0x01){//output
K4zuki 78:434514b8d383 417 gpio1[k]->output();
K4zuki 78:434514b8d383 418 }else{//input
K4zuki 78:434514b8d383 419 gpio1[k]->input();
K4zuki 78:434514b8d383 420 gpio1[k]->mode(PullUp);
K4zuki 78:434514b8d383 421 }
K4zuki 78:434514b8d383 422 data >>= 1;
K4zuki 78:434514b8d383 423 }
K4zuki 78:434514b8d383 424 data = registers[GPIO1_CONF-'0'];
K4zuki 78:434514b8d383 425 break;
K4zuki 78:434514b8d383 426 }
K4zuki 78:434514b8d383 427 #endif
K4zuki 78:434514b8d383 428 case I2C_CONF:
K4zuki 78:434514b8d383 429 {
K4zuki 78:434514b8d383 430 registers[I2C_CONF-'0'] = data;
K4zuki 78:434514b8d383 431 #if defined(TARGET_LPC1768)
K4zuki 78:434514b8d383 432 dev1.frequency(100000 * ((0x03 & (data >> 6)) + 1));
K4zuki 78:434514b8d383 433 #else
K4zuki 78:434514b8d383 434 dev1.frequency(200000 * ((0x03 & (data >> 6)) + 1));
K4zuki 78:434514b8d383 435 #endif
K4zuki 78:434514b8d383 436 #ifdef isI2C2
K4zuki 78:434514b8d383 437 dev2.frequency(100000 * ((0x03 & (data >> 4)) + 1));
K4zuki 78:434514b8d383 438 #endif
K4zuki 78:434514b8d383 439 #ifdef isI2C3
K4zuki 78:434514b8d383 440 dev3.frequency(100000 * ((0x03 & (data >> 2)) + 1));
K4zuki 78:434514b8d383 441 #endif
K4zuki 78:434514b8d383 442 #ifdef isI2C4
K4zuki 78:434514b8d383 443 dev4.frequency(100000 * ((0x03 & (data >> 0)) + 1));
K4zuki 78:434514b8d383 444 #endif
K4zuki 78:434514b8d383 445 break;
K4zuki 78:434514b8d383 446 }
K4zuki 78:434514b8d383 447 case SPI_CONF:
K4zuki 78:434514b8d383 448 {
K4zuki 78:434514b8d383 449 registers[SPI_CONF-'0'] = data;
K4zuki 78:434514b8d383 450 format = ((data & 0x04) + 4) << 1;
K4zuki 78:434514b8d383 451 _spi.format(format, 0x03 & (data));
K4zuki 78:434514b8d383 452 _spi.frequency(1000000 * ((0x07 & (data >> 4)) + 1));
K4zuki 78:434514b8d383 453 enabled = (data & 0x08) >> 3;
K4zuki 78:434514b8d383 454 /*
K4zuki 78:434514b8d383 455 7 not used
K4zuki 78:434514b8d383 456 6:4 frequency
K4zuki 78:434514b8d383 457 3 CE pol
K4zuki 78:434514b8d383 458 2 word size(0=8bit,1=16bit)
K4zuki 78:434514b8d383 459 1:0 pol(corresponds to spi.format())
K4zuki 78:434514b8d383 460 */
K4zuki 78:434514b8d383 461 disabled = ~enabled;
K4zuki 78:434514b8d383 462 break;
K4zuki 78:434514b8d383 463 }
K4zuki 78:434514b8d383 464 default:
K4zuki 78:434514b8d383 465 {
K4zuki 78:434514b8d383 466 break;
K4zuki 78:434514b8d383 467 }
K4zuki 78:434514b8d383 468 }
K4zuki 78:434514b8d383 469 send[j/3] = data;
K4zuki 78:434514b8d383 470 }
K4zuki 78:434514b8d383 471 i += (length + 1);
K4zuki 78:434514b8d383 472 length /= 3;
K4zuki 78:434514b8d383 473 }
K4zuki 78:434514b8d383 474 break;
K4zuki 78:434514b8d383 475 }
K4zuki 78:434514b8d383 476 case CMD_I:
K4zuki 78:434514b8d383 477 {
K4zuki 78:434514b8d383 478 s = false;
K4zuki 78:434514b8d383 479 length = plength - 2;
K4zuki 78:434514b8d383 480 if(length < 1){
K4zuki 78:434514b8d383 481 pc.printf("bad packet! %d\n\r",length);
K4zuki 78:434514b8d383 482 i = plength + 1;
K4zuki 78:434514b8d383 483 length = 0;
K4zuki 78:434514b8d383 484 }else{
K4zuki 78:434514b8d383 485 for(int j=0; j<length; j++){
K4zuki 78:434514b8d383 486 address = recieve[i+1+j];
K4zuki 78:434514b8d383 487 _data=0;
K4zuki 78:434514b8d383 488 switch(address){
K4zuki 78:434514b8d383 489 case GPIO0_STAT:
K4zuki 78:434514b8d383 490 {
K4zuki 78:434514b8d383 491 for(int k=0; k<8; k++){
K4zuki 78:434514b8d383 492 _data = gpio0[k]->read();
K4zuki 78:434514b8d383 493 data |= (_data << k);
K4zuki 78:434514b8d383 494 }
K4zuki 78:434514b8d383 495 registers[GPIO0_STAT-'0'] = data;
K4zuki 78:434514b8d383 496 break;
K4zuki 78:434514b8d383 497 }
K4zuki 78:434514b8d383 498 #ifdef isGPIO1
K4zuki 78:434514b8d383 499 case GPIO1_STAT:
K4zuki 78:434514b8d383 500 {
K4zuki 78:434514b8d383 501 for(int k=0; k<8; k++){
K4zuki 78:434514b8d383 502 _data = gpio1[k]->read();
K4zuki 78:434514b8d383 503 data |= (_data << k);
K4zuki 78:434514b8d383 504 }
K4zuki 78:434514b8d383 505 registers[GPIO1_STAT-'0'] = data;
K4zuki 78:434514b8d383 506 break;
K4zuki 78:434514b8d383 507 }
K4zuki 78:434514b8d383 508 #endif
K4zuki 78:434514b8d383 509 default:
K4zuki 78:434514b8d383 510 {
K4zuki 78:434514b8d383 511 data = 0xAA;
K4zuki 78:434514b8d383 512 break;
K4zuki 78:434514b8d383 513 }
K4zuki 78:434514b8d383 514 }
K4zuki 78:434514b8d383 515 send[j] = (char)data;
K4zuki 78:434514b8d383 516 data = 0;
K4zuki 78:434514b8d383 517 }
K4zuki 78:434514b8d383 518 i += (length+1);
K4zuki 78:434514b8d383 519 }
K4zuki 78:434514b8d383 520 break;
K4zuki 78:434514b8d383 521 }
K4zuki 78:434514b8d383 522 case CMD_O:
K4zuki 78:434514b8d383 523 {
K4zuki 78:434514b8d383 524 s = false;
K4zuki 78:434514b8d383 525 length = plength - 2;
K4zuki 78:434514b8d383 526 if(length < 3){
K4zuki 78:434514b8d383 527 pc.printf("bad packet! %d\n\r",length);
K4zuki 78:434514b8d383 528 i = plength + 1;
K4zuki 78:434514b8d383 529 length = 0;
K4zuki 78:434514b8d383 530 }else{
K4zuki 78:434514b8d383 531 for(int j=0; j<length; j+=3){
K4zuki 78:434514b8d383 532 address = recieve[i+1+j];
K4zuki 78:434514b8d383 533 data = 0xff & (recieve[i+2+j] << 4 | (recieve[i+3+j] & 0x0F));
K4zuki 78:434514b8d383 534 switch(address){
K4zuki 78:434514b8d383 535 case GPIO0_STAT:
K4zuki 78:434514b8d383 536 {
K4zuki 78:434514b8d383 537 _data = registers[GPIO0_CONF-'0'];
K4zuki 78:434514b8d383 538 for(int k=0; k<8; k++){
K4zuki 78:434514b8d383 539 if(_data&0x01){ // output
K4zuki 78:434514b8d383 540 gpio0[k]->write(data&0x01);
K4zuki 78:434514b8d383 541 }else{ // input
K4zuki 78:434514b8d383 542 ; // do nothing
K4zuki 78:434514b8d383 543 }
K4zuki 78:434514b8d383 544 data >>= 1;
K4zuki 78:434514b8d383 545 _data >>= 1;
K4zuki 78:434514b8d383 546 }
K4zuki 78:434514b8d383 547 break;
K4zuki 78:434514b8d383 548 }
K4zuki 78:434514b8d383 549 #ifdef isGPIO1
K4zuki 78:434514b8d383 550 case GPIO1_STAT:
K4zuki 78:434514b8d383 551 {
K4zuki 78:434514b8d383 552 _data = registers[GPIO1_CONF-'0'];
K4zuki 78:434514b8d383 553 for(int k=0; k<8; k++){
K4zuki 78:434514b8d383 554 if(_data&0x01){ // output
K4zuki 78:434514b8d383 555 gpio1[k]->write(data&0x01);
K4zuki 78:434514b8d383 556 }else{ // input
K4zuki 78:434514b8d383 557 ; // do nothing
K4zuki 78:434514b8d383 558 }
K4zuki 78:434514b8d383 559 data >>= 1;
K4zuki 78:434514b8d383 560 _data >>= 1;
K4zuki 78:434514b8d383 561 }
K4zuki 78:434514b8d383 562 break;
K4zuki 78:434514b8d383 563 }
K4zuki 78:434514b8d383 564 #endif
K4zuki 78:434514b8d383 565 default:
K4zuki 78:434514b8d383 566 {
K4zuki 78:434514b8d383 567 break;
K4zuki 78:434514b8d383 568 }
K4zuki 78:434514b8d383 569 }
K4zuki 78:434514b8d383 570 send[j/3] = data;
K4zuki 78:434514b8d383 571 }
K4zuki 78:434514b8d383 572 }
K4zuki 78:434514b8d383 573 i += (length+1);
K4zuki 78:434514b8d383 574 length /= 3;
K4zuki 78:434514b8d383 575 // pc.printf("command O is not implemented, ");
K4zuki 78:434514b8d383 576 break;
K4zuki 78:434514b8d383 577 }
K4zuki 78:434514b8d383 578 case CMD_E:
K4zuki 78:434514b8d383 579 {
K4zuki 78:434514b8d383 580 s = false;
K4zuki 78:434514b8d383 581 /*
K4zuki 78:434514b8d383 582 "0| 1 2| 3 4| 5 6 7 8 9 10 11 12|13" //plength=14
K4zuki 78:434514b8d383 583 "E| 0x_0 _1| 0x_0 _0| 0x_D _E| P" //minimum plength=8
K4zuki 78:434514b8d383 584 "E| 0x_0 _1| 0x_0 _0| 0x_D _E|_A _D| P" //minimum plength=10(16bit)
K4zuki 78:434514b8d383 585 "E| 0x_0 _4| 0x_0 _0| 0x_D _E _A _D _B _E _A _F| P" //write
K4zuki 78:434514b8d383 586 "E| 0x_0 _4| 0x_0 _4| 0x_D _E _A _D _B _E _A _F| P" //write and read
K4zuki 78:434514b8d383 587 */
K4zuki 78:434514b8d383 588 length = plength - 2; //6
K4zuki 78:434514b8d383 589 if(length < 6){
K4zuki 78:434514b8d383 590 pc.printf("bad packet! %d\n\r",length);
K4zuki 78:434514b8d383 591 i = plength + 1;
K4zuki 78:434514b8d383 592 length = 0;
K4zuki 78:434514b8d383 593 }else{
K4zuki 78:434514b8d383 594 length = length-4; //actual data in packet
K4zuki 78:434514b8d383 595 data = 0xff & ((recieve[i+1]<<4) | (recieve[i+2]&0x0F)); // write length
K4zuki 78:434514b8d383 596 read = 0xff & ((recieve[i+3]<<4) | (recieve[i+4]&0x0F)); // read length
K4zuki 78:434514b8d383 597 switch(format){
K4zuki 78:434514b8d383 598 case 8:
K4zuki 78:434514b8d383 599 {
K4zuki 78:434514b8d383 600 _cs.write(enabled);
K4zuki 78:434514b8d383 601 for(int j = 0; j < length; j += 2){
K4zuki 78:434514b8d383 602 _data = 0xff & ((recieve[i+5+j+0]<<4) | (recieve[i+5+j+1]&0x0F));
K4zuki 78:434514b8d383 603 ack = _spi.write(_data);
K4zuki 78:434514b8d383 604 // pc.printf("s%02X,",_data);
K4zuki 78:434514b8d383 605 send[j/2] = ack;
K4zuki 78:434514b8d383 606 }
K4zuki 78:434514b8d383 607 for(int j = length; j < (length+2*read); j+=2){
K4zuki 78:434514b8d383 608 ack = _spi.write(0xAA); //dummy data to write
K4zuki 78:434514b8d383 609 // pc.printf("a%02X,",ack);
K4zuki 78:434514b8d383 610 send[j/2] = ack;
K4zuki 78:434514b8d383 611 }
K4zuki 78:434514b8d383 612 _cs.write(disabled);
K4zuki 78:434514b8d383 613 break;
K4zuki 78:434514b8d383 614 }
K4zuki 78:434514b8d383 615 case 16:
K4zuki 78:434514b8d383 616 {
K4zuki 78:434514b8d383 617 if((data%2) || (read%2)){ //invalid
K4zuki 78:434514b8d383 618 pc.printf("bad packet! %d, %d\n\r",data,read);
K4zuki 78:434514b8d383 619 i = plength + 1;
K4zuki 78:434514b8d383 620 length = 0;
K4zuki 78:434514b8d383 621 }else{
K4zuki 78:434514b8d383 622 _cs.write(enabled);
K4zuki 78:434514b8d383 623 for(int j = 0; j < length; j += 4){
K4zuki 78:434514b8d383 624 _data = 0xffff & (((recieve[i+5+j+0] & 0x0F)<<12)|
K4zuki 78:434514b8d383 625 ((recieve[i+5+j+1] & 0x0F)<<8 )|
K4zuki 78:434514b8d383 626 ((recieve[i+5+j+2] & 0x0F)<<4 )|
K4zuki 78:434514b8d383 627 ((recieve[i+5+j+3] & 0x0F)<<0 )
K4zuki 78:434514b8d383 628 );
K4zuki 78:434514b8d383 629 ack = _spi.write(_data);
K4zuki 78:434514b8d383 630 // pc.printf("s%04X,",_data);
K4zuki 78:434514b8d383 631 send[(j/2)+0] = 0xFF & (ack>>8);
K4zuki 78:434514b8d383 632 send[(j/2)+1] = 0xFF & (ack>>0);
K4zuki 78:434514b8d383 633 }
K4zuki 78:434514b8d383 634 for(int j = length; j < (length+2*read); j += 4){
K4zuki 78:434514b8d383 635 ack = _spi.write(0xAAAA); //dummy data to write
K4zuki 78:434514b8d383 636 // pc.printf("a%04X,",ack);
K4zuki 78:434514b8d383 637 send[(j/2)+0] = 0xFF & (ack>>8);
K4zuki 78:434514b8d383 638 send[(j/2)+1] = 0xFF & (ack>>0);
K4zuki 78:434514b8d383 639 }
K4zuki 78:434514b8d383 640 _cs.write(disabled);
K4zuki 78:434514b8d383 641 }
K4zuki 78:434514b8d383 642 break;
K4zuki 78:434514b8d383 643 }
K4zuki 78:434514b8d383 644 default:
K4zuki 78:434514b8d383 645 {
K4zuki 78:434514b8d383 646 pc.printf("this shold not happen %d\n\r",format);
K4zuki 78:434514b8d383 647 break;
K4zuki 78:434514b8d383 648 }
K4zuki 78:434514b8d383 649
K4zuki 78:434514b8d383 650 }
K4zuki 78:434514b8d383 651 // pc.printf("command E is for SPI transmission\n\r");
K4zuki 78:434514b8d383 652 length = read + data;
K4zuki 78:434514b8d383 653 i = (plength-1);
K4zuki 78:434514b8d383 654 }
K4zuki 78:434514b8d383 655 break;
K4zuki 78:434514b8d383 656 }
K4zuki 78:434514b8d383 657 case 'Z':
K4zuki 78:434514b8d383 658 {
K4zuki 78:434514b8d383 659 s = false;
K4zuki 78:434514b8d383 660 pc.printf("command Z is not implemented\n\r");
K4zuki 78:434514b8d383 661 i=plength;
K4zuki 78:434514b8d383 662 break;
K4zuki 78:434514b8d383 663 }
K4zuki 78:434514b8d383 664 case 'V':
K4zuki 78:434514b8d383 665 {
K4zuki 78:434514b8d383 666 s = false;
K4zuki 78:434514b8d383 667 pc.printf("command V is not implemented\n\r");
K4zuki 78:434514b8d383 668 i=plength;
K4zuki 78:434514b8d383 669 break;
K4zuki 78:434514b8d383 670 }
K4zuki 78:434514b8d383 671 default:
K4zuki 78:434514b8d383 672 {
K4zuki 78:434514b8d383 673 s = false;
K4zuki 78:434514b8d383 674 pc.printf("command %c is not implemented\n\r", recieve[i]);
K4zuki 78:434514b8d383 675 i=plength;
K4zuki 78:434514b8d383 676 break;
K4zuki 78:434514b8d383 677 }
K4zuki 78:434514b8d383 678 }
K4zuki 78:434514b8d383 679 }
K4zuki 78:434514b8d383 680 i=0;
K4zuki 78:434514b8d383 681 length=0;
K4zuki 78:434514b8d383 682 }
K4zuki 78:434514b8d383 683 }