Junhao Zhang
/
DEBUG_10K
AFSD
Fork of DEBUG_10K by
selection.cpp
- Committer:
- junhaozhang
- Date:
- 2018-03-22
- Revision:
- 2:d93488b7eec5
- Parent:
- 0:1b13f03ce7eb
File content as of revision 2:d93488b7eec5:
#include "mbed.h" #include "selection.h" //define the PWM output port PwmOut PWMout(p21); //define the address bit of MUX for multi-Vin //MSB B_A LSB, NB an inverter - transiver // 01 1st 100kHz // 10 2rd 10kHz // 11 3rd 1kHz DigitalOut VAddrA1(p6); DigitalOut VAddrA0(p5); //define the address bit of MUX for ResistorArray //MSB CBA LSB, NB an inverter - transiver // 110 1st 1kohm // 101 2rd // 100 3rd // 011 4th // 010 5th // 001 6th // 000 7th DigitalOut RAddrA0(p9); DigitalOut RAddrA1(p10); DigitalOut RAddrA2(p11); void RAddr (int in) { switch (in){ case 0:RAddrA2=0; RAddrA1=0; RAddrA0=0; break; case 1:RAddrA2=0; RAddrA1=0; RAddrA0=1; break; case 2:RAddrA2=0; RAddrA1=1; RAddrA0=0; break; case 3: RAddrA2=0; RAddrA1=1; RAddrA0=1; break; case 4: RAddrA2=1; RAddrA1=0; RAddrA0=0; break; case 5: RAddrA2=1; RAddrA1=0; RAddrA0=1; break; case 6:RAddrA2=1; RAddrA1=1; RAddrA0=0; break; case 7:RAddrA2=1; RAddrA1=1; RAddrA0=1; break; default:RAddrA2=1; RAddrA1=1; RAddrA0=1; } } void VAddr (int in) { switch (in){ case 100:PWMout.period(0.00001f); //100kHz_10us_0.00001s, PWMout.write(0.50f); // 50% duty cycle, relative to period VAddrA1=0; VAddrA0=1; break; case 10:PWMout.period(0.0001f); //10kHz_100us_0.0001s, PWMout.write(0.50f); // 50% duty cycle, relative to period VAddrA1=1; VAddrA0=0; break; case 1: PWMout.period(0.001f); //1kHz_1ms_0.001s, PWMout.write(0.50f); // 50% duty cycle, relative to period VAddrA1=1; VAddrA0=1; break; default:PWMout.period(0.1f); PWMout.write(0.50f); // 50% duty cycle, relative to period VAddrA1=0; VAddrA0=0; } }