Junhao Zhang / Mbed 2 deprecated DEBUG_10K

AFSD

Dependencies:   mbed

Fork of DEBUG_10K by Xu ZHANG

selection.cpp@2:d93488b7eec5, 2018-03-22 (annotated)

Committer:
junhaozhang
Date:
Thu Mar 22 20:17:06 2018 +0000
Revision:
2:d93488b7eec5
Parent:
0:1b13f03ce7eb 
ZHANG XU

Who changed what in which revision?

UserRevisionLine numberNew contents of line
xuzhang 0:1b13f03ce7eb 1 #include "mbed.h"
xuzhang 0:1b13f03ce7eb 2 #include "selection.h"
xuzhang 0:1b13f03ce7eb 3 //define the PWM output port
xuzhang 0:1b13f03ce7eb 4 PwmOut PWMout(p21);
xuzhang 0:1b13f03ce7eb 5
xuzhang 0:1b13f03ce7eb 6 //define the address bit of MUX for multi-Vin
xuzhang 0:1b13f03ce7eb 7 //MSB B_A LSB, NB an inverter - transiver
xuzhang 0:1b13f03ce7eb 8 // 01 1st 100kHz
xuzhang 0:1b13f03ce7eb 9 // 10 2rd 10kHz
xuzhang 0:1b13f03ce7eb 10 // 11 3rd 1kHz
xuzhang 0:1b13f03ce7eb 11 DigitalOut VAddrA1(p6);
xuzhang 0:1b13f03ce7eb 12 DigitalOut VAddrA0(p5);
xuzhang 0:1b13f03ce7eb 13
xuzhang 0:1b13f03ce7eb 14 //define the address bit of MUX for ResistorArray
xuzhang 0:1b13f03ce7eb 15 //MSB CBA LSB, NB an inverter - transiver
xuzhang 0:1b13f03ce7eb 16 // 110 1st 1kohm
xuzhang 0:1b13f03ce7eb 17 // 101 2rd
xuzhang 0:1b13f03ce7eb 18 // 100 3rd
xuzhang 0:1b13f03ce7eb 19 // 011 4th
xuzhang 0:1b13f03ce7eb 20 // 010 5th
xuzhang 0:1b13f03ce7eb 21 // 001 6th
xuzhang 0:1b13f03ce7eb 22 // 000 7th
xuzhang 0:1b13f03ce7eb 23 DigitalOut RAddrA0(p9);
xuzhang 0:1b13f03ce7eb 24 DigitalOut RAddrA1(p10);
xuzhang 0:1b13f03ce7eb 25 DigitalOut RAddrA2(p11);
xuzhang 0:1b13f03ce7eb 26
xuzhang 0:1b13f03ce7eb 27
xuzhang 0:1b13f03ce7eb 28 void RAddr (int in)
xuzhang 0:1b13f03ce7eb 29 {
xuzhang 0:1b13f03ce7eb 30 switch (in){
xuzhang 0:1b13f03ce7eb 31 case 0:RAddrA2=0;
xuzhang 0:1b13f03ce7eb 32 RAddrA1=0;
xuzhang 0:1b13f03ce7eb 33 RAddrA0=0;
xuzhang 0:1b13f03ce7eb 34 break;
xuzhang 0:1b13f03ce7eb 35
xuzhang 0:1b13f03ce7eb 36 case 1:RAddrA2=0;
xuzhang 0:1b13f03ce7eb 37 RAddrA1=0;
xuzhang 0:1b13f03ce7eb 38 RAddrA0=1;
xuzhang 0:1b13f03ce7eb 39 break;
xuzhang 0:1b13f03ce7eb 40 case 2:RAddrA2=0;
xuzhang 0:1b13f03ce7eb 41 RAddrA1=1;
xuzhang 0:1b13f03ce7eb 42 RAddrA0=0;
xuzhang 0:1b13f03ce7eb 43 break;
xuzhang 0:1b13f03ce7eb 44 case 3: RAddrA2=0;
xuzhang 0:1b13f03ce7eb 45 RAddrA1=1;
xuzhang 0:1b13f03ce7eb 46 RAddrA0=1;
xuzhang 0:1b13f03ce7eb 47 break;
xuzhang 0:1b13f03ce7eb 48 case 4: RAddrA2=1;
xuzhang 0:1b13f03ce7eb 49 RAddrA1=0;
xuzhang 0:1b13f03ce7eb 50 RAddrA0=0;
xuzhang 0:1b13f03ce7eb 51 break;
xuzhang 0:1b13f03ce7eb 52 case 5: RAddrA2=1;
xuzhang 0:1b13f03ce7eb 53 RAddrA1=0;
xuzhang 0:1b13f03ce7eb 54 RAddrA0=1;
xuzhang 0:1b13f03ce7eb 55 break;
xuzhang 0:1b13f03ce7eb 56 case 6:RAddrA2=1;
xuzhang 0:1b13f03ce7eb 57 RAddrA1=1;
xuzhang 0:1b13f03ce7eb 58 RAddrA0=0;
xuzhang 0:1b13f03ce7eb 59 break;
xuzhang 0:1b13f03ce7eb 60 case 7:RAddrA2=1;
xuzhang 0:1b13f03ce7eb 61 RAddrA1=1;
xuzhang 0:1b13f03ce7eb 62 RAddrA0=1;
xuzhang 0:1b13f03ce7eb 63 break;
xuzhang 0:1b13f03ce7eb 64 default:RAddrA2=1;
xuzhang 0:1b13f03ce7eb 65 RAddrA1=1;
xuzhang 0:1b13f03ce7eb 66 RAddrA0=1;
xuzhang 0:1b13f03ce7eb 67 }
xuzhang 0:1b13f03ce7eb 68 }
xuzhang 0:1b13f03ce7eb 69 void VAddr (int in)
xuzhang 0:1b13f03ce7eb 70 {
xuzhang 0:1b13f03ce7eb 71 switch (in){
xuzhang 0:1b13f03ce7eb 72
xuzhang 0:1b13f03ce7eb 73 case 100:PWMout.period(0.00001f); //100kHz_10us_0.00001s,
xuzhang 0:1b13f03ce7eb 74 PWMout.write(0.50f); // 50% duty cycle, relative to period
xuzhang 0:1b13f03ce7eb 75 VAddrA1=0;
xuzhang 0:1b13f03ce7eb 76 VAddrA0=1;
xuzhang 0:1b13f03ce7eb 77 break;
xuzhang 0:1b13f03ce7eb 78 case 10:PWMout.period(0.0001f); //10kHz_100us_0.0001s,
xuzhang 0:1b13f03ce7eb 79 PWMout.write(0.50f); // 50% duty cycle, relative to period
xuzhang 0:1b13f03ce7eb 80 VAddrA1=1;
xuzhang 0:1b13f03ce7eb 81 VAddrA0=0;
xuzhang 0:1b13f03ce7eb 82 break;
xuzhang 0:1b13f03ce7eb 83 case 1: PWMout.period(0.001f); //1kHz_1ms_0.001s,
xuzhang 0:1b13f03ce7eb 84 PWMout.write(0.50f); // 50% duty cycle, relative to period
xuzhang 0:1b13f03ce7eb 85 VAddrA1=1;
xuzhang 0:1b13f03ce7eb 86 VAddrA0=1;
xuzhang 0:1b13f03ce7eb 87 break;
xuzhang 0:1b13f03ce7eb 88 default:PWMout.period(0.1f);
xuzhang 0:1b13f03ce7eb 89 PWMout.write(0.50f); // 50% duty cycle, relative to period
xuzhang 0:1b13f03ce7eb 90 VAddrA1=0;
xuzhang 0:1b13f03ce7eb 91 VAddrA0=0;
xuzhang 0:1b13f03ce7eb 92 }
xuzhang 0:1b13f03ce7eb 93 }