joseph adamu
/
CW_final_thr
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Fork of
CW_copy
by 
Calvin Kalintra
sd-driver/SDBlockDevice.cpp@1:dc648c5624b9, 2018-01-10 (annotated)
- Committer:
- joseph_adamu
- Date:
- Wed Jan 10 09:50:29 2018 +0000
- Revision:
- 1:dc648c5624b9
version for export
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| joseph_adamu | 1:dc648c5624b9 | 1 | /* mbed Microcontroller Library |
| joseph_adamu | 1:dc648c5624b9 | 2 | * Copyright (c) 2006-2012 ARM Limited |
| joseph_adamu | 1:dc648c5624b9 | 3 | * |
| joseph_adamu | 1:dc648c5624b9 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| joseph_adamu | 1:dc648c5624b9 | 5 | * of this software and associated documentation files (the "Software"), to deal |
| joseph_adamu | 1:dc648c5624b9 | 6 | * in the Software without restriction, including without limitation the rights |
| joseph_adamu | 1:dc648c5624b9 | 7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| joseph_adamu | 1:dc648c5624b9 | 8 | * copies of the Software, and to permit persons to whom the Software is |
| joseph_adamu | 1:dc648c5624b9 | 9 | * furnished to do so, subject to the following conditions: |
| joseph_adamu | 1:dc648c5624b9 | 10 | * |
| joseph_adamu | 1:dc648c5624b9 | 11 | * The above copyright notice and this permission notice shall be included in |
| joseph_adamu | 1:dc648c5624b9 | 12 | * all copies or substantial portions of the Software. |
| joseph_adamu | 1:dc648c5624b9 | 13 | * |
| joseph_adamu | 1:dc648c5624b9 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| joseph_adamu | 1:dc648c5624b9 | 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| joseph_adamu | 1:dc648c5624b9 | 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| joseph_adamu | 1:dc648c5624b9 | 17 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| joseph_adamu | 1:dc648c5624b9 | 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| joseph_adamu | 1:dc648c5624b9 | 19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| joseph_adamu | 1:dc648c5624b9 | 20 | * SOFTWARE. |
| joseph_adamu | 1:dc648c5624b9 | 21 | */ |
| joseph_adamu | 1:dc648c5624b9 | 22 | /* Introduction |
| joseph_adamu | 1:dc648c5624b9 | 23 | * ------------ |
| joseph_adamu | 1:dc648c5624b9 | 24 | * SD and MMC cards support a number of interfaces, but common to them all |
| joseph_adamu | 1:dc648c5624b9 | 25 | * is one based on SPI. Since we already have the mbed SPI Interface, it will |
| joseph_adamu | 1:dc648c5624b9 | 26 | * be used for SD cards. |
| joseph_adamu | 1:dc648c5624b9 | 27 | * |
| joseph_adamu | 1:dc648c5624b9 | 28 | * The main reference I'm using is Chapter 7, "SPI Mode" of: |
| joseph_adamu | 1:dc648c5624b9 | 29 | * http://www.sdcard.org/developers/tech/sdcard/pls/Simplified_Physical_Layer_Spec.pdf |
| joseph_adamu | 1:dc648c5624b9 | 30 | * |
| joseph_adamu | 1:dc648c5624b9 | 31 | * SPI Startup |
| joseph_adamu | 1:dc648c5624b9 | 32 | * ----------- |
| joseph_adamu | 1:dc648c5624b9 | 33 | * The SD card powers up in SD mode. The start-up procedure is complicated |
| joseph_adamu | 1:dc648c5624b9 | 34 | * by the requirement to support older SDCards in a backwards compatible |
| joseph_adamu | 1:dc648c5624b9 | 35 | * way with the new higher capacity variants SDHC and SDHC. |
| joseph_adamu | 1:dc648c5624b9 | 36 | * |
| joseph_adamu | 1:dc648c5624b9 | 37 | * The following figures from the specification with associated text describe |
| joseph_adamu | 1:dc648c5624b9 | 38 | * the SPI mode initialisation process: |
| joseph_adamu | 1:dc648c5624b9 | 39 | * - Figure 7-1: SD Memory Card State Diagram (SPI mode) |
| joseph_adamu | 1:dc648c5624b9 | 40 | * - Figure 7-2: SPI Mode Initialization Flow |
| joseph_adamu | 1:dc648c5624b9 | 41 | * |
| joseph_adamu | 1:dc648c5624b9 | 42 | * Firstly, a low initial clock should be selected (in the range of 100- |
| joseph_adamu | 1:dc648c5624b9 | 43 | * 400kHZ). After initialisation has been completed, the switch to a |
| joseph_adamu | 1:dc648c5624b9 | 44 | * higher clock speed can be made (e.g. 1MHz). Newer cards will support |
| joseph_adamu | 1:dc648c5624b9 | 45 | * higher speeds than the default _transfer_sck defined here. |
| joseph_adamu | 1:dc648c5624b9 | 46 | * |
| joseph_adamu | 1:dc648c5624b9 | 47 | * Next, note the following from the SDCard specification (note to |
| joseph_adamu | 1:dc648c5624b9 | 48 | * Figure 7-1): |
| joseph_adamu | 1:dc648c5624b9 | 49 | * |
| joseph_adamu | 1:dc648c5624b9 | 50 | * In any of the cases CMD1 is not recommended because it may be difficult for the host |
| joseph_adamu | 1:dc648c5624b9 | 51 | * to distinguish between MultiMediaCard and SD Memory Card |
| joseph_adamu | 1:dc648c5624b9 | 52 | * |
| joseph_adamu | 1:dc648c5624b9 | 53 | * Hence CMD1 is not used for the initialisation sequence. |
| joseph_adamu | 1:dc648c5624b9 | 54 | * |
| joseph_adamu | 1:dc648c5624b9 | 55 | * The SPI interface mode is selected by asserting CS low and sending the |
| joseph_adamu | 1:dc648c5624b9 | 56 | * reset command (CMD0). The card will respond with a (R1) response. |
| joseph_adamu | 1:dc648c5624b9 | 57 | * In practice many cards initially respond with 0xff or invalid data |
| joseph_adamu | 1:dc648c5624b9 | 58 | * which is ignored. Data is read until a valid response is received |
| joseph_adamu | 1:dc648c5624b9 | 59 | * or the number of re-reads has exceeded a maximim count. If a valid |
| joseph_adamu | 1:dc648c5624b9 | 60 | * response is not received then the CMD0 can be retried. This |
| joseph_adamu | 1:dc648c5624b9 | 61 | * has been found to successfully initialise cards where the SPI master |
| joseph_adamu | 1:dc648c5624b9 | 62 | * (on MCU) has been reset but the SDCard has not, so the first |
| joseph_adamu | 1:dc648c5624b9 | 63 | * CMD0 may be lost. |
| joseph_adamu | 1:dc648c5624b9 | 64 | * |
| joseph_adamu | 1:dc648c5624b9 | 65 | * CMD8 is optionally sent to determine the voltage range supported, and |
| joseph_adamu | 1:dc648c5624b9 | 66 | * indirectly determine whether it is a version 1.x SD/non-SD card or |
| joseph_adamu | 1:dc648c5624b9 | 67 | * version 2.x. I'll just ignore this for now. |
| joseph_adamu | 1:dc648c5624b9 | 68 | * |
| joseph_adamu | 1:dc648c5624b9 | 69 | * ACMD41 is repeatedly issued to initialise the card, until "in idle" |
| joseph_adamu | 1:dc648c5624b9 | 70 | * (bit 0) of the R1 response goes to '0', indicating it is initialised. |
| joseph_adamu | 1:dc648c5624b9 | 71 | * |
| joseph_adamu | 1:dc648c5624b9 | 72 | * You should also indicate whether the host supports High Capicity cards, |
| joseph_adamu | 1:dc648c5624b9 | 73 | * and check whether the card is high capacity - i'll also ignore this |
| joseph_adamu | 1:dc648c5624b9 | 74 | * |
| joseph_adamu | 1:dc648c5624b9 | 75 | * SPI Protocol |
| joseph_adamu | 1:dc648c5624b9 | 76 | * ------------ |
| joseph_adamu | 1:dc648c5624b9 | 77 | * The SD SPI protocol is based on transactions made up of 8-bit words, with |
| joseph_adamu | 1:dc648c5624b9 | 78 | * the host starting every bus transaction by asserting the CS signal low. The |
| joseph_adamu | 1:dc648c5624b9 | 79 | * card always responds to commands, data blocks and errors. |
| joseph_adamu | 1:dc648c5624b9 | 80 | * |
| joseph_adamu | 1:dc648c5624b9 | 81 | * The protocol supports a CRC, but by default it is off (except for the |
| joseph_adamu | 1:dc648c5624b9 | 82 | * first reset CMD0, where the CRC can just be pre-calculated, and CMD8) |
| joseph_adamu | 1:dc648c5624b9 | 83 | * I'll leave the CRC off I think! |
| joseph_adamu | 1:dc648c5624b9 | 84 | * |
| joseph_adamu | 1:dc648c5624b9 | 85 | * Standard capacity cards have variable data block sizes, whereas High |
| joseph_adamu | 1:dc648c5624b9 | 86 | * Capacity cards fix the size of data block to 512 bytes. I'll therefore |
| joseph_adamu | 1:dc648c5624b9 | 87 | * just always use the Standard Capacity cards with a block size of 512 bytes. |
| joseph_adamu | 1:dc648c5624b9 | 88 | * This is set with CMD16. |
| joseph_adamu | 1:dc648c5624b9 | 89 | * |
| joseph_adamu | 1:dc648c5624b9 | 90 | * You can read and write single blocks (CMD17, CMD25) or multiple blocks |
| joseph_adamu | 1:dc648c5624b9 | 91 | * (CMD18, CMD25). For simplicity, I'll just use single block accesses. When |
| joseph_adamu | 1:dc648c5624b9 | 92 | * the card gets a read command, it responds with a response token, and then |
| joseph_adamu | 1:dc648c5624b9 | 93 | * a data token or an error. |
| joseph_adamu | 1:dc648c5624b9 | 94 | * |
| joseph_adamu | 1:dc648c5624b9 | 95 | * SPI Command Format |
| joseph_adamu | 1:dc648c5624b9 | 96 | * ------------------ |
| joseph_adamu | 1:dc648c5624b9 | 97 | * Commands are 6-bytes long, containing the command, 32-bit argument, and CRC. |
| joseph_adamu | 1:dc648c5624b9 | 98 | * |
| joseph_adamu | 1:dc648c5624b9 | 99 | * +---------------+------------+------------+-----------+----------+--------------+ |
| joseph_adamu | 1:dc648c5624b9 | 100 | * | 01 | cmd[5:0] | arg[31:24] | arg[23:16] | arg[15:8] | arg[7:0] | crc[6:0] | 1 | |
| joseph_adamu | 1:dc648c5624b9 | 101 | * +---------------+------------+------------+-----------+----------+--------------+ |
| joseph_adamu | 1:dc648c5624b9 | 102 | * |
| joseph_adamu | 1:dc648c5624b9 | 103 | * As I'm not using CRC, I can fix that byte to what is needed for CMD0 (0x95) |
| joseph_adamu | 1:dc648c5624b9 | 104 | * |
| joseph_adamu | 1:dc648c5624b9 | 105 | * All Application Specific commands shall be preceded with APP_CMD (CMD55). |
| joseph_adamu | 1:dc648c5624b9 | 106 | * |
| joseph_adamu | 1:dc648c5624b9 | 107 | * SPI Response Format |
| joseph_adamu | 1:dc648c5624b9 | 108 | * ------------------- |
| joseph_adamu | 1:dc648c5624b9 | 109 | * The main response format (R1) is a status byte (normally zero). Key flags: |
| joseph_adamu | 1:dc648c5624b9 | 110 | * idle - 1 if the card is in an idle state/initialising |
| joseph_adamu | 1:dc648c5624b9 | 111 | * cmd - 1 if an illegal command code was detected |
| joseph_adamu | 1:dc648c5624b9 | 112 | * |
| joseph_adamu | 1:dc648c5624b9 | 113 | * +-------------------------------------------------+ |
| joseph_adamu | 1:dc648c5624b9 | 114 | * R1 | 0 | arg | addr | seq | crc | cmd | erase | idle | |
| joseph_adamu | 1:dc648c5624b9 | 115 | * +-------------------------------------------------+ |
| joseph_adamu | 1:dc648c5624b9 | 116 | * |
| joseph_adamu | 1:dc648c5624b9 | 117 | * R1b is the same, except it is followed by a busy signal (zeros) until |
| joseph_adamu | 1:dc648c5624b9 | 118 | * the first non-zero byte when it is ready again. |
| joseph_adamu | 1:dc648c5624b9 | 119 | * |
| joseph_adamu | 1:dc648c5624b9 | 120 | * Data Response Token |
| joseph_adamu | 1:dc648c5624b9 | 121 | * ------------------- |
| joseph_adamu | 1:dc648c5624b9 | 122 | * Every data block written to the card is acknowledged by a byte |
| joseph_adamu | 1:dc648c5624b9 | 123 | * response token |
| joseph_adamu | 1:dc648c5624b9 | 124 | * |
| joseph_adamu | 1:dc648c5624b9 | 125 | * +----------------------+ |
| joseph_adamu | 1:dc648c5624b9 | 126 | * | xxx | 0 | status | 1 | |
| joseph_adamu | 1:dc648c5624b9 | 127 | * +----------------------+ |
| joseph_adamu | 1:dc648c5624b9 | 128 | * 010 - OK! |
| joseph_adamu | 1:dc648c5624b9 | 129 | * 101 - CRC Error |
| joseph_adamu | 1:dc648c5624b9 | 130 | * 110 - Write Error |
| joseph_adamu | 1:dc648c5624b9 | 131 | * |
| joseph_adamu | 1:dc648c5624b9 | 132 | * Single Block Read and Write |
| joseph_adamu | 1:dc648c5624b9 | 133 | * --------------------------- |
| joseph_adamu | 1:dc648c5624b9 | 134 | * |
| joseph_adamu | 1:dc648c5624b9 | 135 | * Block transfers have a byte header, followed by the data, followed |
| joseph_adamu | 1:dc648c5624b9 | 136 | * by a 16-bit CRC. In our case, the data will always be 512 bytes. |
| joseph_adamu | 1:dc648c5624b9 | 137 | * |
| joseph_adamu | 1:dc648c5624b9 | 138 | * +------+---------+---------+- - - -+---------+-----------+----------+ |
| joseph_adamu | 1:dc648c5624b9 | 139 | * | 0xFE | data[0] | data[1] | | data[n] | crc[15:8] | crc[7:0] | |
| joseph_adamu | 1:dc648c5624b9 | 140 | * +------+---------+---------+- - - -+---------+-----------+----------+ |
| joseph_adamu | 1:dc648c5624b9 | 141 | */ |
| joseph_adamu | 1:dc648c5624b9 | 142 | |
| joseph_adamu | 1:dc648c5624b9 | 143 | /* If the target has no SPI support then SDCard is not supported */ |
| joseph_adamu | 1:dc648c5624b9 | 144 | #ifdef DEVICE_SPI |
| joseph_adamu | 1:dc648c5624b9 | 145 | |
| joseph_adamu | 1:dc648c5624b9 | 146 | #include "SDBlockDevice.h" |
| joseph_adamu | 1:dc648c5624b9 | 147 | #include "mbed_debug.h" |
| joseph_adamu | 1:dc648c5624b9 | 148 | #include <errno.h> |
| joseph_adamu | 1:dc648c5624b9 | 149 | |
| joseph_adamu | 1:dc648c5624b9 | 150 | /* Required version: 5.6.1 and above */ |
| joseph_adamu | 1:dc648c5624b9 | 151 | #ifdef MBED_MAJOR_VERSION |
| joseph_adamu | 1:dc648c5624b9 | 152 | #if (MBED_VERSION < MBED_ENCODE_VERSION(5,6,1)) |
| joseph_adamu | 1:dc648c5624b9 | 153 | #error "Incompatible mbed-os version detected! Required 5.5.4 and above" |
| joseph_adamu | 1:dc648c5624b9 | 154 | #endif |
| joseph_adamu | 1:dc648c5624b9 | 155 | #else |
| joseph_adamu | 1:dc648c5624b9 | 156 | #warning "mbed-os version 5.6.1 or above required" |
| joseph_adamu | 1:dc648c5624b9 | 157 | #endif |
| joseph_adamu | 1:dc648c5624b9 | 158 | |
| joseph_adamu | 1:dc648c5624b9 | 159 | #define SD_COMMAND_TIMEOUT 5000 /*!< Timeout in ms for response */ |
| joseph_adamu | 1:dc648c5624b9 | 160 | #define SD_CMD0_GO_IDLE_STATE_RETRIES 5 /*!< Number of retries for sending CMDO */ |
| joseph_adamu | 1:dc648c5624b9 | 161 | #define SD_DBG 0 /*!< 1 - Enable debugging */ |
| joseph_adamu | 1:dc648c5624b9 | 162 | #define SD_CMD_TRACE 0 /*!< 1 - Enable SD command tracing */ |
| joseph_adamu | 1:dc648c5624b9 | 163 | |
| joseph_adamu | 1:dc648c5624b9 | 164 | #define SD_BLOCK_DEVICE_ERROR_WOULD_BLOCK -5001 /*!< operation would block */ |
| joseph_adamu | 1:dc648c5624b9 | 165 | #define SD_BLOCK_DEVICE_ERROR_UNSUPPORTED -5002 /*!< unsupported operation */ |
| joseph_adamu | 1:dc648c5624b9 | 166 | #define SD_BLOCK_DEVICE_ERROR_PARAMETER -5003 /*!< invalid parameter */ |
| joseph_adamu | 1:dc648c5624b9 | 167 | #define SD_BLOCK_DEVICE_ERROR_NO_INIT -5004 /*!< uninitialized */ |
| joseph_adamu | 1:dc648c5624b9 | 168 | #define SD_BLOCK_DEVICE_ERROR_NO_DEVICE -5005 /*!< device is missing or not connected */ |
| joseph_adamu | 1:dc648c5624b9 | 169 | #define SD_BLOCK_DEVICE_ERROR_WRITE_PROTECTED -5006 /*!< write protected */ |
| joseph_adamu | 1:dc648c5624b9 | 170 | #define SD_BLOCK_DEVICE_ERROR_UNUSABLE -5007 /*!< unusable card */ |
| joseph_adamu | 1:dc648c5624b9 | 171 | #define SD_BLOCK_DEVICE_ERROR_NO_RESPONSE -5008 /*!< No response from device */ |
| joseph_adamu | 1:dc648c5624b9 | 172 | #define SD_BLOCK_DEVICE_ERROR_CRC -5009 /*!< CRC error */ |
| joseph_adamu | 1:dc648c5624b9 | 173 | #define SD_BLOCK_DEVICE_ERROR_ERASE -5010 /*!< Erase error: reset/sequence */ |
| joseph_adamu | 1:dc648c5624b9 | 174 | #define SD_BLOCK_DEVICE_ERROR_WRITE -5011 /*!< SPI Write error: !SPI_DATA_ACCEPTED */ |
| joseph_adamu | 1:dc648c5624b9 | 175 | |
| joseph_adamu | 1:dc648c5624b9 | 176 | #define BLOCK_SIZE_HC 512 /*!< Block size supported for SD card is 512 bytes */ |
| joseph_adamu | 1:dc648c5624b9 | 177 | #define WRITE_BL_PARTIAL 0 /*!< Partial block write - Not supported */ |
| joseph_adamu | 1:dc648c5624b9 | 178 | #define CRC_SUPPORT 0 /*!< CRC - Not supported */ |
| joseph_adamu | 1:dc648c5624b9 | 179 | #define SPI_CMD(x) (0x40 | (x & 0x3f)) |
| joseph_adamu | 1:dc648c5624b9 | 180 | |
| joseph_adamu | 1:dc648c5624b9 | 181 | /* R1 Response Format */ |
| joseph_adamu | 1:dc648c5624b9 | 182 | #define R1_NO_RESPONSE (0xFF) |
| joseph_adamu | 1:dc648c5624b9 | 183 | #define R1_RESPONSE_RECV (0x80) |
| joseph_adamu | 1:dc648c5624b9 | 184 | #define R1_IDLE_STATE (1 << 0) |
| joseph_adamu | 1:dc648c5624b9 | 185 | #define R1_ERASE_RESET (1 << 1) |
| joseph_adamu | 1:dc648c5624b9 | 186 | #define R1_ILLEGAL_COMMAND (1 << 2) |
| joseph_adamu | 1:dc648c5624b9 | 187 | #define R1_COM_CRC_ERROR (1 << 3) |
| joseph_adamu | 1:dc648c5624b9 | 188 | #define R1_ERASE_SEQUENCE_ERROR (1 << 4) |
| joseph_adamu | 1:dc648c5624b9 | 189 | #define R1_ADDRESS_ERROR (1 << 5) |
| joseph_adamu | 1:dc648c5624b9 | 190 | #define R1_PARAMETER_ERROR (1 << 6) |
| joseph_adamu | 1:dc648c5624b9 | 191 | |
| joseph_adamu | 1:dc648c5624b9 | 192 | // Types |
| joseph_adamu | 1:dc648c5624b9 | 193 | #define SDCARD_NONE 0 /**< No card is present */ |
| joseph_adamu | 1:dc648c5624b9 | 194 | #define SDCARD_V1 1 /**< v1.x Standard Capacity */ |
| joseph_adamu | 1:dc648c5624b9 | 195 | #define SDCARD_V2 2 /**< v2.x Standard capacity SD card */ |
| joseph_adamu | 1:dc648c5624b9 | 196 | #define SDCARD_V2HC 3 /**< v2.x High capacity SD card */ |
| joseph_adamu | 1:dc648c5624b9 | 197 | #define CARD_UNKNOWN 4 /**< Unknown or unsupported card */ |
| joseph_adamu | 1:dc648c5624b9 | 198 | |
| joseph_adamu | 1:dc648c5624b9 | 199 | /* SIZE in Bytes */ |
| joseph_adamu | 1:dc648c5624b9 | 200 | #define PACKET_SIZE 6 /*!< SD Packet size CMD+ARG+CRC */ |
| joseph_adamu | 1:dc648c5624b9 | 201 | #define R1_RESPONSE_SIZE 1 /*!< Size of R1 response */ |
| joseph_adamu | 1:dc648c5624b9 | 202 | #define R2_RESPONSE_SIZE 2 /*!< Size of R2 response */ |
| joseph_adamu | 1:dc648c5624b9 | 203 | #define R3_R7_RESPONSE_SIZE 5 /*!< Size of R3/R7 response */ |
| joseph_adamu | 1:dc648c5624b9 | 204 | |
| joseph_adamu | 1:dc648c5624b9 | 205 | /* R1b Response */ |
| joseph_adamu | 1:dc648c5624b9 | 206 | #define DEVICE_BUSY (0x00) |
| joseph_adamu | 1:dc648c5624b9 | 207 | |
| joseph_adamu | 1:dc648c5624b9 | 208 | /* R2 Response Format */ |
| joseph_adamu | 1:dc648c5624b9 | 209 | #define R2_CARD_LOCKED (1 << 0) |
| joseph_adamu | 1:dc648c5624b9 | 210 | #define R2_CMD_FAILED (1 << 1) |
| joseph_adamu | 1:dc648c5624b9 | 211 | #define R2_ERROR (1 << 2) |
| joseph_adamu | 1:dc648c5624b9 | 212 | #define R2_CC_ERROR (1 << 3) |
| joseph_adamu | 1:dc648c5624b9 | 213 | #define R2_CC_FAILED (1 << 4) |
| joseph_adamu | 1:dc648c5624b9 | 214 | #define R2_WP_VIOLATION (1 << 5) |
| joseph_adamu | 1:dc648c5624b9 | 215 | #define R2_ERASE_PARAM (1 << 6) |
| joseph_adamu | 1:dc648c5624b9 | 216 | #define R2_OUT_OF_RANGE (1 << 7) |
| joseph_adamu | 1:dc648c5624b9 | 217 | |
| joseph_adamu | 1:dc648c5624b9 | 218 | /* R3 Response : OCR Register */ |
| joseph_adamu | 1:dc648c5624b9 | 219 | #define OCR_HCS_CCS (0x1 << 30) |
| joseph_adamu | 1:dc648c5624b9 | 220 | #define OCR_LOW_VOLTAGE (0x01 << 24) |
| joseph_adamu | 1:dc648c5624b9 | 221 | #define OCR_3_3V (0x1 << 20) |
| joseph_adamu | 1:dc648c5624b9 | 222 | |
| joseph_adamu | 1:dc648c5624b9 | 223 | /* R7 response pattern for CMD8 */ |
| joseph_adamu | 1:dc648c5624b9 | 224 | #define CMD8_PATTERN (0xAA) |
| joseph_adamu | 1:dc648c5624b9 | 225 | |
| joseph_adamu | 1:dc648c5624b9 | 226 | /* CRC Enable */ |
| joseph_adamu | 1:dc648c5624b9 | 227 | #define CRC_ENABLE (0) /*!< CRC 1 - Enable 0 - Disable */ |
| joseph_adamu | 1:dc648c5624b9 | 228 | |
| joseph_adamu | 1:dc648c5624b9 | 229 | /* Control Tokens */ |
| joseph_adamu | 1:dc648c5624b9 | 230 | #define SPI_DATA_RESPONSE_MASK (0x1F) |
| joseph_adamu | 1:dc648c5624b9 | 231 | #define SPI_DATA_ACCEPTED (0x05) |
| joseph_adamu | 1:dc648c5624b9 | 232 | #define SPI_DATA_CRC_ERROR (0x0B) |
| joseph_adamu | 1:dc648c5624b9 | 233 | #define SPI_DATA_WRITE_ERROR (0x0D) |
| joseph_adamu | 1:dc648c5624b9 | 234 | #define SPI_START_BLOCK (0xFE) /*!< For Single Block Read/Write and Multiple Block Read */ |
| joseph_adamu | 1:dc648c5624b9 | 235 | #define SPI_START_BLK_MUL_WRITE (0xFC) /*!< Start Multi-block write */ |
| joseph_adamu | 1:dc648c5624b9 | 236 | #define SPI_STOP_TRAN (0xFD) /*!< Stop Multi-block write */ |
| joseph_adamu | 1:dc648c5624b9 | 237 | |
| joseph_adamu | 1:dc648c5624b9 | 238 | #define SPI_DATA_READ_ERROR_MASK (0xF) /*!< Data Error Token: 4 LSB bits */ |
| joseph_adamu | 1:dc648c5624b9 | 239 | #define SPI_READ_ERROR (0x1 << 0) /*!< Error */ |
| joseph_adamu | 1:dc648c5624b9 | 240 | #define SPI_READ_ERROR_CC (0x1 << 1) /*!< CC Error*/ |
| joseph_adamu | 1:dc648c5624b9 | 241 | #define SPI_READ_ERROR_ECC_C (0x1 << 2) /*!< Card ECC failed */ |
| joseph_adamu | 1:dc648c5624b9 | 242 | #define SPI_READ_ERROR_OFR (0x1 << 3) /*!< Out of Range */ |
| joseph_adamu | 1:dc648c5624b9 | 243 | |
| joseph_adamu | 1:dc648c5624b9 | 244 | SDBlockDevice::SDBlockDevice(PinName mosi, PinName miso, PinName sclk, PinName cs, uint64_t hz) |
| joseph_adamu | 1:dc648c5624b9 | 245 | : _spi(mosi, miso, sclk), _cs(cs), _is_initialized(0) |
| joseph_adamu | 1:dc648c5624b9 | 246 | { |
| joseph_adamu | 1:dc648c5624b9 | 247 | _cs = 1; |
| joseph_adamu | 1:dc648c5624b9 | 248 | _card_type = SDCARD_NONE; |
| joseph_adamu | 1:dc648c5624b9 | 249 | |
| joseph_adamu | 1:dc648c5624b9 | 250 | // Set default to 100kHz for initialisation and 1MHz for data transfer |
| joseph_adamu | 1:dc648c5624b9 | 251 | _init_sck = 100000; |
| joseph_adamu | 1:dc648c5624b9 | 252 | _transfer_sck = hz; |
| joseph_adamu | 1:dc648c5624b9 | 253 | |
| joseph_adamu | 1:dc648c5624b9 | 254 | // Only HC block size is supported. |
| joseph_adamu | 1:dc648c5624b9 | 255 | _block_size = BLOCK_SIZE_HC; |
| joseph_adamu | 1:dc648c5624b9 | 256 | } |
| joseph_adamu | 1:dc648c5624b9 | 257 | |
| joseph_adamu | 1:dc648c5624b9 | 258 | SDBlockDevice::~SDBlockDevice() |
| joseph_adamu | 1:dc648c5624b9 | 259 | { |
| joseph_adamu | 1:dc648c5624b9 | 260 | if (_is_initialized) { |
| joseph_adamu | 1:dc648c5624b9 | 261 | deinit(); |
| joseph_adamu | 1:dc648c5624b9 | 262 | } |
| joseph_adamu | 1:dc648c5624b9 | 263 | } |
| joseph_adamu | 1:dc648c5624b9 | 264 | |
| joseph_adamu | 1:dc648c5624b9 | 265 | int SDBlockDevice::_initialise_card() |
| joseph_adamu | 1:dc648c5624b9 | 266 | { |
| joseph_adamu | 1:dc648c5624b9 | 267 | // Detail debugging is for commands |
| joseph_adamu | 1:dc648c5624b9 | 268 | _dbg = SD_DBG ? SD_CMD_TRACE : 0; |
| joseph_adamu | 1:dc648c5624b9 | 269 | int32_t status = BD_ERROR_OK; |
| joseph_adamu | 1:dc648c5624b9 | 270 | uint32_t response, arg; |
| joseph_adamu | 1:dc648c5624b9 | 271 | |
| joseph_adamu | 1:dc648c5624b9 | 272 | // Initialize the SPI interface: Card by default is in SD mode |
| joseph_adamu | 1:dc648c5624b9 | 273 | _spi_init(); |
| joseph_adamu | 1:dc648c5624b9 | 274 | |
| joseph_adamu | 1:dc648c5624b9 | 275 | // The card is transitioned from SDCard mode to SPI mode by sending the CMD0 + CS Asserted("0") |
| joseph_adamu | 1:dc648c5624b9 | 276 | if (_go_idle_state() != R1_IDLE_STATE) { |
| joseph_adamu | 1:dc648c5624b9 | 277 | debug_if(SD_DBG, "No disk, or could not put SD card in to SPI idle state\n"); |
| joseph_adamu | 1:dc648c5624b9 | 278 | return SD_BLOCK_DEVICE_ERROR_NO_DEVICE; |
| joseph_adamu | 1:dc648c5624b9 | 279 | } |
| joseph_adamu | 1:dc648c5624b9 | 280 | |
| joseph_adamu | 1:dc648c5624b9 | 281 | // Send CMD8, if the card rejects the command then it's probably using the |
| joseph_adamu | 1:dc648c5624b9 | 282 | // legacy protocol, or is a MMC, or just flat-out broken |
| joseph_adamu | 1:dc648c5624b9 | 283 | status = _cmd8(); |
| joseph_adamu | 1:dc648c5624b9 | 284 | if (BD_ERROR_OK != status && SD_BLOCK_DEVICE_ERROR_UNSUPPORTED != status) { |
| joseph_adamu | 1:dc648c5624b9 | 285 | return status; |
| joseph_adamu | 1:dc648c5624b9 | 286 | } |
| joseph_adamu | 1:dc648c5624b9 | 287 | |
| joseph_adamu | 1:dc648c5624b9 | 288 | // Read OCR - CMD58 Response contains OCR register |
| joseph_adamu | 1:dc648c5624b9 | 289 | if (BD_ERROR_OK != (status = _cmd(CMD58_READ_OCR, 0x0, 0x0, &response))) { |
| joseph_adamu | 1:dc648c5624b9 | 290 | return status; |
| joseph_adamu | 1:dc648c5624b9 | 291 | } |
| joseph_adamu | 1:dc648c5624b9 | 292 | |
| joseph_adamu | 1:dc648c5624b9 | 293 | // Check if card supports voltage range: 3.3V |
| joseph_adamu | 1:dc648c5624b9 | 294 | if (!(response & OCR_3_3V)) { |
| joseph_adamu | 1:dc648c5624b9 | 295 | _card_type = CARD_UNKNOWN; |
| joseph_adamu | 1:dc648c5624b9 | 296 | status = SD_BLOCK_DEVICE_ERROR_UNUSABLE; |
| joseph_adamu | 1:dc648c5624b9 | 297 | return status; |
| joseph_adamu | 1:dc648c5624b9 | 298 | } |
| joseph_adamu | 1:dc648c5624b9 | 299 | |
| joseph_adamu | 1:dc648c5624b9 | 300 | // HCS is set 1 for HC/XC capacity cards for ACMD41, if supported |
| joseph_adamu | 1:dc648c5624b9 | 301 | arg = 0x0; |
| joseph_adamu | 1:dc648c5624b9 | 302 | if (SDCARD_V2 == _card_type) { |
| joseph_adamu | 1:dc648c5624b9 | 303 | arg |= OCR_HCS_CCS; |
| joseph_adamu | 1:dc648c5624b9 | 304 | } |
| joseph_adamu | 1:dc648c5624b9 | 305 | |
| joseph_adamu | 1:dc648c5624b9 | 306 | /* Idle state bit in the R1 response of ACMD41 is used by the card to inform the host |
| joseph_adamu | 1:dc648c5624b9 | 307 | * if initialization of ACMD41 is completed. "1" indicates that the card is still initializing. |
| joseph_adamu | 1:dc648c5624b9 | 308 | * "0" indicates completion of initialization. The host repeatedly issues ACMD41 until |
| joseph_adamu | 1:dc648c5624b9 | 309 | * this bit is set to "0". |
| joseph_adamu | 1:dc648c5624b9 | 310 | */ |
| joseph_adamu | 1:dc648c5624b9 | 311 | _spi_timer.start(); |
| joseph_adamu | 1:dc648c5624b9 | 312 | do { |
| joseph_adamu | 1:dc648c5624b9 | 313 | status = _cmd(ACMD41_SD_SEND_OP_COND, arg, 1, &response); |
| joseph_adamu | 1:dc648c5624b9 | 314 | } while ((response & R1_IDLE_STATE) && (_spi_timer.read_ms() < SD_COMMAND_TIMEOUT)); |
| joseph_adamu | 1:dc648c5624b9 | 315 | _spi_timer.stop(); |
| joseph_adamu | 1:dc648c5624b9 | 316 | |
| joseph_adamu | 1:dc648c5624b9 | 317 | // Initialization complete: ACMD41 successful |
| joseph_adamu | 1:dc648c5624b9 | 318 | if ((BD_ERROR_OK != status) || (0x00 != response)) { |
| joseph_adamu | 1:dc648c5624b9 | 319 | _card_type = CARD_UNKNOWN; |
| joseph_adamu | 1:dc648c5624b9 | 320 | debug_if(SD_DBG, "Timeout waiting for card\n"); |
| joseph_adamu | 1:dc648c5624b9 | 321 | return status; |
| joseph_adamu | 1:dc648c5624b9 | 322 | } |
| joseph_adamu | 1:dc648c5624b9 | 323 | |
| joseph_adamu | 1:dc648c5624b9 | 324 | if (SDCARD_V2 == _card_type) { |
| joseph_adamu | 1:dc648c5624b9 | 325 | // Get the card capacity CCS: CMD58 |
| joseph_adamu | 1:dc648c5624b9 | 326 | if (BD_ERROR_OK == (status = _cmd(CMD58_READ_OCR, 0x0, 0x0, &response))) { |
| joseph_adamu | 1:dc648c5624b9 | 327 | // High Capacity card |
| joseph_adamu | 1:dc648c5624b9 | 328 | if (response & OCR_HCS_CCS) { |
| joseph_adamu | 1:dc648c5624b9 | 329 | _card_type = SDCARD_V2HC; |
| joseph_adamu | 1:dc648c5624b9 | 330 | debug_if(SD_DBG, "Card Initialized: High Capacity Card \n"); |
| joseph_adamu | 1:dc648c5624b9 | 331 | } else { |
| joseph_adamu | 1:dc648c5624b9 | 332 | debug_if(SD_DBG, "Card Initialized: Standard Capacity Card: Version 2.x \n"); |
| joseph_adamu | 1:dc648c5624b9 | 333 | } |
| joseph_adamu | 1:dc648c5624b9 | 334 | } |
| joseph_adamu | 1:dc648c5624b9 | 335 | } else { |
| joseph_adamu | 1:dc648c5624b9 | 336 | _card_type = SDCARD_V1; |
| joseph_adamu | 1:dc648c5624b9 | 337 | debug_if(SD_DBG, "Card Initialized: Version 1.x Card\n"); |
| joseph_adamu | 1:dc648c5624b9 | 338 | } |
| joseph_adamu | 1:dc648c5624b9 | 339 | |
| joseph_adamu | 1:dc648c5624b9 | 340 | // Disable CRC |
| joseph_adamu | 1:dc648c5624b9 | 341 | status = _cmd(CMD59_CRC_ON_OFF, 0); |
| joseph_adamu | 1:dc648c5624b9 | 342 | |
| joseph_adamu | 1:dc648c5624b9 | 343 | return status; |
| joseph_adamu | 1:dc648c5624b9 | 344 | } |
| joseph_adamu | 1:dc648c5624b9 | 345 | |
| joseph_adamu | 1:dc648c5624b9 | 346 | |
| joseph_adamu | 1:dc648c5624b9 | 347 | int SDBlockDevice::init() |
| joseph_adamu | 1:dc648c5624b9 | 348 | { |
| joseph_adamu | 1:dc648c5624b9 | 349 | _lock.lock(); |
| joseph_adamu | 1:dc648c5624b9 | 350 | int err = _initialise_card(); |
| joseph_adamu | 1:dc648c5624b9 | 351 | _is_initialized = (err == BD_ERROR_OK); |
| joseph_adamu | 1:dc648c5624b9 | 352 | if (!_is_initialized) { |
| joseph_adamu | 1:dc648c5624b9 | 353 | debug_if(SD_DBG, "Fail to initialize card\n"); |
| joseph_adamu | 1:dc648c5624b9 | 354 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 355 | return err; |
| joseph_adamu | 1:dc648c5624b9 | 356 | } |
| joseph_adamu | 1:dc648c5624b9 | 357 | debug_if(SD_DBG, "init card = %d\n", _is_initialized); |
| joseph_adamu | 1:dc648c5624b9 | 358 | _sectors = _sd_sectors(); |
| joseph_adamu | 1:dc648c5624b9 | 359 | // CMD9 failed |
| joseph_adamu | 1:dc648c5624b9 | 360 | if (0 == _sectors) { |
| joseph_adamu | 1:dc648c5624b9 | 361 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 362 | return BD_ERROR_DEVICE_ERROR; |
| joseph_adamu | 1:dc648c5624b9 | 363 | } |
| joseph_adamu | 1:dc648c5624b9 | 364 | |
| joseph_adamu | 1:dc648c5624b9 | 365 | // Set block length to 512 (CMD16) |
| joseph_adamu | 1:dc648c5624b9 | 366 | if (_cmd(CMD16_SET_BLOCKLEN, _block_size) != 0) { |
| joseph_adamu | 1:dc648c5624b9 | 367 | debug_if(SD_DBG, "Set %d-byte block timed out\n", _block_size); |
| joseph_adamu | 1:dc648c5624b9 | 368 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 369 | return BD_ERROR_DEVICE_ERROR; |
| joseph_adamu | 1:dc648c5624b9 | 370 | } |
| joseph_adamu | 1:dc648c5624b9 | 371 | |
| joseph_adamu | 1:dc648c5624b9 | 372 | // Set SCK for data transfer |
| joseph_adamu | 1:dc648c5624b9 | 373 | err = _freq(); |
| joseph_adamu | 1:dc648c5624b9 | 374 | if (err) { |
| joseph_adamu | 1:dc648c5624b9 | 375 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 376 | return err; |
| joseph_adamu | 1:dc648c5624b9 | 377 | } |
| joseph_adamu | 1:dc648c5624b9 | 378 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 379 | return BD_ERROR_OK; |
| joseph_adamu | 1:dc648c5624b9 | 380 | } |
| joseph_adamu | 1:dc648c5624b9 | 381 | |
| joseph_adamu | 1:dc648c5624b9 | 382 | int SDBlockDevice::deinit() |
| joseph_adamu | 1:dc648c5624b9 | 383 | { |
| joseph_adamu | 1:dc648c5624b9 | 384 | _lock.lock(); |
| joseph_adamu | 1:dc648c5624b9 | 385 | _is_initialized = false; |
| joseph_adamu | 1:dc648c5624b9 | 386 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 387 | return 0; |
| joseph_adamu | 1:dc648c5624b9 | 388 | } |
| joseph_adamu | 1:dc648c5624b9 | 389 | |
| joseph_adamu | 1:dc648c5624b9 | 390 | |
| joseph_adamu | 1:dc648c5624b9 | 391 | int SDBlockDevice::program(const void *b, bd_addr_t addr, bd_size_t size) |
| joseph_adamu | 1:dc648c5624b9 | 392 | { |
| joseph_adamu | 1:dc648c5624b9 | 393 | if (!is_valid_program(addr, size)) { |
| joseph_adamu | 1:dc648c5624b9 | 394 | return SD_BLOCK_DEVICE_ERROR_PARAMETER; |
| joseph_adamu | 1:dc648c5624b9 | 395 | } |
| joseph_adamu | 1:dc648c5624b9 | 396 | |
| joseph_adamu | 1:dc648c5624b9 | 397 | _lock.lock(); |
| joseph_adamu | 1:dc648c5624b9 | 398 | if (!_is_initialized) { |
| joseph_adamu | 1:dc648c5624b9 | 399 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 400 | return SD_BLOCK_DEVICE_ERROR_NO_INIT; |
| joseph_adamu | 1:dc648c5624b9 | 401 | } |
| joseph_adamu | 1:dc648c5624b9 | 402 | |
| joseph_adamu | 1:dc648c5624b9 | 403 | const uint8_t *buffer = static_cast<const uint8_t*>(b); |
| joseph_adamu | 1:dc648c5624b9 | 404 | int status = BD_ERROR_OK; |
| joseph_adamu | 1:dc648c5624b9 | 405 | uint8_t response; |
| joseph_adamu | 1:dc648c5624b9 | 406 | |
| joseph_adamu | 1:dc648c5624b9 | 407 | // Get block count |
| joseph_adamu | 1:dc648c5624b9 | 408 | bd_addr_t blockCnt = size / _block_size; |
| joseph_adamu | 1:dc648c5624b9 | 409 | |
| joseph_adamu | 1:dc648c5624b9 | 410 | // SDSC Card (CCS=0) uses byte unit address |
| joseph_adamu | 1:dc648c5624b9 | 411 | // SDHC and SDXC Cards (CCS=1) use block unit address (512 Bytes unit) |
| joseph_adamu | 1:dc648c5624b9 | 412 | if(SDCARD_V2HC == _card_type) { |
| joseph_adamu | 1:dc648c5624b9 | 413 | addr = addr / _block_size; |
| joseph_adamu | 1:dc648c5624b9 | 414 | } |
| joseph_adamu | 1:dc648c5624b9 | 415 | |
| joseph_adamu | 1:dc648c5624b9 | 416 | // Send command to perform write operation |
| joseph_adamu | 1:dc648c5624b9 | 417 | if (blockCnt == 1) { |
| joseph_adamu | 1:dc648c5624b9 | 418 | // Single block write command |
| joseph_adamu | 1:dc648c5624b9 | 419 | if (BD_ERROR_OK != (status = _cmd(CMD24_WRITE_BLOCK, addr))) { |
| joseph_adamu | 1:dc648c5624b9 | 420 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 421 | return status; |
| joseph_adamu | 1:dc648c5624b9 | 422 | } |
| joseph_adamu | 1:dc648c5624b9 | 423 | |
| joseph_adamu | 1:dc648c5624b9 | 424 | // Write data |
| joseph_adamu | 1:dc648c5624b9 | 425 | response = _write(buffer, SPI_START_BLOCK, _block_size); |
| joseph_adamu | 1:dc648c5624b9 | 426 | |
| joseph_adamu | 1:dc648c5624b9 | 427 | // Only CRC and general write error are communicated via response token |
| joseph_adamu | 1:dc648c5624b9 | 428 | if ((response == SPI_DATA_CRC_ERROR) || (response == SPI_DATA_WRITE_ERROR)) { |
| joseph_adamu | 1:dc648c5624b9 | 429 | debug_if(SD_DBG, "Single Block Write failed: 0x%x \n", response); |
| joseph_adamu | 1:dc648c5624b9 | 430 | status = SD_BLOCK_DEVICE_ERROR_WRITE; |
| joseph_adamu | 1:dc648c5624b9 | 431 | } |
| joseph_adamu | 1:dc648c5624b9 | 432 | } else { |
| joseph_adamu | 1:dc648c5624b9 | 433 | // Pre-erase setting prior to multiple block write operation |
| joseph_adamu | 1:dc648c5624b9 | 434 | _cmd(ACMD23_SET_WR_BLK_ERASE_COUNT, blockCnt, 1); |
| joseph_adamu | 1:dc648c5624b9 | 435 | |
| joseph_adamu | 1:dc648c5624b9 | 436 | // Multiple block write command |
| joseph_adamu | 1:dc648c5624b9 | 437 | if (BD_ERROR_OK != (status = _cmd(CMD25_WRITE_MULTIPLE_BLOCK, addr))) { |
| joseph_adamu | 1:dc648c5624b9 | 438 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 439 | return status; |
| joseph_adamu | 1:dc648c5624b9 | 440 | } |
| joseph_adamu | 1:dc648c5624b9 | 441 | |
| joseph_adamu | 1:dc648c5624b9 | 442 | // Write the data: one block at a time |
| joseph_adamu | 1:dc648c5624b9 | 443 | do { |
| joseph_adamu | 1:dc648c5624b9 | 444 | response = _write(buffer, SPI_START_BLK_MUL_WRITE, _block_size); |
| joseph_adamu | 1:dc648c5624b9 | 445 | if (response != SPI_DATA_ACCEPTED) { |
| joseph_adamu | 1:dc648c5624b9 | 446 | debug_if(SD_DBG, "Multiple Block Write failed: 0x%x \n", response); |
| joseph_adamu | 1:dc648c5624b9 | 447 | break; |
| joseph_adamu | 1:dc648c5624b9 | 448 | } |
| joseph_adamu | 1:dc648c5624b9 | 449 | buffer += _block_size; |
| joseph_adamu | 1:dc648c5624b9 | 450 | }while (--blockCnt); // Receive all blocks of data |
| joseph_adamu | 1:dc648c5624b9 | 451 | |
| joseph_adamu | 1:dc648c5624b9 | 452 | /* In a Multiple Block write operation, the stop transmission will be done by |
| joseph_adamu | 1:dc648c5624b9 | 453 | * sending 'Stop Tran' token instead of 'Start Block' token at the beginning |
| joseph_adamu | 1:dc648c5624b9 | 454 | * of the next block |
| joseph_adamu | 1:dc648c5624b9 | 455 | */ |
| joseph_adamu | 1:dc648c5624b9 | 456 | _spi.write(SPI_STOP_TRAN); |
| joseph_adamu | 1:dc648c5624b9 | 457 | } |
| joseph_adamu | 1:dc648c5624b9 | 458 | |
| joseph_adamu | 1:dc648c5624b9 | 459 | _deselect(); |
| joseph_adamu | 1:dc648c5624b9 | 460 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 461 | return status; |
| joseph_adamu | 1:dc648c5624b9 | 462 | } |
| joseph_adamu | 1:dc648c5624b9 | 463 | |
| joseph_adamu | 1:dc648c5624b9 | 464 | int SDBlockDevice::read(void *b, bd_addr_t addr, bd_size_t size) |
| joseph_adamu | 1:dc648c5624b9 | 465 | { |
| joseph_adamu | 1:dc648c5624b9 | 466 | if (!is_valid_read(addr, size)) { |
| joseph_adamu | 1:dc648c5624b9 | 467 | return SD_BLOCK_DEVICE_ERROR_PARAMETER; |
| joseph_adamu | 1:dc648c5624b9 | 468 | } |
| joseph_adamu | 1:dc648c5624b9 | 469 | |
| joseph_adamu | 1:dc648c5624b9 | 470 | _lock.lock(); |
| joseph_adamu | 1:dc648c5624b9 | 471 | if (!_is_initialized) { |
| joseph_adamu | 1:dc648c5624b9 | 472 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 473 | return SD_BLOCK_DEVICE_ERROR_PARAMETER; |
| joseph_adamu | 1:dc648c5624b9 | 474 | } |
| joseph_adamu | 1:dc648c5624b9 | 475 | |
| joseph_adamu | 1:dc648c5624b9 | 476 | uint8_t *buffer = static_cast<uint8_t *>(b); |
| joseph_adamu | 1:dc648c5624b9 | 477 | int status = BD_ERROR_OK; |
| joseph_adamu | 1:dc648c5624b9 | 478 | bd_addr_t blockCnt = size / _block_size; |
| joseph_adamu | 1:dc648c5624b9 | 479 | |
| joseph_adamu | 1:dc648c5624b9 | 480 | // SDSC Card (CCS=0) uses byte unit address |
| joseph_adamu | 1:dc648c5624b9 | 481 | // SDHC and SDXC Cards (CCS=1) use block unit address (512 Bytes unit) |
| joseph_adamu | 1:dc648c5624b9 | 482 | if (SDCARD_V2HC == _card_type) { |
| joseph_adamu | 1:dc648c5624b9 | 483 | addr = addr / _block_size; |
| joseph_adamu | 1:dc648c5624b9 | 484 | } |
| joseph_adamu | 1:dc648c5624b9 | 485 | |
| joseph_adamu | 1:dc648c5624b9 | 486 | // Write command ro receive data |
| joseph_adamu | 1:dc648c5624b9 | 487 | if (blockCnt > 1) { |
| joseph_adamu | 1:dc648c5624b9 | 488 | status = _cmd(CMD18_READ_MULTIPLE_BLOCK, addr); |
| joseph_adamu | 1:dc648c5624b9 | 489 | } else { |
| joseph_adamu | 1:dc648c5624b9 | 490 | status = _cmd(CMD17_READ_SINGLE_BLOCK, addr); |
| joseph_adamu | 1:dc648c5624b9 | 491 | } |
| joseph_adamu | 1:dc648c5624b9 | 492 | if (BD_ERROR_OK != status) { |
| joseph_adamu | 1:dc648c5624b9 | 493 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 494 | return status; |
| joseph_adamu | 1:dc648c5624b9 | 495 | } |
| joseph_adamu | 1:dc648c5624b9 | 496 | |
| joseph_adamu | 1:dc648c5624b9 | 497 | // receive the data : one block at a time |
| joseph_adamu | 1:dc648c5624b9 | 498 | while (blockCnt) { |
| joseph_adamu | 1:dc648c5624b9 | 499 | if (0 != _read(buffer, _block_size)) { |
| joseph_adamu | 1:dc648c5624b9 | 500 | status = SD_BLOCK_DEVICE_ERROR_NO_RESPONSE; |
| joseph_adamu | 1:dc648c5624b9 | 501 | break; |
| joseph_adamu | 1:dc648c5624b9 | 502 | } |
| joseph_adamu | 1:dc648c5624b9 | 503 | buffer += _block_size; |
| joseph_adamu | 1:dc648c5624b9 | 504 | --blockCnt; |
| joseph_adamu | 1:dc648c5624b9 | 505 | } |
| joseph_adamu | 1:dc648c5624b9 | 506 | _deselect(); |
| joseph_adamu | 1:dc648c5624b9 | 507 | |
| joseph_adamu | 1:dc648c5624b9 | 508 | // Send CMD12(0x00000000) to stop the transmission for multi-block transfer |
| joseph_adamu | 1:dc648c5624b9 | 509 | if (size > _block_size) { |
| joseph_adamu | 1:dc648c5624b9 | 510 | status = _cmd(CMD12_STOP_TRANSMISSION, 0x0); |
| joseph_adamu | 1:dc648c5624b9 | 511 | } |
| joseph_adamu | 1:dc648c5624b9 | 512 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 513 | return status; |
| joseph_adamu | 1:dc648c5624b9 | 514 | } |
| joseph_adamu | 1:dc648c5624b9 | 515 | |
| joseph_adamu | 1:dc648c5624b9 | 516 | bool SDBlockDevice::_is_valid_trim(bd_addr_t addr, bd_size_t size) |
| joseph_adamu | 1:dc648c5624b9 | 517 | { |
| joseph_adamu | 1:dc648c5624b9 | 518 | return ( |
| joseph_adamu | 1:dc648c5624b9 | 519 | addr % _erase_size == 0 && |
| joseph_adamu | 1:dc648c5624b9 | 520 | size % _erase_size == 0 && |
| joseph_adamu | 1:dc648c5624b9 | 521 | addr + size <= this->size()); |
| joseph_adamu | 1:dc648c5624b9 | 522 | } |
| joseph_adamu | 1:dc648c5624b9 | 523 | |
| joseph_adamu | 1:dc648c5624b9 | 524 | int SDBlockDevice::trim(bd_addr_t addr, bd_size_t size) |
| joseph_adamu | 1:dc648c5624b9 | 525 | { |
| joseph_adamu | 1:dc648c5624b9 | 526 | if (!_is_valid_trim(addr, size)) { |
| joseph_adamu | 1:dc648c5624b9 | 527 | return SD_BLOCK_DEVICE_ERROR_PARAMETER; |
| joseph_adamu | 1:dc648c5624b9 | 528 | } |
| joseph_adamu | 1:dc648c5624b9 | 529 | |
| joseph_adamu | 1:dc648c5624b9 | 530 | _lock.lock(); |
| joseph_adamu | 1:dc648c5624b9 | 531 | if (!_is_initialized) { |
| joseph_adamu | 1:dc648c5624b9 | 532 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 533 | return SD_BLOCK_DEVICE_ERROR_NO_INIT; |
| joseph_adamu | 1:dc648c5624b9 | 534 | } |
| joseph_adamu | 1:dc648c5624b9 | 535 | int status = BD_ERROR_OK; |
| joseph_adamu | 1:dc648c5624b9 | 536 | |
| joseph_adamu | 1:dc648c5624b9 | 537 | size -= _block_size; |
| joseph_adamu | 1:dc648c5624b9 | 538 | // SDSC Card (CCS=0) uses byte unit address |
| joseph_adamu | 1:dc648c5624b9 | 539 | // SDHC and SDXC Cards (CCS=1) use block unit address (512 Bytes unit) |
| joseph_adamu | 1:dc648c5624b9 | 540 | if (SDCARD_V2HC == _card_type) { |
| joseph_adamu | 1:dc648c5624b9 | 541 | size = size / _block_size; |
| joseph_adamu | 1:dc648c5624b9 | 542 | addr = addr / _block_size; |
| joseph_adamu | 1:dc648c5624b9 | 543 | } |
| joseph_adamu | 1:dc648c5624b9 | 544 | |
| joseph_adamu | 1:dc648c5624b9 | 545 | // Start lba sent in start command |
| joseph_adamu | 1:dc648c5624b9 | 546 | if (BD_ERROR_OK != (status = _cmd(CMD32_ERASE_WR_BLK_START_ADDR, addr))) { |
| joseph_adamu | 1:dc648c5624b9 | 547 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 548 | return status; |
| joseph_adamu | 1:dc648c5624b9 | 549 | } |
| joseph_adamu | 1:dc648c5624b9 | 550 | |
| joseph_adamu | 1:dc648c5624b9 | 551 | // End lba = addr+size sent in end addr command |
| joseph_adamu | 1:dc648c5624b9 | 552 | if (BD_ERROR_OK != (status = _cmd(CMD33_ERASE_WR_BLK_END_ADDR, addr+size))) { |
| joseph_adamu | 1:dc648c5624b9 | 553 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 554 | return status; |
| joseph_adamu | 1:dc648c5624b9 | 555 | } |
| joseph_adamu | 1:dc648c5624b9 | 556 | status = _cmd(CMD38_ERASE, 0x0); |
| joseph_adamu | 1:dc648c5624b9 | 557 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 558 | return status; |
| joseph_adamu | 1:dc648c5624b9 | 559 | } |
| joseph_adamu | 1:dc648c5624b9 | 560 | |
| joseph_adamu | 1:dc648c5624b9 | 561 | bd_size_t SDBlockDevice::get_read_size() const |
| joseph_adamu | 1:dc648c5624b9 | 562 | { |
| joseph_adamu | 1:dc648c5624b9 | 563 | return _block_size; |
| joseph_adamu | 1:dc648c5624b9 | 564 | } |
| joseph_adamu | 1:dc648c5624b9 | 565 | |
| joseph_adamu | 1:dc648c5624b9 | 566 | bd_size_t SDBlockDevice::get_program_size() const |
| joseph_adamu | 1:dc648c5624b9 | 567 | { |
| joseph_adamu | 1:dc648c5624b9 | 568 | return _block_size; |
| joseph_adamu | 1:dc648c5624b9 | 569 | } |
| joseph_adamu | 1:dc648c5624b9 | 570 | |
| joseph_adamu | 1:dc648c5624b9 | 571 | bd_size_t SDBlockDevice::size() const |
| joseph_adamu | 1:dc648c5624b9 | 572 | { |
| joseph_adamu | 1:dc648c5624b9 | 573 | bd_size_t sectors = 0; |
| joseph_adamu | 1:dc648c5624b9 | 574 | _lock.lock(); |
| joseph_adamu | 1:dc648c5624b9 | 575 | if (_is_initialized) { |
| joseph_adamu | 1:dc648c5624b9 | 576 | sectors = _sectors; |
| joseph_adamu | 1:dc648c5624b9 | 577 | } |
| joseph_adamu | 1:dc648c5624b9 | 578 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 579 | return _block_size*sectors; |
| joseph_adamu | 1:dc648c5624b9 | 580 | } |
| joseph_adamu | 1:dc648c5624b9 | 581 | |
| joseph_adamu | 1:dc648c5624b9 | 582 | void SDBlockDevice::debug(bool dbg) |
| joseph_adamu | 1:dc648c5624b9 | 583 | { |
| joseph_adamu | 1:dc648c5624b9 | 584 | _dbg = dbg; |
| joseph_adamu | 1:dc648c5624b9 | 585 | } |
| joseph_adamu | 1:dc648c5624b9 | 586 | |
| joseph_adamu | 1:dc648c5624b9 | 587 | int SDBlockDevice::frequency(uint64_t freq) |
| joseph_adamu | 1:dc648c5624b9 | 588 | { |
| joseph_adamu | 1:dc648c5624b9 | 589 | _lock.lock(); |
| joseph_adamu | 1:dc648c5624b9 | 590 | _transfer_sck = freq; |
| joseph_adamu | 1:dc648c5624b9 | 591 | int err = _freq(); |
| joseph_adamu | 1:dc648c5624b9 | 592 | _lock.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 593 | return err; |
| joseph_adamu | 1:dc648c5624b9 | 594 | } |
| joseph_adamu | 1:dc648c5624b9 | 595 | |
| joseph_adamu | 1:dc648c5624b9 | 596 | // PRIVATE FUNCTIONS |
| joseph_adamu | 1:dc648c5624b9 | 597 | int SDBlockDevice::_freq(void) |
| joseph_adamu | 1:dc648c5624b9 | 598 | { |
| joseph_adamu | 1:dc648c5624b9 | 599 | // Max frequency supported is 25MHZ |
| joseph_adamu | 1:dc648c5624b9 | 600 | if (_transfer_sck <= 25000000) { |
| joseph_adamu | 1:dc648c5624b9 | 601 | _spi.frequency(_transfer_sck); |
| joseph_adamu | 1:dc648c5624b9 | 602 | return 0; |
| joseph_adamu | 1:dc648c5624b9 | 603 | } else { // TODO: Switch function to be implemented for higher frequency |
| joseph_adamu | 1:dc648c5624b9 | 604 | _transfer_sck = 25000000; |
| joseph_adamu | 1:dc648c5624b9 | 605 | _spi.frequency(_transfer_sck); |
| joseph_adamu | 1:dc648c5624b9 | 606 | return -EINVAL; |
| joseph_adamu | 1:dc648c5624b9 | 607 | } |
| joseph_adamu | 1:dc648c5624b9 | 608 | } |
| joseph_adamu | 1:dc648c5624b9 | 609 | |
| joseph_adamu | 1:dc648c5624b9 | 610 | uint8_t SDBlockDevice::_cmd_spi(SDBlockDevice::cmdSupported cmd, uint32_t arg) { |
| joseph_adamu | 1:dc648c5624b9 | 611 | uint8_t response; |
| joseph_adamu | 1:dc648c5624b9 | 612 | char cmdPacket[PACKET_SIZE]; |
| joseph_adamu | 1:dc648c5624b9 | 613 | |
| joseph_adamu | 1:dc648c5624b9 | 614 | // Prepare the command packet |
| joseph_adamu | 1:dc648c5624b9 | 615 | cmdPacket[0] = SPI_CMD(cmd); |
| joseph_adamu | 1:dc648c5624b9 | 616 | cmdPacket[1] = (arg >> 24); |
| joseph_adamu | 1:dc648c5624b9 | 617 | cmdPacket[2] = (arg >> 16); |
| joseph_adamu | 1:dc648c5624b9 | 618 | cmdPacket[3] = (arg >> 8); |
| joseph_adamu | 1:dc648c5624b9 | 619 | cmdPacket[4] = (arg >> 0); |
| joseph_adamu | 1:dc648c5624b9 | 620 | // CMD0 is executed in SD mode, hence should have correct CRC |
| joseph_adamu | 1:dc648c5624b9 | 621 | // CMD8 CRC verification is always enabled |
| joseph_adamu | 1:dc648c5624b9 | 622 | switch(cmd) { |
| joseph_adamu | 1:dc648c5624b9 | 623 | case CMD0_GO_IDLE_STATE: |
| joseph_adamu | 1:dc648c5624b9 | 624 | cmdPacket[5] = 0x95; |
| joseph_adamu | 1:dc648c5624b9 | 625 | break; |
| joseph_adamu | 1:dc648c5624b9 | 626 | case CMD8_SEND_IF_COND: |
| joseph_adamu | 1:dc648c5624b9 | 627 | cmdPacket[5] = 0x87; |
| joseph_adamu | 1:dc648c5624b9 | 628 | break; |
| joseph_adamu | 1:dc648c5624b9 | 629 | default: |
| joseph_adamu | 1:dc648c5624b9 | 630 | cmdPacket[5] = 0xFF; // Make sure bit 0-End bit is high |
| joseph_adamu | 1:dc648c5624b9 | 631 | break; |
| joseph_adamu | 1:dc648c5624b9 | 632 | } |
| joseph_adamu | 1:dc648c5624b9 | 633 | |
| joseph_adamu | 1:dc648c5624b9 | 634 | // send a command |
| joseph_adamu | 1:dc648c5624b9 | 635 | for (int i = 0; i < PACKET_SIZE; i++) { |
| joseph_adamu | 1:dc648c5624b9 | 636 | _spi.write(cmdPacket[i]); |
| joseph_adamu | 1:dc648c5624b9 | 637 | } |
| joseph_adamu | 1:dc648c5624b9 | 638 | |
| joseph_adamu | 1:dc648c5624b9 | 639 | // The received byte immediataly following CMD12 is a stuff byte, |
| joseph_adamu | 1:dc648c5624b9 | 640 | // it should be discarded before receive the response of the CMD12. |
| joseph_adamu | 1:dc648c5624b9 | 641 | if (CMD12_STOP_TRANSMISSION == cmd) { |
| joseph_adamu | 1:dc648c5624b9 | 642 | _spi.write(SPI_FILL_CHAR); |
| joseph_adamu | 1:dc648c5624b9 | 643 | } |
| joseph_adamu | 1:dc648c5624b9 | 644 | |
| joseph_adamu | 1:dc648c5624b9 | 645 | // Loop for response: Response is sent back within command response time (NCR), 0 to 8 bytes for SDC |
| joseph_adamu | 1:dc648c5624b9 | 646 | for (int i = 0; i < 0x10; i++) { |
| joseph_adamu | 1:dc648c5624b9 | 647 | response = _spi.write(SPI_FILL_CHAR); |
| joseph_adamu | 1:dc648c5624b9 | 648 | // Got the response |
| joseph_adamu | 1:dc648c5624b9 | 649 | if (!(response & R1_RESPONSE_RECV)) { |
| joseph_adamu | 1:dc648c5624b9 | 650 | break; |
| joseph_adamu | 1:dc648c5624b9 | 651 | } |
| joseph_adamu | 1:dc648c5624b9 | 652 | } |
| joseph_adamu | 1:dc648c5624b9 | 653 | return response; |
| joseph_adamu | 1:dc648c5624b9 | 654 | } |
| joseph_adamu | 1:dc648c5624b9 | 655 | |
| joseph_adamu | 1:dc648c5624b9 | 656 | int SDBlockDevice::_cmd(SDBlockDevice::cmdSupported cmd, uint32_t arg, bool isAcmd, uint32_t *resp) { |
| joseph_adamu | 1:dc648c5624b9 | 657 | int32_t status = BD_ERROR_OK; |
| joseph_adamu | 1:dc648c5624b9 | 658 | uint32_t response; |
| joseph_adamu | 1:dc648c5624b9 | 659 | |
| joseph_adamu | 1:dc648c5624b9 | 660 | // Select card and wait for card to be ready before sending next command |
| joseph_adamu | 1:dc648c5624b9 | 661 | // Note: next command will fail if card is not ready |
| joseph_adamu | 1:dc648c5624b9 | 662 | _select(); |
| joseph_adamu | 1:dc648c5624b9 | 663 | |
| joseph_adamu | 1:dc648c5624b9 | 664 | // No need to wait for card to be ready when sending the stop command |
| joseph_adamu | 1:dc648c5624b9 | 665 | if (CMD12_STOP_TRANSMISSION != cmd) { |
| joseph_adamu | 1:dc648c5624b9 | 666 | if (false == _wait_ready(SD_COMMAND_TIMEOUT)) { |
| joseph_adamu | 1:dc648c5624b9 | 667 | debug_if(SD_DBG, "Card not ready yet \n"); |
| joseph_adamu | 1:dc648c5624b9 | 668 | } |
| joseph_adamu | 1:dc648c5624b9 | 669 | } |
| joseph_adamu | 1:dc648c5624b9 | 670 | |
| joseph_adamu | 1:dc648c5624b9 | 671 | // Re-try command |
| joseph_adamu | 1:dc648c5624b9 | 672 | for(int i = 0; i < 3; i++) { |
| joseph_adamu | 1:dc648c5624b9 | 673 | // Send CMD55 for APP command first |
| joseph_adamu | 1:dc648c5624b9 | 674 | if (isAcmd) { |
| joseph_adamu | 1:dc648c5624b9 | 675 | response = _cmd_spi(CMD55_APP_CMD, 0x0); |
| joseph_adamu | 1:dc648c5624b9 | 676 | // Wait for card to be ready after CMD55 |
| joseph_adamu | 1:dc648c5624b9 | 677 | if (false == _wait_ready(SD_COMMAND_TIMEOUT)) { |
| joseph_adamu | 1:dc648c5624b9 | 678 | debug_if(SD_DBG, "Card not ready yet \n"); |
| joseph_adamu | 1:dc648c5624b9 | 679 | } |
| joseph_adamu | 1:dc648c5624b9 | 680 | } |
| joseph_adamu | 1:dc648c5624b9 | 681 | |
| joseph_adamu | 1:dc648c5624b9 | 682 | // Send command over SPI interface |
| joseph_adamu | 1:dc648c5624b9 | 683 | response = _cmd_spi(cmd, arg); |
| joseph_adamu | 1:dc648c5624b9 | 684 | if (R1_NO_RESPONSE == response) { |
| joseph_adamu | 1:dc648c5624b9 | 685 | debug_if(SD_DBG, "No response CMD:%d \n", cmd); |
| joseph_adamu | 1:dc648c5624b9 | 686 | continue; |
| joseph_adamu | 1:dc648c5624b9 | 687 | } |
| joseph_adamu | 1:dc648c5624b9 | 688 | break; |
| joseph_adamu | 1:dc648c5624b9 | 689 | } |
| joseph_adamu | 1:dc648c5624b9 | 690 | |
| joseph_adamu | 1:dc648c5624b9 | 691 | // Pass the response to the command call if required |
| joseph_adamu | 1:dc648c5624b9 | 692 | if (NULL != resp) { |
| joseph_adamu | 1:dc648c5624b9 | 693 | *resp = response; |
| joseph_adamu | 1:dc648c5624b9 | 694 | } |
| joseph_adamu | 1:dc648c5624b9 | 695 | |
| joseph_adamu | 1:dc648c5624b9 | 696 | // Process the response R1 : Exit on CRC/Illegal command error/No response |
| joseph_adamu | 1:dc648c5624b9 | 697 | if (R1_NO_RESPONSE == response) { |
| joseph_adamu | 1:dc648c5624b9 | 698 | _deselect(); |
| joseph_adamu | 1:dc648c5624b9 | 699 | debug_if(SD_DBG, "No response CMD:%d response: 0x%x\n",cmd, response); |
| joseph_adamu | 1:dc648c5624b9 | 700 | return SD_BLOCK_DEVICE_ERROR_NO_DEVICE; // No device |
| joseph_adamu | 1:dc648c5624b9 | 701 | } |
| joseph_adamu | 1:dc648c5624b9 | 702 | if (response & R1_COM_CRC_ERROR) { |
| joseph_adamu | 1:dc648c5624b9 | 703 | _deselect(); |
| joseph_adamu | 1:dc648c5624b9 | 704 | debug_if(SD_DBG, "CRC error CMD:%d response 0x%x \n",cmd, response); |
| joseph_adamu | 1:dc648c5624b9 | 705 | return SD_BLOCK_DEVICE_ERROR_CRC; // CRC error |
| joseph_adamu | 1:dc648c5624b9 | 706 | } |
| joseph_adamu | 1:dc648c5624b9 | 707 | if (response & R1_ILLEGAL_COMMAND) { |
| joseph_adamu | 1:dc648c5624b9 | 708 | _deselect(); |
| joseph_adamu | 1:dc648c5624b9 | 709 | debug_if(SD_DBG, "Illegal command CMD:%d response 0x%x\n",cmd, response); |
| joseph_adamu | 1:dc648c5624b9 | 710 | if (CMD8_SEND_IF_COND == cmd) { // Illegal command is for Ver1 or not SD Card |
| joseph_adamu | 1:dc648c5624b9 | 711 | _card_type = CARD_UNKNOWN; |
| joseph_adamu | 1:dc648c5624b9 | 712 | } |
| joseph_adamu | 1:dc648c5624b9 | 713 | return SD_BLOCK_DEVICE_ERROR_UNSUPPORTED; // Command not supported |
| joseph_adamu | 1:dc648c5624b9 | 714 | } |
| joseph_adamu | 1:dc648c5624b9 | 715 | |
| joseph_adamu | 1:dc648c5624b9 | 716 | debug_if(_dbg, "CMD:%d \t arg:0x%x \t Response:0x%x \n", cmd, arg, response); |
| joseph_adamu | 1:dc648c5624b9 | 717 | // Set status for other errors |
| joseph_adamu | 1:dc648c5624b9 | 718 | if ((response & R1_ERASE_RESET) || (response & R1_ERASE_SEQUENCE_ERROR)) { |
| joseph_adamu | 1:dc648c5624b9 | 719 | status = SD_BLOCK_DEVICE_ERROR_ERASE; // Erase error |
| joseph_adamu | 1:dc648c5624b9 | 720 | }else if ((response & R1_ADDRESS_ERROR) || (response & R1_PARAMETER_ERROR)) { |
| joseph_adamu | 1:dc648c5624b9 | 721 | // Misaligned address / invalid address block length |
| joseph_adamu | 1:dc648c5624b9 | 722 | status = SD_BLOCK_DEVICE_ERROR_PARAMETER; |
| joseph_adamu | 1:dc648c5624b9 | 723 | } |
| joseph_adamu | 1:dc648c5624b9 | 724 | |
| joseph_adamu | 1:dc648c5624b9 | 725 | // Get rest of the response part for other commands |
| joseph_adamu | 1:dc648c5624b9 | 726 | switch(cmd) { |
| joseph_adamu | 1:dc648c5624b9 | 727 | case CMD8_SEND_IF_COND: // Response R7 |
| joseph_adamu | 1:dc648c5624b9 | 728 | debug_if(_dbg, "V2-Version Card\n"); |
| joseph_adamu | 1:dc648c5624b9 | 729 | _card_type = SDCARD_V2; |
| joseph_adamu | 1:dc648c5624b9 | 730 | // Note: No break here, need to read rest of the response |
| joseph_adamu | 1:dc648c5624b9 | 731 | case CMD58_READ_OCR: // Response R3 |
| joseph_adamu | 1:dc648c5624b9 | 732 | response = (_spi.write(SPI_FILL_CHAR) << 24); |
| joseph_adamu | 1:dc648c5624b9 | 733 | response |= (_spi.write(SPI_FILL_CHAR) << 16); |
| joseph_adamu | 1:dc648c5624b9 | 734 | response |= (_spi.write(SPI_FILL_CHAR) << 8); |
| joseph_adamu | 1:dc648c5624b9 | 735 | response |= _spi.write(SPI_FILL_CHAR); |
| joseph_adamu | 1:dc648c5624b9 | 736 | debug_if(_dbg, "R3/R7: 0x%x \n", response); |
| joseph_adamu | 1:dc648c5624b9 | 737 | break; |
| joseph_adamu | 1:dc648c5624b9 | 738 | |
| joseph_adamu | 1:dc648c5624b9 | 739 | case CMD12_STOP_TRANSMISSION: // Response R1b |
| joseph_adamu | 1:dc648c5624b9 | 740 | case CMD38_ERASE: |
| joseph_adamu | 1:dc648c5624b9 | 741 | _wait_ready(SD_COMMAND_TIMEOUT); |
| joseph_adamu | 1:dc648c5624b9 | 742 | break; |
| joseph_adamu | 1:dc648c5624b9 | 743 | |
| joseph_adamu | 1:dc648c5624b9 | 744 | case ACMD13_SD_STATUS: // Response R2 |
| joseph_adamu | 1:dc648c5624b9 | 745 | response = _spi.write(SPI_FILL_CHAR); |
| joseph_adamu | 1:dc648c5624b9 | 746 | debug_if(_dbg, "R2: 0x%x \n", response); |
| joseph_adamu | 1:dc648c5624b9 | 747 | break; |
| joseph_adamu | 1:dc648c5624b9 | 748 | |
| joseph_adamu | 1:dc648c5624b9 | 749 | default: // Response R1 |
| joseph_adamu | 1:dc648c5624b9 | 750 | break; |
| joseph_adamu | 1:dc648c5624b9 | 751 | } |
| joseph_adamu | 1:dc648c5624b9 | 752 | |
| joseph_adamu | 1:dc648c5624b9 | 753 | // Pass the updated response to the command |
| joseph_adamu | 1:dc648c5624b9 | 754 | if (NULL != resp) { |
| joseph_adamu | 1:dc648c5624b9 | 755 | *resp = response; |
| joseph_adamu | 1:dc648c5624b9 | 756 | } |
| joseph_adamu | 1:dc648c5624b9 | 757 | |
| joseph_adamu | 1:dc648c5624b9 | 758 | // Do not deselect card if read is in progress. |
| joseph_adamu | 1:dc648c5624b9 | 759 | if (((CMD9_SEND_CSD == cmd) || (ACMD22_SEND_NUM_WR_BLOCKS == cmd) || |
| joseph_adamu | 1:dc648c5624b9 | 760 | (CMD24_WRITE_BLOCK == cmd) || (CMD25_WRITE_MULTIPLE_BLOCK == cmd) || |
| joseph_adamu | 1:dc648c5624b9 | 761 | (CMD17_READ_SINGLE_BLOCK == cmd) || (CMD18_READ_MULTIPLE_BLOCK == cmd)) |
| joseph_adamu | 1:dc648c5624b9 | 762 | && (BD_ERROR_OK == status)) { |
| joseph_adamu | 1:dc648c5624b9 | 763 | return BD_ERROR_OK; |
| joseph_adamu | 1:dc648c5624b9 | 764 | } |
| joseph_adamu | 1:dc648c5624b9 | 765 | // Deselect card |
| joseph_adamu | 1:dc648c5624b9 | 766 | _deselect(); |
| joseph_adamu | 1:dc648c5624b9 | 767 | return status; |
| joseph_adamu | 1:dc648c5624b9 | 768 | } |
| joseph_adamu | 1:dc648c5624b9 | 769 | |
| joseph_adamu | 1:dc648c5624b9 | 770 | int SDBlockDevice::_cmd8() { |
| joseph_adamu | 1:dc648c5624b9 | 771 | uint32_t arg = (CMD8_PATTERN << 0); // [7:0]check pattern |
| joseph_adamu | 1:dc648c5624b9 | 772 | uint32_t response = 0; |
| joseph_adamu | 1:dc648c5624b9 | 773 | int32_t status = BD_ERROR_OK; |
| joseph_adamu | 1:dc648c5624b9 | 774 | |
| joseph_adamu | 1:dc648c5624b9 | 775 | arg |= (0x1 << 8); // 2.7-3.6V // [11:8]supply voltage(VHS) |
| joseph_adamu | 1:dc648c5624b9 | 776 | |
| joseph_adamu | 1:dc648c5624b9 | 777 | status = _cmd(CMD8_SEND_IF_COND, arg, 0x0, &response); |
| joseph_adamu | 1:dc648c5624b9 | 778 | // Verify voltage and pattern for V2 version of card |
| joseph_adamu | 1:dc648c5624b9 | 779 | if ((BD_ERROR_OK == status) && (SDCARD_V2 == _card_type)) { |
| joseph_adamu | 1:dc648c5624b9 | 780 | // If check pattern is not matched, CMD8 communication is not valid |
| joseph_adamu | 1:dc648c5624b9 | 781 | if((response & 0xFFF) != arg) |
| joseph_adamu | 1:dc648c5624b9 | 782 | { |
| joseph_adamu | 1:dc648c5624b9 | 783 | debug_if(SD_DBG, "CMD8 Pattern mismatch 0x%x : 0x%x\n", arg, response); |
| joseph_adamu | 1:dc648c5624b9 | 784 | _card_type = CARD_UNKNOWN; |
| joseph_adamu | 1:dc648c5624b9 | 785 | status = SD_BLOCK_DEVICE_ERROR_UNUSABLE; |
| joseph_adamu | 1:dc648c5624b9 | 786 | } |
| joseph_adamu | 1:dc648c5624b9 | 787 | } |
| joseph_adamu | 1:dc648c5624b9 | 788 | return status; |
| joseph_adamu | 1:dc648c5624b9 | 789 | } |
| joseph_adamu | 1:dc648c5624b9 | 790 | |
| joseph_adamu | 1:dc648c5624b9 | 791 | uint32_t SDBlockDevice::_go_idle_state() { |
| joseph_adamu | 1:dc648c5624b9 | 792 | uint32_t response; |
| joseph_adamu | 1:dc648c5624b9 | 793 | |
| joseph_adamu | 1:dc648c5624b9 | 794 | /* Reseting the MCU SPI master may not reset the on-board SDCard, in which |
| joseph_adamu | 1:dc648c5624b9 | 795 | * case when MCU power-on occurs the SDCard will resume operations as |
| joseph_adamu | 1:dc648c5624b9 | 796 | * though there was no reset. In this scenario the first CMD0 will |
| joseph_adamu | 1:dc648c5624b9 | 797 | * not be interpreted as a command and get lost. For some cards retrying |
| joseph_adamu | 1:dc648c5624b9 | 798 | * the command overcomes this situation. */ |
| joseph_adamu | 1:dc648c5624b9 | 799 | for (int i = 0; i < SD_CMD0_GO_IDLE_STATE_RETRIES; i++) { |
| joseph_adamu | 1:dc648c5624b9 | 800 | _cmd(CMD0_GO_IDLE_STATE, 0x0, 0x0, &response); |
| joseph_adamu | 1:dc648c5624b9 | 801 | if (R1_IDLE_STATE == response) |
| joseph_adamu | 1:dc648c5624b9 | 802 | break; |
| joseph_adamu | 1:dc648c5624b9 | 803 | wait_ms(1); |
| joseph_adamu | 1:dc648c5624b9 | 804 | } |
| joseph_adamu | 1:dc648c5624b9 | 805 | return response; |
| joseph_adamu | 1:dc648c5624b9 | 806 | } |
| joseph_adamu | 1:dc648c5624b9 | 807 | |
| joseph_adamu | 1:dc648c5624b9 | 808 | int SDBlockDevice::_read_bytes(uint8_t *buffer, uint32_t length) { |
| joseph_adamu | 1:dc648c5624b9 | 809 | uint16_t crc; |
| joseph_adamu | 1:dc648c5624b9 | 810 | |
| joseph_adamu | 1:dc648c5624b9 | 811 | // read until start byte (0xFE) |
| joseph_adamu | 1:dc648c5624b9 | 812 | if (false == _wait_token(SPI_START_BLOCK)) { |
| joseph_adamu | 1:dc648c5624b9 | 813 | debug_if(SD_DBG, "Read timeout\n"); |
| joseph_adamu | 1:dc648c5624b9 | 814 | _deselect(); |
| joseph_adamu | 1:dc648c5624b9 | 815 | return SD_BLOCK_DEVICE_ERROR_NO_RESPONSE; |
| joseph_adamu | 1:dc648c5624b9 | 816 | } |
| joseph_adamu | 1:dc648c5624b9 | 817 | |
| joseph_adamu | 1:dc648c5624b9 | 818 | // read data |
| joseph_adamu | 1:dc648c5624b9 | 819 | for (uint32_t i = 0; i < length; i++) { |
| joseph_adamu | 1:dc648c5624b9 | 820 | buffer[i] = _spi.write(SPI_FILL_CHAR); |
| joseph_adamu | 1:dc648c5624b9 | 821 | } |
| joseph_adamu | 1:dc648c5624b9 | 822 | |
| joseph_adamu | 1:dc648c5624b9 | 823 | // Read the CRC16 checksum for the data block |
| joseph_adamu | 1:dc648c5624b9 | 824 | crc = (_spi.write(SPI_FILL_CHAR) << 8); |
| joseph_adamu | 1:dc648c5624b9 | 825 | crc |= _spi.write(SPI_FILL_CHAR); |
| joseph_adamu | 1:dc648c5624b9 | 826 | |
| joseph_adamu | 1:dc648c5624b9 | 827 | _deselect(); |
| joseph_adamu | 1:dc648c5624b9 | 828 | return 0; |
| joseph_adamu | 1:dc648c5624b9 | 829 | } |
| joseph_adamu | 1:dc648c5624b9 | 830 | |
| joseph_adamu | 1:dc648c5624b9 | 831 | int SDBlockDevice::_read(uint8_t *buffer, uint32_t length) { |
| joseph_adamu | 1:dc648c5624b9 | 832 | uint16_t crc; |
| joseph_adamu | 1:dc648c5624b9 | 833 | |
| joseph_adamu | 1:dc648c5624b9 | 834 | // read until start byte (0xFE) |
| joseph_adamu | 1:dc648c5624b9 | 835 | if (false == _wait_token(SPI_START_BLOCK)) { |
| joseph_adamu | 1:dc648c5624b9 | 836 | debug_if(SD_DBG, "Read timeout\n"); |
| joseph_adamu | 1:dc648c5624b9 | 837 | _deselect(); |
| joseph_adamu | 1:dc648c5624b9 | 838 | return SD_BLOCK_DEVICE_ERROR_NO_RESPONSE; |
| joseph_adamu | 1:dc648c5624b9 | 839 | } |
| joseph_adamu | 1:dc648c5624b9 | 840 | |
| joseph_adamu | 1:dc648c5624b9 | 841 | // read data |
| joseph_adamu | 1:dc648c5624b9 | 842 | _spi.write(NULL, 0, (char*)buffer, length); |
| joseph_adamu | 1:dc648c5624b9 | 843 | |
| joseph_adamu | 1:dc648c5624b9 | 844 | // Read the CRC16 checksum for the data block |
| joseph_adamu | 1:dc648c5624b9 | 845 | crc = (_spi.write(SPI_FILL_CHAR) << 8); |
| joseph_adamu | 1:dc648c5624b9 | 846 | crc |= _spi.write(SPI_FILL_CHAR); |
| joseph_adamu | 1:dc648c5624b9 | 847 | |
| joseph_adamu | 1:dc648c5624b9 | 848 | return 0; |
| joseph_adamu | 1:dc648c5624b9 | 849 | } |
| joseph_adamu | 1:dc648c5624b9 | 850 | |
| joseph_adamu | 1:dc648c5624b9 | 851 | uint8_t SDBlockDevice::_write(const uint8_t *buffer, uint8_t token, uint32_t length) { |
| joseph_adamu | 1:dc648c5624b9 | 852 | uint16_t crc = 0xFFFF; |
| joseph_adamu | 1:dc648c5624b9 | 853 | uint8_t response = 0xFF; |
| joseph_adamu | 1:dc648c5624b9 | 854 | |
| joseph_adamu | 1:dc648c5624b9 | 855 | // indicate start of block |
| joseph_adamu | 1:dc648c5624b9 | 856 | _spi.write(token); |
| joseph_adamu | 1:dc648c5624b9 | 857 | |
| joseph_adamu | 1:dc648c5624b9 | 858 | // write the data |
| joseph_adamu | 1:dc648c5624b9 | 859 | _spi.write((char*)buffer, length, NULL, 0); |
| joseph_adamu | 1:dc648c5624b9 | 860 | |
| joseph_adamu | 1:dc648c5624b9 | 861 | // write the checksum CRC16 |
| joseph_adamu | 1:dc648c5624b9 | 862 | _spi.write(crc >> 8); |
| joseph_adamu | 1:dc648c5624b9 | 863 | _spi.write(crc); |
| joseph_adamu | 1:dc648c5624b9 | 864 | |
| joseph_adamu | 1:dc648c5624b9 | 865 | // check the response token |
| joseph_adamu | 1:dc648c5624b9 | 866 | response = _spi.write(SPI_FILL_CHAR); |
| joseph_adamu | 1:dc648c5624b9 | 867 | |
| joseph_adamu | 1:dc648c5624b9 | 868 | // Wait for last block to be written |
| joseph_adamu | 1:dc648c5624b9 | 869 | if (false == _wait_ready(SD_COMMAND_TIMEOUT)) { |
| joseph_adamu | 1:dc648c5624b9 | 870 | debug_if(SD_DBG, "Card not ready yet \n"); |
| joseph_adamu | 1:dc648c5624b9 | 871 | } |
| joseph_adamu | 1:dc648c5624b9 | 872 | |
| joseph_adamu | 1:dc648c5624b9 | 873 | return (response & SPI_DATA_RESPONSE_MASK); |
| joseph_adamu | 1:dc648c5624b9 | 874 | } |
| joseph_adamu | 1:dc648c5624b9 | 875 | |
| joseph_adamu | 1:dc648c5624b9 | 876 | static uint32_t ext_bits(unsigned char *data, int msb, int lsb) { |
| joseph_adamu | 1:dc648c5624b9 | 877 | uint32_t bits = 0; |
| joseph_adamu | 1:dc648c5624b9 | 878 | uint32_t size = 1 + msb - lsb; |
| joseph_adamu | 1:dc648c5624b9 | 879 | for (uint32_t i = 0; i < size; i++) { |
| joseph_adamu | 1:dc648c5624b9 | 880 | uint32_t position = lsb + i; |
| joseph_adamu | 1:dc648c5624b9 | 881 | uint32_t byte = 15 - (position >> 3); |
| joseph_adamu | 1:dc648c5624b9 | 882 | uint32_t bit = position & 0x7; |
| joseph_adamu | 1:dc648c5624b9 | 883 | uint32_t value = (data[byte] >> bit) & 1; |
| joseph_adamu | 1:dc648c5624b9 | 884 | bits |= value << i; |
| joseph_adamu | 1:dc648c5624b9 | 885 | } |
| joseph_adamu | 1:dc648c5624b9 | 886 | return bits; |
| joseph_adamu | 1:dc648c5624b9 | 887 | } |
| joseph_adamu | 1:dc648c5624b9 | 888 | |
| joseph_adamu | 1:dc648c5624b9 | 889 | uint32_t SDBlockDevice::_sd_sectors() { |
| joseph_adamu | 1:dc648c5624b9 | 890 | uint32_t c_size, c_size_mult, read_bl_len; |
| joseph_adamu | 1:dc648c5624b9 | 891 | uint32_t block_len, mult, blocknr; |
| joseph_adamu | 1:dc648c5624b9 | 892 | uint32_t hc_c_size; |
| joseph_adamu | 1:dc648c5624b9 | 893 | bd_size_t blocks = 0, capacity = 0; |
| joseph_adamu | 1:dc648c5624b9 | 894 | |
| joseph_adamu | 1:dc648c5624b9 | 895 | // CMD9, Response R2 (R1 byte + 16-byte block read) |
| joseph_adamu | 1:dc648c5624b9 | 896 | if (_cmd(CMD9_SEND_CSD, 0x0) != 0x0) { |
| joseph_adamu | 1:dc648c5624b9 | 897 | debug_if(SD_DBG, "Didn't get a response from the disk\n"); |
| joseph_adamu | 1:dc648c5624b9 | 898 | return 0; |
| joseph_adamu | 1:dc648c5624b9 | 899 | } |
| joseph_adamu | 1:dc648c5624b9 | 900 | uint8_t csd[16]; |
| joseph_adamu | 1:dc648c5624b9 | 901 | if (_read_bytes(csd, 16) != 0) { |
| joseph_adamu | 1:dc648c5624b9 | 902 | debug_if(SD_DBG, "Couldn't read csd response from disk\n"); |
| joseph_adamu | 1:dc648c5624b9 | 903 | return 0; |
| joseph_adamu | 1:dc648c5624b9 | 904 | } |
| joseph_adamu | 1:dc648c5624b9 | 905 | |
| joseph_adamu | 1:dc648c5624b9 | 906 | // csd_structure : csd[127:126] |
| joseph_adamu | 1:dc648c5624b9 | 907 | int csd_structure = ext_bits(csd, 127, 126); |
| joseph_adamu | 1:dc648c5624b9 | 908 | switch (csd_structure) { |
| joseph_adamu | 1:dc648c5624b9 | 909 | case 0: |
| joseph_adamu | 1:dc648c5624b9 | 910 | c_size = ext_bits(csd, 73, 62); // c_size : csd[73:62] |
| joseph_adamu | 1:dc648c5624b9 | 911 | c_size_mult = ext_bits(csd, 49, 47); // c_size_mult : csd[49:47] |
| joseph_adamu | 1:dc648c5624b9 | 912 | read_bl_len = ext_bits(csd, 83, 80); // read_bl_len : csd[83:80] - the *maximum* read block length |
| joseph_adamu | 1:dc648c5624b9 | 913 | block_len = 1 << read_bl_len; // BLOCK_LEN = 2^READ_BL_LEN |
| joseph_adamu | 1:dc648c5624b9 | 914 | mult = 1 << (c_size_mult + 2); // MULT = 2^C_SIZE_MULT+2 (C_SIZE_MULT < 8) |
| joseph_adamu | 1:dc648c5624b9 | 915 | blocknr = (c_size + 1) * mult; // BLOCKNR = (C_SIZE+1) * MULT |
| joseph_adamu | 1:dc648c5624b9 | 916 | capacity = blocknr * block_len; // memory capacity = BLOCKNR * BLOCK_LEN |
| joseph_adamu | 1:dc648c5624b9 | 917 | blocks = capacity / _block_size; |
| joseph_adamu | 1:dc648c5624b9 | 918 | debug_if(SD_DBG, "Standard Capacity: c_size: %d \n", c_size); |
| joseph_adamu | 1:dc648c5624b9 | 919 | debug_if(SD_DBG, "Sectors: 0x%x : %llu\n", blocks, blocks); |
| joseph_adamu | 1:dc648c5624b9 | 920 | debug_if(SD_DBG, "Capacity: 0x%x : %llu MB\n", capacity, (capacity/(1024U*1024U))); |
| joseph_adamu | 1:dc648c5624b9 | 921 | |
| joseph_adamu | 1:dc648c5624b9 | 922 | // ERASE_BLK_EN = 1: Erase in multiple of 512 bytes supported |
| joseph_adamu | 1:dc648c5624b9 | 923 | if (ext_bits(csd, 46, 46)) { |
| joseph_adamu | 1:dc648c5624b9 | 924 | _erase_size = BLOCK_SIZE_HC; |
| joseph_adamu | 1:dc648c5624b9 | 925 | } else { |
| joseph_adamu | 1:dc648c5624b9 | 926 | // ERASE_BLK_EN = 1: Erase in multiple of SECTOR_SIZE supported |
| joseph_adamu | 1:dc648c5624b9 | 927 | _erase_size = BLOCK_SIZE_HC * (ext_bits(csd, 45, 39) + 1); |
| joseph_adamu | 1:dc648c5624b9 | 928 | } |
| joseph_adamu | 1:dc648c5624b9 | 929 | break; |
| joseph_adamu | 1:dc648c5624b9 | 930 | |
| joseph_adamu | 1:dc648c5624b9 | 931 | case 1: |
| joseph_adamu | 1:dc648c5624b9 | 932 | hc_c_size = ext_bits(csd, 69, 48); // device size : C_SIZE : [69:48] |
| joseph_adamu | 1:dc648c5624b9 | 933 | blocks = (hc_c_size+1) << 10; // block count = C_SIZE+1) * 1K byte (512B is block size) |
| joseph_adamu | 1:dc648c5624b9 | 934 | debug_if(SD_DBG, "SDHC/SDXC Card: hc_c_size: %d \n", hc_c_size); |
| joseph_adamu | 1:dc648c5624b9 | 935 | debug_if(SD_DBG, "Sectors: 0x%x : %llu\n", blocks, blocks); |
| joseph_adamu | 1:dc648c5624b9 | 936 | debug_if(SD_DBG, "Capacity: %llu MB\n", (blocks/(2048U))); |
| joseph_adamu | 1:dc648c5624b9 | 937 | // ERASE_BLK_EN is fixed to 1, which means host can erase one or multiple of 512 bytes. |
| joseph_adamu | 1:dc648c5624b9 | 938 | _erase_size = BLOCK_SIZE_HC; |
| joseph_adamu | 1:dc648c5624b9 | 939 | break; |
| joseph_adamu | 1:dc648c5624b9 | 940 | |
| joseph_adamu | 1:dc648c5624b9 | 941 | default: |
| joseph_adamu | 1:dc648c5624b9 | 942 | debug_if(SD_DBG, "CSD struct unsupported\r\n"); |
| joseph_adamu | 1:dc648c5624b9 | 943 | return 0; |
| joseph_adamu | 1:dc648c5624b9 | 944 | }; |
| joseph_adamu | 1:dc648c5624b9 | 945 | return blocks; |
| joseph_adamu | 1:dc648c5624b9 | 946 | } |
| joseph_adamu | 1:dc648c5624b9 | 947 | |
| joseph_adamu | 1:dc648c5624b9 | 948 | // SPI function to wait till chip is ready and sends start token |
| joseph_adamu | 1:dc648c5624b9 | 949 | bool SDBlockDevice::_wait_token(uint8_t token) { |
| joseph_adamu | 1:dc648c5624b9 | 950 | _spi_timer.reset(); |
| joseph_adamu | 1:dc648c5624b9 | 951 | _spi_timer.start(); |
| joseph_adamu | 1:dc648c5624b9 | 952 | |
| joseph_adamu | 1:dc648c5624b9 | 953 | do { |
| joseph_adamu | 1:dc648c5624b9 | 954 | if (token == _spi.write(SPI_FILL_CHAR)) { |
| joseph_adamu | 1:dc648c5624b9 | 955 | _spi_timer.stop(); |
| joseph_adamu | 1:dc648c5624b9 | 956 | return true; |
| joseph_adamu | 1:dc648c5624b9 | 957 | } |
| joseph_adamu | 1:dc648c5624b9 | 958 | } while (_spi_timer.read_ms() < 300); // Wait for 300 msec for start token |
| joseph_adamu | 1:dc648c5624b9 | 959 | _spi_timer.stop(); |
| joseph_adamu | 1:dc648c5624b9 | 960 | debug_if(SD_DBG, "_wait_token: timeout\n"); |
| joseph_adamu | 1:dc648c5624b9 | 961 | return false; |
| joseph_adamu | 1:dc648c5624b9 | 962 | } |
| joseph_adamu | 1:dc648c5624b9 | 963 | |
| joseph_adamu | 1:dc648c5624b9 | 964 | // SPI function to wait till chip is ready |
| joseph_adamu | 1:dc648c5624b9 | 965 | // The host controller should wait for end of the process until DO goes high (a 0xFF is received). |
| joseph_adamu | 1:dc648c5624b9 | 966 | bool SDBlockDevice::_wait_ready(uint16_t ms) { |
| joseph_adamu | 1:dc648c5624b9 | 967 | uint8_t response; |
| joseph_adamu | 1:dc648c5624b9 | 968 | _spi_timer.reset(); |
| joseph_adamu | 1:dc648c5624b9 | 969 | _spi_timer.start(); |
| joseph_adamu | 1:dc648c5624b9 | 970 | do { |
| joseph_adamu | 1:dc648c5624b9 | 971 | response = _spi.write(SPI_FILL_CHAR); |
| joseph_adamu | 1:dc648c5624b9 | 972 | if (response == 0xFF) { |
| joseph_adamu | 1:dc648c5624b9 | 973 | _spi_timer.stop(); |
| joseph_adamu | 1:dc648c5624b9 | 974 | return true; |
| joseph_adamu | 1:dc648c5624b9 | 975 | } |
| joseph_adamu | 1:dc648c5624b9 | 976 | } while (_spi_timer.read_ms() < ms); |
| joseph_adamu | 1:dc648c5624b9 | 977 | _spi_timer.stop(); |
| joseph_adamu | 1:dc648c5624b9 | 978 | return false; |
| joseph_adamu | 1:dc648c5624b9 | 979 | } |
| joseph_adamu | 1:dc648c5624b9 | 980 | |
| joseph_adamu | 1:dc648c5624b9 | 981 | // SPI function to wait for count |
| joseph_adamu | 1:dc648c5624b9 | 982 | void SDBlockDevice::_spi_wait(uint8_t count) |
| joseph_adamu | 1:dc648c5624b9 | 983 | { |
| joseph_adamu | 1:dc648c5624b9 | 984 | for (uint8_t i = 0; i < count; ++i) { |
| joseph_adamu | 1:dc648c5624b9 | 985 | _spi.write(SPI_FILL_CHAR); |
| joseph_adamu | 1:dc648c5624b9 | 986 | } |
| joseph_adamu | 1:dc648c5624b9 | 987 | } |
| joseph_adamu | 1:dc648c5624b9 | 988 | |
| joseph_adamu | 1:dc648c5624b9 | 989 | void SDBlockDevice::_spi_init() { |
| joseph_adamu | 1:dc648c5624b9 | 990 | _spi.lock(); |
| joseph_adamu | 1:dc648c5624b9 | 991 | // Set to SCK for initialization, and clock card with cs = 1 |
| joseph_adamu | 1:dc648c5624b9 | 992 | _spi.frequency(_init_sck); |
| joseph_adamu | 1:dc648c5624b9 | 993 | _spi.format(8, 0); |
| joseph_adamu | 1:dc648c5624b9 | 994 | _spi.set_default_write_value(SPI_FILL_CHAR); |
| joseph_adamu | 1:dc648c5624b9 | 995 | // Initial 74 cycles required for few cards, before selecting SPI mode |
| joseph_adamu | 1:dc648c5624b9 | 996 | _cs = 1; |
| joseph_adamu | 1:dc648c5624b9 | 997 | _spi_wait(10); |
| joseph_adamu | 1:dc648c5624b9 | 998 | _spi.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 999 | } |
| joseph_adamu | 1:dc648c5624b9 | 1000 | |
| joseph_adamu | 1:dc648c5624b9 | 1001 | void SDBlockDevice::_select() { |
| joseph_adamu | 1:dc648c5624b9 | 1002 | _spi.lock(); |
| joseph_adamu | 1:dc648c5624b9 | 1003 | _spi.write(SPI_FILL_CHAR); |
| joseph_adamu | 1:dc648c5624b9 | 1004 | _cs = 0; |
| joseph_adamu | 1:dc648c5624b9 | 1005 | } |
| joseph_adamu | 1:dc648c5624b9 | 1006 | |
| joseph_adamu | 1:dc648c5624b9 | 1007 | void SDBlockDevice::_deselect() { |
| joseph_adamu | 1:dc648c5624b9 | 1008 | _cs = 1; |
| joseph_adamu | 1:dc648c5624b9 | 1009 | _spi.write(SPI_FILL_CHAR); |
| joseph_adamu | 1:dc648c5624b9 | 1010 | _spi.unlock(); |
| joseph_adamu | 1:dc648c5624b9 | 1011 | } |
| joseph_adamu | 1:dc648c5624b9 | 1012 | |
| joseph_adamu | 1:dc648c5624b9 | 1013 | #endif /* DEVICE_SPI */ |