John Alexander
/
VL53L3_Lib
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Dependencies: X_NUCLEO_COMMON ST_INTERFACES
Dependents: VL53L3ExpansionBoard
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vl53lx_def.h
00001 00002 #ifndef __VL53LX_DEF_H 00003 #define __VL53LX_DEF_H 00004 00005 #include <stdint.h> 00006 #include <stdint.h> 00007 #include <stddef.h> 00008 #include <string.h> 00009 #include <stdio.h> 00010 #include <stdlib.h> 00011 00012 #include "vl53L3_I2c.h" 00013 00014 #ifdef __cplusplus 00015 extern "C" 00016 { 00017 #endif 00018 00019 //define from vl53lx_register_map.h 00020 00021 #define VL53LX_SOFT_RESET 0x0000 00022 00023 #define VL53LX_I2C_SLAVE__DEVICE_ADDRESS 0x0001 00024 00025 #define VL53LX_ANA_CONFIG__VHV_REF_SEL_VDDPIX 0x0002 00026 00027 #define VL53LX_ANA_CONFIG__VHV_REF_SEL_VQUENCH 0x0003 00028 00029 #define VL53LX_ANA_CONFIG__REG_AVDD1V2_SEL 0x0004 00030 00031 #define VL53LX_ANA_CONFIG__FAST_OSC__TRIM 0x0005 00032 00033 #define VL53LX_OSC_MEASURED__FAST_OSC__FREQUENCY 0x0006 00034 00035 #define VL53LX_OSC_MEASURED__FAST_OSC__FREQUENCY_HI 0x0006 00036 00037 #define VL53LX_OSC_MEASURED__FAST_OSC__FREQUENCY_LO 0x0007 00038 00039 #define VL53LX_VHV_CONFIG__TIMEOUT_MACROP_LOOP_BOUND 0x0008 00040 00041 #define VL53LX_VHV_CONFIG__COUNT_THRESH 0x0009 00042 00043 #define VL53LX_VHV_CONFIG__OFFSET 0x000A 00044 00045 #define VL53LX_VHV_CONFIG__INIT 0x000B 00046 00047 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_0 0x000D 00048 00049 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_1 0x000E 00050 00051 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_2 0x000F 00052 00053 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_3 0x0010 00054 00055 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_4 0x0011 00056 00057 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_5 0x0012 00058 00059 #define VL53LX_GLOBAL_CONFIG__REF_EN_START_SELECT 0x0013 00060 00061 #define VL53LX_REF_SPAD_MAN__NUM_REQUESTED_REF_SPADS 0x0014 00062 00063 #define VL53LX_REF_SPAD_MAN__REF_LOCATION 0x0015 00064 00065 #define VL53LX_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS 0x0016 00066 00067 #define VL53LX_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_HI 0x0016 00068 00069 #define VL53LX_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_LO 0x0017 00070 00071 #define VL53LX_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS 0x0018 00072 00073 #define VL53LX_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_HI 0x0018 00074 00075 #define VL53LX_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_LO 0x0019 00076 00077 #define VL53LX_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS 0x001A 00078 00079 #define VL53LX_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_HI 0x001A 00080 00081 #define VL53LX_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_LO 0x001B 00082 00083 #define VL53LX_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS 0x001C 00084 00085 #define VL53LX_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS_HI 0x001C 00086 00087 #define VL53LX_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS_LO 0x001D 00088 00089 #define VL53LX_ALGO__PART_TO_PART_RANGE_OFFSET_MM 0x001E 00090 00091 #define VL53LX_ALGO__PART_TO_PART_RANGE_OFFSET_MM_HI 0x001E 00092 00093 #define VL53LX_ALGO__PART_TO_PART_RANGE_OFFSET_MM_LO 0x001F 00094 00095 #define VL53LX_MM_CONFIG__INNER_OFFSET_MM 0x0020 00096 00097 #define VL53LX_MM_CONFIG__INNER_OFFSET_MM_HI 0x0020 00098 00099 #define VL53LX_MM_CONFIG__INNER_OFFSET_MM_LO 0x0021 00100 00101 #define VL53LX_MM_CONFIG__OUTER_OFFSET_MM 0x0022 00102 00103 #define VL53LX_MM_CONFIG__OUTER_OFFSET_MM_HI 0x0022 00104 00105 #define VL53LX_MM_CONFIG__OUTER_OFFSET_MM_LO 0x0023 00106 00107 #define VL53LX_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS 0x0024 00108 00109 #define VL53LX_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS_HI 0x0024 00110 00111 #define VL53LX_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS_LO 0x0025 00112 00113 #define VL53LX_DEBUG__CTRL 0x0026 00114 00115 #define VL53LX_TEST_MODE__CTRL 0x0027 00116 00117 #define VL53LX_CLK_GATING__CTRL 0x0028 00118 00119 #define VL53LX_NVM_BIST__CTRL 0x0029 00120 00121 #define VL53LX_NVM_BIST__NUM_NVM_WORDS 0x002A 00122 00123 #define VL53LX_NVM_BIST__START_ADDRESS 0x002B 00124 00125 #define VL53LX_HOST_IF__STATUS 0x002C 00126 00127 #define VL53LX_PAD_I2C_HV__CONFIG 0x002D 00128 00129 #define VL53LX_PAD_I2C_HV__EXTSUP_CONFIG 0x002E 00130 00131 #define VL53LX_GPIO_HV_PAD__CTRL 0x002F 00132 00133 #define VL53LX_GPIO_HV_MUX__CTRL 0x0030 00134 00135 #define VL53LX_GPIO__TIO_HV_STATUS 0x0031 00136 00137 #define VL53LX_GPIO__FIO_HV_STATUS 0x0032 00138 00139 #define VL53LX_ANA_CONFIG__SPAD_SEL_PSWIDTH 0x0033 00140 00141 #define VL53LX_ANA_CONFIG__VCSEL_PULSE_WIDTH_OFFSET 0x0034 00142 00143 #define VL53LX_ANA_CONFIG__FAST_OSC__CONFIG_CTRL 0x0035 00144 00145 #define VL53LX_SIGMA_ESTIMATOR__EFFECTIVE_PULSE_WIDTH_NS 0x0036 00146 00147 #define VL53LX_SIGMA_ESTIMATOR__EFFECTIVE_AMBIENT_WIDTH_NS 0x0037 00148 00149 #define VL53LX_SIGMA_ESTIMATOR__SIGMA_REF_MM 0x0038 00150 00151 #define VL53LX_ALGO__CROSSTALK_COMPENSATION_VALID_HEIGHT_MM 0x0039 00152 00153 #define VL53LX_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_0 0x003A 00154 00155 #define VL53LX_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_1 0x003B 00156 00157 #define VL53LX_ALGO__RANGE_IGNORE_THRESHOLD_MCPS 0x003C 00158 00159 #define VL53LX_ALGO__RANGE_IGNORE_THRESHOLD_MCPS_HI 0x003C 00160 00161 #define VL53LX_ALGO__RANGE_IGNORE_THRESHOLD_MCPS_LO 0x003D 00162 00163 #define VL53LX_ALGO__RANGE_IGNORE_VALID_HEIGHT_MM 0x003E 00164 00165 #define VL53LX_ALGO__RANGE_MIN_CLIP 0x003F 00166 00167 #define VL53LX_ALGO__CONSISTENCY_CHECK__TOLERANCE 0x0040 00168 00169 #define VL53LX_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_2 0x0041 00170 00171 #define VL53LX_SD_CONFIG__RESET_STAGES_MSB 0x0042 00172 00173 #define VL53LX_SD_CONFIG__RESET_STAGES_LSB 0x0043 00174 00175 #define VL53LX_GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE 0x0044 00176 00177 #define VL53LX_GLOBAL_CONFIG__STREAM_DIVIDER 0x0045 00178 00179 #define VL53LX_SYSTEM__INTERRUPT_CONFIG_GPIO 0x0046 00180 00181 #define VL53LX_CAL_CONFIG__VCSEL_START 0x0047 00182 00183 #define VL53LX_CAL_CONFIG__REPEAT_RATE 0x0048 00184 00185 #define VL53LX_CAL_CONFIG__REPEAT_RATE_HI 0x0048 00186 00187 #define VL53LX_CAL_CONFIG__REPEAT_RATE_LO 0x0049 00188 00189 #define VL53LX_GLOBAL_CONFIG__VCSEL_WIDTH 0x004A 00190 00191 #define VL53LX_PHASECAL_CONFIG__TIMEOUT_MACROP 0x004B 00192 00193 #define VL53LX_PHASECAL_CONFIG__TARGET 0x004C 00194 00195 #define VL53LX_PHASECAL_CONFIG__OVERRIDE 0x004D 00196 00197 #define VL53LX_DSS_CONFIG__ROI_MODE_CONTROL 0x004F 00198 00199 #define VL53LX_SYSTEM__THRESH_RATE_HIGH 0x0050 00200 00201 #define VL53LX_SYSTEM__THRESH_RATE_HIGH_HI 0x0050 00202 00203 #define VL53LX_SYSTEM__THRESH_RATE_HIGH_LO 0x0051 00204 00205 #define VL53LX_SYSTEM__THRESH_RATE_LOW 0x0052 00206 00207 #define VL53LX_SYSTEM__THRESH_RATE_LOW_HI 0x0052 00208 00209 #define VL53LX_SYSTEM__THRESH_RATE_LOW_LO 0x0053 00210 00211 #define VL53LX_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT 0x0054 00212 00213 #define VL53LX_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_HI 0x0054 00214 00215 #define VL53LX_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_LO 0x0055 00216 00217 #define VL53LX_DSS_CONFIG__MANUAL_BLOCK_SELECT 0x0056 00218 00219 #define VL53LX_DSS_CONFIG__APERTURE_ATTENUATION 0x0057 00220 00221 #define VL53LX_DSS_CONFIG__MAX_SPADS_LIMIT 0x0058 00222 00223 #define VL53LX_DSS_CONFIG__MIN_SPADS_LIMIT 0x0059 00224 00225 #define VL53LX_MM_CONFIG__TIMEOUT_MACROP_A_HI 0x005A 00226 00227 #define VL53LX_MM_CONFIG__TIMEOUT_MACROP_A_LO 0x005B 00228 00229 #define VL53LX_MM_CONFIG__TIMEOUT_MACROP_B_HI 0x005C 00230 00231 #define VL53LX_MM_CONFIG__TIMEOUT_MACROP_B_LO 0x005D 00232 00233 #define VL53LX_RANGE_CONFIG__TIMEOUT_MACROP_A_HI 0x005E 00234 00235 #define VL53LX_RANGE_CONFIG__TIMEOUT_MACROP_A_LO 0x005F 00236 00237 #define VL53LX_RANGE_CONFIG__VCSEL_PERIOD_A 0x0060 00238 00239 #define VL53LX_RANGE_CONFIG__TIMEOUT_MACROP_B_HI 0x0061 00240 00241 #define VL53LX_RANGE_CONFIG__TIMEOUT_MACROP_B_LO 0x0062 00242 00243 #define VL53LX_RANGE_CONFIG__VCSEL_PERIOD_B 0x0063 00244 00245 #define VL53LX_RANGE_CONFIG__SIGMA_THRESH 0x0064 00246 00247 #define VL53LX_RANGE_CONFIG__SIGMA_THRESH_HI 0x0064 00248 00249 #define VL53LX_RANGE_CONFIG__SIGMA_THRESH_LO 0x0065 00250 00251 #define VL53LX_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS 0x0066 00252 00253 #define VL53LX_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI 0x0066 00254 00255 #define VL53LX_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO 0x0067 00256 00257 #define VL53LX_RANGE_CONFIG__VALID_PHASE_LOW 0x0068 00258 00259 #define VL53LX_RANGE_CONFIG__VALID_PHASE_HIGH 0x0069 00260 00261 #define VL53LX_SYSTEM__INTERMEASUREMENT_PERIOD 0x006C 00262 00263 #define VL53LX_SYSTEM__INTERMEASUREMENT_PERIOD_3 0x006C 00264 00265 #define VL53LX_SYSTEM__INTERMEASUREMENT_PERIOD_2 0x006D 00266 00267 #define VL53LX_SYSTEM__INTERMEASUREMENT_PERIOD_1 0x006E 00268 00269 #define VL53LX_SYSTEM__INTERMEASUREMENT_PERIOD_0 0x006F 00270 00271 #define VL53LX_SYSTEM__FRACTIONAL_ENABLE 0x0070 00272 00273 #define VL53LX_SYSTEM__GROUPED_PARAMETER_HOLD_0 0x0071 00274 00275 #define VL53LX_SYSTEM__THRESH_HIGH 0x0072 00276 00277 #define VL53LX_SYSTEM__THRESH_HIGH_HI 0x0072 00278 00279 #define VL53LX_SYSTEM__THRESH_HIGH_LO 0x0073 00280 00281 #define VL53LX_SYSTEM__THRESH_LOW 0x0074 00282 00283 #define VL53LX_SYSTEM__THRESH_LOW_HI 0x0074 00284 00285 #define VL53LX_SYSTEM__THRESH_LOW_LO 0x0075 00286 00287 #define VL53LX_SYSTEM__ENABLE_XTALK_PER_QUADRANT 0x0076 00288 00289 #define VL53LX_SYSTEM__SEED_CONFIG 0x0077 00290 00291 #define VL53LX_SD_CONFIG__WOI_SD0 0x0078 00292 00293 #define VL53LX_SD_CONFIG__WOI_SD1 0x0079 00294 00295 #define VL53LX_SD_CONFIG__INITIAL_PHASE_SD0 0x007A 00296 00297 #define VL53LX_SD_CONFIG__INITIAL_PHASE_SD1 0x007B 00298 00299 #define VL53LX_SYSTEM__GROUPED_PARAMETER_HOLD_1 0x007C 00300 00301 #define VL53LX_SD_CONFIG__FIRST_ORDER_SELECT 0x007D 00302 00303 #define VL53LX_SD_CONFIG__QUANTIFIER 0x007E 00304 00305 #define VL53LX_ROI_CONFIG__USER_ROI_CENTRE_SPAD 0x007F 00306 00307 #define VL53LX_ROI_CONFIG__USER_ROI_REQUESTED_GLOBAL_XY_SIZE 0x0080 00308 00309 #define VL53LX_SYSTEM__SEQUENCE_CONFIG 0x0081 00310 00311 #define VL53LX_SYSTEM__GROUPED_PARAMETER_HOLD 0x0082 00312 00313 #define VL53LX_POWER_MANAGEMENT__GO1_POWER_FORCE 0x0083 00314 00315 #define VL53LX_SYSTEM__STREAM_COUNT_CTRL 0x0084 00316 00317 #define VL53LX_FIRMWARE__ENABLE 0x0085 00318 00319 #define VL53LX_SYSTEM__INTERRUPT_CLEAR 0x0086 00320 00321 #define VL53LX_SYSTEM__MODE_START 0x0087 00322 00323 #define VL53LX_RESULT__INTERRUPT_STATUS 0x0088 00324 00325 #define VL53LX_RESULT__RANGE_STATUS 0x0089 00326 00327 #define VL53LX_RESULT__REPORT_STATUS 0x008A 00328 00329 #define VL53LX_RESULT__STREAM_COUNT 0x008B 00330 00331 #define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x008C 00332 00333 #define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x008C 00334 00335 #define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x008D 00336 00337 #define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x008E 00338 00339 #define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x008E 00340 00341 #define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x008F 00342 00343 #define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0090 00344 00345 #define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0090 00346 00347 #define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0091 00348 00349 #define VL53LX_RESULT__SIGMA_SD0 0x0092 00350 00351 #define VL53LX_RESULT__SIGMA_SD0_HI 0x0092 00352 00353 #define VL53LX_RESULT__SIGMA_SD0_LO 0x0093 00354 00355 #define VL53LX_RESULT__PHASE_SD0 0x0094 00356 00357 #define VL53LX_RESULT__PHASE_SD0_HI 0x0094 00358 00359 #define VL53LX_RESULT__PHASE_SD0_LO 0x0095 00360 00361 #define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0096 00362 00363 #define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0096 00364 00365 #define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0097 00366 00367 #define VL53LX_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0098 00368 00369 #define VL53LX__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0098 00370 00371 #define VL53LX___PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0099 00372 00373 #define VL53LX_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x009A 00374 00375 #define VL53LX_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x009A 00376 00377 #define VL53LX_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x009B 00378 00379 #define VL53LX_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x009C 00380 00381 #define VL53LX_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x009C 00382 00383 #define VL53LX_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x009D 00384 00385 #define VL53LX_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x009E 00386 00387 #define VL53LX_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x009E 00388 00389 #define VL53LX_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x009F 00390 00391 #define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x00A0 00392 00393 #define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x00A0 00394 00395 #define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x00A1 00396 00397 #define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x00A2 00398 00399 #define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x00A2 00400 00401 #define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x00A3 00402 00403 #define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x00A4 00404 00405 #define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x00A4 00406 00407 #define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x00A5 00408 00409 #define VL53LX_RESULT__SIGMA_SD1 0x00A6 00410 00411 #define VL53LX_RESULT__SIGMA_SD1_HI 0x00A6 00412 00413 #define VL53LX_RESULT__SIGMA_SD1_LO 0x00A7 00414 00415 #define VL53LX_RESULT__PHASE_SD1 0x00A8 00416 00417 #define VL53LX_RESULT__PHASE_SD1_HI 0x00A8 00418 00419 #define VL53LX_RESULT__PHASE_SD1_LO 0x00A9 00420 00421 #define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x00AA 00422 00423 #define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x00AA 00424 00425 #define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x00AB 00426 00427 #define VL53LX_RESULT__SPARE_0_SD1 0x00AC 00428 00429 #define VL53LX_RESULT__SPARE_0_SD1_HI 0x00AC 00430 00431 #define VL53LX_RESULT__SPARE_0_SD1_LO 0x00AD 00432 00433 #define VL53LX_RESULT__SPARE_1_SD1 0x00AE 00434 00435 #define VL53LX_RESULT__SPARE_1_SD1_HI 0x00AE 00436 00437 #define VL53LX_RESULT__SPARE_1_SD1_LO 0x00AF 00438 00439 #define VL53LX_RESULT__SPARE_2_SD1 0x00B0 00440 00441 #define VL53LX_RESULT__SPARE_2_SD1_HI 0x00B0 00442 00443 #define VL53LX_RESULT__SPARE_2_SD1_LO 0x00B1 00444 00445 #define VL53LX_RESULT__SPARE_3_SD1 0x00B2 00446 00447 #define VL53LX_RESULT__THRESH_INFO 0x00B3 00448 00449 #define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x00B4 00450 00451 #define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x00B4 00452 00453 #define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x00B5 00454 00455 #define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x00B6 00456 00457 #define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x00B7 00458 00459 #define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x00B8 00460 00461 #define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x00B8 00462 00463 #define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x00B9 00464 00465 #define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x00BA 00466 00467 #define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x00BB 00468 00469 #define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x00BC 00470 00471 #define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x00BC 00472 00473 #define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x00BD 00474 00475 #define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x00BE 00476 00477 #define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x00BF 00478 00479 #define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x00C0 00480 00481 #define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x00C0 00482 00483 #define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x00C1 00484 00485 #define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x00C2 00486 00487 #define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x00C3 00488 00489 #define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x00C4 00490 00491 #define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x00C4 00492 00493 #define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x00C5 00494 00495 #define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x00C6 00496 00497 #define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x00C7 00498 00499 #define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x00C8 00500 00501 #define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x00C8 00502 00503 #define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x00C9 00504 00505 #define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x00CA 00506 00507 #define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x00CB 00508 00509 #define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x00CC 00510 00511 #define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x00CC 00512 00513 #define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x00CD 00514 00515 #define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x00CE 00516 00517 #define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x00CF 00518 00519 #define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x00D0 00520 00521 #define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x00D0 00522 00523 #define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x00D1 00524 00525 #define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x00D2 00526 00527 #define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x00D3 00528 00529 #define VL53LX_RESULT_CORE__SPARE_0 0x00D4 00530 00531 #define VL53LX_PHASECAL_RESULT__REFERENCE_PHASE 0x00D6 00532 00533 #define VL53LX_PHASECAL_RESULT__REFERENCE_PHASE_HI 0x00D6 00534 00535 #define VL53LX_PHASECAL_RESULT__REFERENCE_PHASE_LO 0x00D7 00536 00537 #define VL53LX_PHASECAL_RESULT__VCSEL_START 0x00D8 00538 00539 #define VL53LX_REF_SPAD_CHAR_RESULT__NUM_ACTUAL_REF_SPADS 0x00D9 00540 00541 #define VL53LX_REF_SPAD_CHAR_RESULT__REF_LOCATION 0x00DA 00542 00543 #define VL53LX_VHV_RESULT__COLDBOOT_STATUS 0x00DB 00544 00545 #define VL53LX_VHV_RESULT__SEARCH_RESULT 0x00DC 00546 00547 #define VL53LX_VHV_RESULT__LATEST_SETTING 0x00DD 00548 00549 #define VL53LX_RESULT__OSC_CALIBRATE_VAL 0x00DE 00550 00551 #define VL53LX_RESULT__OSC_CALIBRATE_VAL_HI 0x00DE 00552 00553 #define VL53LX_RESULT__OSC_CALIBRATE_VAL_LO 0x00DF 00554 00555 #define VL53LX_ANA_CONFIG__POWERDOWN_GO1 0x00E0 00556 00557 #define VL53LX_ANA_CONFIG__REF_BG_CTRL 0x00E1 00558 00559 #define VL53LX_ANA_CONFIG__REGDVDD1V2_CTRL 0x00E2 00560 00561 #define VL53LX_ANA_CONFIG__OSC_SLOW_CTRL 0x00E3 00562 00563 #define VL53LX_TEST_MODE__STATUS 0x00E4 00564 00565 #define VL53LX_FIRMWARE__SYSTEM_STATUS 0x00E5 00566 00567 #define VL53LX_FIRMWARE__MODE_STATUS 0x00E6 00568 00569 #define VL53LX_FIRMWARE__SECONDARY_MODE_STATUS 0x00E7 00570 00571 #define VL53LX_FIRMWARE__CAL_REPEAT_RATE_COUNTER 0x00E8 00572 00573 #define VL53LX_FIRMWARE__CAL_REPEAT_RATE_COUNTER_HI 0x00E8 00574 00575 #define VL53LX_FIRMWARE__CAL_REPEAT_RATE_COUNTER_LO 0x00E9 00576 00577 #define VL53LX_FIRMWARE__HISTOGRAM_BIN 0x00EA 00578 00579 #define VL53LX_GPH__SYSTEM__THRESH_HIGH 0x00EC 00580 00581 #define VL53LX_GPH__SYSTEM__THRESH_HIGH_HI 0x00EC 00582 00583 #define VL53LX_GPH__SYSTEM__THRESH_HIGH_LO 0x00ED 00584 00585 #define VL53LX_GPH__SYSTEM__THRESH_LOW 0x00EE 00586 00587 #define VL53LX_GPH__SYSTEM__THRESH_LOW_HI 0x00EE 00588 00589 #define VL53LX_GPH__SYSTEM__THRESH_LOW_LO 0x00EF 00590 00591 #define VL53LX_GPH__SYSTEM__ENABLE_XTALK_PER_QUADRANT 0x00F0 00592 00593 #define VL53LX_GPH__SPARE_0 0x00F1 00594 00595 #define VL53LX_GPH__SD_CONFIG__WOI_SD0 0x00F2 00596 00597 #define VL53LX_GPH__SD_CONFIG__WOI_SD1 0x00F3 00598 00599 #define VL53LX_GPH__SD_CONFIG__INITIAL_PHASE_SD0 0x00F4 00600 00601 #define VL53LX_GPH__SD_CONFIG__INITIAL_PHASE_SD1 0x00F5 00602 00603 #define VL53LX_GPH__SD_CONFIG__FIRST_ORDER_SELECT 0x00F6 00604 00605 #define VL53LX_GPH__SD_CONFIG__QUANTIFIER 0x00F7 00606 00607 #define VL53LX_GPH__ROI_CONFIG__USER_ROI_CENTRE_SPAD 0x00F8 00608 00609 #define VL53LX_GPH__ROI_CONFIG__USER_ROI_REQUESTED_GLOBAL_XY_SIZE 0x00F9 00610 00611 #define VL53LX_GPH__SYSTEM__SEQUENCE_CONFIG 0x00FA 00612 00613 #define VL53LX_GPH__GPH_ID 0x00FB 00614 00615 #define VL53LX_SYSTEM__INTERRUPT_SET 0x00FC 00616 00617 #define VL53LX_INTERRUPT_MANAGER__ENABLES 0x00FD 00618 00619 #define VL53LX_INTERRUPT_MANAGER__CLEAR 0x00FE 00620 00621 #define VL53LX_INTERRUPT_MANAGER__STATUS 0x00FF 00622 00623 #define VL53LX_MCU_TO_HOST_BANK__WR_ACCESS_EN 0x0100 00624 00625 #define VL53LX_POWER_MANAGEMENT__GO1_RESET_STATUS 0x0101 00626 00627 #define VL53LX_PAD_STARTUP_MODE__VALUE_RO 0x0102 00628 00629 #define VL53LX_PAD_STARTUP_MODE__VALUE_CTRL 0x0103 00630 00631 #define VL53LX_PLL_PERIOD_US 0x0104 00632 00633 #define VL53LX_PLL_PERIOD_US_3 0x0104 00634 00635 #define VL53LX_PLL_PERIOD_US_2 0x0105 00636 00637 #define VL53LX_PLL_PERIOD_US_1 0x0106 00638 00639 #define VL53LX_PLL_PERIOD_US_0 0x0107 00640 00641 #define VL53LX_INTERRUPT_SCHEDULER__DATA_OUT 0x0108 00642 00643 #define VL53LX_INTERRUPT_SCHEDULER__DATA_OUT_3 0x0108 00644 00645 #define VL53LX_INTERRUPT_SCHEDULER__DATA_OUT_2 0x0109 00646 00647 #define VL53LX_INTERRUPT_SCHEDULER__DATA_OUT_1 0x010A 00648 00649 #define VL53LX_INTERRUPT_SCHEDULER__DATA_OUT_0 0x010B 00650 00651 #define VL53LX_NVM_BIST__COMPLETE 0x010C 00652 00653 #define VL53LX_NVM_BIST__STATUS 0x010D 00654 00655 #define VL53LX_IDENTIFICATION__MODEL_ID 0x010F 00656 00657 #define VL53LX_IDENTIFICATION__MODULE_TYPE 0x0110 00658 00659 #define VL53LX_IDENTIFICATION__REVISION_ID 0x0111 00660 00661 #define VL53LX_IDENTIFICATION__MODULE_ID 0x0112 00662 00663 #define VL53LX_IDENTIFICATION__MODULE_ID_HI 0x0112 00664 00665 #define VL53LX_IDENTIFICATION__MODULE_ID_LO 0x0113 00666 00667 #define VL53LX_ANA_CONFIG__FAST_OSC__TRIM_MAX 0x0114 00668 00669 #define VL53LX_ANA_CONFIG__FAST_OSC__FREQ_SET 0x0115 00670 00671 #define VL53LX_ANA_CONFIG__VCSEL_TRIM 0x0116 00672 00673 #define VL53LX_ANA_CONFIG__VCSEL_SELION 0x0117 00674 00675 #define VL53LX_ANA_CONFIG__VCSEL_SELION_MAX 0x0118 00676 00677 #define VL53LX_PROTECTED_LASER_SAFETY__LOCK_BIT 0x0119 00678 00679 #define VL53LX_LASER_SAFETY__KEY 0x011A 00680 00681 #define VL53LX_LASER_SAFETY__KEY_RO 0x011B 00682 00683 #define VL53LX_LASER_SAFETY__CLIP 0x011C 00684 00685 #define VL53LX_LASER_SAFETY__MULT 0x011D 00686 00687 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_0 0x011E 00688 00689 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_1 0x011F 00690 00691 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_2 0x0120 00692 00693 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_3 0x0121 00694 00695 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_4 0x0122 00696 00697 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_5 0x0123 00698 00699 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_6 0x0124 00700 00701 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_7 0x0125 00702 00703 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_8 0x0126 00704 00705 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_9 0x0127 00706 00707 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_10 0x0128 00708 00709 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_11 0x0129 00710 00711 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_12 0x012A 00712 00713 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_13 0x012B 00714 00715 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_14 0x012C 00716 00717 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_15 0x012D 00718 00719 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_16 0x012E 00720 00721 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_17 0x012F 00722 00723 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_18 0x0130 00724 00725 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_19 0x0131 00726 00727 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_20 0x0132 00728 00729 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_21 0x0133 00730 00731 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_22 0x0134 00732 00733 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_23 0x0135 00734 00735 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_24 0x0136 00736 00737 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_25 0x0137 00738 00739 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_26 0x0138 00740 00741 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_27 0x0139 00742 00743 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_28 0x013A 00744 00745 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_29 0x013B 00746 00747 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_30 0x013C 00748 00749 #define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_31 0x013D 00750 00751 #define VL53LX_ROI_CONFIG__MODE_ROI_CENTRE_SPAD 0x013E 00752 00753 #define VL53LX_ROI_CONFIG__MODE_ROI_XY_SIZE 0x013F 00754 00755 #define VL53LX_GO2_HOST_BANK_ACCESS__OVERRIDE 0x0300 00756 00757 #define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLICAND 0x0400 00758 00759 #define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLICAND_3 0x0400 00760 00761 #define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLICAND_2 0x0401 00762 00763 #define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLICAND_1 0x0402 00764 00765 #define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLICAND_0 0x0403 00766 00767 #define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLIER 0x0404 00768 00769 #define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLIER_3 0x0404 00770 00771 #define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLIER_2 0x0405 00772 00773 #define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLIER_1 0x0406 00774 00775 #define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLIER_0 0x0407 00776 00777 #define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_HI 0x0408 00778 00779 #define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_HI_3 0x0408 00780 00781 #define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_HI_2 0x0409 00782 00783 #define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_HI_1 0x040A 00784 00785 #define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_HI_0 0x040B 00786 00787 #define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_LO 0x040C 00788 00789 #define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_LO_3 0x040C 00790 00791 #define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_LO_2 0x040D 00792 00793 #define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_LO_1 0x040E 00794 00795 #define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_LO_0 0x040F 00796 00797 #define VL53LX_MCU_UTIL_MULTIPLIER__START 0x0410 00798 00799 #define VL53LX_MCU_UTIL_MULTIPLIER__STATUS 0x0411 00800 00801 #define VL53LX_MCU_UTIL_DIVIDER__START 0x0412 00802 00803 #define VL53LX_MCU_UTIL_DIVIDER__STATUS 0x0413 00804 00805 #define VL53LX_MCU_UTIL_DIVIDER__DIVIDEND 0x0414 00806 00807 #define VL53LX_MCU_UTIL_DIVIDER__DIVIDEND_3 0x0414 00808 00809 #define VL53LX_MCU_UTIL_DIVIDER__DIVIDEND_2 0x0415 00810 00811 #define VL53LX_MCU_UTIL_DIVIDER__DIVIDEND_1 0x0416 00812 00813 #define VL53LX_MCU_UTIL_DIVIDER__DIVIDEND_0 0x0417 00814 00815 #define VL53LX_MCU_UTIL_DIVIDER__DIVISOR 0x0418 00816 00817 #define VL53LX_MCU_UTIL_DIVIDER__DIVISOR_3 0x0418 00818 00819 #define VL53LX_MCU_UTIL_DIVIDER__DIVISOR_2 0x0419 00820 00821 #define VL53LX_MCU_UTIL_DIVIDER__DIVISOR_1 0x041A 00822 00823 #define VL53LX_MCU_UTIL_DIVIDER__DIVISOR_0 0x041B 00824 00825 #define VL53LX_MCU_UTIL_DIVIDER__QUOTIENT 0x041C 00826 00827 #define VL53LX_MCU_UTIL_DIVIDER__QUOTIENT_3 0x041C 00828 00829 #define VL53LX_MCU_UTIL_DIVIDER__QUOTIENT_2 0x041D 00830 00831 #define VL53LX_MCU_UTIL_DIVIDER__QUOTIENT_1 0x041E 00832 00833 #define VL53LX_MCU_UTIL_DIVIDER__QUOTIENT_0 0x041F 00834 00835 #define VL53LX_TIMER0__VALUE_IN 0x0420 00836 00837 #define VL53LX_TIMER0__VALUE_IN_3 0x0420 00838 00839 #define VL53LX_TIMER0__VALUE_IN_2 0x0421 00840 00841 #define VL53LX_TIMER0__VALUE_IN_1 0x0422 00842 00843 #define VL53LX_TIMER0__VALUE_IN_0 0x0423 00844 00845 #define VL53LX_TIMER1__VALUE_IN 0x0424 00846 00847 #define VL53LX_TIMER1__VALUE_IN_3 0x0424 00848 00849 #define VL53LX_TIMER1__VALUE_IN_2 0x0425 00850 00851 #define VL53LX_TIMER1__VALUE_IN_1 0x0426 00852 00853 #define VL53LX_TIMER1__VALUE_IN_0 0x0427 00854 00855 #define VL53LX_TIMER0__CTRL 0x0428 00856 00857 #define VL53LX_TIMER1__CTRL 0x0429 00858 00859 #define VL53LX_MCU_GENERAL_PURPOSE__GP_0 0x042C 00860 00861 #define VL53LX_MCU_GENERAL_PURPOSE__GP_1 0x042D 00862 00863 #define VL53LX_MCU_GENERAL_PURPOSE__GP_2 0x042E 00864 00865 #define VL53LX_MCU_GENERAL_PURPOSE__GP_3 0x042F 00866 00867 #define VL53LX_MCU_RANGE_CALC__CONFIG 0x0430 00868 00869 #define VL53LX_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE 0x0432 00870 00871 #define VL53LX_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE_HI 0x0432 00872 00873 #define VL53LX_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE_LO 0x0433 00874 00875 #define VL53LX_MCU_RANGE_CALC__SPARE_4 0x0434 00876 00877 #define VL53LX_MCU_RANGE_CALC__SPARE_4_3 0x0434 00878 00879 #define VL53LX_MCU_RANGE_CALC__SPARE_4_2 0x0435 00880 00881 #define VL53LX_MCU_RANGE_CALC__SPARE_4_1 0x0436 00882 00883 #define VL53LX_MCU_RANGE_CALC__SPARE_4_0 0x0437 00884 00885 #define VL53LX_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC 0x0438 00886 00887 #define VL53LX_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC_HI 0x0438 00888 00889 #define VL53LX_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC_LO 0x0439 00890 00891 #define VL53LX_MCU_RANGE_CALC__ALGO_VCSEL_PERIOD 0x043C 00892 00893 #define VL53LX_MCU_RANGE_CALC__SPARE_5 0x043D 00894 00895 #define VL53LX_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS 0x043E 00896 00897 #define VL53LX_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS_HI 0x043E 00898 00899 #define VL53LX_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS_LO 0x043F 00900 00901 #define VL53LX_MCU_RANGE_CALC__ALGO_ACCUM_PHASE 0x0440 00902 00903 #define VL53LX_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_3 0x0440 00904 00905 #define VL53LX_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_2 0x0441 00906 00907 #define VL53LX_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_1 0x0442 00908 00909 #define VL53LX_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_0 0x0443 00910 00911 #define VL53LX_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS 0x0444 00912 00913 #define VL53LX_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_3 0x0444 00914 00915 #define VL53LX_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_2 0x0445 00916 00917 #define VL53LX_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_1 0x0446 00918 00919 #define VL53LX_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_0 0x0447 00920 00921 #define VL53LX_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS 0x0448 00922 00923 #define VL53LX_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_3 0x0448 00924 00925 #define VL53LX_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_2 0x0449 00926 00927 #define VL53LX_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_1 0x044A 00928 00929 #define VL53LX_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_0 0x044B 00930 00931 #define VL53LX_MCU_RANGE_CALC__SPARE_6 0x044C 00932 00933 #define VL53LX_MCU_RANGE_CALC__SPARE_6_HI 0x044C 00934 00935 #define VL53LX_MCU_RANGE_CALC__SPARE_6_LO 0x044D 00936 00937 #define VL53LX_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD 0x044E 00938 00939 #define VL53LX_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD_HI 0x044E 00940 00941 #define VL53LX_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD_LO 0x044F 00942 00943 #define VL53LX_MCU_RANGE_CALC__NUM_SPADS 0x0450 00944 00945 #define VL53LX_MCU_RANGE_CALC__NUM_SPADS_HI 0x0450 00946 00947 #define VL53LX_MCU_RANGE_CALC__NUM_SPADS_LO 0x0451 00948 00949 #define VL53LX_MCU_RANGE_CALC__PHASE_OUTPUT 0x0452 00950 00951 #define VL53LX_MCU_RANGE_CALC__PHASE_OUTPUT_HI 0x0452 00952 00953 #define VL53LX_MCU_RANGE_CALC__PHASE_OUTPUT_LO 0x0453 00954 00955 #define VL53LX_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS 0x0454 00956 00957 #define VL53LX_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_3 0x0454 00958 00959 #define VL53LX_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_2 0x0455 00960 00961 #define VL53LX_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_1 0x0456 00962 00963 #define VL53LX_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_0 0x0457 00964 00965 #define VL53LX_MCU_RANGE_CALC__SPARE_7 0x0458 00966 00967 #define VL53LX_MCU_RANGE_CALC__SPARE_8 0x0459 00968 00969 #define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS 0x045A 00970 00971 #define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS_HI 0x045A 00972 00973 #define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS_LO 0x045B 00974 00975 #define VL53LX_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS 0x045C 00976 00977 #define VL53LX_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS_HI 0x045C 00978 00979 #define VL53LX_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS_LO 0x045D 00980 00981 #define VL53LX_MCU_RANGE_CALC__AMBIENT_RATE_MCPS 0x045E 00982 00983 #define VL53LX_MCU_RANGE_CALC__AMBIENT_RATE_MCPS_HI 0x045E 00984 00985 #define VL53LX_MCU_RANGE_CALC__AMBIENT_RATE_MCPS_LO 0x045F 00986 00987 #define VL53LX_MCU_RANGE_CALC__XTALK 0x0460 00988 00989 #define VL53LX_MCU_RANGE_CALC__XTALK_HI 0x0460 00990 00991 #define VL53LX_MCU_RANGE_CALC__XTALK_LO 0x0461 00992 00993 #define VL53LX_MCU_RANGE_CALC__CALC_STATUS 0x0462 00994 00995 #define VL53LX_MCU_RANGE_CALC__DEBUG 0x0463 00996 00997 #define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS 0x0464 00998 00999 #define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_HI 0x0464 01000 01001 #define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_LO 0x0465 01002 01003 #define VL53LX_MCU_RANGE_CALC__SPARE_0 0x0468 01004 01005 #define VL53LX_MCU_RANGE_CALC__SPARE_1 0x0469 01006 01007 #define VL53LX_MCU_RANGE_CALC__SPARE_2 0x046A 01008 01009 #define VL53LX_MCU_RANGE_CALC__SPARE_3 0x046B 01010 01011 #define VL53LX_PATCH__CTRL 0x0470 01012 01013 #define VL53LX_PATCH__JMP_ENABLES 0x0472 01014 01015 #define VL53LX_PATCH__JMP_ENABLES_HI 0x0472 01016 01017 #define VL53LX_PATCH__JMP_ENABLES_LO 0x0473 01018 01019 #define VL53LX_PATCH__DATA_ENABLES 0x0474 01020 01021 #define VL53LX_PATCH__DATA_ENABLES_HI 0x0474 01022 01023 #define VL53LX_PATCH__DATA_ENABLES_LO 0x0475 01024 01025 #define VL53LX_PATCH__OFFSET_0 0x0476 01026 01027 #define VL53LX_PATCH__OFFSET_0_HI 0x0476 01028 01029 #define VL53LX_PATCH__OFFSET_0_LO 0x0477 01030 01031 #define VL53LX_PATCH__OFFSET_1 0x0478 01032 01033 #define VL53LX_PATCH__OFFSET_1_HI 0x0478 01034 01035 #define VL53LX_PATCH__OFFSET_1_LO 0x0479 01036 01037 #define VL53LX_PATCH__OFFSET_2 0x047A 01038 01039 #define VL53LX_PATCH__OFFSET_2_HI 0x047A 01040 01041 #define VL53LX_PATCH__OFFSET_2_LO 0x047B 01042 01043 #define VL53LX_PATCH__OFFSET_3 0x047C 01044 01045 #define VL53LX_PATCH__OFFSET_3_HI 0x047C 01046 01047 #define VL53LX_PATCH__OFFSET_3_LO 0x047D 01048 01049 #define VL53LX_PATCH__OFFSET_4 0x047E 01050 01051 #define VL53LX_PATCH__OFFSET_4_HI 0x047E 01052 01053 #define VL53LX_PATCH__OFFSET_4_LO 0x047F 01054 01055 #define VL53LX_PATCH__OFFSET_5 0x0480 01056 01057 #define VL53LX_PATCH__OFFSET_5_HI 0x0480 01058 01059 #define VL53LX_PATCH__OFFSET_5_LO 0x0481 01060 01061 #define VL53LX_PATCH__OFFSET_6 0x0482 01062 01063 #define VL53LX_PATCH__OFFSET_6_HI 0x0482 01064 01065 #define VL53LX_PATCH__OFFSET_6_LO 0x0483 01066 01067 #define VL53LX_PATCH__OFFSET_7 0x0484 01068 01069 #define VL53LX_PATCH__OFFSET_7_HI 0x0484 01070 01071 #define VL53LX_PATCH__OFFSET_7_LO 0x0485 01072 01073 #define VL53LX_PATCH__OFFSET_8 0x0486 01074 01075 #define VL53LX_PATCH__OFFSET_8_HI 0x0486 01076 01077 #define VL53LX_PATCH__OFFSET_8_LO 0x0487 01078 01079 #define VL53LX_PATCH__OFFSET_9 0x0488 01080 01081 #define VL53LX_PATCH__OFFSET_9_HI 0x0488 01082 01083 #define VL53LX_PATCH__OFFSET_9_LO 0x0489 01084 01085 #define VL53LX_PATCH__OFFSET_10 0x048A 01086 01087 #define VL53LX_PATCH__OFFSET_10_HI 0x048A 01088 01089 #define VL53LX_PATCH__OFFSET_10_LO 0x048B 01090 01091 #define VL53LX_PATCH__OFFSET_11 0x048C 01092 01093 #define VL53LX_PATCH__OFFSET_11_HI 0x048C 01094 01095 #define VL53LX_PATCH__OFFSET_11_LO 0x048D 01096 01097 #define VL53LX_PATCH__OFFSET_12 0x048E 01098 01099 #define VL53LX_PATCH__OFFSET_12_HI 0x048E 01100 01101 #define VL53LX_PATCH__OFFSET_12_LO 0x048F 01102 01103 #define VL53LX_PATCH__OFFSET_13 0x0490 01104 01105 #define VL53LX_PATCH__OFFSET_13_HI 0x0490 01106 01107 #define VL53LX_PATCH__OFFSET_13_LO 0x0491 01108 01109 #define VL53LX_PATCH__OFFSET_14 0x0492 01110 01111 #define VL53LX_PATCH__OFFSET_14_HI 0x0492 01112 01113 #define VL53LX_PATCH__OFFSET_14_LO 0x0493 01114 01115 #define VL53LX_PATCH__OFFSET_15 0x0494 01116 01117 #define VL53LX_PATCH__OFFSET_15_HI 0x0494 01118 01119 #define VL53LX_PATCH__OFFSET_15_LO 0x0495 01120 01121 #define VL53LX_PATCH__ADDRESS_0 0x0496 01122 01123 #define VL53LX_PATCH__ADDRESS_0_HI 0x0496 01124 01125 #define VL53LX_PATCH__ADDRESS_0_LO 0x0497 01126 01127 #define VL53LX_PATCH__ADDRESS_1 0x0498 01128 01129 #define VL53LX_PATCH__ADDRESS_1_HI 0x0498 01130 01131 #define VL53LX_PATCH__ADDRESS_1_LO 0x0499 01132 01133 #define VL53LX_PATCH__ADDRESS_2 0x049A 01134 01135 #define VL53LX_PATCH__ADDRESS_2_HI 0x049A 01136 01137 #define VL53LX_PATCH__ADDRESS_2_LO 0x049B 01138 01139 #define VL53LX_PATCH__ADDRESS_3 0x049C 01140 01141 #define VL53LX_PATCH__ADDRESS_3_HI 0x049C 01142 01143 #define VL53LX_PATCH__ADDRESS_3_LO 0x049D 01144 01145 #define VL53LX_PATCH__ADDRESS_4 0x049E 01146 01147 #define VL53LX_PATCH__ADDRESS_4_HI 0x049E 01148 01149 #define VL53LX_PATCH__ADDRESS_4_LO 0x049F 01150 01151 #define VL53LX_PATCH__ADDRESS_5 0x04A0 01152 01153 #define VL53LX_PATCH__ADDRESS_5_HI 0x04A0 01154 01155 #define VL53LX_PATCH__ADDRESS_5_LO 0x04A1 01156 01157 #define VL53LX_PATCH__ADDRESS_6 0x04A2 01158 01159 #define VL53LX_PATCH__ADDRESS_6_HI 0x04A2 01160 01161 #define VL53LX_PATCH__ADDRESS_6_LO 0x04A3 01162 01163 #define VL53LX_PATCH__ADDRESS_7 0x04A4 01164 01165 #define VL53LX_PATCH__ADDRESS_7_HI 0x04A4 01166 01167 #define VL53LX_PATCH__ADDRESS_7_LO 0x04A5 01168 01169 #define VL53LX_PATCH__ADDRESS_8 0x04A6 01170 01171 #define VL53LX_PATCH__ADDRESS_8_HI 0x04A6 01172 01173 #define VL53LX_PATCH__ADDRESS_8_LO 0x04A7 01174 01175 #define VL53LX_PATCH__ADDRESS_9 0x04A8 01176 01177 #define VL53LX_PATCH__ADDRESS_9_HI 0x04A8 01178 01179 #define VL53LX_PATCH__ADDRESS_9_LO 0x04A9 01180 01181 #define VL53LX_PATCH__ADDRESS_10 0x04AA 01182 01183 #define VL53LX_PATCH__ADDRESS_10_HI 0x04AA 01184 01185 #define VL53LX_PATCH__ADDRESS_10_LO 0x04AB 01186 01187 #define VL53LX_PATCH__ADDRESS_11 0x04AC 01188 01189 #define VL53LX_PATCH__ADDRESS_11_HI 0x04AC 01190 01191 #define VL53LX_PATCH__ADDRESS_11_LO 0x04AD 01192 01193 #define VL53LX_PATCH__ADDRESS_12 0x04AE 01194 01195 #define VL53LX_PATCH__ADDRESS_12_HI 0x04AE 01196 01197 #define VL53LX_PATCH__ADDRESS_12_LO 0x04AF 01198 01199 #define VL53LX_PATCH__ADDRESS_13 0x04B0 01200 01201 #define VL53LX_PATCH__ADDRESS_13_HI 0x04B0 01202 01203 #define VL53LX_PATCH__ADDRESS_13_LO 0x04B1 01204 01205 #define VL53LX_PATCH__ADDRESS_14 0x04B2 01206 01207 #define VL53LX_PATCH__ADDRESS_14_HI 0x04B2 01208 01209 #define VL53LX_PATCH__ADDRESS_14_LO 0x04B3 01210 01211 #define VL53LX_PATCH__ADDRESS_15 0x04B4 01212 01213 #define VL53LX_PATCH__ADDRESS_15_HI 0x04B4 01214 01215 #define VL53LX_PATCH__ADDRESS_15_LO 0x04B5 01216 01217 #define VL53LX_SPI_ASYNC_MUX__CTRL 0x04C0 01218 01219 #define VL53LX_CLK__CONFIG 0x04C4 01220 01221 #define VL53LX_GPIO_LV_MUX__CTRL 0x04CC 01222 01223 #define VL53LX_GPIO_LV_PAD__CTRL 0x04CD 01224 01225 #define VL53LX_PAD_I2C_LV__CONFIG 0x04D0 01226 01227 #define VL53LX_PAD_STARTUP_MODE__VALUE_RO_GO1 0x04D4 01228 01229 #define VL53LX_HOST_IF__STATUS_GO1 0x04D5 01230 01231 #define VL53LX_MCU_CLK_GATING__CTRL 0x04D8 01232 01233 #define VL53LX_TEST__BIST_ROM_CTRL 0x04E0 01234 01235 #define VL53LX_TEST__BIST_ROM_RESULT 0x04E1 01236 01237 #define VL53LX_TEST__BIST_ROM_MCU_SIG 0x04E2 01238 01239 #define VL53LX_TEST__BIST_ROM_MCU_SIG_HI 0x04E2 01240 01241 #define VL53LX_TEST__BIST_ROM_MCU_SIG_LO 0x04E3 01242 01243 #define VL53LX_TEST__BIST_RAM_CTRL 0x04E4 01244 01245 #define VL53LX_TEST__BIST_RAM_RESULT 0x04E5 01246 01247 #define VL53LX_TEST__TMC 0x04E8 01248 01249 #define VL53LX_TEST__PLL_BIST_MIN_THRESHOLD 0x04F0 01250 01251 #define VL53LX_TEST__PLL_BIST_MIN_THRESHOLD_HI 0x04F0 01252 01253 #define VL53LX_TEST__PLL_BIST_MIN_THRESHOLD_LO 0x04F1 01254 01255 #define VL53LX_TEST__PLL_BIST_MAX_THRESHOLD 0x04F2 01256 01257 #define VL53LX_TEST__PLL_BIST_MAX_THRESHOLD_HI 0x04F2 01258 01259 #define VL53LX_TEST__PLL_BIST_MAX_THRESHOLD_LO 0x04F3 01260 01261 #define VL53LX_TEST__PLL_BIST_COUNT_OUT 0x04F4 01262 01263 #define VL53LX_TEST__PLL_BIST_COUNT_OUT_HI 0x04F4 01264 01265 #define VL53LX_TEST__PLL_BIST_COUNT_OUT_LO 0x04F5 01266 01267 #define VL53LX_TEST__PLL_BIST_GONOGO 0x04F6 01268 01269 #define VL53LX_TEST__PLL_BIST_CTRL 0x04F7 01270 01271 #define VL53LX_RANGING_CORE__DEVICE_ID 0x0680 01272 01273 #define VL53LX_RANGING_CORE__REVISION_ID 0x0681 01274 01275 #define VL53LX_RANGING_CORE__CLK_CTRL1 0x0683 01276 01277 #define VL53LX_RANGING_CORE__CLK_CTRL2 0x0684 01278 01279 #define VL53LX_RANGING_CORE__WOI_1 0x0685 01280 01281 #define VL53LX_RANGING_CORE__WOI_REF_1 0x0686 01282 01283 #define VL53LX_RANGING_CORE__START_RANGING 0x0687 01284 01285 #define VL53LX_RANGING_CORE__LOW_LIMIT_1 0x0690 01286 01287 #define VL53LX_RANGING_CORE__HIGH_LIMIT_1 0x0691 01288 01289 #define VL53LX_RANGING_CORE__LOW_LIMIT_REF_1 0x0692 01290 01291 #define VL53LX_RANGING_CORE__HIGH_LIMIT_REF_1 0x0693 01292 01293 #define VL53LX_RANGING_CORE__QUANTIFIER_1_MSB 0x0694 01294 01295 #define VL53LX_RANGING_CORE__QUANTIFIER_1_LSB 0x0695 01296 01297 #define VL53LX_RANGING_CORE__QUANTIFIER_REF_1_MSB 0x0696 01298 01299 #define VL53LX_RANGING_CORE__QUANTIFIER_REF_1_LSB 0x0697 01300 01301 #define VL53LX_RANGING_CORE__AMBIENT_OFFSET_1_MSB 0x0698 01302 01303 #define VL53LX_RANGING_CORE__AMBIENT_OFFSET_1_LSB 0x0699 01304 01305 #define VL53LX_RANGING_CORE__AMBIENT_OFFSET_REF_1_MSB 0x069A 01306 01307 #define VL53LX_RANGING_CORE__AMBIENT_OFFSET_REF_1_LSB 0x069B 01308 01309 #define VL53LX_RANGING_CORE__FILTER_STRENGTH_1 0x069C 01310 01311 #define VL53LX_RANGING_CORE__FILTER_STRENGTH_REF_1 0x069D 01312 01313 #define VL53LX_RANGING_CORE__SIGNAL_EVENT_LIMIT_1_MSB 0x069E 01314 01315 #define VL53LX_RANGING_CORE__SIGNAL_EVENT_LIMIT_1_LSB 0x069F 01316 01317 #define VL53LX_RANGING_CORE__SIGNAL_EVENT_LIMIT_REF_1_MSB 0x06A0 01318 01319 #define VL53LX_RANGING_CORE__SIGNAL_EVENT_LIMIT_REF_1_LSB 0x06A1 01320 01321 #define VL53LX_RANGING_CORE__TIMEOUT_OVERALL_PERIODS_MSB 0x06A4 01322 01323 #define VL53LX_RANGING_CORE__TIMEOUT_OVERALL_PERIODS_LSB 0x06A5 01324 01325 #define VL53LX_RANGING_CORE__INVERT_HW 0x06A6 01326 01327 #define VL53LX_RANGING_CORE__FORCE_HW 0x06A7 01328 01329 #define VL53LX_RANGING_CORE__STATIC_HW_VALUE 0x06A8 01330 01331 #define VL53LX_RANGING_CORE__FORCE_CONTINUOUS_AMBIENT 0x06A9 01332 01333 #define VL53LX_RANGING_CORE__TEST_PHASE_SELECT_TO_FILTER 0x06AA 01334 01335 #define VL53LX_RANGING_CORE__TEST_PHASE_SELECT_TO_TIMING_GEN 0x06AB 01336 01337 #define VL53LX_RANGING_CORE__INITIAL_PHASE_VALUE_1 0x06AC 01338 01339 #define VL53LX_RANGING_CORE__INITIAL_PHASE_VALUE_REF_1 0x06AD 01340 01341 #define VL53LX_RANGING_CORE__FORCE_UP_IN 0x06AE 01342 01343 #define VL53LX_RANGING_CORE__FORCE_DN_IN 0x06AF 01344 01345 #define VL53LX_RANGING_CORE__STATIC_UP_VALUE_1 0x06B0 01346 01347 #define VL53LX_RANGING_CORE__STATIC_UP_VALUE_REF_1 0x06B1 01348 01349 #define VL53LX_RANGING_CORE__STATIC_DN_VALUE_1 0x06B2 01350 01351 #define VL53LX_RANGING_CORE__STATIC_DN_VALUE_REF_1 0x06B3 01352 01353 #define VL53LX_RANGING_CORE__MONITOR_UP_DN 0x06B4 01354 01355 #define VL53LX_RANGING_CORE__INVERT_UP_DN 0x06B5 01356 01357 #define VL53LX_RANGING_CORE__CPUMP_1 0x06B6 01358 01359 #define VL53LX_RANGING_CORE__CPUMP_2 0x06B7 01360 01361 #define VL53LX_RANGING_CORE__CPUMP_3 0x06B8 01362 01363 #define VL53LX_RANGING_CORE__OSC_1 0x06B9 01364 01365 #define VL53LX_RANGING_CORE__PLL_1 0x06BB 01366 01367 #define VL53LX_RANGING_CORE__PLL_2 0x06BC 01368 01369 #define VL53LX_RANGING_CORE__REFERENCE_1 0x06BD 01370 01371 #define VL53LX_RANGING_CORE__REFERENCE_3 0x06BF 01372 01373 #define VL53LX_RANGING_CORE__REFERENCE_4 0x06C0 01374 01375 #define VL53LX_RANGING_CORE__REFERENCE_5 0x06C1 01376 01377 #define VL53LX_RANGING_CORE__REGAVDD1V2 0x06C3 01378 01379 #define VL53LX_RANGING_CORE__CALIB_1 0x06C4 01380 01381 #define VL53LX_RANGING_CORE__CALIB_2 0x06C5 01382 01383 #define VL53LX_RANGING_CORE__CALIB_3 0x06C6 01384 01385 #define VL53LX_RANGING_CORE__TST_MUX_SEL1 0x06C9 01386 01387 #define VL53LX_RANGING_CORE__TST_MUX_SEL2 0x06CA 01388 01389 #define VL53LX_RANGING_CORE__TST_MUX 0x06CB 01390 01391 #define VL53LX_RANGING_CORE__GPIO_OUT_TESTMUX 0x06CC 01392 01393 #define VL53LX_RANGING_CORE__CUSTOM_FE 0x06CD 01394 01395 #define VL53LX_RANGING_CORE__CUSTOM_FE_2 0x06CE 01396 01397 #define VL53LX_RANGING_CORE__SPAD_READOUT 0x06CF 01398 01399 #define VL53LX_RANGING_CORE__SPAD_READOUT_1 0x06D0 01400 01401 #define VL53LX_RANGING_CORE__SPAD_READOUT_2 0x06D1 01402 01403 #define VL53LX_RANGING_CORE__SPAD_PS 0x06D2 01404 01405 #define VL53LX_RANGING_CORE__LASER_SAFETY_2 0x06D4 01406 01407 #define VL53LX_RANGING_CORE__NVM_CTRL__MODE 0x0780 01408 01409 #define VL53LX_RANGING_CORE__NVM_CTRL__PDN 0x0781 01410 01411 #define VL53LX_RANGING_CORE__NVM_CTRL__PROGN 0x0782 01412 01413 #define VL53LX_RANGING_CORE__NVM_CTRL__READN 0x0783 01414 01415 #define VL53LX_RANGING_CORE__NVM_CTRL__PULSE_WIDTH_MSB 0x0784 01416 01417 #define VL53LX_RANGING_CORE__NVM_CTRL__PULSE_WIDTH_LSB 0x0785 01418 01419 #define VL53LX_RANGING_CORE__NVM_CTRL__HV_RISE_MSB 0x0786 01420 01421 #define VL53LX_RANGING_CORE__NVM_CTRL__HV_RISE_LSB 0x0787 01422 01423 #define VL53LX_RANGING_CORE__NVM_CTRL__HV_FALL_MSB 0x0788 01424 01425 #define VL53LX_RANGING_CORE__NVM_CTRL__HV_FALL_LSB 0x0789 01426 01427 #define VL53LX_RANGING_CORE__NVM_CTRL__TST 0x078A 01428 01429 #define VL53LX_RANGING_CORE__NVM_CTRL__TESTREAD 0x078B 01430 01431 #define VL53LX_RANGING_CORE__NVM_CTRL__DATAIN_MMM 0x078C 01432 01433 #define VL53LX_RANGING_CORE__NVM_CTRL__DATAIN_LMM 0x078D 01434 01435 #define VL53LX_RANGING_CORE__NVM_CTRL__DATAIN_LLM 0x078E 01436 01437 #define VL53LX_RANGING_CORE__NVM_CTRL__DATAIN_LLL 0x078F 01438 01439 #define VL53LX_RANGING_CORE__NVM_CTRL__DATAOUT_MMM 0x0790 01440 01441 #define VL53LX_RANGING_CORE__NVM_CTRL__DATAOUT_LMM 0x0791 01442 01443 #define VL53LX_RANGING_CORE__NVM_CTRL__DATAOUT_LLM 0x0792 01444 01445 #define VL53LX_RANGING_CORE__NVM_CTRL__DATAOUT_LLL 0x0793 01446 01447 #define VL53LX_RANGING_CORE__NVM_CTRL__ADDR 0x0794 01448 01449 #define VL53LX_RANGING_CORE__NVM_CTRL__DATAOUT_ECC 0x0795 01450 01451 #define VL53LX_RANGING_CORE__RET_SPAD_EN_0 0x0796 01452 01453 #define VL53LX_RANGING_CORE__RET_SPAD_EN_1 0x0797 01454 01455 #define VL53LX_RANGING_CORE__RET_SPAD_EN_2 0x0798 01456 01457 #define VL53LX_RANGING_CORE__RET_SPAD_EN_3 0x0799 01458 01459 #define VL53LX_RANGING_CORE__RET_SPAD_EN_4 0x079A 01460 01461 #define VL53LX_RANGING_CORE__RET_SPAD_EN_5 0x079B 01462 01463 #define VL53LX_RANGING_CORE__RET_SPAD_EN_6 0x079C 01464 01465 #define VL53LX_RANGING_CORE__RET_SPAD_EN_7 0x079D 01466 01467 #define VL53LX_RANGING_CORE__RET_SPAD_EN_8 0x079E 01468 01469 #define VL53LX_RANGING_CORE__RET_SPAD_EN_9 0x079F 01470 01471 #define VL53LX_RANGING_CORE__RET_SPAD_EN_10 0x07A0 01472 01473 #define VL53LX_RANGING_CORE__RET_SPAD_EN_11 0x07A1 01474 01475 #define VL53LX_RANGING_CORE__RET_SPAD_EN_12 0x07A2 01476 01477 #define VL53LX_RANGING_CORE__RET_SPAD_EN_13 0x07A3 01478 01479 #define VL53LX_RANGING_CORE__RET_SPAD_EN_14 0x07A4 01480 01481 #define VL53LX_RANGING_CORE__RET_SPAD_EN_15 0x07A5 01482 01483 #define VL53LX_RANGING_CORE__RET_SPAD_EN_16 0x07A6 01484 01485 #define VL53LX_RANGING_CORE__RET_SPAD_EN_17 0x07A7 01486 01487 #define VL53LX_RANGING_CORE__SPAD_SHIFT_EN 0x07BA 01488 01489 #define VL53LX_RANGING_CORE__SPAD_DISABLE_CTRL 0x07BB 01490 01491 #define VL53LX_RANGING_CORE__SPAD_EN_SHIFT_OUT_DEBUG 0x07BC 01492 01493 #define VL53LX_RANGING_CORE__SPI_MODE 0x07BD 01494 01495 #define VL53LX_RANGING_CORE__GPIO_DIR 0x07BE 01496 01497 #define VL53LX_RANGING_CORE__VCSEL_PERIOD 0x0880 01498 01499 #define VL53LX_RANGING_CORE__VCSEL_START 0x0881 01500 01501 #define VL53LX_RANGING_CORE__VCSEL_STOP 0x0882 01502 01503 #define VL53LX_RANGING_CORE__VCSEL_1 0x0885 01504 01505 #define VL53LX_RANGING_CORE__VCSEL_STATUS 0x088D 01506 01507 #define VL53LX_RANGING_CORE__STATUS 0x0980 01508 01509 #define VL53LX_RANGING_CORE__LASER_CONTINUITY_STATE 0x0981 01510 01511 #define VL53LX_RANGING_CORE__RANGE_1_MMM 0x0982 01512 01513 #define VL53LX_RANGING_CORE__RANGE_1_LMM 0x0983 01514 01515 #define VL53LX_RANGING_CORE__RANGE_1_LLM 0x0984 01516 01517 #define VL53LX_RANGING_CORE__RANGE_1_LLL 0x0985 01518 01519 #define VL53LX_RANGING_CORE__RANGE_REF_1_MMM 0x0986 01520 01521 #define VL53LX_RANGING_CORE__RANGE_REF_1_LMM 0x0987 01522 01523 #define VL53LX_RANGING_CORE__RANGE_REF_1_LLM 0x0988 01524 01525 #define VL53LX_RANGING_CORE__RANGE_REF_1_LLL 0x0989 01526 01527 #define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_MMM 0x098A 01528 01529 #define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LMM 0x098B 01530 01531 #define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LLM 0x098C 01532 01533 #define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LLL 0x098D 01534 01535 #define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_1_MMM 0x098E 01536 01537 #define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LMM 0x098F 01538 01539 #define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LLM 0x0990 01540 01541 #define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LLL 0x0991 01542 01543 #define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_MMM 0x0992 01544 01545 #define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LMM 0x0993 01546 01547 #define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LLM 0x0994 01548 01549 #define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LLL 0x0995 01550 01551 #define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_MM 0x0996 01552 01553 #define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_LM 0x0997 01554 01555 #define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_LL 0x0998 01556 01557 #define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_MM 0x0999 01558 01559 #define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_LM 0x099A 01560 01561 #define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_LL 0x099B 01562 01563 #define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_MMM 0x099C 01564 01565 #define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LMM 0x099D 01566 01567 #define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LLM 0x099E 01568 01569 #define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LLL 0x099F 01570 01571 #define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_MMM 0x09A0 01572 01573 #define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LMM 0x09A1 01574 01575 #define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LLM 0x09A2 01576 01577 #define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LLL 0x09A3 01578 01579 #define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_MMM 0x09A4 01580 01581 #define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LMM 0x09A5 01582 01583 #define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LLM 0x09A6 01584 01585 #define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LLL 0x09A7 01586 01587 #define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_MM 0x09A8 01588 01589 #define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_LM 0x09A9 01590 01591 #define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_LL 0x09AA 01592 01593 #define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_REF_MM 0x09AB 01594 01595 #define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_REF_LM 0x09AC 01596 01597 #define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_REF_LL 0x09AD 01598 01599 #define VL53LX_RANGING_CORE__GPIO_CONFIG__A0 0x0A00 01600 01601 #define VL53LX_RANGING_CORE__RESET_CONTROL__A0 0x0A01 01602 01603 #define VL53LX_RANGING_CORE__INTR_MANAGER__A0 0x0A02 01604 01605 #define VL53LX_RANGING_CORE__POWER_FSM_TIME_OSC__A0 0x0A06 01606 01607 #define VL53LX_RANGING_CORE__VCSEL_ATEST__A0 0x0A07 01608 01609 #define VL53LX_RANGING_CORE__VCSEL_PERIOD_CLIPPED__A0 0x0A08 01610 01611 #define VL53LX_RANGING_CORE__VCSEL_STOP_CLIPPED__A0 0x0A09 01612 01613 #define VL53LX_RANGING_CORE__CALIB_2__A0 0x0A0A 01614 01615 #define VL53LX_RANGING_CORE__STOP_CONDITION__A0 0x0A0B 01616 01617 #define VL53LX_RANGING_CORE__STATUS_RESET__A0 0x0A0C 01618 01619 #define VL53LX_RANGING_CORE__READOUT_CFG__A0 0x0A0D 01620 01621 #define VL53LX_RANGING_CORE__WINDOW_SETTING__A0 0x0A0E 01622 01623 #define VL53LX_RANGING_CORE__VCSEL_DELAY__A0 0x0A1A 01624 01625 #define VL53LX_RANGING_CORE__REFERENCE_2__A0 0x0A1B 01626 01627 #define VL53LX_RANGING_CORE__REGAVDD1V2__A0 0x0A1D 01628 01629 #define VL53LX_RANGING_CORE__TST_MUX__A0 0x0A1F 01630 01631 #define VL53LX_RANGING_CORE__CUSTOM_FE_2__A0 0x0A20 01632 01633 #define VL53LX_RANGING_CORE__SPAD_READOUT__A0 0x0A21 01634 01635 #define VL53LX_RANGING_CORE__CPUMP_1__A0 0x0A22 01636 01637 #define VL53LX_RANGING_CORE__SPARE_REGISTER__A0 0x0A23 01638 01639 #define VL53LX_RANGING_CORE__VCSEL_CONT_STAGE5_BYPASS__A0 0x0A24 01640 01641 #define VL53LX_RANGING_CORE__RET_SPAD_EN_18 0x0A25 01642 01643 #define VL53LX_RANGING_CORE__RET_SPAD_EN_19 0x0A26 01644 01645 #define VL53LX_RANGING_CORE__RET_SPAD_EN_20 0x0A27 01646 01647 #define VL53LX_RANGING_CORE__RET_SPAD_EN_21 0x0A28 01648 01649 #define VL53LX_RANGING_CORE__RET_SPAD_EN_22 0x0A29 01650 01651 #define VL53LX_RANGING_CORE__RET_SPAD_EN_23 0x0A2A 01652 01653 #define VL53LX_RANGING_CORE__RET_SPAD_EN_24 0x0A2B 01654 01655 #define VL53LX_RANGING_CORE__RET_SPAD_EN_25 0x0A2C 01656 01657 #define VL53LX_RANGING_CORE__RET_SPAD_EN_26 0x0A2D 01658 01659 #define VL53LX_RANGING_CORE__RET_SPAD_EN_27 0x0A2E 01660 01661 #define VL53LX_RANGING_CORE__RET_SPAD_EN_28 0x0A2F 01662 01663 #define VL53LX_RANGING_CORE__RET_SPAD_EN_29 0x0A30 01664 01665 #define VL53LX_RANGING_CORE__RET_SPAD_EN_30 0x0A31 01666 01667 #define VL53LX_RANGING_CORE__RET_SPAD_EN_31 0x0A32 01668 01669 #define VL53LX_RANGING_CORE__REF_SPAD_EN_0__EWOK 0x0A33 01670 01671 #define VL53LX_RANGING_CORE__REF_SPAD_EN_1__EWOK 0x0A34 01672 01673 #define VL53LX_RANGING_CORE__REF_SPAD_EN_2__EWOK 0x0A35 01674 01675 #define VL53LX_RANGING_CORE__REF_SPAD_EN_3__EWOK 0x0A36 01676 01677 #define VL53LX_RANGING_CORE__REF_SPAD_EN_4__EWOK 0x0A37 01678 01679 #define VL53LX_RANGING_CORE__REF_SPAD_EN_5__EWOK 0x0A38 01680 01681 #define VL53LX_RANGING_CORE__REF_EN_START_SELECT 0x0A39 01682 01683 #define VL53LX_RANGING_CORE__REGDVDD1V2_ATEST__EWOK 0x0A41 01684 01685 #define VL53LX_SOFT_RESET_GO1 0x0B00 01686 01687 #define VL53LX_PRIVATE__PATCH_BASE_ADDR_RSLV 0x0E00 01688 01689 #define VL53LX_PREV_SHADOW_RESULT__INTERRUPT_STATUS 0x0ED0 01690 01691 #define VL53LX_PREV_SHADOW_RESULT__RANGE_STATUS 0x0ED1 01692 01693 #define VL53LX_PREV_SHADOW_RESULT__REPORT_STATUS 0x0ED2 01694 01695 #define VL53LX_PREV_SHADOW_RESULT__STREAM_COUNT 0x0ED3 01696 01697 #define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x0ED4 01698 01699 #define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0ED4 01700 01701 #define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0ED5 01702 01703 #define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x0ED6 01704 01705 #define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0ED6 01706 01707 #define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0ED7 01708 01709 #define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0ED8 01710 01711 #define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0ED8 01712 01713 #define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0ED9 01714 01715 #define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD0 0x0EDA 01716 01717 #define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD0_HI 0x0EDA 01718 01719 #define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD0_LO 0x0EDB 01720 01721 #define VL53LX_PREV_SHADOW_RESULT__PHASE_SD0 0x0EDC 01722 01723 #define VL53LX_PREV_SHADOW_RESULT__PHASE_SD0_HI 0x0EDC 01724 01725 #define VL53LX_PREV_SHADOW_RESULT__PHASE_SD0_LO 0x0EDD 01726 01727 #define VL53LX_PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0EDE 01728 01729 #define VL53LX_PREV__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0EDE 01730 01731 #define VL53LX_PREV__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0EDF 01732 01733 #define VL53LX_PREV__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0EE0 01734 01735 #define VL53LX_PPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0EE0 01736 01737 #define VL53LX_PPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0EE1 01738 01739 #define VL53LX_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0EE2 01740 01741 #define VL53LX_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0EE2 01742 01743 #define VL53LX_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0EE3 01744 01745 #define VL53LX_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0EE4 01746 01747 #define VL53LX_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0EE4 01748 01749 #define VL53LX_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0EE5 01750 01751 #define VL53LX_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x0EE6 01752 01753 #define VL53LX_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0EE6 01754 01755 #define VL53LX_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0EE7 01756 01757 #define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x0EE8 01758 01759 #define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x0EE8 01760 01761 #define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x0EE9 01762 01763 #define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x0EEA 01764 01765 #define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x0EEA 01766 01767 #define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x0EEB 01768 01769 #define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x0EEC 01770 01771 #define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x0EEC 01772 01773 #define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x0EED 01774 01775 #define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD1 0x0EEE 01776 01777 #define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD1_HI 0x0EEE 01778 01779 #define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD1_LO 0x0EEF 01780 01781 #define VL53LX_PREV_SHADOW_RESULT__PHASE_SD1 0x0EF0 01782 01783 #define VL53LX_PREV_SHADOW_RESULT__PHASE_SD1_HI 0x0EF0 01784 01785 #define VL53LX_PREV_SHADOW_RESULT__PHASE_SD1_LO 0x0EF1 01786 01787 #define VL53LX_PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x0EF2 01788 01789 #define VL53LX_PFINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x0EF2 01790 01791 #define VL53LX_PFINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x0EF3 01792 01793 #define VL53LX_PREV_SHADOW_RESULT__SPARE_0_SD1 0x0EF4 01794 01795 #define VL53LX_PREV_SHADOW_RESULT__SPARE_0_SD1_HI 0x0EF4 01796 01797 #define VL53LX_PREV_SHADOW_RESULT__SPARE_0_SD1_LO 0x0EF5 01798 01799 #define VL53LX_PREV_SHADOW_RESULT__SPARE_1_SD1 0x0EF6 01800 01801 #define VL53LX_PREV_SHADOW_RESULT__SPARE_1_SD1_HI 0x0EF6 01802 01803 #define VL53LX_PREV_SHADOW_RESULT__SPARE_1_SD1_LO 0x0EF7 01804 01805 #define VL53LX_PREV_SHADOW_RESULT__SPARE_2_SD1 0x0EF8 01806 01807 #define VL53LX_PREV_SHADOW_RESULT__SPARE_2_SD1_HI 0x0EF8 01808 01809 #define VL53LX_PREV_SHADOW_RESULT__SPARE_2_SD1_LO 0x0EF9 01810 01811 #define VL53LX_PREV_SHADOW_RESULT__SPARE_3_SD1 0x0EFA 01812 01813 #define VL53LX_PREV_SHADOW_RESULT__SPARE_3_SD1_HI 0x0EFA 01814 01815 #define VL53LX_PREV_SHADOW_RESULT__SPARE_3_SD1_LO 0x0EFB 01816 01817 #define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x0EFC 01818 01819 #define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x0EFC 01820 01821 #define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x0EFD 01822 01823 #define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x0EFE 01824 01825 #define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x0EFF 01826 01827 #define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x0F00 01828 01829 #define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x0F00 01830 01831 #define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x0F01 01832 01833 #define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x0F02 01834 01835 #define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x0F03 01836 01837 #define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x0F04 01838 01839 #define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x0F04 01840 01841 #define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x0F05 01842 01843 #define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x0F06 01844 01845 #define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x0F07 01846 01847 #define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x0F08 01848 01849 #define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x0F08 01850 01851 #define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x0F09 01852 01853 #define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x0F0A 01854 01855 #define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x0F0B 01856 01857 #define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x0F0C 01858 01859 #define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x0F0C 01860 01861 #define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x0F0D 01862 01863 #define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x0F0E 01864 01865 #define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x0F0F 01866 01867 #define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x0F10 01868 01869 #define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x0F10 01870 01871 #define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x0F11 01872 01873 #define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x0F12 01874 01875 #define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x0F13 01876 01877 #define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x0F14 01878 01879 #define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x0F14 01880 01881 #define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x0F15 01882 01883 #define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x0F16 01884 01885 #define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x0F17 01886 01887 #define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x0F18 01888 01889 #define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x0F18 01890 01891 #define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x0F19 01892 01893 #define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x0F1A 01894 01895 #define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x0F1B 01896 01897 #define VL53LX_PREV_SHADOW_RESULT_CORE__SPARE_0 0x0F1C 01898 01899 #define VL53LX_RESULT__DEBUG_STATUS 0x0F20 01900 01901 #define VL53LX_RESULT__DEBUG_STAGE 0x0F21 01902 01903 #define VL53LX_GPH__SYSTEM__THRESH_RATE_HIGH 0x0F24 01904 01905 #define VL53LX_GPH__SYSTEM__THRESH_RATE_HIGH_HI 0x0F24 01906 01907 #define VL53LX_GPH__SYSTEM__THRESH_RATE_HIGH_LO 0x0F25 01908 01909 #define VL53LX_GPH__SYSTEM__THRESH_RATE_LOW 0x0F26 01910 01911 #define VL53LX_GPH__SYSTEM__THRESH_RATE_LOW_HI 0x0F26 01912 01913 #define VL53LX_GPH__SYSTEM__THRESH_RATE_LOW_LO 0x0F27 01914 01915 #define VL53LX_GPH__SYSTEM__INTERRUPT_CONFIG_GPIO 0x0F28 01916 01917 #define VL53LX_GPH__DSS_CONFIG__ROI_MODE_CONTROL 0x0F2F 01918 01919 #define VL53LX_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT 0x0F30 01920 01921 #define VL53LX_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_HI 0x0F30 01922 01923 #define VL53LX_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_LO 0x0F31 01924 01925 #define VL53LX_GPH__DSS_CONFIG__MANUAL_BLOCK_SELECT 0x0F32 01926 01927 #define VL53LX_GPH__DSS_CONFIG__MAX_SPADS_LIMIT 0x0F33 01928 01929 #define VL53LX_GPH__DSS_CONFIG__MIN_SPADS_LIMIT 0x0F34 01930 01931 #define VL53LX_GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI 0x0F36 01932 01933 #define VL53LX_GPH__MM_CONFIG__TIMEOUT_MACROP_A_LO 0x0F37 01934 01935 #define VL53LX_GPH__MM_CONFIG__TIMEOUT_MACROP_B_HI 0x0F38 01936 01937 #define VL53LX_GPH__MM_CONFIG__TIMEOUT_MACROP_B_LO 0x0F39 01938 01939 #define VL53LX_GPH__RANGE_CONFIG__TIMEOUT_MACROP_A_HI 0x0F3A 01940 01941 #define VL53LX_GPH__RANGE_CONFIG__TIMEOUT_MACROP_A_LO 0x0F3B 01942 01943 #define VL53LX_GPH__RANGE_CONFIG__VCSEL_PERIOD_A 0x0F3C 01944 01945 #define VL53LX_GPH__RANGE_CONFIG__VCSEL_PERIOD_B 0x0F3D 01946 01947 #define VL53LX_GPH__RANGE_CONFIG__TIMEOUT_MACROP_B_HI 0x0F3E 01948 01949 #define VL53LX_GPH__RANGE_CONFIG__TIMEOUT_MACROP_B_LO 0x0F3F 01950 01951 #define VL53LX_GPH__RANGE_CONFIG__SIGMA_THRESH 0x0F40 01952 01953 #define VL53LX_GPH__RANGE_CONFIG__SIGMA_THRESH_HI 0x0F40 01954 01955 #define VL53LX_GPH__RANGE_CONFIG__SIGMA_THRESH_LO 0x0F41 01956 01957 #define VL53LX_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS 0x0F42 01958 01959 #define VL53LX_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI 0x0F42 01960 01961 #define VL53LX_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO 0x0F43 01962 01963 #define VL53LX_GPH__RANGE_CONFIG__VALID_PHASE_LOW 0x0F44 01964 01965 #define VL53LX_GPH__RANGE_CONFIG__VALID_PHASE_HIGH 0x0F45 01966 01967 #define VL53LX_FIRMWARE__INTERNAL_STREAM_COUNT_DIV 0x0F46 01968 01969 #define VL53LX_FIRMWARE__INTERNAL_STREAM_COUNTER_VAL 0x0F47 01970 01971 #define VL53LX_DSS_CALC__ROI_CTRL 0x0F54 01972 01973 #define VL53LX_DSS_CALC__SPARE_1 0x0F55 01974 01975 #define VL53LX_DSS_CALC__SPARE_2 0x0F56 01976 01977 #define VL53LX_DSS_CALC__SPARE_3 0x0F57 01978 01979 #define VL53LX_DSS_CALC__SPARE_4 0x0F58 01980 01981 #define VL53LX_DSS_CALC__SPARE_5 0x0F59 01982 01983 #define VL53LX_DSS_CALC__SPARE_6 0x0F5A 01984 01985 #define VL53LX_DSS_CALC__SPARE_7 0x0F5B 01986 01987 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_0 0x0F5C 01988 01989 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_1 0x0F5D 01990 01991 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_2 0x0F5E 01992 01993 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_3 0x0F5F 01994 01995 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_4 0x0F60 01996 01997 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_5 0x0F61 01998 01999 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_6 0x0F62 02000 02001 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_7 0x0F63 02002 02003 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_8 0x0F64 02004 02005 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_9 0x0F65 02006 02007 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_10 0x0F66 02008 02009 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_11 0x0F67 02010 02011 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_12 0x0F68 02012 02013 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_13 0x0F69 02014 02015 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_14 0x0F6A 02016 02017 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_15 0x0F6B 02018 02019 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_16 0x0F6C 02020 02021 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_17 0x0F6D 02022 02023 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_18 0x0F6E 02024 02025 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_19 0x0F6F 02026 02027 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_20 0x0F70 02028 02029 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_21 0x0F71 02030 02031 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_22 0x0F72 02032 02033 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_23 0x0F73 02034 02035 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_24 0x0F74 02036 02037 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_25 0x0F75 02038 02039 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_26 0x0F76 02040 02041 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_27 0x0F77 02042 02043 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_28 0x0F78 02044 02045 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_29 0x0F79 02046 02047 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_30 0x0F7A 02048 02049 #define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_31 0x0F7B 02050 02051 #define VL53LX_DSS_CALC__USER_ROI_0 0x0F7C 02052 02053 #define VL53LX_DSS_CALC__USER_ROI_1 0x0F7D 02054 02055 #define VL53LX_DSS_CALC__MODE_ROI_0 0x0F7E 02056 02057 #define VL53LX_DSS_CALC__MODE_ROI_1 0x0F7F 02058 02059 #define VL53LX_SIGMA_ESTIMATOR_CALC__SPARE_0 0x0F80 02060 02061 #define VL53LX_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS 0x0F82 02062 02063 #define VL53LX_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS_HI 0x0F82 02064 02065 #define VL53LX_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS_LO 0x0F83 02066 02067 #define VL53LX_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF 0x0F84 02068 02069 #define VL53LX_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_3 0x0F84 02070 02071 #define VL53LX_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_2 0x0F85 02072 02073 #define VL53LX_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_1 0x0F86 02074 02075 #define VL53LX_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_0 0x0F87 02076 02077 #define VL53LX_PHASECAL_RESULT__PHASE_OUTPUT_REF 0x0F88 02078 02079 #define VL53LX_PHASECAL_RESULT__PHASE_OUTPUT_REF_HI 0x0F88 02080 02081 #define VL53LX_PHASECAL_RESULT__PHASE_OUTPUT_REF_LO 0x0F89 02082 02083 #define VL53LX_DSS_RESULT__TOTAL_RATE_PER_SPAD 0x0F8A 02084 02085 #define VL53LX_DSS_RESULT__TOTAL_RATE_PER_SPAD_HI 0x0F8A 02086 02087 #define VL53LX_DSS_RESULT__TOTAL_RATE_PER_SPAD_LO 0x0F8B 02088 02089 #define VL53LX_DSS_RESULT__ENABLED_BLOCKS 0x0F8C 02090 02091 #define VL53LX_DSS_RESULT__NUM_REQUESTED_SPADS 0x0F8E 02092 02093 #define VL53LX_DSS_RESULT__NUM_REQUESTED_SPADS_HI 0x0F8E 02094 02095 #define VL53LX_DSS_RESULT__NUM_REQUESTED_SPADS_LO 0x0F8F 02096 02097 #define VL53LX_MM_RESULT__INNER_INTERSECTION_RATE 0x0F92 02098 02099 #define VL53LX_MM_RESULT__INNER_INTERSECTION_RATE_HI 0x0F92 02100 02101 #define VL53LX_MM_RESULT__INNER_INTERSECTION_RATE_LO 0x0F93 02102 02103 #define VL53LX_MM_RESULT__OUTER_COMPLEMENT_RATE 0x0F94 02104 02105 #define VL53LX_MM_RESULT__OUTER_COMPLEMENT_RATE_HI 0x0F94 02106 02107 #define VL53LX_MM_RESULT__OUTER_COMPLEMENT_RATE_LO 0x0F95 02108 02109 #define VL53LX_MM_RESULT__TOTAL_OFFSET 0x0F96 02110 02111 #define VL53LX_MM_RESULT__TOTAL_OFFSET_HI 0x0F96 02112 02113 #define VL53LX_MM_RESULT__TOTAL_OFFSET_LO 0x0F97 02114 02115 #define VL53LX_XTALK_CALC__XTALK_FOR_ENABLED_SPADS 0x0F98 02116 02117 #define VL53LX_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_3 0x0F98 02118 02119 #define VL53LX_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_2 0x0F99 02120 02121 #define VL53LX_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_1 0x0F9A 02122 02123 #define VL53LX_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_0 0x0F9B 02124 02125 #define VL53LX_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS 0x0F9C 02126 02127 #define VL53LX_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_3 0x0F9C 02128 02129 #define VL53LX_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_2 0x0F9D 02130 02131 #define VL53LX_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_1 0x0F9E 02132 02133 #define VL53LX_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_0 0x0F9F 02134 02135 #define VL53LX_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS 0x0FA0 02136 02137 #define VL53LX_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_3 0x0FA0 02138 02139 #define VL53LX_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_2 0x0FA1 02140 02141 #define VL53LX_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_1 0x0FA2 02142 02143 #define VL53LX_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_0 0x0FA3 02144 02145 #define VL53LX_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS 0x0FA4 02146 02147 #define VL53LX_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_3 0x0FA4 02148 02149 #define VL53LX_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_2 0x0FA5 02150 02151 #define VL53LX_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_1 0x0FA6 02152 02153 #define VL53LX_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_0 0x0FA7 02154 02155 #define VL53LX_RANGE_RESULT__ACCUM_PHASE 0x0FA8 02156 02157 #define VL53LX_RANGE_RESULT__ACCUM_PHASE_3 0x0FA8 02158 02159 #define VL53LX_RANGE_RESULT__ACCUM_PHASE_2 0x0FA9 02160 02161 #define VL53LX_RANGE_RESULT__ACCUM_PHASE_1 0x0FAA 02162 02163 #define VL53LX_RANGE_RESULT__ACCUM_PHASE_0 0x0FAB 02164 02165 #define VL53LX_RANGE_RESULT__OFFSET_CORRECTED_RANGE 0x0FAC 02166 02167 #define VL53LX_RANGE_RESULT__OFFSET_CORRECTED_RANGE_HI 0x0FAC 02168 02169 #define VL53LX_RANGE_RESULT__OFFSET_CORRECTED_RANGE_LO 0x0FAD 02170 02171 #define VL53LX_SHADOW_PHASECAL_RESULT__VCSEL_START 0x0FAE 02172 02173 #define VL53LX_SHADOW_RESULT__INTERRUPT_STATUS 0x0FB0 02174 02175 #define VL53LX_SHADOW_RESULT__RANGE_STATUS 0x0FB1 02176 02177 #define VL53LX_SHADOW_RESULT__REPORT_STATUS 0x0FB2 02178 02179 #define VL53LX_SHADOW_RESULT__STREAM_COUNT 0x0FB3 02180 02181 #define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FB4 02182 02183 #define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FB4 02184 02185 #define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FB5 02186 02187 #define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x0FB6 02188 02189 #define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0FB6 02190 02191 #define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0FB7 02192 02193 #define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0FB8 02194 02195 #define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0FB8 02196 02197 #define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0FB9 02198 02199 #define VL53LX_SHADOW_RESULT__SIGMA_SD0 0x0FBA 02200 02201 #define VL53LX_SHADOW_RESULT__SIGMA_SD0_HI 0x0FBA 02202 02203 #define VL53LX_SHADOW_RESULT__SIGMA_SD0_LO 0x0FBB 02204 02205 #define VL53LX_SHADOW_RESULT__PHASE_SD0 0x0FBC 02206 02207 #define VL53LX_SHADOW_RESULT__PHASE_SD0_HI 0x0FBC 02208 02209 #define VL53LX_SHADOW_RESULT__PHASE_SD0_LO 0x0FBD 02210 02211 #define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0FBE 02212 02213 #define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0FBE 02214 02215 #define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0FBF 02216 02217 #define VL53LX_SHPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0FC0 02218 02219 #define VL53LX_SHPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0FC0 02220 02221 #define VL53LX_SHPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0FC1 02222 02223 #define VL53LX_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FC2 02224 02225 #define VL53LX_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FC2 02226 02227 #define VL53LX_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FC3 02228 02229 #define VL53LX_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FC4 02230 02231 #define VL53LX_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FC4 02232 02233 #define VL53LX_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FC5 02234 02235 #define VL53LX_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x0FC6 02236 02237 #define VL53LX_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0FC6 02238 02239 #define VL53LX_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0FC7 02240 02241 #define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x0FC8 02242 02243 #define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x0FC8 02244 02245 #define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x0FC9 02246 02247 #define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x0FCA 02248 02249 #define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x0FCA 02250 02251 #define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x0FCB 02252 02253 #define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x0FCC 02254 02255 #define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x0FCC 02256 02257 #define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x0FCD 02258 02259 #define VL53LX_SHADOW_RESULT__SIGMA_SD1 0x0FCE 02260 02261 #define VL53LX_SHADOW_RESULT__SIGMA_SD1_HI 0x0FCE 02262 02263 #define VL53LX_SHADOW_RESULT__SIGMA_SD1_LO 0x0FCF 02264 02265 #define VL53LX_SHADOW_RESULT__PHASE_SD1 0x0FD0 02266 02267 #define VL53LX_SHADOW_RESULT__PHASE_SD1_HI 0x0FD0 02268 02269 #define VL53LX_SHADOW_RESULT__PHASE_SD1_LO 0x0FD1 02270 02271 #define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x0FD2 02272 02273 #define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x0FD2 02274 02275 #define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x0FD3 02276 02277 #define VL53LX_SHADOW_RESULT__SPARE_0_SD1 0x0FD4 02278 02279 #define VL53LX_SHADOW_RESULT__SPARE_0_SD1_HI 0x0FD4 02280 02281 #define VL53LX_SHADOW_RESULT__SPARE_0_SD1_LO 0x0FD5 02282 02283 #define VL53LX_SHADOW_RESULT__SPARE_1_SD1 0x0FD6 02284 02285 #define VL53LX_SHADOW_RESULT__SPARE_1_SD1_HI 0x0FD6 02286 02287 #define VL53LX_SHADOW_RESULT__SPARE_1_SD1_LO 0x0FD7 02288 02289 #define VL53LX_SHADOW_RESULT__SPARE_2_SD1 0x0FD8 02290 02291 #define VL53LX_SHADOW_RESULT__SPARE_2_SD1_HI 0x0FD8 02292 02293 #define VL53LX_SHADOW_RESULT__SPARE_2_SD1_LO 0x0FD9 02294 02295 #define VL53LX_SHADOW_RESULT__SPARE_3_SD1 0x0FDA 02296 02297 #define VL53LX_SHADOW_RESULT__THRESH_INFO 0x0FDB 02298 02299 #define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x0FDC 02300 02301 #define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x0FDC 02302 02303 #define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x0FDD 02304 02305 #define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x0FDE 02306 02307 #define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x0FDF 02308 02309 #define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x0FE0 02310 02311 #define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x0FE0 02312 02313 #define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x0FE1 02314 02315 #define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x0FE2 02316 02317 #define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x0FE3 02318 02319 #define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x0FE4 02320 02321 #define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x0FE4 02322 02323 #define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x0FE5 02324 02325 #define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x0FE6 02326 02327 #define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x0FE7 02328 02329 #define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x0FE8 02330 02331 #define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x0FE8 02332 02333 #define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x0FE9 02334 02335 #define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x0FEA 02336 02337 #define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x0FEB 02338 02339 #define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x0FEC 02340 02341 #define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x0FEC 02342 02343 #define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x0FED 02344 02345 #define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x0FEE 02346 02347 #define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x0FEF 02348 02349 #define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x0FF0 02350 02351 #define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x0FF0 02352 02353 #define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x0FF1 02354 02355 #define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x0FF2 02356 02357 #define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x0FF3 02358 02359 #define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x0FF4 02360 02361 #define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x0FF4 02362 02363 #define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x0FF5 02364 02365 #define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x0FF6 02366 02367 #define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x0FF7 02368 02369 #define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x0FF8 02370 02371 #define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x0FF8 02372 02373 #define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x0FF9 02374 02375 #define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x0FFA 02376 02377 #define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x0FFB 02378 02379 #define VL53LX_SHADOW_RESULT_CORE__SPARE_0 0x0FFC 02380 02381 #define VL53LX_SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_HI 0x0FFE 02382 02383 #define VL53LX_SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_LO 0x0FFF 02384 02385 02386 02387 02388 02389 // define from vl53lx_error_exceptions.h 02390 02391 #ifndef _VL53LX_ERROR_EXCEPTIONS_H_ 02392 #define _VL53LX_ERROR_EXCEPTIONS_H_ 02393 02394 #define IGNORE_DIVISION_BY_ZERO 0 02395 02396 #define IGNORE_XTALK_EXTRACTION_NO_SAMPLE_FAIL 0 02397 #define IGNORE_XTALK_EXTRACTION_SIGMA_LIMIT_FAIL 0 02398 #define IGNORE_XTALK_EXTRACTION_NO_SAMPLE_FOR_GRADIENT_WARN 0 02399 #define IGNORE_XTALK_EXTRACTION_SIGMA_LIMIT_FOR_GRADIENT_WARN 0 02400 #define IGNORE_XTALK_EXTRACTION_MISSING_SAMPLES_WARN 0 02401 02402 #define IGNORE_REF_SPAD_CHAR_NOT_ENOUGH_SPADS 0 02403 #define IGNORE_REF_SPAD_CHAR_RATE_TOO_HIGH 0 02404 #define IGNORE_REF_SPAD_CHAR_RATE_TOO_LOW 0 02405 02406 #define IGNORE_OFFSET_CAL_MISSING_SAMPLES 0 02407 #define IGNORE_OFFSET_CAL_SIGMA_TOO_HIGH 0 02408 #define IGNORE_OFFSET_CAL_RATE_TOO_HIGH 0 02409 #define IGNORE_OFFSET_CAL_SPAD_COUNT_TOO_LOW 0 02410 02411 #define IGNORE_ZONE_CAL_MISSING_SAMPLES 0 02412 #define IGNORE_ZONE_CAL_SIGMA_TOO_HIGH 0 02413 #define IGNORE_ZONE_CAL_RATE_TOO_HIGH 0 02414 02415 #endif 02416 02417 // define from vl53lx_platform_user_defines.h 02418 02419 #define do_division_u(dividend, divisor) (dividend / divisor) 02420 02421 #define do_division_s(dividend, divisor) (dividend / divisor) 02422 02423 02424 02425 #ifdef _MSC_VER 02426 #define DISABLE_WARNINGS() { \ 02427 __pragma(warning(push)); \ 02428 __pragma(warning(disable:4127)); \ 02429 } 02430 #define ENABLE_WARNINGS() { \ 02431 __pragma(warning( pop )); \ 02432 } 02433 #else 02434 02435 02436 #define DISABLE_WARNINGS() 02437 #define ENABLE_WARNINGS() 02438 #endif 02439 02440 02441 02442 02443 /*vl53lx_register_settings.h*/ 02444 02445 02446 #define VL53LX_DEVICESCHEDULERMODE_PSEUDO_SOLO 0x00 02447 #define VL53LX_DEVICESCHEDULERMODE_STREAMING 0x01 02448 #define VL53LX_DEVICESCHEDULERMODE_HISTOGRAM 0x02 02449 02450 02451 02452 02453 02454 #define VL53LX_DEVICEREADOUTMODE_SINGLE_SD (0x00 << 2) 02455 #define VL53LX_DEVICEREADOUTMODE_DUAL_SD (0x01 << 2) 02456 #define VL53LX_DEVICEREADOUTMODE_SPLIT_READOUT (0x02 << 2) 02457 #define VL53LX_DEVICEREADOUTMODE_SPLIT_MANUAL (0x03 << 2) 02458 02459 02460 02461 02462 02463 02464 #define VL53LX_DEVICEMEASUREMENTMODE_MODE_MASK 0xF0 02465 #define VL53LX_DEVICEMEASUREMENTMODE_STOP_MASK 0x0F 02466 02467 #define VL53LX_GROUPEDPARAMETERHOLD_ID_MASK 0x02 02468 02469 02470 02471 #define VL53LX_EWOK_I2C_DEV_ADDR_DEFAULT 0x29 02472 02473 #define VL53LX_OSC_FREQUENCY 0x00 02474 #define VL53LX_OSC_TRIM_DEFAULT 0x00 02475 #define VL53LX_OSC_FREQ_SET_DEFAULT 0x00 02476 02477 #define VL53LX_RANGE_HISTOGRAM_REF 0x08 02478 #define VL53LX_RANGE_HISTOGRAM_RET 0x10 02479 #define VL53LX_RANGE_HISTOGRAM_BOTH 0x18 02480 #define VL53LX_RANGE_HISTOGRAM_INIT 0x20 02481 #define VL53LX_RANGE_VHV_INIT 0x40 02482 02483 02484 #define VL53LX_RESULT_RANGE_STATUS 0x1F 02485 02486 02487 #define VL53LX_SYSTEM__SEED_CONFIG__MANUAL 0x00 02488 #define VL53LX_SYSTEM__SEED_CONFIG__STANDARD 0x01 02489 #define VL53LX_SYSTEM__SEED_CONFIG__EVEN_UPDATE_ONLY 0x02 02490 02491 02492 #define VL53LX_INTERRUPT_CONFIG_LEVEL_LOW 0x00 02493 #define VL53LX_INTERRUPT_CONFIG_LEVEL_HIGH 0x01 02494 #define VL53LX_INTERRUPT_CONFIG_OUT_OF_WINDOW 0x02 02495 #define VL53LX_INTERRUPT_CONFIG_IN_WINDOW 0x03 02496 #define VL53LX_INTERRUPT_CONFIG_NEW_SAMPLE_READY 0x20 02497 02498 02499 #define VL53LX_CLEAR_RANGE_INT 0x01 02500 #define VL53LX_CLEAR_ERROR_INT 0x02 02501 02502 02503 #define VL53LX_SEQUENCE_VHV_EN 0x01 02504 #define VL53LX_SEQUENCE_PHASECAL_EN 0x02 02505 #define VL53LX_SEQUENCE_REFERENCE_PHASE_EN 0x04 02506 #define VL53LX_SEQUENCE_DSS1_EN 0x08 02507 #define VL53LX_SEQUENCE_DSS2_EN 0x10 02508 #define VL53LX_SEQUENCE_MM1_EN 0x20 02509 #define VL53LX_SEQUENCE_MM2_EN 0x40 02510 #define VL53LX_SEQUENCE_RANGE_EN 0x80 02511 02512 02513 #define VL53LX_DSS_CONTROL__ROI_SUBTRACT 0x20 02514 #define VL53LX_DSS_CONTROL__ROI_INTERSECT 0x10 02515 02516 #define VL53LX_DSS_CONTROL__MODE_DISABLED 0x00 02517 #define VL53LX_DSS_CONTROL__MODE_TARGET_RATE 0x01 02518 #define VL53LX_DSS_CONTROL__MODE_EFFSPADS 0x02 02519 #define VL53LX_DSS_CONTROL__MODE_BLOCKSELECT 0x03 02520 02521 02522 02523 #define VL53LX_RANGING_CORE__SPAD_READOUT__STANDARD 0x45 02524 #define VL53LX_RANGING_CORE__SPAD_READOUT__RETURN_ARRAY_ONLY 0x05 02525 #define VL53LX_RANGING_CORE__SPAD_READOUT__REFERENCE_ARRAY_ONLY 0x55 02526 #define VL53LX_RANGING_CORE__SPAD_READOUT__RETURN_SPLIT_ARRAY 0x25 02527 #define VL53LX_RANGING_CORE__SPAD_READOUT__CALIB_PULSES 0xF5 02528 02529 02530 #define VL53LX_LASER_SAFETY__KEY_VALUE 0x6C 02531 02532 02533 02534 #define VL53LX_RANGE_STATUS__RANGE_STATUS_MASK 0x1F 02535 #define VL53LX_RANGE_STATUS__MAX_THRESHOLD_HIT_MASK 0x20 02536 #define VL53LX_RANGE_STATUS__MIN_THRESHOLD_HIT_MASK 0x40 02537 #define VL53LX_RANGE_STATUS__GPH_ID_RANGE_STATUS_MASK 0x80 02538 02539 02540 02541 #define VL53LX_INTERRUPT_STATUS__INT_STATUS_MASK 0x07 02542 #define VL53LX_INTERRUPT_STATUS__INT_ERROR_STATUS_MASK 0x18 02543 #define VL53LX_INTERRUPT_STATUS__GPH_ID_INT_STATUS_MASK 0x20 02544 02545 02546 /* vl53lx_nvm_map.h */ 02547 02548 02549 02550 02551 #define VL53LX_NVM__IDENTIFICATION__MODEL_ID 0x0008 02552 02553 #define VL53LX_NVM__IDENTIFICATION__MODULE_TYPE 0x000C 02554 02555 #define VL53LX_NVM__IDENTIFICATION__REVISION_ID 0x000D 02556 02557 #define VL53LX_NVM__IDENTIFICATION__MODULE_ID 0x000E 02558 02559 #define VL53LX_NVM__I2C_VALID 0x0010 02560 02561 #define VL53LX_NVM__I2C_SLAVE__DEVICE_ADDRESS 0x0011 02562 02563 #define VL53LX_NVM__EWS__OSC_MEASURED__FAST_OSC_FREQUENCY 0x0014 02564 02565 #define VL53LX_NVM__EWS__FAST_OSC_TRIM_MAX 0x0016 02566 02567 #define VL53LX_NVM__EWS__FAST_OSC_FREQ_SET 0x0017 02568 02569 #define VL53LX_NVM__EWS__SLOW_OSC_CALIBRATION 0x0018 02570 02571 #define VL53LX_NVM__FMT__OSC_MEASURED__FAST_OSC_FREQUENCY 0x001C 02572 02573 #define VL53LX_NVM__FMT__FAST_OSC_TRIM_MAX 0x001E 02574 02575 #define VL53LX_NVM__FMT__FAST_OSC_FREQ_SET 0x001F 02576 02577 #define VL53LX_NVM__FMT__SLOW_OSC_CALIBRATION 0x0020 02578 02579 #define VL53LX_NVM__VHV_CONFIG_UNLOCK 0x0028 02580 02581 #define VL53LX_NVM__REF_SELVDDPIX 0x0029 02582 02583 #define VL53LX_NVM__REF_SELVQUENCH 0x002A 02584 02585 #define VL53LX_NVM__REGAVDD1V2_SEL_REGDVDD1V2_SEL 0x002B 02586 02587 #define VL53LX_NVM__VHV_CONFIG__TIMEOUT_MACROP_LOOP_BOUND 0x002C 02588 02589 #define VL53LX_NVM__VHV_CONFIG__COUNT_THRESH 0x002D 02590 02591 #define VL53LX_NVM__VHV_CONFIG__OFFSET 0x002E 02592 02593 #define VL53LX_NVM__VHV_CONFIG__INIT 0x002F 02594 02595 #define VL53LX_NVM__LASER_SAFETY__VCSEL_TRIM_LL 0x0030 02596 02597 #define VL53LX_NVM__LASER_SAFETY__VCSEL_SELION_LL 0x0031 02598 02599 #define VL53LX_NVM__LASER_SAFETY__VCSEL_SELION_MAX_LL 0x0032 02600 02601 #define VL53LX_NVM__LASER_SAFETY__MULT_LL 0x0034 02602 02603 #define VL53LX_NVM__LASER_SAFETY__CLIP_LL 0x0035 02604 02605 #define VL53LX_NVM__LASER_SAFETY__VCSEL_TRIM_LD 0x0038 02606 02607 #define VL53LX_NVM__LASER_SAFETY__VCSEL_SELION_LD 0x0039 02608 02609 #define VL53LX_NVM__LASER_SAFETY__VCSEL_SELION_MAX_LD 0x003A 02610 02611 #define VL53LX_NVM__LASER_SAFETY__MULT_LD 0x003C 02612 02613 #define VL53LX_NVM__LASER_SAFETY__CLIP_LD 0x003D 02614 02615 #define VL53LX_NVM__LASER_SAFETY_LOCK_BYTE 0x0040 02616 02617 #define VL53LX_NVM__LASER_SAFETY_UNLOCK_BYTE 0x0044 02618 02619 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_0_ 0x0048 02620 02621 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_1_ 0x0049 02622 02623 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_2_ 0x004A 02624 02625 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_3_ 0x004B 02626 02627 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_4_ 0x004C 02628 02629 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_5_ 0x004D 02630 02631 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_6_ 0x004E 02632 02633 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_7_ 0x004F 02634 02635 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_8_ 0x0050 02636 02637 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_9_ 0x0051 02638 02639 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_10_ 0x0052 02640 02641 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_11_ 0x0053 02642 02643 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_12_ 0x0054 02644 02645 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_13_ 0x0055 02646 02647 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_14_ 0x0056 02648 02649 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_15_ 0x0057 02650 02651 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_16_ 0x0058 02652 02653 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_17_ 0x0059 02654 02655 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_18_ 0x005A 02656 02657 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_19_ 0x005B 02658 02659 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_20_ 0x005C 02660 02661 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_21_ 0x005D 02662 02663 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_22_ 0x005E 02664 02665 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_23_ 0x005F 02666 02667 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_24_ 0x0060 02668 02669 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_25_ 0x0061 02670 02671 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_26_ 0x0062 02672 02673 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_27_ 0x0063 02674 02675 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_28_ 0x0064 02676 02677 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_29_ 0x0065 02678 02679 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_30_ 0x0066 02680 02681 #define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_31_ 0x0067 02682 02683 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_0_ 0x0068 02684 02685 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_1_ 0x0069 02686 02687 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_2_ 0x006A 02688 02689 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_3_ 0x006B 02690 02691 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_4_ 0x006C 02692 02693 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_5_ 0x006D 02694 02695 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_0_ 0x0070 02696 02697 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_1_ 0x0071 02698 02699 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_2_ 0x0072 02700 02701 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_3_ 0x0073 02702 02703 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_4_ 0x0074 02704 02705 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_5_ 0x0075 02706 02707 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_0_ 0x0078 02708 02709 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_1_ 0x0079 02710 02711 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_2_ 0x007A 02712 02713 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_3_ 0x007B 02714 02715 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_4_ 0x007C 02716 02717 #define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_5_ 0x007D 02718 02719 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_0_ 0x0080 02720 02721 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_1_ 0x0081 02722 02723 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_2_ 0x0082 02724 02725 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_3_ 0x0083 02726 02727 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_4_ 0x0084 02728 02729 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_5_ 0x0085 02730 02731 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_6_ 0x0086 02732 02733 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_7_ 0x0087 02734 02735 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_8_ 0x0088 02736 02737 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_9_ 0x0089 02738 02739 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_10_ 0x008A 02740 02741 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_11_ 0x008B 02742 02743 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_12_ 0x008C 02744 02745 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_13_ 0x008D 02746 02747 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_14_ 0x008E 02748 02749 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_15_ 0x008F 02750 02751 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_16_ 0x0090 02752 02753 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_17_ 0x0091 02754 02755 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_18_ 0x0092 02756 02757 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_19_ 0x0093 02758 02759 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_20_ 0x0094 02760 02761 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_21_ 0x0095 02762 02763 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_22_ 0x0096 02764 02765 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_23_ 0x0097 02766 02767 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_24_ 0x0098 02768 02769 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_25_ 0x0099 02770 02771 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_26_ 0x009A 02772 02773 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_27_ 0x009B 02774 02775 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_28_ 0x009C 02776 02777 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_29_ 0x009D 02778 02779 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_30_ 0x009E 02780 02781 #define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_31_ 0x009F 02782 02783 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_0_ 0x00A0 02784 02785 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_1_ 0x00A1 02786 02787 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_2_ 0x00A2 02788 02789 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_3_ 0x00A3 02790 02791 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_4_ 0x00A4 02792 02793 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_5_ 0x00A5 02794 02795 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_0_ 0x00A8 02796 02797 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_1_ 0x00A9 02798 02799 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_2_ 0x00AA 02800 02801 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_3_ 0x00AB 02802 02803 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_4_ 0x00AC 02804 02805 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_5_ 0x00AD 02806 02807 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_0_ 0x00B0 02808 02809 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_1_ 0x00B1 02810 02811 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_2_ 0x00B2 02812 02813 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_3_ 0x00B3 02814 02815 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_4_ 0x00B4 02816 02817 #define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_5_ 0x00B5 02818 02819 #define VL53LX_NVM__FMT__ROI_CONFIG__MODE_ROI_CENTRE_SPAD 0x00B8 02820 02821 #define VL53LX_NVM__FMT__ROI_CONFIG__MODE_ROI_XY_SIZE 0x00B9 02822 02823 #define VL53LX_NVM__FMT__REF_SPAD_APPLY__NUM_REQUESTED_REF_SPAD 0x00BC 02824 02825 #define VL53LX_NVM__FMT__REF_SPAD_MAN__REF_LOCATION 0x00BD 02826 02827 #define VL53LX_NVM__FMT__MM_CONFIG__INNER_OFFSET_MM 0x00C0 02828 02829 #define VL53LX_NVM__FMT__MM_CONFIG__OUTER_OFFSET_MM 0x00C2 02830 02831 #define VL53LX_NVM__FMT__ALGO__PART_TO_PART_RANGE_OFFSET_MM 0x00C4 02832 02833 #define VL53LX_NVM__FMT__ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS 0x00C8 02834 02835 #define VL53LX_NVM__FMT__ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS \ 02836 0x00CA 02837 02838 #define VL53LX_NVM__FMT__ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS \ 02839 0x00CC 02840 02841 #define VL53LX_NVM__FMT__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_0 0x00CE 02842 02843 #define VL53LX_NVM__FMT__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_1 0x00CF 02844 02845 #define VL53LX_NVM__CUSTOMER_NVM_SPACE_PROGRAMMED 0x00E0 02846 02847 #define VL53LX_NVM__CUST__I2C_SLAVE__DEVICE_ADDRESS 0x00E4 02848 02849 #define VL53LX_NVM__CUST__REF_SPAD_APPLY__NUM_REQUESTED_REF_SPAD 0x00E8 02850 02851 #define VL53LX_NVM__CUST__REF_SPAD_MAN__REF_LOCATION 0x00E9 02852 02853 #define VL53LX_NVM__CUST__MM_CONFIG__INNER_OFFSET_MM 0x00EC 02854 02855 #define VL53LX_NVM__CUST__MM_CONFIG__OUTER_OFFSET_MM 0x00EE 02856 02857 #define VL53LX_NVM__CUST__ALGO__PART_TO_PART_RANGE_OFFSET_MM 0x00F0 02858 02859 #define VL53LX_NVM__CUST__ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS 0x00F4 02860 02861 #define VL53LX_NVM__CUST__ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS \ 02862 0x00F6 02863 02864 #define VL53LX_NVM__CUST__ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS \ 02865 0x00F8 02866 02867 #define VL53LX_NVM__CUST__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_0 0x00FA 02868 02869 #define VL53LX_NVM__CUST__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_1 0x00FB 02870 02871 #define VL53LX_NVM__FMT__FGC__BYTE_0 0x01DC 02872 02873 #define VL53LX_NVM__FMT__FGC__BYTE_1 0x01DD 02874 02875 #define VL53LX_NVM__FMT__FGC__BYTE_2 0x01DE 02876 02877 #define VL53LX_NVM__FMT__FGC__BYTE_3 0x01DF 02878 02879 #define VL53LX_NVM__FMT__FGC__BYTE_4 0x01E0 02880 02881 #define VL53LX_NVM__FMT__FGC__BYTE_5 0x01E1 02882 02883 #define VL53LX_NVM__FMT__FGC__BYTE_6 0x01E2 02884 02885 #define VL53LX_NVM__FMT__FGC__BYTE_7 0x01E3 02886 02887 #define VL53LX_NVM__FMT__FGC__BYTE_8 0x01E4 02888 02889 #define VL53LX_NVM__FMT__FGC__BYTE_9 0x01E5 02890 02891 #define VL53LX_NVM__FMT__FGC__BYTE_10 0x01E6 02892 02893 #define VL53LX_NVM__FMT__FGC__BYTE_11 0x01E7 02894 02895 #define VL53LX_NVM__FMT__FGC__BYTE_12 0x01E8 02896 02897 #define VL53LX_NVM__FMT__FGC__BYTE_13 0x01E9 02898 02899 #define VL53LX_NVM__FMT__FGC__BYTE_14 0x01EA 02900 02901 #define VL53LX_NVM__FMT__FGC__BYTE_15 0x01EB 02902 02903 #define VL53LX_NVM__FMT__TEST_PROGRAM_MAJOR_MINOR 0x01EC 02904 02905 #define VL53LX_NVM__FMT__MAP_MAJOR_MINOR 0x01ED 02906 02907 #define VL53LX_NVM__FMT__YEAR_MONTH 0x01EE 02908 02909 #define VL53LX_NVM__FMT__DAY_MODULE_DATE_PHASE 0x01EF 02910 02911 #define VL53LX_NVM__FMT__TIME 0x01F0 02912 02913 #define VL53LX_NVM__FMT__TESTER_ID 0x01F2 02914 02915 #define VL53LX_NVM__FMT__SITE_ID 0x01F3 02916 02917 #define VL53LX_NVM__EWS__TEST_PROGRAM_MAJOR_MINOR 0x01F4 02918 02919 #define VL53LX_NVM__EWS__PROBE_CARD_MAJOR_MINOR 0x01F5 02920 02921 #define VL53LX_NVM__EWS__TESTER_ID 0x01F6 02922 02923 #define VL53LX_NVM__EWS__LOT__BYTE_0 0x01F8 02924 02925 #define VL53LX_NVM__EWS__LOT__BYTE_1 0x01F9 02926 02927 #define VL53LX_NVM__EWS__LOT__BYTE_2 0x01FA 02928 02929 #define VL53LX_NVM__EWS__LOT__BYTE_3 0x01FB 02930 02931 #define VL53LX_NVM__EWS__LOT__BYTE_4 0x01FC 02932 02933 #define VL53LX_NVM__EWS__LOT__BYTE_5 0x01FD 02934 02935 #define VL53LX_NVM__EWS__WAFER 0x01FD 02936 02937 #define VL53LX_NVM__EWS__XCOORD 0x01FE 02938 02939 #define VL53LX_NVM__EWS__YCOORD 0x01FF 02940 02941 02942 #define VL53LX_NVM__FMT__OPTICAL_CENTRE_DATA_INDEX 0x00B8 02943 #define VL53LX_NVM__FMT__OPTICAL_CENTRE_DATA_SIZE 4 02944 02945 #define VL53LX_NVM__FMT__CAL_PEAK_RATE_MAP_DATA_INDEX 0x015C 02946 #define VL53LX_NVM__FMT__CAL_PEAK_RATE_MAP_DATA_SIZE 56 02947 02948 #define VL53LX_NVM__FMT__ADDITIONAL_OFFSET_CAL_DATA_INDEX 0x0194 02949 #define VL53LX_NVM__FMT__ADDITIONAL_OFFSET_CAL_DATA_SIZE 8 02950 02951 #define VL53LX_NVM__FMT__RANGE_RESULTS__140MM_MM_PRE_RANGE 0x019C 02952 #define VL53LX_NVM__FMT__RANGE_RESULTS__140MM_DARK 0x01AC 02953 #define VL53LX_NVM__FMT__RANGE_RESULTS__400MM_DARK 0x01BC 02954 #define VL53LX_NVM__FMT__RANGE_RESULTS__400MM_AMBIENT 0x01CC 02955 #define VL53LX_NVM__FMT__RANGE_RESULTS__SIZE_BYTES 16 02956 02957 02958 02959 02960 02961 02962 /* vl53lx_tuning_parm_defaults.h */ 02963 02964 02965 02966 #define VL53LX_TUNINGPARM_VERSION_DEFAULT \ 02967 ((uint16_t) 29) 02968 #define VL53LX_TUNINGPARM_KEY_TABLE_VERSION_DEFAULT \ 02969 ((uint16_t) 14) 02970 #define VL53LX_TUNINGPARM_LLD_VERSION_DEFAULT \ 02971 ((uint16_t) 12180) 02972 #define VL53LX_TUNINGPARM_HIST_ALGO_SELECT_DEFAULT \ 02973 ((uint8_t) 4) 02974 #define VL53LX_TUNINGPARM_HIST_TARGET_ORDER_DEFAULT \ 02975 ((uint8_t) 1) 02976 #define VL53LX_TUNINGPARM_HIST_FILTER_WOI_0_DEFAULT \ 02977 ((uint8_t) 1) 02978 #define VL53LX_TUNINGPARM_HIST_FILTER_WOI_1_DEFAULT \ 02979 ((uint8_t) 2) 02980 #define VL53LX_TUNINGPARM_HIST_AMB_EST_METHOD_DEFAULT \ 02981 ((uint8_t) 1) 02982 #define VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_0_DEFAULT \ 02983 ((uint8_t) 80) 02984 #define VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_1_DEFAULT \ 02985 ((uint8_t) 100) 02986 #define VL53LX_TUNINGPARM_HIST_MIN_AMB_THRESH_EVENTS_DEFAULT \ 02987 ((int32_t) 16) 02988 #define VL53LX_TUNINGPARM_HIST_AMB_EVENTS_SCALER_DEFAULT \ 02989 ((uint16_t) 4157) 02990 #define VL53LX_TUNINGPARM_HIST_NOISE_THRESHOLD_DEFAULT \ 02991 ((uint16_t) 50) 02992 #define VL53LX_TUNINGPARM_HIST_SIGNAL_TOTAL_EVENTS_LIMIT_DEFAULT \ 02993 ((int32_t) 100) 02994 #define VL53LX_TUNINGPARM_HIST_SIGMA_EST_REF_MM_DEFAULT \ 02995 ((uint8_t) 1) 02996 #define VL53LX_TUNINGPARM_HIST_SIGMA_THRESH_MM_DEFAULT \ 02997 ((uint16_t) 180) 02998 #define VL53LX_TUNINGPARM_HIST_GAIN_FACTOR_DEFAULT \ 02999 ((uint16_t) 1987) 03000 #define VL53LX_TUNINGPARM_CONSISTENCY_HIST_PHASE_TOLERANCE_DEFAULT \ 03001 ((uint8_t) 8) 03002 #define VL53LX_TUNINGPARM_CONSISTENCY_HIST_MIN_MAX_TOLERANCE_MM_DEFAULT \ 03003 ((uint16_t) 0) 03004 #define VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA_DEFAULT \ 03005 ((uint8_t) 0) 03006 #define VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA_MIN_SPAD_LIMIT_DEFAULT \ 03007 ((uint16_t) 2048) 03008 #define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_LONG_RANGE_DEFAULT \ 03009 ((uint8_t) 9) 03010 #define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_MED_RANGE_DEFAULT \ 03011 ((uint8_t) 5) 03012 #define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_SHORT_RANGE_DEFAULT \ 03013 ((uint8_t) 3) 03014 #define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_LONG_RANGE_DEFAULT \ 03015 ((uint8_t) 6) 03016 #define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_MED_RANGE_DEFAULT \ 03017 ((uint8_t) 6) 03018 #define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_SHORT_RANGE_DEFAULT \ 03019 ((uint8_t) 6) 03020 #define VL53LX_TUNINGPARM_XTALK_DETECT_MIN_VALID_RANGE_MM_DEFAULT \ 03021 ((int16_t) -50) 03022 #define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RANGE_MM_DEFAULT \ 03023 ((int16_t) 50) 03024 #define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_SIGMA_MM_DEFAULT \ 03025 ((uint16_t) 140) 03026 #define VL53LX_TUNINGPARM_XTALK_DETECT_MIN_MAX_TOLERANCE_DEFAULT \ 03027 ((uint16_t) 50) 03028 #define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RATE_KCPS_DEFAULT \ 03029 ((uint16_t) 400) 03030 #define VL53LX_TUNINGPARM_XTALK_DETECT_EVENT_SIGMA_DEFAULT \ 03031 ((uint8_t) 80) 03032 #define VL53LX_TUNINGPARM_HIST_XTALK_MARGIN_KCPS_DEFAULT \ 03033 ((int16_t) 0) 03034 #define VL53LX_TUNINGPARM_CONSISTENCY_LITE_PHASE_TOLERANCE_DEFAULT \ 03035 ((uint8_t) 2) 03036 #define VL53LX_TUNINGPARM_PHASECAL_TARGET_DEFAULT \ 03037 ((uint8_t) 33) 03038 #define VL53LX_TUNINGPARM_LITE_CAL_REPEAT_RATE_DEFAULT \ 03039 ((uint16_t) 0) 03040 #define VL53LX_TUNINGPARM_LITE_RANGING_GAIN_FACTOR_DEFAULT \ 03041 ((uint16_t) 2011) 03042 #define VL53LX_TUNINGPARM_LITE_MIN_CLIP_MM_DEFAULT \ 03043 ((uint8_t) 0) 03044 #define VL53LX_TUNINGPARM_LITE_LONG_SIGMA_THRESH_MM_DEFAULT \ 03045 ((uint16_t) 60) 03046 #define VL53LX_TUNINGPARM_LITE_MED_SIGMA_THRESH_MM_DEFAULT \ 03047 ((uint16_t) 60) 03048 #define VL53LX_TUNINGPARM_LITE_SHORT_SIGMA_THRESH_MM_DEFAULT \ 03049 ((uint16_t) 60) 03050 #define VL53LX_TUNINGPARM_LITE_LONG_MIN_COUNT_RATE_RTN_MCPS_DEFAULT \ 03051 ((uint16_t) 128) 03052 #define VL53LX_TUNINGPARM_LITE_MED_MIN_COUNT_RATE_RTN_MCPS_DEFAULT \ 03053 ((uint16_t) 128) 03054 #define VL53LX_TUNINGPARM_LITE_SHORT_MIN_COUNT_RATE_RTN_MCPS_DEFAULT \ 03055 ((uint16_t) 128) 03056 #define VL53LX_TUNINGPARM_LITE_SIGMA_EST_PULSE_WIDTH_DEFAULT \ 03057 ((uint8_t) 8) 03058 #define VL53LX_TUNINGPARM_LITE_SIGMA_EST_AMB_WIDTH_NS_DEFAULT \ 03059 ((uint8_t) 16) 03060 #define VL53LX_TUNINGPARM_LITE_SIGMA_REF_MM_DEFAULT \ 03061 ((uint8_t) 1) 03062 #define VL53LX_TUNINGPARM_LITE_RIT_MULT_DEFAULT \ 03063 ((uint8_t) 64) 03064 #define VL53LX_TUNINGPARM_LITE_SEED_CONFIG_DEFAULT \ 03065 ((uint8_t) 2) 03066 #define VL53LX_TUNINGPARM_LITE_QUANTIFIER_DEFAULT \ 03067 ((uint8_t) 2) 03068 #define VL53LX_TUNINGPARM_LITE_FIRST_ORDER_SELECT_DEFAULT \ 03069 ((uint8_t) 0) 03070 #define VL53LX_TUNINGPARM_LITE_XTALK_MARGIN_KCPS_DEFAULT \ 03071 ((int16_t) 0) 03072 #define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_LONG_RANGE_DEFAULT \ 03073 ((uint8_t) 14) 03074 #define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_MED_RANGE_DEFAULT \ 03075 ((uint8_t) 10) 03076 #define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_SHORT_RANGE_DEFAULT \ 03077 ((uint8_t) 6) 03078 #define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_LONG_RANGE_DEFAULT \ 03079 ((uint8_t) 14) 03080 #define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_MED_RANGE_DEFAULT \ 03081 ((uint8_t) 10) 03082 #define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_SHORT_RANGE_DEFAULT \ 03083 ((uint8_t) 6) 03084 #define VL53LX_TUNINGPARM_TIMED_SEED_CONFIG_DEFAULT \ 03085 ((uint8_t) 1) 03086 #define VL53LX_TUNINGPARM_DMAX_CFG_SIGNAL_THRESH_SIGMA_DEFAULT \ 03087 ((uint8_t) 32) 03088 #define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_0_DEFAULT \ 03089 ((uint16_t) 15) 03090 #define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_1_DEFAULT \ 03091 ((uint16_t) 52) 03092 #define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_2_DEFAULT \ 03093 ((uint16_t) 200) 03094 #define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_3_DEFAULT \ 03095 ((uint16_t) 364) 03096 #define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_4_DEFAULT \ 03097 ((uint16_t) 400) 03098 #define VL53LX_TUNINGPARM_VHV_LOOPBOUND_DEFAULT \ 03099 ((uint8_t) 129) 03100 #define VL53LX_TUNINGPARM_REFSPADCHAR_DEVICE_TEST_MODE_DEFAULT \ 03101 ((uint8_t) 8) 03102 #define VL53LX_TUNINGPARM_REFSPADCHAR_VCSEL_PERIOD_DEFAULT \ 03103 ((uint8_t) 11) 03104 #define VL53LX_TUNINGPARM_REFSPADCHAR_PHASECAL_TIMEOUT_US_DEFAULT \ 03105 ((uint32_t) 1000) 03106 #define VL53LX_TUNINGPARM_REFSPADCHAR_TARGET_COUNT_RATE_MCPS_DEFAULT \ 03107 ((uint16_t) 2560) 03108 #define VL53LX_TUNINGPARM_REFSPADCHAR_MIN_COUNTRATE_LIMIT_MCPS_DEFAULT \ 03109 ((uint16_t) 1280) 03110 #define VL53LX_TUNINGPARM_REFSPADCHAR_MAX_COUNTRATE_LIMIT_MCPS_DEFAULT \ 03111 ((uint16_t) 5120) 03112 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_NUM_OF_SAMPLES_DEFAULT \ 03113 ((uint8_t) 7) 03114 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_MIN_FILTER_THRESH_MM_DEFAULT \ 03115 ((int16_t) -70) 03116 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_FILTER_THRESH_MM_DEFAULT \ 03117 ((int16_t) 70) 03118 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_RATE_MCPS_DEFAULT \ 03119 ((uint16_t) 5120) 03120 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_PHASECAL_TIMEOUT_US_DEFAULT \ 03121 ((uint32_t) 15000) 03122 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_VALID_RATE_KCPS_DEFAULT \ 03123 ((uint16_t) 640) 03124 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_SIGMA_THRESHOLD_MM_DEFAULT \ 03125 ((uint16_t) 140) 03126 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_TIMEOUT_US_DEFAULT \ 03127 ((uint32_t) 2000) 03128 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_BIN_TIMEOUT_US_DEFAULT \ 03129 ((uint32_t) 10000) 03130 #define VL53LX_TUNINGPARM_OFFSET_CAL_DSS_RATE_MCPS_DEFAULT \ 03131 ((uint16_t) 2560) 03132 #define VL53LX_TUNINGPARM_OFFSET_CAL_PHASECAL_TIMEOUT_US_DEFAULT \ 03133 ((uint32_t) 15000) 03134 #define VL53LX_TUNINGPARM_OFFSET_CAL_MM_TIMEOUT_US_DEFAULT \ 03135 ((uint32_t) 13000) 03136 #define VL53LX_TUNINGPARM_OFFSET_CAL_RANGE_TIMEOUT_US_DEFAULT \ 03137 ((uint32_t) 13000) 03138 #define VL53LX_TUNINGPARM_OFFSET_CAL_PRE_SAMPLES_DEFAULT \ 03139 ((uint8_t) 8) 03140 #define VL53LX_TUNINGPARM_OFFSET_CAL_MM1_SAMPLES_DEFAULT \ 03141 ((uint8_t) 40) 03142 #define VL53LX_TUNINGPARM_OFFSET_CAL_MM2_SAMPLES_DEFAULT \ 03143 ((uint8_t) 9) 03144 #define VL53LX_TUNINGPARM_ZONE_CAL_DSS_RATE_MCPS_DEFAULT \ 03145 ((uint16_t) 5120) 03146 #define VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_TIMEOUT_US_DEFAULT \ 03147 ((uint32_t) 15000) 03148 #define VL53LX_TUNINGPARM_ZONE_CAL_DSS_TIMEOUT_US_DEFAULT \ 03149 ((uint32_t) 2000) 03150 #define VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_NUM_SAMPLES_DEFAULT \ 03151 ((uint16_t) 16) 03152 #define VL53LX_TUNINGPARM_ZONE_CAL_RANGE_TIMEOUT_US_DEFAULT \ 03153 ((uint32_t) 1000) 03154 #define VL53LX_TUNINGPARM_ZONE_CAL_ZONE_NUM_SAMPLES_DEFAULT \ 03155 ((uint16_t) 8) 03156 #define VL53LX_TUNINGPARM_SPADMAP_VCSEL_PERIOD_DEFAULT \ 03157 ((uint8_t) 18) 03158 #define VL53LX_TUNINGPARM_SPADMAP_VCSEL_START_DEFAULT \ 03159 ((uint8_t) 15) 03160 #define VL53LX_TUNINGPARM_SPADMAP_RATE_LIMIT_MCPS_DEFAULT \ 03161 ((uint16_t) 12) 03162 #define VL53LX_TUNINGPARM_LITE_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT \ 03163 ((uint16_t) 2560) 03164 #define VL53LX_TUNINGPARM_RANGING_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT \ 03165 ((uint16_t) 5120) 03166 #define VL53LX_TUNINGPARM_MZ_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT \ 03167 ((uint16_t) 5120) 03168 #define VL53LX_TUNINGPARM_TIMED_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT \ 03169 ((uint16_t) 2560) 03170 #define VL53LX_TUNINGPARM_LITE_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \ 03171 ((uint32_t) 1000) 03172 #define VL53LX_TUNINGPARM_RANGING_LONG_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \ 03173 ((uint32_t) 15000) 03174 #define VL53LX_TUNINGPARM_RANGING_MED_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \ 03175 ((uint32_t) 9000) 03176 #define VL53LX_TUNINGPARM_RANGING_SHORT_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \ 03177 ((uint32_t) 6000) 03178 #define VL53LX_TUNINGPARM_MZ_LONG_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \ 03179 ((uint32_t) 15000) 03180 #define VL53LX_TUNINGPARM_MZ_MED_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \ 03181 ((uint32_t) 9000) 03182 #define VL53LX_TUNINGPARM_MZ_SHORT_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \ 03183 ((uint32_t) 6000) 03184 #define VL53LX_TUNINGPARM_TIMED_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \ 03185 ((uint32_t) 1000) 03186 #define VL53LX_TUNINGPARM_LITE_MM_CONFIG_TIMEOUT_US_DEFAULT \ 03187 ((uint32_t) 2000) 03188 #define VL53LX_TUNINGPARM_RANGING_MM_CONFIG_TIMEOUT_US_DEFAULT \ 03189 ((uint32_t) 2000) 03190 #define VL53LX_TUNINGPARM_MZ_MM_CONFIG_TIMEOUT_US_DEFAULT \ 03191 ((uint32_t) 2000) 03192 #define VL53LX_TUNINGPARM_TIMED_MM_CONFIG_TIMEOUT_US_DEFAULT \ 03193 ((uint32_t) 2000) 03194 #define VL53LX_TUNINGPARM_LITE_RANGE_CONFIG_TIMEOUT_US_DEFAULT \ 03195 ((uint32_t) 63000) 03196 #define VL53LX_TUNINGPARM_RANGING_RANGE_CONFIG_TIMEOUT_US_DEFAULT \ 03197 ((uint32_t) 2500) 03198 #define VL53LX_TUNINGPARM_MZ_RANGE_CONFIG_TIMEOUT_US_DEFAULT \ 03199 ((uint32_t) 2500) 03200 #define VL53LX_TUNINGPARM_TIMED_RANGE_CONFIG_TIMEOUT_US_DEFAULT \ 03201 ((uint32_t) 13000) 03202 #define VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_MARGIN_DEFAULT \ 03203 ((uint16_t) 0) 03204 #define VL53LX_TUNINGPARM_DYNXTALK_NOISE_MARGIN_DEFAULT \ 03205 ((uint32_t) 100) 03206 #define VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT_DEFAULT \ 03207 ((uint32_t) 0) 03208 #define VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT_HI_DEFAULT \ 03209 ((uint8_t) 0) 03210 #define VL53LX_TUNINGPARM_DYNXTALK_SAMPLE_LIMIT_DEFAULT \ 03211 ((uint32_t) 200) 03212 #define VL53LX_TUNINGPARM_DYNXTALK_SINGLE_XTALK_DELTA_DEFAULT \ 03213 ((uint32_t) 2048) 03214 #define VL53LX_TUNINGPARM_DYNXTALK_AVERAGED_XTALK_DELTA_DEFAULT \ 03215 ((uint32_t) 308) 03216 #define VL53LX_TUNINGPARM_DYNXTALK_CLIP_LIMIT_DEFAULT \ 03217 ((uint32_t) 10240) 03218 #define VL53LX_TUNINGPARM_DYNXTALK_SCALER_CALC_METHOD_DEFAULT \ 03219 ((uint8_t) 0) 03220 #define VL53LX_TUNINGPARM_DYNXTALK_XGRADIENT_SCALER_DEFAULT \ 03221 ((int16_t) 256) 03222 #define VL53LX_TUNINGPARM_DYNXTALK_YGRADIENT_SCALER_DEFAULT \ 03223 ((int16_t) 256) 03224 #define VL53LX_TUNINGPARM_DYNXTALK_USER_SCALER_SET_DEFAULT \ 03225 ((uint8_t) 0) 03226 #define VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_COR_SINGLE_APPLY_DEFAULT \ 03227 ((uint8_t) 0) 03228 #define VL53LX_TUNINGPARM_DYNXTALK_XTALK_AMB_THRESHOLD_DEFAULT \ 03229 ((uint32_t) 128) 03230 #define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_AMB_THRESHOLD_KCPS_DEFAULT \ 03231 ((uint32_t) 57671680) 03232 #define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_SAMPLE_LIMIT_DEFAULT \ 03233 ((uint32_t) 40) 03234 #define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_XTALK_OFFSET_KCPS_DEFAULT \ 03235 ((uint32_t) 410) 03236 #define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_MIN_RANGE_MM_DEFAULT \ 03237 ((uint16_t) 900) 03238 #define VL53LX_TUNINGPARM_LOWPOWERAUTO_VHV_LOOP_BOUND_DEFAULT \ 03239 ((uint8_t) 3) 03240 #define VL53LX_TUNINGPARM_LOWPOWERAUTO_MM_CONFIG_TIMEOUT_US_DEFAULT \ 03241 ((uint32_t) 1) 03242 #define VL53LX_TUNINGPARM_LOWPOWERAUTO_RANGE_CONFIG_TIMEOUT_US_DEFAULT \ 03243 ((uint32_t) 8000) 03244 #define VL53LX_TUNINGPARM_VERY_SHORT_DSS_RATE_MCPS_DEFAULT \ 03245 ((uint16_t) 10240) 03246 #define VL53LX_TUNINGPARM_PHASECAL_PATCH_POWER_DEFAULT \ 03247 ((uint32_t) 0) 03248 #define VL53LX_TUNINGPARM_HIST_MERGE_DEFAULT \ 03249 ((uint32_t) 1) 03250 #define VL53LX_TUNINGPARM_RESET_MERGE_THRESHOLD_DEFAULT \ 03251 ((uint32_t) 15000) 03252 #define VL53LX_TUNINGPARM_HIST_MERGE_MAX_SIZE_DEFAULT \ 03253 ((uint32_t) 6) 03254 #define VL53LX_TUNINGPARM_DYNXTALK_MAX_SMUDGE_FACTOR_DEFAULT \ 03255 ((uint32_t) 2000) 03256 03257 03258 03259 /* vl53lx_preset_setup.h */ 03260 03261 03262 /* indexes for the bare driver tuning setting API function */ 03263 03264 enum VL53LX_Tuning_t { 03265 VL53LX_TUNING_VERSION = 0, 03266 VL53LX_TUNING_PROXY_MIN, 03267 VL53LX_TUNING_SINGLE_TARGET_XTALK_TARGET_DISTANCE_MM, 03268 VL53LX_TUNING_SINGLE_TARGET_XTALK_SAMPLE_NUMBER, 03269 VL53LX_TUNING_MIN_AMBIENT_DMAX_VALID, 03270 VL53LX_TUNING_MAX_SIMPLE_OFFSET_CALIBRATION_SAMPLE_NUMBER, 03271 VL53LX_TUNING_XTALK_FULL_ROI_TARGET_DISTANCE_MM, 03272 VL53LX_TUNING_SIMPLE_OFFSET_CALIBRATION_REPEAT, 03273 VL53LX_TUNING_XTALK_FULL_ROI_BIN_SUM_MARGIN, 03274 VL53LX_TUNING_XTALK_FULL_ROI_DEFAULT_OFFSET, 03275 VL53LX_TUNING_ZERO_DISTANCE_OFFSET_NON_LINEAR_FACTOR, 03276 VL53LX_TUNING_MAX_TUNABLE_KEY 03277 }; 03278 03279 03280 /* default values for the tuning settings parameters */ 03281 #define TUNING_VERSION 0x0007 03282 03283 #define TUNING_PROXY_MIN -30 /* min distance in mm */ 03284 #define TUNING_SINGLE_TARGET_XTALK_TARGET_DISTANCE_MM 600 03285 /* Target distance in mm for single target Xtalk */ 03286 #define TUNING_SINGLE_TARGET_XTALK_SAMPLE_NUMBER 50 03287 /* Number of sample used for single target Xtalk */ 03288 #define TUNING_MIN_AMBIENT_DMAX_VALID 8 03289 /* Minimum ambient level to state the Dmax returned by the device is valid */ 03290 #ifdef SMALL_FOOTPRINT 03291 #define TUNING_MAX_SIMPLE_OFFSET_CALIBRATION_SAMPLE_NUMBER 50 03292 #else 03293 #define TUNING_MAX_SIMPLE_OFFSET_CALIBRATION_SAMPLE_NUMBER 10 03294 #endif 03295 /* Maximum loops to perform simple offset calibration */ 03296 #define TUNING_XTALK_FULL_ROI_TARGET_DISTANCE_MM 600 03297 /* Target distance in mm for target Xtalk from Bins method*/ 03298 #ifdef SMALL_FOOTPRINT 03299 #define TUNING_SIMPLE_OFFSET_CALIBRATION_REPEAT 1 03300 #else 03301 #define TUNING_SIMPLE_OFFSET_CALIBRATION_REPEAT 3 03302 #endif 03303 /* Number of loops done during the simple offset calibration*/ 03304 #define TUNING_ZERO_DISTANCE_OFFSET_NON_LINEAR_FACTOR_DEFAULT 9 03305 /* zero distance offset calibration non linear compensation default value */ 03306 03307 /* The following settings are related to the fix for ticket EwokP #558410 */ 03308 #define TUNING_XTALK_FULL_ROI_BIN_SUM_MARGIN 24 03309 /* Acceptance margin for the xtalk_shape bin_data sum computation */ 03310 #define TUNING_XTALK_FULL_ROI_DEFAULT_OFFSET 50 03311 /* Recovery value for Xtalk compensation plane offset in kcps */ 03312 /* 50 stands for ~0.10 kcps cover glass in 7.9 format */ 03313 /* End of settings related to the fix for ticket EwokP #558410 */ 03314 03315 03316 03317 03318 // define from vl53lx_platform_user_config 03319 03320 #define VL53LX_BYTES_PER_WORD 2 03321 #define VL53LX_BYTES_PER_DWORD 4 03322 03323 /* Define polling delays */ 03324 #define VL53LX_BOOT_COMPLETION_POLLING_TIMEOUT_MS 500 03325 #define VL53LX_RANGE_COMPLETION_POLLING_TIMEOUT_MS 2000 03326 #define VL53LX_TEST_COMPLETION_POLLING_TIMEOUT_MS 10000 03327 03328 #define VL53LX_POLLING_DELAY_MS 1 03329 03330 /* Define LLD TuningParms Page Base Address 03331 * - Part of Patch_AddedTuningParms_11761 03332 */ 03333 #define VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS 0x8000 03334 #define VL53LX_TUNINGPARM_PRIVATE_PAGE_BASE_ADDRESS 0xC000 03335 03336 #define VL53LX_OFFSET_CAL_MIN_MM1_EFFECTIVE_SPADS 0x0500 03337 /*!< Lower Limit for the MM1 effective SPAD count during offset 03338 calibration Format 8.8 0x0500 -> 5.0 effective SPADs */ 03339 03340 #define VL53LX_GAIN_FACTOR__STANDARD_DEFAULT 0x0800 03341 /*!< Default standard ranging gain correction factor 03342 1.11 format. 1.0 = 0x0800, 0.980 = 0x07D7 */ 03343 #define VL53LX_GAIN_FACTOR__HISTOGRAM_DEFAULT 0x0800 03344 /*!< Default histogram ranging gain correction factor 03345 1.11 format. 1.0 = 0x0800, 0.975 = 0x07CC */ 03346 03347 03348 #define VL53LX_OFFSET_CAL_MIN_EFFECTIVE_SPADS 0x0500 03349 /*!< Lower Limit for the MM1 effective SPAD count during offset 03350 calibration Format 8.8 0x0500 -> 5.0 effective SPADs */ 03351 03352 #define VL53LX_OFFSET_CAL_MAX_PRE_PEAK_RATE_MCPS 0x1900 03353 /*!< Max Limit for the pre range preak rate during offset 03354 calibration Format 9.7 0x1900 -> 50.0 Mcps. 03355 If larger then in pile up */ 03356 03357 #define VL53LX_OFFSET_CAL_MAX_SIGMA_MM 0x0040 03358 /*!< Max sigma estimate limit during offset calibration 03359 Check applies to pre-range, mm1 and mm2 ranges 03360 Format 14.2 0x0040 -> 16.0mm. */ 03361 03362 #define VL53LX_ZONE_CAL_MAX_PRE_PEAK_RATE_MCPS 0x1900 03363 /*!< Max Peak Rate Limit for the during zone calibration 03364 Format 9.7 0x1900 -> 50.0 Mcps. 03365 If larger then in pile up */ 03366 03367 #define VL53LX_ZONE_CAL_MAX_SIGMA_MM 0x0040 03368 /*!< Max sigma estimate limit during zone calibration 03369 Format 14.2 0x0040 -> 16.0mm. */ 03370 03371 03372 #define VL53LX_XTALK_EXTRACT_MAX_SIGMA_MM 0x008C 03373 /*!< Max Sigma value allowed for a successful xtalk extraction 03374 Format 14.2 0x008C -> 35.0 mm.*/ 03375 03376 #ifndef VL53LX_MAX_USER_ZONES 03377 #define VL53LX_MAX_USER_ZONES 16 03378 /*!< Max number of user Zones - maximal limitation from 03379 FW stream divide - value of 254 */ 03380 #endif 03381 03382 #define VL53LX_MAX_RANGE_RESULTS 4 03383 #define VL53LX_BUFFER_SIZE 5 03384 03385 /*!< Sets the maximum number of targets distances the histogram 03386 post processing can generate */ 03387 03388 #define VL53LX_MAX_STRING_LENGTH 512 03389 /*!< Sets the maximum string length */ 03390 03391 03392 // typedef from vl53lx_types.h 03393 03394 03395 #ifndef NULL 03396 #error "Error NULL definition should be done. Please add required include " 03397 #endif 03398 03399 03400 #if !defined(STDINT_H) && !defined(_STDINT_H) && !defined(_GCC_STDINT_H) && !defined(__STDINT_DECLS) && !defined(_GCC_WRAP_STDINT_H) && !defined(_STDINT) 03401 03402 #pragma message("Please review type definition of STDINT define for your platform and add to list above ") 03403 03404 typedef unsigned long long uint64_t; 03405 typedef unsigned int uint32_t; 03406 typedef int int32_t; 03407 typedef unsigned short uint16_t; 03408 typedef short int16_t; 03409 typedef unsigned char uint8_t; 03410 typedef signed char int8_t; 03411 03412 #endif 03413 03414 typedef uint32_t FixPoint1616_t; 03415 03416 03417 03418 // define from vl53lx_error_codes.h 03419 03420 03421 03422 /* 03423 **************************************** 03424 * PRIVATE define do not edit 03425 *************************************** 03426 */ 03427 03428 /* 03429 * @defgroup VL53LX_define_Error_group Error and Warning code returned by API 03430 * The following DEFINE are used to identify the PAL ERROR 03431 * @{ 03432 */ 03433 03434 typedef int8_t VL53LX_Error; 03435 03436 #define VL53LX_ERROR_NONE ((VL53LX_Error) 0) 03437 #define VL53LX_ERROR_CALIBRATION_WARNING ((VL53LX_Error) - 1) 03438 /*!< Warning invalid calibration data may be in used 03439 * \a VL53LX_InitData() 03440 * \a VL53LX_GetOffsetCalibrationData 03441 * \a VL53LX_SetOffsetCalibrationData 03442 */ 03443 #define VL53LX_ERROR_MIN_CLIPPED ((VL53LX_Error) - 2) 03444 /*!< Warning parameter passed was clipped to min before to be applied */ 03445 03446 #define VL53LX_ERROR_UNDEFINED ((VL53LX_Error) - 3) 03447 /*!< Unqualified error */ 03448 #define VL53LX_ERROR_INVALID_PARAMS ((VL53LX_Error) - 4) 03449 /*!< Parameter passed is invalid or out of range */ 03450 #define VL53LX_ERROR_NOT_SUPPORTED ((VL53LX_Error) - 5) 03451 /*!< Function is not supported in current mode or configuration */ 03452 #define VL53LX_ERROR_RANGE_ERROR ((VL53LX_Error) - 6) 03453 /*!< Device report a ranging error interrupt status */ 03454 #define VL53LX_ERROR_TIME_OUT ((VL53LX_Error) - 7) 03455 /*!< Aborted due to time out */ 03456 #define VL53LX_ERROR_MODE_NOT_SUPPORTED ((VL53LX_Error) - 8) 03457 /*!< Asked mode is not supported by the device */ 03458 #define VL53LX_ERROR_BUFFER_TOO_SMALL ((VL53LX_Error) - 9) 03459 /*!< ... */ 03460 #define VL53LX_ERROR_COMMS_BUFFER_TOO_SMALL ((VL53LX_Error) - 10) 03461 /*!< Supplied buffer is larger than I2C supports */ 03462 #define VL53LX_ERROR_GPIO_NOT_EXISTING ((VL53LX_Error) - 11) 03463 /*!< User tried to setup a non-existing GPIO pin */ 03464 #define VL53LX_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED ((VL53LX_Error) - 12) 03465 /*!< unsupported GPIO functionality */ 03466 #define VL53LX_ERROR_CONTROL_INTERFACE ((VL53LX_Error) - 13) 03467 /*!< error reported from IO functions */ 03468 #define VL53LX_ERROR_INVALID_COMMAND ((VL53LX_Error) - 14) 03469 /*!< The command is not allowed in the current device state 03470 * (power down) 03471 */ 03472 #define VL53LX_ERROR_DIVISION_BY_ZERO ((VL53LX_Error) - 15) 03473 /*!< In the function a division by zero occurs */ 03474 #define VL53LX_ERROR_REF_SPAD_INIT ((VL53LX_Error) - 16) 03475 /*!< Error during reference SPAD initialization */ 03476 #define VL53LX_ERROR_GPH_SYNC_CHECK_FAIL ((VL53LX_Error) - 17) 03477 /*!< GPH sync interrupt check fail - API out of sync with device*/ 03478 #define VL53LX_ERROR_STREAM_COUNT_CHECK_FAIL ((VL53LX_Error) - 18) 03479 /*!< Stream count check fail - API out of sync with device */ 03480 #define VL53LX_ERROR_GPH_ID_CHECK_FAIL ((VL53LX_Error) - 19) 03481 /*!< GPH ID check fail - API out of sync with device */ 03482 #define VL53LX_ERROR_ZONE_STREAM_COUNT_CHECK_FAIL ((VL53LX_Error) - 20) 03483 /*!< Zone dynamic config stream count check failed - API out of sync */ 03484 #define VL53LX_ERROR_ZONE_GPH_ID_CHECK_FAIL ((VL53LX_Error) - 21) 03485 /*!< Zone dynamic config GPH ID check failed - API out of sync */ 03486 03487 #define VL53LX_ERROR_XTALK_EXTRACTION_NO_SAMPLE_FAIL ((VL53LX_Error) - 22) 03488 /*!< Thrown when run_xtalk_extraction fn has 0 successful samples 03489 * when using the full array to sample the xtalk. In this case there is 03490 * not enough information to generate new Xtalk parm info. The function 03491 * will exit and leave the current xtalk parameters unaltered 03492 */ 03493 #define VL53LX_ERROR_XTALK_EXTRACTION_SIGMA_LIMIT_FAIL ((VL53LX_Error) - 23) 03494 /*!< Thrown when run_xtalk_extraction fn has found that the 03495 * avg sigma estimate of the full array xtalk sample is > than the 03496 * maximal limit allowed. In this case the xtalk sample is too noisy for 03497 * measurement. The function will exit and leave the current xtalk 03498 * parameters unaltered. 03499 */ 03500 03501 03502 #define VL53LX_ERROR_OFFSET_CAL_NO_SAMPLE_FAIL ((VL53LX_Error) - 24) 03503 /*!< Thrown if there one of stages has no valid offset calibration 03504 * samples. A fatal error calibration not valid 03505 */ 03506 #define VL53LX_ERROR_OFFSET_CAL_NO_SPADS_ENABLED_FAIL ((VL53LX_Error) - 25) 03507 /*!< Thrown if there one of stages has zero effective SPADS 03508 * Traps the case when MM1 SPADs is zero. 03509 * A fatal error calibration not valid 03510 */ 03511 #define VL53LX_ERROR_ZONE_CAL_NO_SAMPLE_FAIL ((VL53LX_Error) - 26) 03512 /*!< Thrown if then some of the zones have no valid samples 03513 * A fatal error calibration not valid 03514 */ 03515 03516 #define VL53LX_ERROR_TUNING_PARM_KEY_MISMATCH ((VL53LX_Error) - 27) 03517 /*!< Thrown if the tuning file key table version does not match with 03518 * expected value. The driver expects the key table version to match 03519 * the compiled default version number in the define 03520 * #VL53LX_TUNINGPARM_KEY_TABLE_VERSION_DEFAULT 03521 */ 03522 03523 #define VL53LX_WARNING_REF_SPAD_CHAR_NOT_ENOUGH_SPADS ((VL53LX_Error) - 28) 03524 /*!< Thrown if there are less than 5 good SPADs are available. */ 03525 #define VL53LX_WARNING_REF_SPAD_CHAR_RATE_TOO_HIGH ((VL53LX_Error) - 29) 03526 /*!< Thrown if the final reference rate is greater than 03527 * the upper reference rate limit - default is 40 Mcps. 03528 * Implies a minimum Q3 (x10) SPAD (5) selected 03529 */ 03530 #define VL53LX_WARNING_REF_SPAD_CHAR_RATE_TOO_LOW ((VL53LX_Error) - 30) 03531 /*!< Thrown if the final reference rate is less than 03532 * the lower reference rate limit - default is 10 Mcps. 03533 * Implies maximum Q1 (x1) SPADs selected 03534 */ 03535 03536 03537 #define VL53LX_WARNING_OFFSET_CAL_MISSING_SAMPLES ((VL53LX_Error) - 31) 03538 /*!< Thrown if there is less than the requested number of 03539 * valid samples. 03540 */ 03541 #define VL53LX_WARNING_OFFSET_CAL_SIGMA_TOO_HIGH ((VL53LX_Error) - 32) 03542 /*!< Thrown if the offset calibration range sigma estimate is greater 03543 * than 8.0 mm. This is the recommended min value to yield a stable 03544 * offset measurement 03545 */ 03546 #define VL53LX_WARNING_OFFSET_CAL_RATE_TOO_HIGH ((VL53LX_Error) - 33) 03547 /*!< Thrown when VL53LX_run_offset_calibration() peak rate is greater 03548 * than that 50.0Mcps. This is the recommended max rate to avoid 03549 * pile-up influencing the offset measurement 03550 */ 03551 #define VL53LX_WARNING_OFFSET_CAL_SPAD_COUNT_TOO_LOW ((VL53LX_Error) - 34) 03552 /*!< Thrown when VL53LX_run_offset_calibration() when one of stages 03553 * range has less that 5.0 effective SPADS. This is the recommended 03554 * min value to yield a stable offset 03555 */ 03556 03557 03558 #define VL53LX_WARNING_ZONE_CAL_MISSING_SAMPLES ((VL53LX_Error) - 35) 03559 /*!< Thrown if one of more of the zones have less than 03560 * the requested number of valid samples 03561 */ 03562 #define VL53LX_WARNING_ZONE_CAL_SIGMA_TOO_HIGH ((VL53LX_Error) - 36) 03563 /*!< Thrown if one or more zones have sigma estimate value greater 03564 * than 8.0 mm. This is the recommended min value to yield a stable 03565 * offset measurement 03566 */ 03567 #define VL53LX_WARNING_ZONE_CAL_RATE_TOO_HIGH ((VL53LX_Error) - 37) 03568 /*!< Thrown if one of more zones have peak rate higher than 03569 * that 50.0Mcps. This is the recommended max rate to avoid 03570 * pile-up influencing the offset measurement 03571 */ 03572 03573 03574 #define VL53LX_WARNING_XTALK_MISSING_SAMPLES ((VL53LX_Error) - 38) 03575 /*!< Thrown to notify that some of the xtalk samples did not yield 03576 * valid ranging pulse data while attempting to measure 03577 * the xtalk signal in vl53lx_run_xtalk_extract(). This can signify any 03578 * of the zones are missing samples, for further debug information the 03579 * xtalk_results struct should be referred to. This warning is for 03580 * notification only, xtalk pulse and shape have still been generated 03581 */ 03582 #define VL53LX_WARNING_XTALK_NO_SAMPLES_FOR_GRADIENT ((VL53LX_Error) - 39) 03583 /*!< Thrown to notify that some of the xtalk samples used for gradient 03584 * generation did not yield valid ranging pulse data while attempting to 03585 * measure the xtalk signal in vl53lx_run_xtalk_extract(). This can 03586 * signify that any one of the zones 0-3 yielded no successful samples. 03587 * xtalk_results struct should be referred to for further debug info. 03588 * This warning is for notification only, the xtalk pulse and shape 03589 * have still been generated. 03590 */ 03591 #define VL53LX_WARNING_XTALK_SIGMA_LIMIT_FOR_GRADIENT ((VL53LX_Error) - 40) 03592 /*!< Thrown to notify that some of the xtalk samples used for gradient 03593 * generation did not pass the sigma limit check while attempting to 03594 * measure the xtalk signal in vl53lx_run_xtalk_extract(). This can 03595 * signify that any one of the zones 0-3 yielded an avg sigma_mm 03596 * value > the limit. The xtalk_results struct should be referred to for 03597 * further debug info. 03598 * This warning is for notification only, the xtalk pulse and shape 03599 * have still been generated. 03600 */ 03601 03602 #define VL53LX_ERROR_NOT_IMPLEMENTED ((VL53LX_Error) - 41) 03603 /*!< Tells requested functionality has not been implemented yet or 03604 * not compatible with the device 03605 */ 03606 #define VL53LX_ERROR_PLATFORM_SPECIFIC_START ((VL53LX_Error) - 60) 03607 /*!< Tells the starting code for platform */ 03608 /** @} VL53LX_define_Error_group */ 03609 03610 03611 03612 /* vl53lx_dmax_private_structs.h */ 03613 03614 03615 03616 03617 03618 03619 03620 03621 typedef struct { 03622 03623 uint32_t VL53LX_p_037; 03624 03625 03626 03627 uint8_t VL53LX_p_063; 03628 03629 03630 uint8_t VL53LX_p_064; 03631 03632 03633 03634 uint16_t VL53LX_p_065; 03635 03636 03637 uint16_t VL53LX_p_066; 03638 03639 03640 uint16_t VL53LX_p_067; 03641 03642 03643 uint16_t VL53LX_p_038; 03644 03645 03646 03647 uint32_t VL53LX_p_009; 03648 03649 03650 uint32_t VL53LX_p_033; 03651 03652 03653 03654 uint16_t VL53LX_p_034; 03655 03656 03657 03658 uint16_t VL53LX_p_004; 03659 03660 03661 03662 uint32_t VL53LX_p_028; 03663 03664 03665 uint32_t VL53LX_p_035; 03666 03667 03668 03669 int16_t VL53LX_p_036; 03670 03671 03672 int16_t VL53LX_p_022; 03673 03674 03675 03676 } VL53LX_hist_gen3_dmax_private_data_t; 03677 03678 03679 03680 03681 // def & typedef from vl53lx_ll_device.h 03682 03683 03684 #define VL53LX_I2C 0x01 03685 #define VL53LX_SPI 0x00 03686 03687 03688 03689 03690 03691 typedef uint8_t VL53LX_WaitMethod; 03692 03693 #define VL53LX_WAIT_METHOD_BLOCKING ((VL53LX_WaitMethod) 0) 03694 #define VL53LX_WAIT_METHOD_NON_BLOCKING ((VL53LX_WaitMethod) 1) 03695 03696 03697 03698 03699 typedef uint8_t VL53LX_DeviceState; 03700 03701 #define VL53LX_DEVICESTATE_POWERDOWN ((VL53LX_DeviceState) 0) 03702 #define VL53LX_DEVICESTATE_HW_STANDBY ((VL53LX_DeviceState) 1) 03703 #define VL53LX_DEVICESTATE_FW_COLDBOOT ((VL53LX_DeviceState) 2) 03704 #define VL53LX_DEVICESTATE_SW_STANDBY ((VL53LX_DeviceState) 3) 03705 #define VL53LX_DEVICESTATE_RANGING_DSS_AUTO ((VL53LX_DeviceState) 4) 03706 #define VL53LX_DEVICESTATE_RANGING_DSS_MANUAL ((VL53LX_DeviceState) 5) 03707 #define VL53LX_DEVICESTATE_RANGING_WAIT_GPH_SYNC ((VL53LX_DeviceState) 6) 03708 #define VL53LX_DEVICESTATE_RANGING_GATHER_DATA ((VL53LX_DeviceState) 7) 03709 #define VL53LX_DEVICESTATE_RANGING_OUTPUT_DATA ((VL53LX_DeviceState) 8) 03710 03711 #define VL53LX_DEVICESTATE_UNKNOWN ((VL53LX_DeviceState) 98) 03712 #define VL53LX_DEVICESTATE_ERROR ((VL53LX_DeviceState) 99) 03713 03714 03715 03716 03717 03718 typedef uint8_t VL53LX_DeviceZonePreset; 03719 03720 #define VL53LX_DEVICEZONEPRESET_NONE \ 03721 ((VL53LX_DeviceZonePreset) 0) 03722 03723 #define VL53LX_DEVICEZONEPRESET_XTALK_PLANAR \ 03724 ((VL53LX_DeviceZonePreset) 1) 03725 #define VL53LX_DEVICEZONEPRESET_1X1_SIZE_16X16 \ 03726 ((VL53LX_DeviceZonePreset) 2) 03727 #define VL53LX_DEVICEZONEPRESET_1X2_SIZE_16X8 \ 03728 ((VL53LX_DeviceZonePreset) 3) 03729 #define VL53LX_DEVICEZONEPRESET_2X1_SIZE_8X16 \ 03730 ((VL53LX_DeviceZonePreset) 4) 03731 #define VL53LX_DEVICEZONEPRESET_2X2_SIZE_8X8 \ 03732 ((VL53LX_DeviceZonePreset) 5) 03733 #define VL53LX_DEVICEZONEPRESET_3X3_SIZE_5X5 \ 03734 ((VL53LX_DeviceZonePreset) 6) 03735 #define VL53LX_DEVICEZONEPRESET_4X4_SIZE_4X4 \ 03736 ((VL53LX_DeviceZonePreset) 7) 03737 #define VL53LX_DEVICEZONEPRESET_5X5_SIZE_4X4 \ 03738 ((VL53LX_DeviceZonePreset) 8) 03739 #define VL53LX_DEVICEZONEPRESET_11X11_SIZE_5X5 \ 03740 ((VL53LX_DeviceZonePreset) 9) 03741 #define VL53LX_DEVICEZONEPRESET_13X13_SIZE_4X4 \ 03742 ((VL53LX_DeviceZonePreset) 10) 03743 03744 #define VL53LX_DEVICEZONEPRESET_1X1_SIZE_4X4_POS_8X8 \ 03745 ((VL53LX_DeviceZonePreset) 11) 03746 03747 #define VL53LX_DEVICEZONEPRESET_CUSTOM \ 03748 ((VL53LX_DeviceZonePreset) 255) 03749 03750 03751 03752 03753 03754 typedef uint8_t VL53LX_DevicePresetModes; 03755 03756 #define VL53LX_DEVICEPRESETMODE_NONE \ 03757 ((VL53LX_DevicePresetModes) 0) 03758 #define VL53LX_DEVICEPRESETMODE_STANDARD_RANGING \ 03759 ((VL53LX_DevicePresetModes) 1) 03760 #define VL53LX_DEVICEPRESETMODE_STANDARD_RANGING_SHORT_RANGE \ 03761 ((VL53LX_DevicePresetModes) 2) 03762 #define VL53LX_DEVICEPRESETMODE_STANDARD_RANGING_LONG_RANGE \ 03763 ((VL53LX_DevicePresetModes) 3) 03764 #define VL53LX_DEVICEPRESETMODE_STANDARD_RANGING_MM1_CAL \ 03765 ((VL53LX_DevicePresetModes) 4) 03766 #define VL53LX_DEVICEPRESETMODE_STANDARD_RANGING_MM2_CAL \ 03767 ((VL53LX_DevicePresetModes) 5) 03768 #define VL53LX_DEVICEPRESETMODE_TIMED_RANGING \ 03769 ((VL53LX_DevicePresetModes) 6) 03770 #define VL53LX_DEVICEPRESETMODE_TIMED_RANGING_SHORT_RANGE \ 03771 ((VL53LX_DevicePresetModes) 7) 03772 #define VL53LX_DEVICEPRESETMODE_TIMED_RANGING_LONG_RANGE \ 03773 ((VL53LX_DevicePresetModes) 8) 03774 #define VL53LX_DEVICEPRESETMODE_NEAR_FARRANGING \ 03775 ((VL53LX_DevicePresetModes) 9) 03776 #define VL53LX_DEVICEPRESETMODE_QUADRANT_RANGING \ 03777 ((VL53LX_DevicePresetModes) 10) 03778 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_RANGING \ 03779 ((VL53LX_DevicePresetModes) 11) 03780 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_RANGING_SHORT_TIMING \ 03781 ((VL53LX_DevicePresetModes) 12) 03782 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_CHARACTERISATION \ 03783 ((VL53LX_DevicePresetModes) 13) 03784 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_XTALK_PLANAR \ 03785 ((VL53LX_DevicePresetModes) 14) 03786 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_XTALK_MM1 \ 03787 ((VL53LX_DevicePresetModes) 15) 03788 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_XTALK_MM2 \ 03789 ((VL53LX_DevicePresetModes) 16) 03790 #define VL53LX_DEVICEPRESETMODE_OLT \ 03791 ((VL53LX_DevicePresetModes) 17) 03792 #define VL53LX_DEVICEPRESETMODE_SINGLESHOT_RANGING \ 03793 ((VL53LX_DevicePresetModes) 18) 03794 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_REF_ARRAY \ 03795 ((VL53LX_DevicePresetModes) 19) 03796 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_RANGING_WITH_MM1 \ 03797 ((VL53LX_DevicePresetModes) 20) 03798 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_RANGING_WITH_MM2 \ 03799 ((VL53LX_DevicePresetModes) 21) 03800 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_RANGING_MM1_CAL \ 03801 ((VL53LX_DevicePresetModes) 22) 03802 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_RANGING_MM2_CAL \ 03803 ((VL53LX_DevicePresetModes) 23) 03804 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_MULTIZONE \ 03805 ((VL53LX_DevicePresetModes) 24) 03806 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_MULTIZONE_SHORT_RANGE \ 03807 ((VL53LX_DevicePresetModes) 25) 03808 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_MULTIZONE_LONG_RANGE \ 03809 ((VL53LX_DevicePresetModes) 26) 03810 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_LONG_RANGE \ 03811 ((VL53LX_DevicePresetModes) 27) 03812 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_LONG_RANGE_MM1 \ 03813 ((VL53LX_DevicePresetModes) 28) 03814 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_LONG_RANGE_MM2 \ 03815 ((VL53LX_DevicePresetModes) 29) 03816 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_MEDIUM_RANGE \ 03817 ((VL53LX_DevicePresetModes) 30) 03818 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_MEDIUM_RANGE_MM1 \ 03819 ((VL53LX_DevicePresetModes) 31) 03820 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_MEDIUM_RANGE_MM2 \ 03821 ((VL53LX_DevicePresetModes) 32) 03822 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_SHORT_RANGE \ 03823 ((VL53LX_DevicePresetModes) 33) 03824 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_SHORT_RANGE_MM1 \ 03825 ((VL53LX_DevicePresetModes) 34) 03826 #define VL53LX_DEVICEPRESETMODE_HISTOGRAM_SHORT_RANGE_MM2 \ 03827 ((VL53LX_DevicePresetModes) 35) 03828 #define VL53LX_DEVICEPRESETMODE_LOWPOWERAUTO_SHORT_RANGE \ 03829 ((VL53LX_DevicePresetModes) 36) 03830 #define VL53LX_DEVICEPRESETMODE_LOWPOWERAUTO_MEDIUM_RANGE \ 03831 ((VL53LX_DevicePresetModes) 37) 03832 #define VL53LX_DEVICEPRESETMODE_LOWPOWERAUTO_LONG_RANGE \ 03833 ((VL53LX_DevicePresetModes) 38) 03834 #define VL53LX_DEVICEPRESETMODE_SPECIAL_HISTOGRAM_SHORT_RANGE \ 03835 ((VL53LX_DevicePresetModes) 39) 03836 03837 03838 03839 03840 03841 typedef uint8_t VL53LX_DeviceMeasurementModes; 03842 03843 #define VL53LX_DEVICEMEASUREMENTMODE_STOP \ 03844 ((VL53LX_DeviceMeasurementModes) 0x00) 03845 #define VL53LX_DEVICEMEASUREMENTMODE_SINGLESHOT \ 03846 ((VL53LX_DeviceMeasurementModes) 0x10) 03847 #define VL53LX_DEVICEMEASUREMENTMODE_BACKTOBACK \ 03848 ((VL53LX_DeviceMeasurementModes) 0x20) 03849 #define VL53LX_DEVICEMEASUREMENTMODE_TIMED \ 03850 ((VL53LX_DeviceMeasurementModes) 0x40) 03851 #define VL53LX_DEVICEMEASUREMENTMODE_ABORT \ 03852 ((VL53LX_DeviceMeasurementModes) 0x80) 03853 03854 03855 03856 03857 03858 typedef uint8_t VL53LX_OffsetCalibrationMode; 03859 03860 #define VL53LX_OFFSETCALIBRATIONMODE__NONE \ 03861 ((VL53LX_OffsetCalibrationMode) 0) 03862 #define VL53LX_OFFSETCALIBRATIONMODE__MM1_MM2__STANDARD \ 03863 ((VL53LX_OffsetCalibrationMode) 1) 03864 #define VL53LX_OFFSETCALIBRATIONMODE__MM1_MM2__HISTOGRAM \ 03865 ((VL53LX_OffsetCalibrationMode) 2) 03866 #define VL53LX_OFFSETCALIBRATIONMODE__MM1_MM2__STANDARD_PRE_RANGE_ONLY \ 03867 ((VL53LX_OffsetCalibrationMode) 3) 03868 #define VL53LX_OFFSETCALIBRATIONMODE__MM1_MM2__HISTOGRAM_PRE_RANGE_ONLY \ 03869 ((VL53LX_OffsetCalibrationMode) 4) 03870 03871 03872 03873 03874 03875 typedef uint8_t VL53LX_OffsetCorrectionMode; 03876 03877 #define VL53LX_OFFSETCORRECTIONMODE__NONE \ 03878 ((VL53LX_OffsetCorrectionMode) 0) 03879 #define VL53LX_OFFSETCORRECTIONMODE__MM1_MM2_OFFSETS \ 03880 ((VL53LX_OffsetCorrectionMode) 1) 03881 #define VL53LX_OFFSETCORRECTIONMODE__PER_VCSEL_OFFSETS \ 03882 ((VL53LX_OffsetCorrectionMode) 3) 03883 03884 03885 03886 03887 03888 typedef uint8_t VL53LX_DeviceDmaxMode; 03889 03890 #define VL53LX_DEVICEDMAXMODE__NONE \ 03891 ((VL53LX_DeviceDmaxMode) 0) 03892 #define VL53LX_DEVICEDMAXMODE__FMT_CAL_DATA \ 03893 ((VL53LX_DeviceDmaxMode) 1) 03894 #define VL53LX_DEVICEDMAXMODE__CUST_CAL_DATA \ 03895 ((VL53LX_DeviceDmaxMode) 2) 03896 03897 03898 03899 03900 03901 typedef uint8_t VL53LX_DeviceSequenceConfig; 03902 03903 #define VL53LX_DEVICESEQUENCECONFIG_VHV \ 03904 ((VL53LX_DeviceSequenceConfig) 0) 03905 #define VL53LX_DEVICESEQUENCECONFIG_PHASECAL \ 03906 ((VL53LX_DeviceSequenceConfig) 1) 03907 #define VL53LX_DEVICESEQUENCECONFIG_REFERENCE_PHASE \ 03908 ((VL53LX_DeviceSequenceConfig) 2) 03909 #define VL53LX_DEVICESEQUENCECONFIG_DSS1 \ 03910 ((VL53LX_DeviceSequenceConfig) 3) 03911 #define VL53LX_DEVICESEQUENCECONFIG_DSS2 \ 03912 ((VL53LX_DeviceSequenceConfig) 4) 03913 #define VL53LX_DEVICESEQUENCECONFIG_MM1 \ 03914 ((VL53LX_DeviceSequenceConfig) 5) 03915 #define VL53LX_DEVICESEQUENCECONFIG_MM2 \ 03916 ((VL53LX_DeviceSequenceConfig) 6) 03917 #define VL53LX_DEVICESEQUENCECONFIG_RANGE \ 03918 ((VL53LX_DeviceSequenceConfig) 7) 03919 03920 03921 03922 03923 03924 typedef uint8_t VL53LX_DeviceInterruptPolarity; 03925 03926 #define VL53LX_DEVICEINTERRUPTPOLARITY_ACTIVE_HIGH \ 03927 ((VL53LX_DeviceInterruptPolarity) 0x00) 03928 #define VL53LX_DEVICEINTERRUPTPOLARITY_ACTIVE_LOW \ 03929 ((VL53LX_DeviceInterruptPolarity) 0x10) 03930 #define VL53LX_DEVICEINTERRUPTPOLARITY_BIT_MASK \ 03931 ((VL53LX_DeviceInterruptPolarity) 0x10) 03932 #define VL53LX_DEVICEINTERRUPTPOLARITY_CLEAR_MASK \ 03933 ((VL53LX_DeviceInterruptPolarity) 0xEF) 03934 03935 03936 03937 03938 03939 typedef uint8_t VL53LX_DeviceGpioMode; 03940 03941 #define VL53LX_DEVICEGPIOMODE_OUTPUT_CONSTANT_ZERO \ 03942 ((VL53LX_DeviceGpioMode) 0x00) 03943 #define VL53LX_DEVICEGPIOMODE_OUTPUT_RANGE_AND_ERROR_INTERRUPTS \ 03944 ((VL53LX_DeviceGpioMode) 0x01) 03945 #define VL53LX_DEVICEGPIOMODE_OUTPUT_TIMIER_INTERRUPTS \ 03946 ((VL53LX_DeviceGpioMode) 0x02) 03947 #define VL53LX_DEVICEGPIOMODE_OUTPUT_RANGE_MODE_INTERRUPT_STATUS \ 03948 ((VL53LX_DeviceGpioMode) 0x03) 03949 #define VL53LX_DEVICEGPIOMODE_OUTPUT_SLOW_OSCILLATOR_CLOCK \ 03950 ((VL53LX_DeviceGpioMode) 0x04) 03951 #define VL53LX_DEVICEGPIOMODE_BIT_MASK \ 03952 ((VL53LX_DeviceGpioMode) 0x0F) 03953 #define VL53LX_DEVICEGPIOMODE_CLEAR_MASK \ 03954 ((VL53LX_DeviceGpioMode) 0xF0) 03955 03956 03957 03958 03959 03960 typedef uint8_t VL53LX_DeviceError; 03961 03962 #define VL53LX_DEVICEERROR_NOUPDATE \ 03963 ((VL53LX_DeviceError) 0) 03964 03965 #define VL53LX_DEVICEERROR_VCSELCONTINUITYTESTFAILURE \ 03966 ((VL53LX_DeviceError) 1) 03967 #define VL53LX_DEVICEERROR_VCSELWATCHDOGTESTFAILURE \ 03968 ((VL53LX_DeviceError) 2) 03969 #define VL53LX_DEVICEERROR_NOVHVVALUEFOUND \ 03970 ((VL53LX_DeviceError) 3) 03971 #define VL53LX_DEVICEERROR_MSRCNOTARGET \ 03972 ((VL53LX_DeviceError) 4) 03973 #define VL53LX_DEVICEERROR_RANGEPHASECHECK \ 03974 ((VL53LX_DeviceError) 5) 03975 #define VL53LX_DEVICEERROR_SIGMATHRESHOLDCHECK \ 03976 ((VL53LX_DeviceError) 6) 03977 #define VL53LX_DEVICEERROR_PHASECONSISTENCY \ 03978 ((VL53LX_DeviceError) 7) 03979 #define VL53LX_DEVICEERROR_MINCLIP \ 03980 ((VL53LX_DeviceError) 8) 03981 #define VL53LX_DEVICEERROR_RANGECOMPLETE \ 03982 ((VL53LX_DeviceError) 9) 03983 #define VL53LX_DEVICEERROR_ALGOUNDERFLOW \ 03984 ((VL53LX_DeviceError) 10) 03985 #define VL53LX_DEVICEERROR_ALGOOVERFLOW \ 03986 ((VL53LX_DeviceError) 11) 03987 #define VL53LX_DEVICEERROR_RANGEIGNORETHRESHOLD \ 03988 ((VL53LX_DeviceError) 12) 03989 #define VL53LX_DEVICEERROR_USERROICLIP \ 03990 ((VL53LX_DeviceError) 13) 03991 #define VL53LX_DEVICEERROR_REFSPADCHARNOTENOUGHDPADS \ 03992 ((VL53LX_DeviceError) 14) 03993 #define VL53LX_DEVICEERROR_REFSPADCHARMORETHANTARGET \ 03994 ((VL53LX_DeviceError) 15) 03995 #define VL53LX_DEVICEERROR_REFSPADCHARLESSTHANTARGET \ 03996 ((VL53LX_DeviceError) 16) 03997 #define VL53LX_DEVICEERROR_MULTCLIPFAIL \ 03998 ((VL53LX_DeviceError) 17) 03999 #define VL53LX_DEVICEERROR_GPHSTREAMCOUNT0READY \ 04000 ((VL53LX_DeviceError) 18) 04001 #define VL53LX_DEVICEERROR_RANGECOMPLETE_NO_WRAP_CHECK \ 04002 ((VL53LX_DeviceError) 19) 04003 #define VL53LX_DEVICEERROR_EVENTCONSISTENCY \ 04004 ((VL53LX_DeviceError) 20) 04005 #define VL53LX_DEVICEERROR_MINSIGNALEVENTCHECK \ 04006 ((VL53LX_DeviceError) 21) 04007 #define VL53LX_DEVICEERROR_RANGECOMPLETE_MERGED_PULSE \ 04008 ((VL53LX_DeviceError) 22) 04009 04010 04011 #define VL53LX_DEVICEERROR_PREV_RANGE_NO_TARGETS \ 04012 ((VL53LX_DeviceError) 23) 04013 04014 04015 04016 04017 04018 typedef uint8_t VL53LX_DeviceReportStatus; 04019 04020 #define VL53LX_DEVICEREPORTSTATUS_NOUPDATE \ 04021 ((VL53LX_DeviceReportStatus) 0) 04022 04023 #define VL53LX_DEVICEREPORTSTATUS_ROI_SETUP \ 04024 ((VL53LX_DeviceReportStatus) 1) 04025 #define VL53LX_DEVICEREPORTSTATUS_VHV \ 04026 ((VL53LX_DeviceReportStatus) 2) 04027 #define VL53LX_DEVICEREPORTSTATUS_PHASECAL \ 04028 ((VL53LX_DeviceReportStatus) 3) 04029 #define VL53LX_DEVICEREPORTSTATUS_REFERENCE_PHASE \ 04030 ((VL53LX_DeviceReportStatus) 4) 04031 #define VL53LX_DEVICEREPORTSTATUS_DSS1 \ 04032 ((VL53LX_DeviceReportStatus) 5) 04033 #define VL53LX_DEVICEREPORTSTATUS_DSS2 \ 04034 ((VL53LX_DeviceReportStatus) 6) 04035 #define VL53LX_DEVICEREPORTSTATUS_MM1 \ 04036 ((VL53LX_DeviceReportStatus) 7) 04037 #define VL53LX_DEVICEREPORTSTATUS_MM2 \ 04038 ((VL53LX_DeviceReportStatus) 8) 04039 #define VL53LX_DEVICEREPORTSTATUS_RANGE \ 04040 ((VL53LX_DeviceReportStatus) 9) 04041 #define VL53LX_DEVICEREPORTSTATUS_HISTOGRAM \ 04042 ((VL53LX_DeviceReportStatus) 10) 04043 04044 04045 04046 04047 04048 typedef uint8_t VL53LX_DeviceDssMode; 04049 04050 #define VL53LX_DEVICEDSSMODE__DISABLED \ 04051 ((VL53LX_DeviceDssMode) 0) 04052 #define VL53LX_DEVICEDSSMODE__TARGET_RATE \ 04053 ((VL53LX_DeviceDssMode) 1) 04054 #define VL53LX_DEVICEDSSMODE__REQUESTED_EFFFECTIVE_SPADS \ 04055 ((VL53LX_DeviceDssMode) 2) 04056 #define VL53LX_DEVICEDSSMODE__BLOCK_SELECT \ 04057 ((VL53LX_DeviceDssMode) 3) 04058 04059 04060 04061 04062 04063 04064 typedef uint8_t VL53LX_HistAlgoSelect; 04065 04066 #define VL53LX_HIST_ALGO_SELECT__PW_HIST_GEN1 \ 04067 ((VL53LX_HistAlgoSelect) 1) 04068 #define VL53LX_HIST_ALGO_SELECT__PW_HIST_GEN2 \ 04069 ((VL53LX_HistAlgoSelect) 2) 04070 #define VL53LX_HIST_ALGO_SELECT__PW_HIST_GEN3 \ 04071 ((VL53LX_HistAlgoSelect) 3) 04072 #define VL53LX_HIST_ALGO_SELECT__PW_HIST_GEN4 \ 04073 ((VL53LX_HistAlgoSelect) 4) 04074 04075 04076 04077 04078 04079 04080 typedef uint8_t VL53LX_HistTargetOrder; 04081 04082 #define VL53LX_HIST_TARGET_ORDER__INCREASING_DISTANCE \ 04083 ((VL53LX_HistTargetOrder) 1) 04084 #define VL53LX_HIST_TARGET_ORDER__STRONGEST_FIRST \ 04085 ((VL53LX_HistTargetOrder) 2) 04086 04087 04088 04089 04090 04091 04092 typedef uint8_t VL53LX_HistAmbEstMethod; 04093 04094 #define VL53LX_HIST_AMB_EST_METHOD__AMBIENT_BINS \ 04095 ((VL53LX_HistAmbEstMethod) 1) 04096 #define VL53LX_HIST_AMB_EST_METHOD__THRESHOLDED_BINS \ 04097 ((VL53LX_HistAmbEstMethod) 2) 04098 04099 04100 04101 04102 04103 04104 typedef uint8_t VL53LX_HistXtalkCompEnable; 04105 04106 #define VL53LX_HIST_XTALK_COMP__DIS \ 04107 ((VL53LX_HistXtalkCompEnable) 0) 04108 #define VL53LX_HIST_XTALK_COMP__EN \ 04109 ((VL53LX_HistXtalkCompEnable) 1) 04110 04111 04112 04113 04114 typedef uint8_t VL53LX_DeviceConfigLevel; 04115 04116 #define VL53LX_DEVICECONFIGLEVEL_SYSTEM_CONTROL \ 04117 ((VL53LX_DeviceConfigLevel) 0) 04118 04119 #define VL53LX_DEVICECONFIGLEVEL_DYNAMIC_ONWARDS \ 04120 ((VL53LX_DeviceConfigLevel) 1) 04121 04122 #define VL53LX_DEVICECONFIGLEVEL_TIMING_ONWARDS \ 04123 ((VL53LX_DeviceConfigLevel) 2) 04124 04125 #define VL53LX_DEVICECONFIGLEVEL_GENERAL_ONWARDS \ 04126 ((VL53LX_DeviceConfigLevel) 3) 04127 04128 #define VL53LX_DEVICECONFIGLEVEL_STATIC_ONWARDS \ 04129 ((VL53LX_DeviceConfigLevel) 4) 04130 04131 #define VL53LX_DEVICECONFIGLEVEL_CUSTOMER_ONWARDS \ 04132 ((VL53LX_DeviceConfigLevel) 5) 04133 04134 #define VL53LX_DEVICECONFIGLEVEL_FULL \ 04135 ((VL53LX_DeviceConfigLevel) 6) 04136 04137 04138 04139 04140 04141 04142 typedef uint8_t VL53LX_DeviceResultsLevel; 04143 04144 #define VL53LX_DEVICERESULTSLEVEL_SYSTEM_RESULTS \ 04145 ((VL53LX_DeviceResultsLevel) 0) 04146 04147 #define VL53LX_DEVICERESULTSLEVEL_UPTO_CORE \ 04148 ((VL53LX_DeviceResultsLevel) 1) 04149 04150 #define VL53LX_DEVICERESULTSLEVEL_FULL \ 04151 ((VL53LX_DeviceResultsLevel) 2) 04152 04153 04154 04155 04156 04157 04158 04159 typedef uint8_t VL53LX_DeviceTestMode; 04160 04161 #define VL53LX_DEVICETESTMODE_NONE \ 04162 ((VL53LX_DeviceTestMode) 0x00) 04163 04164 #define VL53LX_DEVICETESTMODE_NVM_ZERO \ 04165 ((VL53LX_DeviceTestMode) 0x01) 04166 04167 #define VL53LX_DEVICETESTMODE_NVM_COPY \ 04168 ((VL53LX_DeviceTestMode) 0x02) 04169 04170 #define VL53LX_DEVICETESTMODE_PATCH \ 04171 ((VL53LX_DeviceTestMode) 0x03) 04172 04173 #define VL53LX_DEVICETESTMODE_DCR \ 04174 ((VL53LX_DeviceTestMode) 0x04) 04175 04176 #define VL53LX_DEVICETESTMODE_LCR_VCSEL_OFF \ 04177 ((VL53LX_DeviceTestMode) 0x05) 04178 04179 #define VL53LX_DEVICETESTMODE_LCR_VCSEL_ON \ 04180 ((VL53LX_DeviceTestMode) 0x06) 04181 04182 #define VL53LX_DEVICETESTMODE_SPOT_CENTRE_LOCATE \ 04183 ((VL53LX_DeviceTestMode) 0x07) 04184 04185 #define VL53LX_DEVICETESTMODE_REF_SPAD_CHAR_WITH_PRE_VHV \ 04186 ((VL53LX_DeviceTestMode) 0x08) 04187 04188 #define VL53LX_DEVICETESTMODE_REF_SPAD_CHAR_ONLY \ 04189 ((VL53LX_DeviceTestMode) 0x09) 04190 04191 04192 04193 04194 04195 04196 04197 typedef uint8_t VL53LX_DeviceSscArray; 04198 04199 #define VL53LX_DEVICESSCARRAY_RTN ((VL53LX_DeviceSscArray) 0x00) 04200 04201 #define VL53LX_DEVICETESTMODE_REF ((VL53LX_DeviceSscArray) 0x01) 04202 04203 04204 04205 04206 04207 04208 04209 #define VL53LX_RETURN_ARRAY_ONLY 0x01 04210 04211 #define VL53LX_REFERENCE_ARRAY_ONLY 0x10 04212 04213 #define VL53LX_BOTH_RETURN_AND_REFERENCE_ARRAYS 0x11 04214 04215 #define VL53LX_NEITHER_RETURN_AND_REFERENCE_ARRAYS 0x00 04216 04217 04218 04219 04220 04221 04222 #define VL53LX_DEVICEINTERRUPTLEVEL_ACTIVE_HIGH 0x00 04223 04224 #define VL53LX_DEVICEINTERRUPTLEVEL_ACTIVE_LOW 0x10 04225 04226 #define VL53LX_DEVICEINTERRUPTLEVEL_ACTIVE_MASK 0x10 04227 04228 04229 04230 04231 04232 04233 #define VL53LX_POLLING_DELAY_US 1000 04234 04235 #define VL53LX_SOFTWARE_RESET_DURATION_US 100 04236 04237 #define VL53LX_FIRMWARE_BOOT_TIME_US 1200 04238 04239 #define VL53LX_ENABLE_POWERFORCE_SETTLING_TIME_US 250 04240 04241 #define VL53LX_SPAD_ARRAY_WIDTH 16 04242 04243 #define VL53LX_SPAD_ARRAY_HEIGHT 16 04244 04245 #define VL53LX_NVM_SIZE_IN_BYTES 512 04246 04247 #define VL53LX_NO_OF_SPAD_ENABLES 256 04248 04249 #define VL53LX_RTN_SPAD_BUFFER_SIZE 32 04250 04251 #define VL53LX_REF_SPAD_BUFFER_SIZE 6 04252 04253 #define VL53LX_AMBIENT_WINDOW_VCSEL_PERIODS 256 04254 04255 #define VL53LX_RANGING_WINDOW_VCSEL_PERIODS 2048 04256 04257 #define VL53LX_MACRO_PERIOD_VCSEL_PERIODS \ 04258 (VL53LX_AMBIENT_WINDOW_VCSEL_PERIODS + \ 04259 VL53LX_RANGING_WINDOW_VCSEL_PERIODS) 04260 04261 #define VL53LX_MAX_ALLOWED_PHASE 0xFFFF 04262 04263 04264 #define VL53LX_RTN_SPAD_UNITY_TRANSMISSION 0x0100 04265 04266 #define VL53LX_RTN_SPAD_APERTURE_TRANSMISSION 0x0038 04267 04268 04269 #define VL53LX_SPAD_TOTAL_COUNT_MAX ((0x01 << 29) - 1) 04270 04271 #define VL53LX_SPAD_TOTAL_COUNT_RES_THRES (0x01 << 24) 04272 04273 #define VL53LX_COUNT_RATE_INTERNAL_MAX ((0x01 << 24) - 1) 04274 04275 #define VL53LX_SPEED_OF_LIGHT_IN_AIR 299704 04276 04277 #define VL53LX_SPEED_OF_LIGHT_IN_AIR_DIV_8 (299704 >> 3) 04278 04279 04280 04281 04282 04283 04284 04285 04286 typedef uint8_t VL53LX_ZoneConfig_BinConfig_select; 04287 04288 #define VL53LX_ZONECONFIG_BINCONFIG__LOWAMB \ 04289 ((VL53LX_ZoneConfig_BinConfig_select) 1) 04290 #define VL53LX_ZONECONFIG_BINCONFIG__MIDAMB \ 04291 ((VL53LX_ZoneConfig_BinConfig_select) 2) 04292 #define VL53LX_ZONECONFIG_BINCONFIG__HIGHAMB \ 04293 ((VL53LX_ZoneConfig_BinConfig_select) 3) 04294 04295 04296 04297 04298 04299 typedef uint8_t VL53LX_GPIO_Interrupt_Mode; 04300 04301 #define VL53LX_GPIOINTMODE_LEVEL_LOW \ 04302 ((VL53LX_GPIO_Interrupt_Mode) 0) 04303 04304 #define VL53LX_GPIOINTMODE_LEVEL_HIGH \ 04305 ((VL53LX_GPIO_Interrupt_Mode) 1) 04306 04307 #define VL53LX_GPIOINTMODE_OUT_OF_WINDOW \ 04308 ((VL53LX_GPIO_Interrupt_Mode) 2) 04309 04310 #define VL53LX_GPIOINTMODE_IN_WINDOW \ 04311 ((VL53LX_GPIO_Interrupt_Mode) 3) 04312 04313 04314 04315 04316 04317 04318 typedef uint16_t VL53LX_TuningParms; 04319 04320 #define VL53LX_TUNINGPARMS_LLD_PUBLIC_MIN_ADDRESS \ 04321 ((VL53LX_TuningParms) VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS) 04322 #define VL53LX_TUNINGPARMS_LLD_PUBLIC_MAX_ADDRESS \ 04323 ((VL53LX_TuningParms) VL53LX_TUNINGPARM_DYNXTALK_MAX_SMUDGE_FACTOR) 04324 04325 #define VL53LX_TUNINGPARMS_LLD_PRIVATE_MIN_ADDRESS \ 04326 ((VL53LX_TuningParms) VL53LX_TUNINGPARM_PRIVATE_PAGE_BASE_ADDRESS) 04327 #define VL53LX_TUNINGPARMS_LLD_PRIVATE_MAX_ADDRESS \ 04328 ((VL53LX_TuningParms) VL53LX_TUNINGPARMS_LLD_PRIVATE_MIN_ADDRESS) 04329 04330 #define VL53LX_TUNINGPARM_VERSION \ 04331 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 0)) 04332 #define VL53LX_TUNINGPARM_KEY_TABLE_VERSION \ 04333 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 1)) 04334 #define VL53LX_TUNINGPARM_LLD_VERSION \ 04335 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 2)) 04336 #define VL53LX_TUNINGPARM_HIST_ALGO_SELECT \ 04337 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 3)) 04338 #define VL53LX_TUNINGPARM_HIST_TARGET_ORDER \ 04339 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 4)) 04340 #define VL53LX_TUNINGPARM_HIST_FILTER_WOI_0 \ 04341 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 5)) 04342 #define VL53LX_TUNINGPARM_HIST_FILTER_WOI_1 \ 04343 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 6)) 04344 #define VL53LX_TUNINGPARM_HIST_AMB_EST_METHOD \ 04345 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 7)) 04346 #define VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_0 \ 04347 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 8)) 04348 #define VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_1 \ 04349 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 9)) 04350 #define VL53LX_TUNINGPARM_HIST_MIN_AMB_THRESH_EVENTS \ 04351 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 10)) 04352 #define VL53LX_TUNINGPARM_HIST_AMB_EVENTS_SCALER \ 04353 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 11)) 04354 #define VL53LX_TUNINGPARM_HIST_NOISE_THRESHOLD \ 04355 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 12)) 04356 #define VL53LX_TUNINGPARM_HIST_SIGNAL_TOTAL_EVENTS_LIMIT \ 04357 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 13)) 04358 #define VL53LX_TUNINGPARM_HIST_SIGMA_EST_REF_MM \ 04359 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 14)) 04360 #define VL53LX_TUNINGPARM_HIST_SIGMA_THRESH_MM \ 04361 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 15)) 04362 #define VL53LX_TUNINGPARM_HIST_GAIN_FACTOR \ 04363 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 16)) 04364 #define VL53LX_TUNINGPARM_CONSISTENCY_HIST_PHASE_TOLERANCE \ 04365 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 17)) 04366 #define VL53LX_TUNINGPARM_CONSISTENCY_HIST_MIN_MAX_TOLERANCE_MM \ 04367 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 18)) 04368 #define VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA \ 04369 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 19)) 04370 #define VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA_MIN_SPAD_LIMIT \ 04371 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 20)) 04372 #define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_LONG_RANGE \ 04373 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 21)) 04374 #define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_MED_RANGE \ 04375 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 22)) 04376 #define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_SHORT_RANGE \ 04377 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 23)) 04378 #define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_LONG_RANGE \ 04379 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 24)) 04380 #define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_MED_RANGE \ 04381 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 25)) 04382 #define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_SHORT_RANGE \ 04383 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 26)) 04384 #define VL53LX_TUNINGPARM_XTALK_DETECT_MIN_VALID_RANGE_MM \ 04385 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 27)) 04386 #define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RANGE_MM \ 04387 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 28)) 04388 #define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_SIGMA_MM \ 04389 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 29)) 04390 #define VL53LX_TUNINGPARM_XTALK_DETECT_MIN_MAX_TOLERANCE \ 04391 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 30)) 04392 #define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RATE_KCPS \ 04393 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 31)) 04394 #define VL53LX_TUNINGPARM_XTALK_DETECT_EVENT_SIGMA \ 04395 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 32)) 04396 #define VL53LX_TUNINGPARM_HIST_XTALK_MARGIN_KCPS \ 04397 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 33)) 04398 #define VL53LX_TUNINGPARM_CONSISTENCY_LITE_PHASE_TOLERANCE \ 04399 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 34)) 04400 #define VL53LX_TUNINGPARM_PHASECAL_TARGET \ 04401 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 35)) 04402 #define VL53LX_TUNINGPARM_LITE_CAL_REPEAT_RATE \ 04403 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 36)) 04404 #define VL53LX_TUNINGPARM_LITE_RANGING_GAIN_FACTOR \ 04405 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 37)) 04406 #define VL53LX_TUNINGPARM_LITE_MIN_CLIP_MM \ 04407 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 38)) 04408 #define VL53LX_TUNINGPARM_LITE_LONG_SIGMA_THRESH_MM \ 04409 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 39)) 04410 #define VL53LX_TUNINGPARM_LITE_MED_SIGMA_THRESH_MM \ 04411 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 40)) 04412 #define VL53LX_TUNINGPARM_LITE_SHORT_SIGMA_THRESH_MM \ 04413 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 41)) 04414 #define VL53LX_TUNINGPARM_LITE_LONG_MIN_COUNT_RATE_RTN_MCPS \ 04415 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 42)) 04416 #define VL53LX_TUNINGPARM_LITE_MED_MIN_COUNT_RATE_RTN_MCPS \ 04417 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 43)) 04418 #define VL53LX_TUNINGPARM_LITE_SHORT_MIN_COUNT_RATE_RTN_MCPS \ 04419 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 44)) 04420 #define VL53LX_TUNINGPARM_LITE_SIGMA_EST_PULSE_WIDTH \ 04421 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 45)) 04422 #define VL53LX_TUNINGPARM_LITE_SIGMA_EST_AMB_WIDTH_NS \ 04423 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 46)) 04424 #define VL53LX_TUNINGPARM_LITE_SIGMA_REF_MM \ 04425 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 47)) 04426 #define VL53LX_TUNINGPARM_LITE_RIT_MULT \ 04427 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 48)) 04428 #define VL53LX_TUNINGPARM_LITE_SEED_CONFIG \ 04429 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 49)) 04430 #define VL53LX_TUNINGPARM_LITE_QUANTIFIER \ 04431 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 50)) 04432 #define VL53LX_TUNINGPARM_LITE_FIRST_ORDER_SELECT \ 04433 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 51)) 04434 #define VL53LX_TUNINGPARM_LITE_XTALK_MARGIN_KCPS \ 04435 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 52)) 04436 #define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_LONG_RANGE \ 04437 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 53)) 04438 #define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_MED_RANGE \ 04439 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 54)) 04440 #define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_SHORT_RANGE \ 04441 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 55)) 04442 #define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_LONG_RANGE \ 04443 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 56)) 04444 #define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_MED_RANGE \ 04445 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 57)) 04446 #define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_SHORT_RANGE \ 04447 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 58)) 04448 #define VL53LX_TUNINGPARM_TIMED_SEED_CONFIG \ 04449 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 59)) 04450 #define VL53LX_TUNINGPARM_DMAX_CFG_SIGNAL_THRESH_SIGMA \ 04451 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 60)) 04452 #define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_0 \ 04453 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 61)) 04454 #define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_1 \ 04455 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 62)) 04456 #define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_2 \ 04457 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 63)) 04458 #define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_3 \ 04459 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 64)) 04460 #define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_4 \ 04461 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 65)) 04462 #define VL53LX_TUNINGPARM_VHV_LOOPBOUND \ 04463 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 66)) 04464 #define VL53LX_TUNINGPARM_REFSPADCHAR_DEVICE_TEST_MODE \ 04465 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 67)) 04466 #define VL53LX_TUNINGPARM_REFSPADCHAR_VCSEL_PERIOD \ 04467 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 68)) 04468 #define VL53LX_TUNINGPARM_REFSPADCHAR_PHASECAL_TIMEOUT_US \ 04469 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 69)) 04470 #define VL53LX_TUNINGPARM_REFSPADCHAR_TARGET_COUNT_RATE_MCPS \ 04471 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 70)) 04472 #define VL53LX_TUNINGPARM_REFSPADCHAR_MIN_COUNTRATE_LIMIT_MCPS \ 04473 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 71)) 04474 #define VL53LX_TUNINGPARM_REFSPADCHAR_MAX_COUNTRATE_LIMIT_MCPS \ 04475 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 72)) 04476 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_NUM_OF_SAMPLES \ 04477 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 73)) 04478 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_MIN_FILTER_THRESH_MM \ 04479 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 74)) 04480 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_FILTER_THRESH_MM \ 04481 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 75)) 04482 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_RATE_MCPS \ 04483 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 76)) 04484 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_PHASECAL_TIMEOUT_US \ 04485 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 77)) 04486 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_VALID_RATE_KCPS \ 04487 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 78)) 04488 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_SIGMA_THRESHOLD_MM \ 04489 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 79)) 04490 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_TIMEOUT_US \ 04491 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 80)) 04492 #define VL53LX_TUNINGPARM_XTALK_EXTRACT_BIN_TIMEOUT_US \ 04493 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 81)) 04494 #define VL53LX_TUNINGPARM_OFFSET_CAL_DSS_RATE_MCPS \ 04495 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 82)) 04496 #define VL53LX_TUNINGPARM_OFFSET_CAL_PHASECAL_TIMEOUT_US \ 04497 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 83)) 04498 #define VL53LX_TUNINGPARM_OFFSET_CAL_MM_TIMEOUT_US \ 04499 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 84)) 04500 #define VL53LX_TUNINGPARM_OFFSET_CAL_RANGE_TIMEOUT_US \ 04501 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 85)) 04502 #define VL53LX_TUNINGPARM_OFFSET_CAL_PRE_SAMPLES \ 04503 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 86)) 04504 #define VL53LX_TUNINGPARM_OFFSET_CAL_MM1_SAMPLES \ 04505 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 87)) 04506 #define VL53LX_TUNINGPARM_OFFSET_CAL_MM2_SAMPLES \ 04507 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 88)) 04508 #define VL53LX_TUNINGPARM_ZONE_CAL_DSS_RATE_MCPS \ 04509 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 89)) 04510 #define VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_TIMEOUT_US \ 04511 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 90)) 04512 #define VL53LX_TUNINGPARM_ZONE_CAL_DSS_TIMEOUT_US \ 04513 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 91)) 04514 #define VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_NUM_SAMPLES \ 04515 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 92)) 04516 #define VL53LX_TUNINGPARM_ZONE_CAL_RANGE_TIMEOUT_US \ 04517 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 93)) 04518 #define VL53LX_TUNINGPARM_ZONE_CAL_ZONE_NUM_SAMPLES \ 04519 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 94)) 04520 #define VL53LX_TUNINGPARM_SPADMAP_VCSEL_PERIOD \ 04521 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 95)) 04522 #define VL53LX_TUNINGPARM_SPADMAP_VCSEL_START \ 04523 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 96)) 04524 #define VL53LX_TUNINGPARM_SPADMAP_RATE_LIMIT_MCPS \ 04525 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 97)) 04526 #define VL53LX_TUNINGPARM_LITE_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS \ 04527 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 98)) 04528 #define VL53LX_TUNINGPARM_RANGING_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS \ 04529 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 99)) 04530 #define VL53LX_TUNINGPARM_MZ_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS \ 04531 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 100)) 04532 #define VL53LX_TUNINGPARM_TIMED_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS \ 04533 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 101)) 04534 #define VL53LX_TUNINGPARM_LITE_PHASECAL_CONFIG_TIMEOUT_US \ 04535 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 102)) 04536 #define VL53LX_TUNINGPARM_RANGING_LONG_PHASECAL_CONFIG_TIMEOUT_US \ 04537 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 103)) 04538 #define VL53LX_TUNINGPARM_RANGING_MED_PHASECAL_CONFIG_TIMEOUT_US \ 04539 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 104)) 04540 #define VL53LX_TUNINGPARM_RANGING_SHORT_PHASECAL_CONFIG_TIMEOUT_US \ 04541 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 105)) 04542 #define VL53LX_TUNINGPARM_MZ_LONG_PHASECAL_CONFIG_TIMEOUT_US \ 04543 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 106)) 04544 #define VL53LX_TUNINGPARM_MZ_MED_PHASECAL_CONFIG_TIMEOUT_US \ 04545 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 107)) 04546 #define VL53LX_TUNINGPARM_MZ_SHORT_PHASECAL_CONFIG_TIMEOUT_US \ 04547 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 108)) 04548 #define VL53LX_TUNINGPARM_TIMED_PHASECAL_CONFIG_TIMEOUT_US \ 04549 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 109)) 04550 #define VL53LX_TUNINGPARM_LITE_MM_CONFIG_TIMEOUT_US \ 04551 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 110)) 04552 #define VL53LX_TUNINGPARM_RANGING_MM_CONFIG_TIMEOUT_US \ 04553 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 111)) 04554 #define VL53LX_TUNINGPARM_MZ_MM_CONFIG_TIMEOUT_US \ 04555 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 112)) 04556 #define VL53LX_TUNINGPARM_TIMED_MM_CONFIG_TIMEOUT_US \ 04557 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 113)) 04558 #define VL53LX_TUNINGPARM_LITE_RANGE_CONFIG_TIMEOUT_US \ 04559 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 114)) 04560 #define VL53LX_TUNINGPARM_RANGING_RANGE_CONFIG_TIMEOUT_US \ 04561 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 115)) 04562 #define VL53LX_TUNINGPARM_MZ_RANGE_CONFIG_TIMEOUT_US \ 04563 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 116)) 04564 #define VL53LX_TUNINGPARM_TIMED_RANGE_CONFIG_TIMEOUT_US \ 04565 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 117)) 04566 #define VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_MARGIN \ 04567 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 118)) 04568 #define VL53LX_TUNINGPARM_DYNXTALK_NOISE_MARGIN \ 04569 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 119)) 04570 #define VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT \ 04571 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 120)) 04572 #define VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT_HI \ 04573 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 121)) 04574 #define VL53LX_TUNINGPARM_DYNXTALK_SAMPLE_LIMIT \ 04575 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 122)) 04576 #define VL53LX_TUNINGPARM_DYNXTALK_SINGLE_XTALK_DELTA \ 04577 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 123)) 04578 #define VL53LX_TUNINGPARM_DYNXTALK_AVERAGED_XTALK_DELTA \ 04579 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 124)) 04580 #define VL53LX_TUNINGPARM_DYNXTALK_CLIP_LIMIT \ 04581 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 125)) 04582 #define VL53LX_TUNINGPARM_DYNXTALK_SCALER_CALC_METHOD \ 04583 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 126)) 04584 #define VL53LX_TUNINGPARM_DYNXTALK_XGRADIENT_SCALER \ 04585 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 127)) 04586 #define VL53LX_TUNINGPARM_DYNXTALK_YGRADIENT_SCALER \ 04587 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 128)) 04588 #define VL53LX_TUNINGPARM_DYNXTALK_USER_SCALER_SET \ 04589 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 129)) 04590 #define VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_COR_SINGLE_APPLY \ 04591 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 130)) 04592 #define VL53LX_TUNINGPARM_DYNXTALK_XTALK_AMB_THRESHOLD \ 04593 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 131)) 04594 #define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_AMB_THRESHOLD_KCPS \ 04595 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 132)) 04596 #define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_SAMPLE_LIMIT \ 04597 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 133)) 04598 #define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_XTALK_OFFSET_KCPS \ 04599 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 134)) 04600 #define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_MIN_RANGE_MM \ 04601 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 135)) 04602 #define VL53LX_TUNINGPARM_LOWPOWERAUTO_VHV_LOOP_BOUND \ 04603 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 136)) 04604 #define VL53LX_TUNINGPARM_LOWPOWERAUTO_MM_CONFIG_TIMEOUT_US \ 04605 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 137)) 04606 #define VL53LX_TUNINGPARM_LOWPOWERAUTO_RANGE_CONFIG_TIMEOUT_US \ 04607 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 138)) 04608 #define VL53LX_TUNINGPARM_VERY_SHORT_DSS_RATE_MCPS \ 04609 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 139)) 04610 #define VL53LX_TUNINGPARM_PHASECAL_PATCH_POWER \ 04611 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 140)) 04612 #define VL53LX_TUNINGPARM_HIST_MERGE \ 04613 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 141)) 04614 #define VL53LX_TUNINGPARM_RESET_MERGE_THRESHOLD \ 04615 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 142)) 04616 #define VL53LX_TUNINGPARM_HIST_MERGE_MAX_SIZE \ 04617 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 143)) 04618 #define VL53LX_TUNINGPARM_DYNXTALK_MAX_SMUDGE_FACTOR \ 04619 ((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 144)) 04620 04621 // define from vl53lx_platform_log.h 04622 04623 #define VL53LX_TRACE_LEVEL_NONE 0x00000000 04624 #define VL53LX_TRACE_LEVEL_ERRORS 0x00000001 04625 #define VL53LX_TRACE_LEVEL_WARNING 0x00000002 04626 #define VL53LX_TRACE_LEVEL_INFO 0x00000004 04627 #define VL53LX_TRACE_LEVEL_DEBUG 0x00000008 04628 #define VL53LX_TRACE_LEVEL_ALL 0x00000010 04629 #define VL53LX_TRACE_LEVEL_IGNORE 0x00000020 04630 04631 #define VL53LX_TRACE_FUNCTION_NONE 0x00000000 04632 #define VL53LX_TRACE_FUNCTION_I2C 0x00000001 04633 #define VL53LX_TRACE_FUNCTION_ALL 0x7fffffff 04634 04635 #define VL53LX_TRACE_MODULE_NONE 0x00000000 04636 #define VL53LX_TRACE_MODULE_API 0x00000001 04637 #define VL53LX_TRACE_MODULE_CORE 0x00000002 04638 #define VL53LX_TRACE_MODULE_PROTECTED 0x00000004 04639 #define VL53LX_TRACE_MODULE_HISTOGRAM 0x00000008 04640 #define VL53LX_TRACE_MODULE_REGISTERS 0x00000010 04641 #define VL53LX_TRACE_MODULE_PLATFORM 0x00000020 04642 #define VL53LX_TRACE_MODULE_NVM 0x00000040 04643 #define VL53LX_TRACE_MODULE_CALIBRATION_DATA 0x00000080 04644 #define VL53LX_TRACE_MODULE_NVM_DATA 0x00000100 04645 #define VL53LX_TRACE_MODULE_HISTOGRAM_DATA 0x00000200 04646 #define VL53LX_TRACE_MODULE_RANGE_RESULTS_DATA 0x00000400 04647 #define VL53LX_TRACE_MODULE_XTALK_DATA 0x00000800 04648 #define VL53LX_TRACE_MODULE_OFFSET_DATA 0x00001000 04649 #define VL53LX_TRACE_MODULE_DATA_INIT 0x00002000 04650 #define VL53LX_TRACE_MODULE_REF_SPAD_CHAR 0x00004000 04651 #define VL53LX_TRACE_MODULE_SPAD_RATE_MAP 0x00008000 04652 04653 04654 04655 // define & typedef from vl53lx_register_structs.h 04656 04657 04658 #define VL53LX_STATIC_NVM_MANAGED_I2C_INDEX \ 04659 VL53LX_I2C_SLAVE__DEVICE_ADDRESS 04660 #define VL53LX_CUSTOMER_NVM_MANAGED_I2C_INDEX \ 04661 VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_0 04662 #define VL53LX_STATIC_CONFIG_I2C_INDEX \ 04663 VL53LX_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS 04664 #define VL53LX_GENERAL_CONFIG_I2C_INDEX \ 04665 VL53LX_GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE 04666 #define VL53LX_TIMING_CONFIG_I2C_INDEX \ 04667 VL53LX_MM_CONFIG__TIMEOUT_MACROP_A_HI 04668 #define VL53LX_DYNAMIC_CONFIG_I2C_INDEX \ 04669 VL53LX_SYSTEM__GROUPED_PARAMETER_HOLD_0 04670 #define VL53LX_SYSTEM_CONTROL_I2C_INDEX \ 04671 VL53LX_POWER_MANAGEMENT__GO1_POWER_FORCE 04672 #define VL53LX_SYSTEM_RESULTS_I2C_INDEX \ 04673 VL53LX_RESULT__INTERRUPT_STATUS 04674 #define VL53LX_CORE_RESULTS_I2C_INDEX \ 04675 VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 04676 #define VL53LX_DEBUG_RESULTS_I2C_INDEX \ 04677 VL53LX_PHASECAL_RESULT__REFERENCE_PHASE 04678 #define VL53LX_NVM_COPY_DATA_I2C_INDEX \ 04679 VL53LX_IDENTIFICATION__MODEL_ID 04680 #define VL53LX_PREV_SHADOW_SYSTEM_RESULTS_I2C_INDEX \ 04681 VL53LX_PREV_SHADOW_RESULT__INTERRUPT_STATUS 04682 #define VL53LX_PREV_SHADOW_CORE_RESULTS_I2C_INDEX \ 04683 VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 04684 #define VL53LX_PATCH_DEBUG_I2C_INDEX \ 04685 VL53LX_RESULT__DEBUG_STATUS 04686 #define VL53LX_GPH_GENERAL_CONFIG_I2C_INDEX \ 04687 VL53LX_GPH__SYSTEM__THRESH_RATE_HIGH 04688 #define VL53LX_GPH_STATIC_CONFIG_I2C_INDEX \ 04689 VL53LX_GPH__DSS_CONFIG__ROI_MODE_CONTROL 04690 #define VL53LX_GPH_TIMING_CONFIG_I2C_INDEX \ 04691 VL53LX_GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI 04692 #define VL53LX_FW_INTERNAL_I2C_INDEX \ 04693 VL53LX_FIRMWARE__INTERNAL_STREAM_COUNT_DIV 04694 #define VL53LX_PATCH_RESULTS_I2C_INDEX \ 04695 VL53LX_DSS_CALC__ROI_CTRL 04696 #define VL53LX_SHADOW_SYSTEM_RESULTS_I2C_INDEX \ 04697 VL53LX_SHADOW_PHASECAL_RESULT__VCSEL_START 04698 #define VL53LX_SHADOW_CORE_RESULTS_I2C_INDEX \ 04699 VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 04700 04701 #define VL53LX_STATIC_NVM_MANAGED_I2C_SIZE_BYTES 11 04702 #define VL53LX_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES 23 04703 #define VL53LX_STATIC_CONFIG_I2C_SIZE_BYTES 32 04704 #define VL53LX_GENERAL_CONFIG_I2C_SIZE_BYTES 22 04705 #define VL53LX_TIMING_CONFIG_I2C_SIZE_BYTES 23 04706 #define VL53LX_DYNAMIC_CONFIG_I2C_SIZE_BYTES 18 04707 #define VL53LX_SYSTEM_CONTROL_I2C_SIZE_BYTES 5 04708 #define VL53LX_SYSTEM_RESULTS_I2C_SIZE_BYTES 44 04709 #define VL53LX_CORE_RESULTS_I2C_SIZE_BYTES 33 04710 #define VL53LX_DEBUG_RESULTS_I2C_SIZE_BYTES 56 04711 #define VL53LX_NVM_COPY_DATA_I2C_SIZE_BYTES 49 04712 #define VL53LX_PREV_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES 44 04713 #define VL53LX_PREV_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES 33 04714 #define VL53LX_PATCH_DEBUG_I2C_SIZE_BYTES 2 04715 #define VL53LX_GPH_GENERAL_CONFIG_I2C_SIZE_BYTES 5 04716 #define VL53LX_GPH_STATIC_CONFIG_I2C_SIZE_BYTES 6 04717 #define VL53LX_GPH_TIMING_CONFIG_I2C_SIZE_BYTES 16 04718 #define VL53LX_FW_INTERNAL_I2C_SIZE_BYTES 2 04719 #define VL53LX_PATCH_RESULTS_I2C_SIZE_BYTES 90 04720 #define VL53LX_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES 82 04721 #define VL53LX_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES 33 04722 04723 04724 04725 04726 typedef struct { 04727 uint8_t i2c_slave__device_address; 04728 04729 uint8_t ana_config__vhv_ref_sel_vddpix; 04730 04731 uint8_t ana_config__vhv_ref_sel_vquench; 04732 04733 uint8_t ana_config__reg_avdd1v2_sel; 04734 04735 uint8_t ana_config__fast_osc__trim; 04736 04737 uint16_t osc_measured__fast_osc__frequency; 04738 04739 uint8_t vhv_config__timeout_macrop_loop_bound; 04740 04741 uint8_t vhv_config__count_thresh; 04742 04743 uint8_t vhv_config__offset; 04744 04745 uint8_t vhv_config__init; 04746 04747 } VL53LX_static_nvm_managed_t; 04748 04749 04750 04751 04752 typedef struct { 04753 uint8_t global_config__spad_enables_ref_0; 04754 04755 uint8_t global_config__spad_enables_ref_1; 04756 04757 uint8_t global_config__spad_enables_ref_2; 04758 04759 uint8_t global_config__spad_enables_ref_3; 04760 04761 uint8_t global_config__spad_enables_ref_4; 04762 04763 uint8_t global_config__spad_enables_ref_5; 04764 04765 uint8_t global_config__ref_en_start_select; 04766 04767 uint8_t ref_spad_man__num_requested_ref_spads; 04768 04769 uint8_t ref_spad_man__ref_location; 04770 04771 uint16_t algo__crosstalk_compensation_plane_offset_kcps; 04772 04773 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps; 04774 04775 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps; 04776 04777 uint16_t ref_spad_char__total_rate_target_mcps; 04778 04779 int16_t algo__part_to_part_range_offset_mm; 04780 04781 int16_t mm_config__inner_offset_mm; 04782 04783 int16_t mm_config__outer_offset_mm; 04784 04785 } VL53LX_customer_nvm_managed_t; 04786 04787 04788 04789 04790 typedef struct { 04791 uint16_t dss_config__target_total_rate_mcps; 04792 04793 uint8_t debug__ctrl; 04794 04795 uint8_t test_mode__ctrl; 04796 04797 uint8_t clk_gating__ctrl; 04798 04799 uint8_t nvm_bist__ctrl; 04800 04801 uint8_t nvm_bist__num_nvm_words; 04802 04803 uint8_t nvm_bist__start_address; 04804 04805 uint8_t host_if__status; 04806 04807 uint8_t pad_i2c_hv__config; 04808 04809 uint8_t pad_i2c_hv__extsup_config; 04810 04811 uint8_t gpio_hv_pad__ctrl; 04812 04813 uint8_t gpio_hv_mux__ctrl; 04814 04815 uint8_t gpio__tio_hv_status; 04816 04817 uint8_t gpio__fio_hv_status; 04818 04819 uint8_t ana_config__spad_sel_pswidth; 04820 04821 uint8_t ana_config__vcsel_pulse_width_offset; 04822 04823 uint8_t ana_config__fast_osc__config_ctrl; 04824 04825 uint8_t sigma_estimator__effective_pulse_width_ns; 04826 04827 uint8_t sigma_estimator__effective_ambient_width_ns; 04828 04829 uint8_t sigma_estimator__sigma_ref_mm; 04830 04831 uint8_t algo__crosstalk_compensation_valid_height_mm; 04832 04833 uint8_t spare_host_config__static_config_spare_0; 04834 04835 uint8_t spare_host_config__static_config_spare_1; 04836 04837 uint16_t algo__range_ignore_threshold_mcps; 04838 04839 uint8_t algo__range_ignore_valid_height_mm; 04840 04841 uint8_t algo__range_min_clip; 04842 04843 uint8_t algo__consistency_check__tolerance; 04844 04845 uint8_t spare_host_config__static_config_spare_2; 04846 04847 uint8_t sd_config__reset_stages_msb; 04848 04849 uint8_t sd_config__reset_stages_lsb; 04850 04851 } VL53LX_static_config_t; 04852 04853 04854 04855 04856 typedef struct { 04857 uint8_t gph_config__stream_count_update_value; 04858 04859 uint8_t global_config__stream_divider; 04860 04861 uint8_t system__interrupt_config_gpio; 04862 04863 uint8_t cal_config__vcsel_start; 04864 04865 uint16_t cal_config__repeat_rate; 04866 04867 uint8_t global_config__vcsel_width; 04868 04869 uint8_t phasecal_config__timeout_macrop; 04870 04871 uint8_t phasecal_config__target; 04872 04873 uint8_t phasecal_config__override; 04874 04875 uint8_t dss_config__roi_mode_control; 04876 04877 uint16_t system__thresh_rate_high; 04878 04879 uint16_t system__thresh_rate_low; 04880 04881 uint16_t dss_config__manual_effective_spads_select; 04882 04883 uint8_t dss_config__manual_block_select; 04884 04885 uint8_t dss_config__aperture_attenuation; 04886 04887 uint8_t dss_config__max_spads_limit; 04888 04889 uint8_t dss_config__min_spads_limit; 04890 04891 } VL53LX_general_config_t; 04892 04893 04894 04895 04896 typedef struct { 04897 uint8_t mm_config__timeout_macrop_a_hi; 04898 04899 uint8_t mm_config__timeout_macrop_a_lo; 04900 04901 uint8_t mm_config__timeout_macrop_b_hi; 04902 04903 uint8_t mm_config__timeout_macrop_b_lo; 04904 04905 uint8_t range_config__timeout_macrop_a_hi; 04906 04907 uint8_t range_config__timeout_macrop_a_lo; 04908 04909 uint8_t range_config__vcsel_period_a; 04910 04911 uint8_t range_config__timeout_macrop_b_hi; 04912 04913 uint8_t range_config__timeout_macrop_b_lo; 04914 04915 uint8_t range_config__vcsel_period_b; 04916 04917 uint16_t range_config__sigma_thresh; 04918 04919 uint16_t range_config__min_count_rate_rtn_limit_mcps; 04920 04921 uint8_t range_config__valid_phase_low; 04922 04923 uint8_t range_config__valid_phase_high; 04924 04925 uint32_t system__intermeasurement_period; 04926 04927 uint8_t system__fractional_enable; 04928 04929 } VL53LX_timing_config_t; 04930 04931 04932 04933 04934 typedef struct { 04935 uint8_t system__grouped_parameter_hold_0; 04936 04937 uint16_t system__thresh_high; 04938 04939 uint16_t system__thresh_low; 04940 04941 uint8_t system__enable_xtalk_per_quadrant; 04942 04943 uint8_t system__seed_config; 04944 04945 uint8_t sd_config__woi_sd0; 04946 04947 uint8_t sd_config__woi_sd1; 04948 04949 uint8_t sd_config__initial_phase_sd0; 04950 04951 uint8_t sd_config__initial_phase_sd1; 04952 04953 uint8_t system__grouped_parameter_hold_1; 04954 04955 uint8_t sd_config__first_order_select; 04956 04957 uint8_t sd_config__quantifier; 04958 04959 uint8_t roi_config__user_roi_centre_spad; 04960 04961 uint8_t roi_config__user_roi_requested_global_xy_size; 04962 04963 uint8_t system__sequence_config; 04964 04965 uint8_t system__grouped_parameter_hold; 04966 04967 } VL53LX_dynamic_config_t; 04968 04969 04970 04971 04972 typedef struct { 04973 uint8_t power_management__go1_power_force; 04974 04975 uint8_t system__stream_count_ctrl; 04976 04977 uint8_t firmware__enable; 04978 04979 uint8_t system__interrupt_clear; 04980 04981 uint8_t system__mode_start; 04982 04983 } VL53LX_system_control_t; 04984 04985 04986 04987 04988 typedef struct { 04989 uint8_t result__interrupt_status; 04990 04991 uint8_t result__range_status; 04992 04993 uint8_t result__report_status; 04994 04995 uint8_t result__stream_count; 04996 04997 uint16_t result__dss_actual_effective_spads_sd0; 04998 04999 uint16_t result__peak_signal_count_rate_mcps_sd0; 05000 05001 uint16_t result__ambient_count_rate_mcps_sd0; 05002 05003 uint16_t result__sigma_sd0; 05004 05005 uint16_t result__phase_sd0; 05006 05007 uint16_t result__final_crosstalk_corrected_range_mm_sd0; 05008 05009 uint16_t result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0; 05010 05011 uint16_t result__mm_inner_actual_effective_spads_sd0; 05012 05013 uint16_t result__mm_outer_actual_effective_spads_sd0; 05014 05015 uint16_t result__avg_signal_count_rate_mcps_sd0; 05016 05017 uint16_t result__dss_actual_effective_spads_sd1; 05018 05019 uint16_t result__peak_signal_count_rate_mcps_sd1; 05020 05021 uint16_t result__ambient_count_rate_mcps_sd1; 05022 05023 uint16_t result__sigma_sd1; 05024 05025 uint16_t result__phase_sd1; 05026 05027 uint16_t result__final_crosstalk_corrected_range_mm_sd1; 05028 05029 uint16_t result__spare_0_sd1; 05030 05031 uint16_t result__spare_1_sd1; 05032 05033 uint16_t result__spare_2_sd1; 05034 05035 uint8_t result__spare_3_sd1; 05036 05037 uint8_t result__thresh_info; 05038 05039 } VL53LX_system_results_t; 05040 05041 05042 05043 05044 typedef struct { 05045 uint32_t result_core__ambient_window_events_sd0; 05046 05047 uint32_t result_core__ranging_total_events_sd0; 05048 05049 int32_t result_core__signal_total_events_sd0; 05050 05051 uint32_t result_core__total_periods_elapsed_sd0; 05052 05053 uint32_t result_core__ambient_window_events_sd1; 05054 05055 uint32_t result_core__ranging_total_events_sd1; 05056 05057 int32_t result_core__signal_total_events_sd1; 05058 05059 uint32_t result_core__total_periods_elapsed_sd1; 05060 05061 uint8_t result_core__spare_0; 05062 05063 } VL53LX_core_results_t; 05064 05065 05066 05067 05068 typedef struct { 05069 uint16_t phasecal_result__reference_phase; 05070 05071 uint8_t phasecal_result__vcsel_start; 05072 05073 uint8_t ref_spad_char_result__num_actual_ref_spads; 05074 05075 uint8_t ref_spad_char_result__ref_location; 05076 05077 uint8_t vhv_result__coldboot_status; 05078 05079 uint8_t vhv_result__search_result; 05080 05081 uint8_t vhv_result__latest_setting; 05082 05083 uint16_t result__osc_calibrate_val; 05084 05085 uint8_t ana_config__powerdown_go1; 05086 05087 uint8_t ana_config__ref_bg_ctrl; 05088 05089 uint8_t ana_config__regdvdd1v2_ctrl; 05090 05091 uint8_t ana_config__osc_slow_ctrl; 05092 05093 uint8_t test_mode__status; 05094 05095 uint8_t firmware__system_status; 05096 05097 uint8_t firmware__mode_status; 05098 05099 uint8_t firmware__secondary_mode_status; 05100 05101 uint16_t firmware__cal_repeat_rate_counter; 05102 05103 uint16_t gph__system__thresh_high; 05104 05105 uint16_t gph__system__thresh_low; 05106 05107 uint8_t gph__system__enable_xtalk_per_quadrant; 05108 05109 uint8_t gph__spare_0; 05110 05111 uint8_t gph__sd_config__woi_sd0; 05112 05113 uint8_t gph__sd_config__woi_sd1; 05114 05115 uint8_t gph__sd_config__initial_phase_sd0; 05116 05117 uint8_t gph__sd_config__initial_phase_sd1; 05118 05119 uint8_t gph__sd_config__first_order_select; 05120 05121 uint8_t gph__sd_config__quantifier; 05122 05123 uint8_t gph__roi_config__user_roi_centre_spad; 05124 05125 uint8_t gph__roi_config__user_roi_requested_global_xy_size; 05126 05127 uint8_t gph__system__sequence_config; 05128 05129 uint8_t gph__gph_id; 05130 05131 uint8_t system__interrupt_set; 05132 05133 uint8_t interrupt_manager__enables; 05134 05135 uint8_t interrupt_manager__clear; 05136 05137 uint8_t interrupt_manager__status; 05138 05139 uint8_t mcu_to_host_bank__wr_access_en; 05140 05141 uint8_t power_management__go1_reset_status; 05142 05143 uint8_t pad_startup_mode__value_ro; 05144 05145 uint8_t pad_startup_mode__value_ctrl; 05146 05147 uint32_t pll_period_us; 05148 05149 uint32_t interrupt_scheduler__data_out; 05150 05151 uint8_t nvm_bist__complete; 05152 05153 uint8_t nvm_bist__status; 05154 05155 } VL53LX_debug_results_t; 05156 05157 05158 05159 05160 typedef struct { 05161 uint8_t identification__model_id; 05162 05163 uint8_t identification__module_type; 05164 05165 uint8_t identification__revision_id; 05166 05167 uint16_t identification__module_id; 05168 05169 uint8_t ana_config__fast_osc__trim_max; 05170 05171 uint8_t ana_config__fast_osc__freq_set; 05172 05173 uint8_t ana_config__vcsel_trim; 05174 05175 uint8_t ana_config__vcsel_selion; 05176 05177 uint8_t ana_config__vcsel_selion_max; 05178 05179 uint8_t protected_laser_safety__lock_bit; 05180 05181 uint8_t laser_safety__key; 05182 05183 uint8_t laser_safety__key_ro; 05184 05185 uint8_t laser_safety__clip; 05186 05187 uint8_t laser_safety__mult; 05188 05189 uint8_t global_config__spad_enables_rtn_0; 05190 05191 uint8_t global_config__spad_enables_rtn_1; 05192 05193 uint8_t global_config__spad_enables_rtn_2; 05194 05195 uint8_t global_config__spad_enables_rtn_3; 05196 05197 uint8_t global_config__spad_enables_rtn_4; 05198 05199 uint8_t global_config__spad_enables_rtn_5; 05200 05201 uint8_t global_config__spad_enables_rtn_6; 05202 05203 uint8_t global_config__spad_enables_rtn_7; 05204 05205 uint8_t global_config__spad_enables_rtn_8; 05206 05207 uint8_t global_config__spad_enables_rtn_9; 05208 05209 uint8_t global_config__spad_enables_rtn_10; 05210 05211 uint8_t global_config__spad_enables_rtn_11; 05212 05213 uint8_t global_config__spad_enables_rtn_12; 05214 05215 uint8_t global_config__spad_enables_rtn_13; 05216 05217 uint8_t global_config__spad_enables_rtn_14; 05218 05219 uint8_t global_config__spad_enables_rtn_15; 05220 05221 uint8_t global_config__spad_enables_rtn_16; 05222 05223 uint8_t global_config__spad_enables_rtn_17; 05224 05225 uint8_t global_config__spad_enables_rtn_18; 05226 05227 uint8_t global_config__spad_enables_rtn_19; 05228 05229 uint8_t global_config__spad_enables_rtn_20; 05230 05231 uint8_t global_config__spad_enables_rtn_21; 05232 05233 uint8_t global_config__spad_enables_rtn_22; 05234 05235 uint8_t global_config__spad_enables_rtn_23; 05236 05237 uint8_t global_config__spad_enables_rtn_24; 05238 05239 uint8_t global_config__spad_enables_rtn_25; 05240 05241 uint8_t global_config__spad_enables_rtn_26; 05242 05243 uint8_t global_config__spad_enables_rtn_27; 05244 05245 uint8_t global_config__spad_enables_rtn_28; 05246 05247 uint8_t global_config__spad_enables_rtn_29; 05248 05249 uint8_t global_config__spad_enables_rtn_30; 05250 05251 uint8_t global_config__spad_enables_rtn_31; 05252 05253 uint8_t roi_config__mode_roi_centre_spad; 05254 05255 uint8_t roi_config__mode_roi_xy_size; 05256 05257 } VL53LX_nvm_copy_data_t; 05258 05259 05260 05261 05262 typedef struct { 05263 uint8_t prev_shadow_result__interrupt_status; 05264 05265 uint8_t prev_shadow_result__range_status; 05266 05267 uint8_t prev_shadow_result__report_status; 05268 05269 uint8_t prev_shadow_result__stream_count; 05270 05271 uint16_t prev_shadow_result__dss_actual_effective_spads_sd0; 05272 05273 uint16_t prev_shadow_result__peak_signal_count_rate_mcps_sd0; 05274 05275 uint16_t prev_shadow_result__ambient_count_rate_mcps_sd0; 05276 05277 uint16_t prev_shadow_result__sigma_sd0; 05278 05279 uint16_t prev_shadow_result__phase_sd0; 05280 05281 uint16_t prev_shadow_result__final_crosstalk_corrected_range_mm_sd0; 05282 05283 uint16_t 05284 psr__peak_signal_count_rate_crosstalk_corrected_mcps_sd0; 05285 05286 uint16_t prev_shadow_result__mm_inner_actual_effective_spads_sd0; 05287 05288 uint16_t prev_shadow_result__mm_outer_actual_effective_spads_sd0; 05289 05290 uint16_t prev_shadow_result__avg_signal_count_rate_mcps_sd0; 05291 05292 uint16_t prev_shadow_result__dss_actual_effective_spads_sd1; 05293 05294 uint16_t prev_shadow_result__peak_signal_count_rate_mcps_sd1; 05295 05296 uint16_t prev_shadow_result__ambient_count_rate_mcps_sd1; 05297 05298 uint16_t prev_shadow_result__sigma_sd1; 05299 05300 uint16_t prev_shadow_result__phase_sd1; 05301 05302 uint16_t prev_shadow_result__final_crosstalk_corrected_range_mm_sd1; 05303 05304 uint16_t prev_shadow_result__spare_0_sd1; 05305 05306 uint16_t prev_shadow_result__spare_1_sd1; 05307 05308 uint16_t prev_shadow_result__spare_2_sd1; 05309 05310 uint16_t prev_shadow_result__spare_3_sd1; 05311 05312 } VL53LX_prev_shadow_system_results_t; 05313 05314 05315 05316 05317 typedef struct { 05318 uint32_t prev_shadow_result_core__ambient_window_events_sd0; 05319 05320 uint32_t prev_shadow_result_core__ranging_total_events_sd0; 05321 05322 int32_t prev_shadow_result_core__signal_total_events_sd0; 05323 05324 uint32_t prev_shadow_result_core__total_periods_elapsed_sd0; 05325 05326 uint32_t prev_shadow_result_core__ambient_window_events_sd1; 05327 05328 uint32_t prev_shadow_result_core__ranging_total_events_sd1; 05329 05330 int32_t prev_shadow_result_core__signal_total_events_sd1; 05331 05332 uint32_t prev_shadow_result_core__total_periods_elapsed_sd1; 05333 05334 uint8_t prev_shadow_result_core__spare_0; 05335 05336 } VL53LX_prev_shadow_core_results_t; 05337 05338 05339 05340 05341 typedef struct { 05342 uint8_t result__debug_status; 05343 05344 uint8_t result__debug_stage; 05345 05346 } VL53LX_patch_debug_t; 05347 05348 05349 05350 05351 typedef struct { 05352 uint16_t gph__system__thresh_rate_high; 05353 05354 uint16_t gph__system__thresh_rate_low; 05355 05356 uint8_t gph__system__interrupt_config_gpio; 05357 05358 } VL53LX_gph_general_config_t; 05359 05360 05361 05362 05363 typedef struct { 05364 uint8_t gph__dss_config__roi_mode_control; 05365 05366 uint16_t gph__dss_config__manual_effective_spads_select; 05367 05368 uint8_t gph__dss_config__manual_block_select; 05369 05370 uint8_t gph__dss_config__max_spads_limit; 05371 05372 uint8_t gph__dss_config__min_spads_limit; 05373 05374 } VL53LX_gph_static_config_t; 05375 05376 05377 05378 05379 typedef struct { 05380 uint8_t gph__mm_config__timeout_macrop_a_hi; 05381 05382 uint8_t gph__mm_config__timeout_macrop_a_lo; 05383 05384 uint8_t gph__mm_config__timeout_macrop_b_hi; 05385 05386 uint8_t gph__mm_config__timeout_macrop_b_lo; 05387 05388 uint8_t gph__range_config__timeout_macrop_a_hi; 05389 05390 uint8_t gph__range_config__timeout_macrop_a_lo; 05391 05392 uint8_t gph__range_config__vcsel_period_a; 05393 05394 uint8_t gph__range_config__vcsel_period_b; 05395 05396 uint8_t gph__range_config__timeout_macrop_b_hi; 05397 05398 uint8_t gph__range_config__timeout_macrop_b_lo; 05399 05400 uint16_t gph__range_config__sigma_thresh; 05401 05402 uint16_t gph__range_config__min_count_rate_rtn_limit_mcps; 05403 05404 uint8_t gph__range_config__valid_phase_low; 05405 05406 uint8_t gph__range_config__valid_phase_high; 05407 05408 } VL53LX_gph_timing_config_t; 05409 05410 05411 05412 05413 typedef struct { 05414 uint8_t firmware__internal_stream_count_div; 05415 05416 uint8_t firmware__internal_stream_counter_val; 05417 05418 } VL53LX_fw_internal_t; 05419 05420 05421 05422 05423 typedef struct { 05424 uint8_t dss_calc__roi_ctrl; 05425 05426 uint8_t dss_calc__spare_1; 05427 05428 uint8_t dss_calc__spare_2; 05429 05430 uint8_t dss_calc__spare_3; 05431 05432 uint8_t dss_calc__spare_4; 05433 05434 uint8_t dss_calc__spare_5; 05435 05436 uint8_t dss_calc__spare_6; 05437 05438 uint8_t dss_calc__spare_7; 05439 05440 uint8_t dss_calc__user_roi_spad_en_0; 05441 05442 uint8_t dss_calc__user_roi_spad_en_1; 05443 05444 uint8_t dss_calc__user_roi_spad_en_2; 05445 05446 uint8_t dss_calc__user_roi_spad_en_3; 05447 05448 uint8_t dss_calc__user_roi_spad_en_4; 05449 05450 uint8_t dss_calc__user_roi_spad_en_5; 05451 05452 uint8_t dss_calc__user_roi_spad_en_6; 05453 05454 uint8_t dss_calc__user_roi_spad_en_7; 05455 05456 uint8_t dss_calc__user_roi_spad_en_8; 05457 05458 uint8_t dss_calc__user_roi_spad_en_9; 05459 05460 uint8_t dss_calc__user_roi_spad_en_10; 05461 05462 uint8_t dss_calc__user_roi_spad_en_11; 05463 05464 uint8_t dss_calc__user_roi_spad_en_12; 05465 05466 uint8_t dss_calc__user_roi_spad_en_13; 05467 05468 uint8_t dss_calc__user_roi_spad_en_14; 05469 05470 uint8_t dss_calc__user_roi_spad_en_15; 05471 05472 uint8_t dss_calc__user_roi_spad_en_16; 05473 05474 uint8_t dss_calc__user_roi_spad_en_17; 05475 05476 uint8_t dss_calc__user_roi_spad_en_18; 05477 05478 uint8_t dss_calc__user_roi_spad_en_19; 05479 05480 uint8_t dss_calc__user_roi_spad_en_20; 05481 05482 uint8_t dss_calc__user_roi_spad_en_21; 05483 05484 uint8_t dss_calc__user_roi_spad_en_22; 05485 05486 uint8_t dss_calc__user_roi_spad_en_23; 05487 05488 uint8_t dss_calc__user_roi_spad_en_24; 05489 05490 uint8_t dss_calc__user_roi_spad_en_25; 05491 05492 uint8_t dss_calc__user_roi_spad_en_26; 05493 05494 uint8_t dss_calc__user_roi_spad_en_27; 05495 05496 uint8_t dss_calc__user_roi_spad_en_28; 05497 05498 uint8_t dss_calc__user_roi_spad_en_29; 05499 05500 uint8_t dss_calc__user_roi_spad_en_30; 05501 05502 uint8_t dss_calc__user_roi_spad_en_31; 05503 05504 uint8_t dss_calc__user_roi_0; 05505 05506 uint8_t dss_calc__user_roi_1; 05507 05508 uint8_t dss_calc__mode_roi_0; 05509 05510 uint8_t dss_calc__mode_roi_1; 05511 05512 uint8_t sigma_estimator_calc__spare_0; 05513 05514 uint16_t vhv_result__peak_signal_rate_mcps; 05515 05516 uint32_t vhv_result__signal_total_events_ref; 05517 05518 uint16_t phasecal_result__phase_output_ref; 05519 05520 uint16_t dss_result__total_rate_per_spad; 05521 05522 uint8_t dss_result__enabled_blocks; 05523 05524 uint16_t dss_result__num_requested_spads; 05525 05526 uint16_t mm_result__inner_intersection_rate; 05527 05528 uint16_t mm_result__outer_complement_rate; 05529 05530 uint16_t mm_result__total_offset; 05531 05532 uint32_t xtalk_calc__xtalk_for_enabled_spads; 05533 05534 uint32_t xtalk_result__avg_xtalk_user_roi_kcps; 05535 05536 uint32_t xtalk_result__avg_xtalk_mm_inner_roi_kcps; 05537 05538 uint32_t xtalk_result__avg_xtalk_mm_outer_roi_kcps; 05539 05540 uint32_t range_result__accum_phase; 05541 05542 uint16_t range_result__offset_corrected_range; 05543 05544 } VL53LX_patch_results_t; 05545 05546 05547 05548 05549 typedef struct { 05550 uint8_t shadow_phasecal_result__vcsel_start; 05551 05552 uint8_t shadow_result__interrupt_status; 05553 05554 uint8_t shadow_result__range_status; 05555 05556 uint8_t shadow_result__report_status; 05557 05558 uint8_t shadow_result__stream_count; 05559 05560 uint16_t shadow_result__dss_actual_effective_spads_sd0; 05561 05562 uint16_t shadow_result__peak_signal_count_rate_mcps_sd0; 05563 05564 uint16_t shadow_result__ambient_count_rate_mcps_sd0; 05565 05566 uint16_t shadow_result__sigma_sd0; 05567 05568 uint16_t shadow_result__phase_sd0; 05569 05570 uint16_t shadow_result__final_crosstalk_corrected_range_mm_sd0; 05571 05572 uint16_t 05573 shr__peak_signal_count_rate_crosstalk_corrected_mcps_sd0; 05574 05575 uint16_t shadow_result__mm_inner_actual_effective_spads_sd0; 05576 05577 uint16_t shadow_result__mm_outer_actual_effective_spads_sd0; 05578 05579 uint16_t shadow_result__avg_signal_count_rate_mcps_sd0; 05580 05581 uint16_t shadow_result__dss_actual_effective_spads_sd1; 05582 05583 uint16_t shadow_result__peak_signal_count_rate_mcps_sd1; 05584 05585 uint16_t shadow_result__ambient_count_rate_mcps_sd1; 05586 05587 uint16_t shadow_result__sigma_sd1; 05588 05589 uint16_t shadow_result__phase_sd1; 05590 05591 uint16_t shadow_result__final_crosstalk_corrected_range_mm_sd1; 05592 05593 uint16_t shadow_result__spare_0_sd1; 05594 05595 uint16_t shadow_result__spare_1_sd1; 05596 05597 uint16_t shadow_result__spare_2_sd1; 05598 05599 uint8_t shadow_result__spare_3_sd1; 05600 05601 uint8_t shadow_result__thresh_info; 05602 05603 uint8_t shadow_phasecal_result__reference_phase_hi; 05604 05605 uint8_t shadow_phasecal_result__reference_phase_lo; 05606 05607 } VL53LX_shadow_system_results_t; 05608 05609 05610 05611 05612 typedef struct { 05613 uint32_t shadow_result_core__ambient_window_events_sd0; 05614 05615 uint32_t shadow_result_core__ranging_total_events_sd0; 05616 05617 int32_t shadow_result_core__signal_total_events_sd0; 05618 05619 uint32_t shadow_result_core__total_periods_elapsed_sd0; 05620 05621 uint32_t shadow_result_core__ambient_window_events_sd1; 05622 05623 uint32_t shadow_result_core__ranging_total_events_sd1; 05624 05625 int32_t shadow_result_core__signal_total_events_sd1; 05626 05627 uint32_t shadow_result_core__total_periods_elapsed_sd1; 05628 05629 uint8_t shadow_result_core__spare_0; 05630 05631 } VL53LX_shadow_core_results_t; 05632 05633 05634 // typedef from vl53lx_dmax_structs.h 05635 05636 #define VL53LX_MAX_AMBIENT_DMAX_VALUES 5 05637 05638 typedef struct { 05639 uint16_t ref__actual_effective_spads; 05640 uint16_t ref__peak_signal_count_rate_mcps; 05641 uint16_t ref__distance_mm; 05642 uint16_t ref_reflectance_pc; 05643 uint16_t coverglass_transmission; 05644 05645 } VL53LX_dmax_calibration_data_t; 05646 05647 05648 05649 05650 typedef struct { 05651 uint8_t signal_thresh_sigma; 05652 uint8_t ambient_thresh_sigma; 05653 int32_t min_ambient_thresh_events; 05654 int32_t signal_total_events_limit; 05655 uint16_t target_reflectance_for_dmax_calc[VL53LX_MAX_AMBIENT_DMAX_VALUES]; 05656 uint16_t max_effective_spads; 05657 uint16_t dss_config__target_total_rate_mcps; 05658 uint8_t dss_config__aperture_attenuation; 05659 } VL53LX_hist_gen3_dmax_config_t; 05660 05661 05662 05663 // define & typedef from vl53lx_hist_structs.h 05664 05665 #define VL53LX_MAX_BIN_SEQUENCE_LENGTH 6 05666 #define VL53LX_MAX_BIN_SEQUENCE_CODE 15 05667 #define VL53LX_HISTOGRAM_BUFFER_SIZE 24 05668 #define VL53LX_XTALK_HISTO_BINS 12 05669 05670 05671 05672 typedef struct { 05673 05674 uint8_t histogram_config__spad_array_selection; 05675 05676 uint8_t histogram_config__low_amb_even_bin_0_1; 05677 uint8_t histogram_config__low_amb_even_bin_2_3; 05678 uint8_t histogram_config__low_amb_even_bin_4_5; 05679 05680 uint8_t histogram_config__low_amb_odd_bin_0_1; 05681 uint8_t histogram_config__low_amb_odd_bin_2_3; 05682 uint8_t histogram_config__low_amb_odd_bin_4_5; 05683 05684 uint8_t histogram_config__mid_amb_even_bin_0_1; 05685 uint8_t histogram_config__mid_amb_even_bin_2_3; 05686 uint8_t histogram_config__mid_amb_even_bin_4_5; 05687 05688 uint8_t histogram_config__mid_amb_odd_bin_0_1; 05689 uint8_t histogram_config__mid_amb_odd_bin_2; 05690 uint8_t histogram_config__mid_amb_odd_bin_3_4; 05691 uint8_t histogram_config__mid_amb_odd_bin_5; 05692 05693 uint8_t histogram_config__user_bin_offset; 05694 05695 uint8_t histogram_config__high_amb_even_bin_0_1; 05696 uint8_t histogram_config__high_amb_even_bin_2_3; 05697 uint8_t histogram_config__high_amb_even_bin_4_5; 05698 05699 uint8_t histogram_config__high_amb_odd_bin_0_1; 05700 uint8_t histogram_config__high_amb_odd_bin_2_3; 05701 uint8_t histogram_config__high_amb_odd_bin_4_5; 05702 05703 uint16_t histogram_config__amb_thresh_low; 05704 05705 uint16_t histogram_config__amb_thresh_high; 05706 05707 05708 } VL53LX_histogram_config_t; 05709 05710 05711 05712 05713 typedef struct { 05714 05715 VL53LX_HistAlgoSelect hist_algo_select; 05716 05717 05718 VL53LX_HistTargetOrder hist_target_order; 05719 05720 05721 uint8_t filter_woi0; 05722 05723 uint8_t filter_woi1; 05724 05725 05726 VL53LX_HistAmbEstMethod hist_amb_est_method; 05727 05728 uint8_t ambient_thresh_sigma0; 05729 05730 uint8_t ambient_thresh_sigma1; 05731 05732 05733 05734 uint16_t ambient_thresh_events_scaler; 05735 05736 05737 05738 int32_t min_ambient_thresh_events; 05739 05740 uint16_t noise_threshold; 05741 05742 05743 int32_t signal_total_events_limit; 05744 05745 uint8_t sigma_estimator__sigma_ref_mm; 05746 05747 uint16_t sigma_thresh; 05748 05749 int16_t range_offset_mm; 05750 05751 uint16_t gain_factor; 05752 05753 05754 uint8_t valid_phase_low; 05755 05756 uint8_t valid_phase_high; 05757 05758 uint8_t algo__consistency_check__phase_tolerance; 05759 05760 uint8_t algo__consistency_check__event_sigma; 05761 05762 05763 05764 uint16_t algo__consistency_check__event_min_spad_count; 05765 05766 05767 05768 uint16_t algo__consistency_check__min_max_tolerance; 05769 05770 05771 uint8_t algo__crosstalk_compensation_enable; 05772 05773 uint32_t algo__crosstalk_compensation_plane_offset_kcps; 05774 05775 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps; 05776 05777 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps; 05778 05779 05780 int16_t algo__crosstalk_detect_min_valid_range_mm; 05781 05782 int16_t algo__crosstalk_detect_max_valid_range_mm; 05783 05784 uint16_t algo__crosstalk_detect_max_valid_rate_kcps; 05785 05786 uint16_t algo__crosstalk_detect_max_sigma_mm; 05787 05788 05789 05790 uint8_t algo__crosstalk_detect_event_sigma; 05791 05792 05793 05794 uint16_t algo__crosstalk_detect_min_max_tolerance; 05795 05796 05797 } VL53LX_hist_post_process_config_t; 05798 05799 05800 05801 typedef struct { 05802 05803 05804 VL53LX_DeviceState cfg_device_state; 05805 05806 VL53LX_DeviceState rd_device_state; 05807 05808 05809 uint8_t zone_id; 05810 05811 uint32_t time_stamp; 05812 05813 05814 uint8_t VL53LX_p_019; 05815 05816 uint8_t VL53LX_p_020; 05817 05818 uint8_t VL53LX_p_021; 05819 05820 uint8_t number_of_ambient_bins; 05821 05822 uint8_t bin_seq[VL53LX_MAX_BIN_SEQUENCE_LENGTH]; 05823 05824 uint8_t bin_rep[VL53LX_MAX_BIN_SEQUENCE_LENGTH]; 05825 05826 int32_t bin_data[VL53LX_HISTOGRAM_BUFFER_SIZE]; 05827 05828 05829 uint8_t result__interrupt_status; 05830 05831 uint8_t result__range_status; 05832 05833 uint8_t result__report_status; 05834 05835 uint8_t result__stream_count; 05836 05837 uint16_t result__dss_actual_effective_spads; 05838 05839 05840 uint16_t phasecal_result__reference_phase; 05841 05842 uint8_t phasecal_result__vcsel_start; 05843 05844 uint8_t cal_config__vcsel_start; 05845 05846 uint16_t vcsel_width; 05847 05848 uint8_t VL53LX_p_005; 05849 05850 uint16_t VL53LX_p_015; 05851 05852 uint32_t total_periods_elapsed; 05853 05854 05855 uint32_t peak_duration_us; 05856 05857 uint32_t woi_duration_us; 05858 05859 05860 int32_t min_bin_value; 05861 05862 int32_t max_bin_value; 05863 05864 05865 uint16_t zero_distance_phase; 05866 05867 uint8_t number_of_ambient_samples; 05868 05869 int32_t ambient_events_sum; 05870 05871 int32_t VL53LX_p_028; 05872 05873 05874 uint8_t roi_config__user_roi_centre_spad; 05875 05876 uint8_t roi_config__user_roi_requested_global_xy_size; 05877 05878 05879 } VL53LX_histogram_bin_data_t; 05880 05881 05882 05883 05884 typedef struct { 05885 05886 05887 uint8_t zone_id; 05888 05889 uint32_t time_stamp; 05890 05891 05892 uint8_t VL53LX_p_019; 05893 05894 uint8_t VL53LX_p_020; 05895 05896 uint8_t VL53LX_p_021; 05897 05898 uint32_t bin_data[VL53LX_XTALK_HISTO_BINS]; 05899 05900 05901 05902 uint16_t phasecal_result__reference_phase; 05903 05904 uint8_t phasecal_result__vcsel_start; 05905 05906 uint8_t cal_config__vcsel_start; 05907 05908 uint16_t vcsel_width; 05909 05910 uint16_t VL53LX_p_015; 05911 05912 uint16_t zero_distance_phase; 05913 05914 05915 } VL53LX_xtalk_histogram_shape_t; 05916 05917 05918 05919 05920 typedef struct { 05921 05922 05923 VL53LX_xtalk_histogram_shape_t xtalk_shape; 05924 05925 VL53LX_histogram_bin_data_t xtalk_hist_removed; 05926 05927 } VL53LX_xtalk_histogram_data_t; 05928 05929 05930 /* vl53lx_hist_private_structs.h */ 05931 05932 #define VL53LX_D_001 8 05933 05934 05935 05936 05937 05938 typedef struct { 05939 05940 uint8_t VL53LX_p_019; 05941 05942 05943 uint8_t VL53LX_p_020; 05944 05945 05946 uint8_t VL53LX_p_021; 05947 05948 05949 uint8_t VL53LX_p_029; 05950 05951 05952 int32_t VL53LX_p_016; 05953 05954 05955 05956 int32_t VL53LX_p_043[VL53LX_HISTOGRAM_BUFFER_SIZE]; 05957 05958 int32_t VL53LX_p_068[VL53LX_HISTOGRAM_BUFFER_SIZE]; 05959 05960 05961 uint8_t VL53LX_p_040[VL53LX_HISTOGRAM_BUFFER_SIZE]; 05962 05963 05964 int32_t VL53LX_p_018[VL53LX_HISTOGRAM_BUFFER_SIZE]; 05965 05966 uint16_t VL53LX_p_014[VL53LX_HISTOGRAM_BUFFER_SIZE]; 05967 05968 uint16_t VL53LX_p_008[VL53LX_HISTOGRAM_BUFFER_SIZE]; 05969 05970 05971 } VL53LX_hist_gen1_algo_private_data_t; 05972 05973 05974 05975 05976 05977 05978 05979 05980 05981 05982 typedef struct { 05983 05984 uint8_t VL53LX_p_019; 05985 05986 05987 uint8_t VL53LX_p_020; 05988 05989 05990 uint8_t VL53LX_p_021; 05991 05992 05993 uint16_t VL53LX_p_015; 05994 05995 05996 uint8_t VL53LX_p_005; 05997 05998 05999 uint8_t VL53LX_p_029; 06000 06001 06002 int32_t VL53LX_p_028; 06003 06004 06005 int32_t VL53LX_p_016; 06006 06007 06008 06009 int32_t VL53LX_p_007[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06010 06011 06012 int32_t VL53LX_p_032[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06013 06014 06015 int32_t VL53LX_p_001[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06016 06017 06018 06019 int32_t VL53LX_p_018[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06020 06021 06022 int32_t VL53LX_p_055[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06023 06024 06025 int32_t VL53LX_p_053[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06026 06027 06028 int32_t VL53LX_p_054[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06029 06030 06031 06032 } VL53LX_hist_gen2_algo_filtered_data_t; 06033 06034 06035 06036 06037 06038 06039 06040 06041 06042 06043 typedef struct { 06044 06045 uint8_t VL53LX_p_019; 06046 06047 06048 uint8_t VL53LX_p_020; 06049 06050 06051 uint8_t VL53LX_p_021; 06052 06053 06054 int32_t VL53LX_p_031; 06055 06056 06057 06058 uint8_t VL53LX_p_069[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06059 06060 06061 uint8_t VL53LX_p_070[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06062 06063 06064 06065 uint32_t VL53LX_p_014[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06066 06067 06068 uint16_t VL53LX_p_008[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06069 06070 06071 06072 uint8_t VL53LX_p_040[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06073 06074 06075 06076 } VL53LX_hist_gen2_algo_detection_data_t; 06077 06078 06079 06080 06081 06082 06083 06084 06085 06086 06087 typedef struct { 06088 06089 uint8_t VL53LX_p_012; 06090 06091 06092 uint8_t VL53LX_p_019; 06093 06094 06095 uint8_t VL53LX_p_023; 06096 06097 06098 uint8_t VL53LX_p_024; 06099 06100 06101 uint8_t VL53LX_p_013; 06102 06103 06104 06105 uint8_t VL53LX_p_025; 06106 06107 06108 uint8_t VL53LX_p_051; 06109 06110 06111 06112 int32_t VL53LX_p_016; 06113 06114 06115 int32_t VL53LX_p_017; 06116 06117 06118 int32_t VL53LX_p_010; 06119 06120 06121 06122 uint32_t VL53LX_p_026; 06123 06124 06125 uint32_t VL53LX_p_011; 06126 06127 06128 uint32_t VL53LX_p_027; 06129 06130 06131 06132 uint16_t VL53LX_p_002; 06133 06134 06135 06136 } VL53LX_hist_pulse_data_t; 06137 06138 06139 06140 06141 06142 06143 06144 06145 06146 06147 typedef struct { 06148 06149 uint8_t VL53LX_p_019; 06150 06151 06152 uint8_t VL53LX_p_020; 06153 06154 06155 uint8_t VL53LX_p_021; 06156 06157 06158 uint8_t VL53LX_p_030; 06159 06160 06161 uint8_t VL53LX_p_039; 06162 06163 06164 int32_t VL53LX_p_028; 06165 06166 06167 int32_t VL53LX_p_031; 06168 06169 06170 06171 uint8_t VL53LX_p_040[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06172 06173 06174 uint8_t VL53LX_p_041[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06175 06176 06177 uint8_t VL53LX_p_042[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06178 06179 06180 06181 int32_t VL53LX_p_052[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06182 06183 06184 int32_t VL53LX_p_043[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06185 06186 06187 int32_t VL53LX_p_018[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06188 06189 06190 06191 uint8_t VL53LX_p_044; 06192 06193 06194 uint8_t VL53LX_p_045; 06195 06196 06197 uint8_t VL53LX_p_046; 06198 06199 06200 06201 VL53LX_hist_pulse_data_t VL53LX_p_003[VL53LX_D_001]; 06202 06203 06204 06205 06206 06207 06208 VL53LX_histogram_bin_data_t VL53LX_p_006; 06209 06210 06211 VL53LX_histogram_bin_data_t VL53LX_p_047; 06212 06213 06214 VL53LX_histogram_bin_data_t VL53LX_p_048; 06215 06216 06217 VL53LX_histogram_bin_data_t VL53LX_p_049; 06218 06219 06220 VL53LX_histogram_bin_data_t VL53LX_p_050; 06221 06222 06223 06224 06225 06226 06227 } VL53LX_hist_gen3_algo_private_data_t; 06228 06229 06230 06231 06232 06233 06234 06235 06236 06237 06238 typedef struct { 06239 06240 uint8_t VL53LX_p_019; 06241 06242 06243 uint8_t VL53LX_p_020; 06244 06245 06246 uint8_t VL53LX_p_021; 06247 06248 06249 06250 int32_t VL53LX_p_007[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06251 06252 06253 int32_t VL53LX_p_032[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06254 06255 06256 int32_t VL53LX_p_001[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06257 06258 06259 06260 int32_t VL53LX_p_053[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06261 06262 06263 int32_t VL53LX_p_054[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06264 06265 06266 06267 uint8_t VL53LX_p_040[VL53LX_HISTOGRAM_BUFFER_SIZE]; 06268 06269 06270 06271 } VL53LX_hist_gen4_algo_filtered_data_t; 06272 06273 06274 06275 // define & typedef from VL53Lx_ll_def.h 06276 06277 06278 06279 06280 #define VL53LX_LL_API_IMPLEMENTATION_VER_MAJOR 1 06281 06282 #define VL53LX_LL_API_IMPLEMENTATION_VER_MINOR 1 06283 06284 #define VL53LX_LL_API_IMPLEMENTATION_VER_SUB 1 06285 06286 #define VL53LX_LL_API_IMPLEMENTATION_VER_REVISION 0 06287 06288 #define VL53LX_LL_API_IMPLEMENTATION_VER_STRING "1.1.1" 06289 06290 06291 #define VL53LX_FIRMWARE_VER_MINIMUM 398 06292 #define VL53LX_FIRMWARE_VER_MAXIMUM 400 06293 06294 06295 06296 06297 #define VL53LX_LL_CALIBRATION_DATA_STRUCT_VERSION 0xECAB0102 06298 06299 06300 06301 06302 #define VL53LX_LL_ZONE_CALIBRATION_DATA_STRUCT_VERSION 0xECAE0101 06303 06304 06305 06306 06307 06308 #define VL53LX_BIN_REC_SIZE 6 06309 06310 #define VL53LX_TIMING_CONF_A_B_SIZE 2 06311 06312 #define VL53LX_FRAME_WAIT_EVENT 6 06313 06314 06315 06316 06317 #define VL53LX_MAX_XTALK_RANGE_RESULTS 5 06318 06319 06320 #define VL53LX_MAX_OFFSET_RANGE_RESULTS 3 06321 06322 06323 #define VL53LX_NVM_MAX_FMT_RANGE_DATA 4 06324 06325 06326 #define VL53LX_NVM_PEAK_RATE_MAP_SAMPLES 25 06327 06328 #define VL53LX_NVM_PEAK_RATE_MAP_WIDTH 5 06329 06330 #define VL53LX_NVM_PEAK_RATE_MAP_HEIGHT 5 06331 06332 06333 06334 06335 #define VL53LX_ERROR_DEVICE_FIRMWARE_TOO_OLD ((VL53LX_Error) - 80) 06336 06337 #define VL53LX_ERROR_DEVICE_FIRMWARE_TOO_NEW ((VL53LX_Error) - 85) 06338 06339 #define VL53LX_ERROR_UNIT_TEST_FAIL ((VL53LX_Error) - 90) 06340 06341 #define VL53LX_ERROR_FILE_READ_FAIL ((VL53LX_Error) - 95) 06342 06343 #define VL53LX_ERROR_FILE_WRITE_FAIL ((VL53LX_Error) - 96) 06344 06345 06346 06347 06348 06349 06350 typedef struct { 06351 uint32_t ll_revision; 06352 uint8_t ll_major; 06353 uint8_t ll_minor; 06354 uint8_t ll_build; 06355 } VL53LX_ll_version_t; 06356 06357 06358 06359 06360 typedef struct { 06361 06362 uint8_t device_test_mode; 06363 uint8_t VL53LX_p_005; 06364 uint32_t timeout_us; 06365 uint16_t target_count_rate_mcps; 06366 06367 uint16_t min_count_rate_limit_mcps; 06368 06369 uint16_t max_count_rate_limit_mcps; 06370 06371 06372 } VL53LX_refspadchar_config_t; 06373 06374 06375 06376 06377 typedef struct { 06378 06379 uint16_t dss_config__target_total_rate_mcps; 06380 06381 uint32_t phasecal_config_timeout_us; 06382 06383 uint32_t mm_config_timeout_us; 06384 06385 uint32_t range_config_timeout_us; 06386 06387 uint8_t num_of_samples; 06388 06389 int16_t algo__crosstalk_extract_min_valid_range_mm; 06390 06391 int16_t algo__crosstalk_extract_max_valid_range_mm; 06392 06393 uint16_t algo__crosstalk_extract_max_valid_rate_kcps; 06394 06395 uint16_t algo__crosstalk_extract_max_sigma_mm; 06396 06397 06398 } VL53LX_xtalkextract_config_t; 06399 06400 06401 06402 06403 typedef struct { 06404 06405 uint16_t dss_config__target_total_rate_mcps; 06406 06407 uint32_t phasecal_config_timeout_us; 06408 06409 uint32_t range_config_timeout_us; 06410 06411 uint32_t mm_config_timeout_us; 06412 06413 uint8_t pre_num_of_samples; 06414 06415 uint8_t mm1_num_of_samples; 06416 06417 uint8_t mm2_num_of_samples; 06418 06419 06420 } VL53LX_offsetcal_config_t; 06421 06422 06423 06424 06425 typedef struct { 06426 06427 uint16_t dss_config__target_total_rate_mcps; 06428 06429 uint32_t phasecal_config_timeout_us; 06430 06431 uint32_t mm_config_timeout_us; 06432 06433 uint32_t range_config_timeout_us; 06434 06435 uint16_t phasecal_num_of_samples; 06436 06437 uint16_t zone_num_of_samples; 06438 06439 06440 } VL53LX_zonecal_config_t; 06441 06442 06443 06444 06445 06446 typedef struct { 06447 06448 VL53LX_DeviceSscArray array_select; 06449 06450 uint8_t VL53LX_p_005; 06451 06452 uint8_t vcsel_start; 06453 06454 uint8_t vcsel_width; 06455 06456 uint32_t timeout_us; 06457 06458 uint16_t rate_limit_mcps; 06459 06460 06461 } VL53LX_ssc_config_t; 06462 06463 06464 06465 06466 typedef struct { 06467 06468 06469 uint32_t algo__crosstalk_compensation_plane_offset_kcps; 06470 06471 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps; 06472 06473 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps; 06474 06475 uint32_t nvm_default__crosstalk_compensation_plane_offset_kcps; 06476 06477 int16_t nvm_default__crosstalk_compensation_x_plane_gradient_kcps; 06478 06479 int16_t nvm_default__crosstalk_compensation_y_plane_gradient_kcps; 06480 06481 uint8_t global_crosstalk_compensation_enable; 06482 06483 int16_t histogram_mode_crosstalk_margin_kcps; 06484 06485 int16_t lite_mode_crosstalk_margin_kcps; 06486 06487 uint8_t crosstalk_range_ignore_threshold_mult; 06488 06489 uint16_t crosstalk_range_ignore_threshold_rate_mcps; 06490 06491 int16_t algo__crosstalk_detect_min_valid_range_mm; 06492 06493 int16_t algo__crosstalk_detect_max_valid_range_mm; 06494 06495 uint16_t algo__crosstalk_detect_max_valid_rate_kcps; 06496 06497 uint16_t algo__crosstalk_detect_max_sigma_mm; 06498 06499 06500 06501 } VL53LX_xtalk_config_t; 06502 06503 06504 06505 06506 typedef struct { 06507 06508 06509 uint16_t tp_tuning_parm_version; 06510 06511 uint16_t tp_tuning_parm_key_table_version; 06512 06513 uint16_t tp_tuning_parm_lld_version; 06514 06515 uint8_t tp_init_phase_rtn_lite_long; 06516 06517 uint8_t tp_init_phase_rtn_lite_med; 06518 06519 uint8_t tp_init_phase_rtn_lite_short; 06520 06521 uint8_t tp_init_phase_ref_lite_long; 06522 06523 uint8_t tp_init_phase_ref_lite_med; 06524 06525 uint8_t tp_init_phase_ref_lite_short; 06526 06527 06528 uint8_t tp_init_phase_rtn_hist_long; 06529 06530 uint8_t tp_init_phase_rtn_hist_med; 06531 06532 uint8_t tp_init_phase_rtn_hist_short; 06533 06534 uint8_t tp_init_phase_ref_hist_long; 06535 06536 uint8_t tp_init_phase_ref_hist_med; 06537 06538 uint8_t tp_init_phase_ref_hist_short; 06539 06540 06541 uint8_t tp_consistency_lite_phase_tolerance; 06542 06543 uint8_t tp_phasecal_target; 06544 06545 uint16_t tp_cal_repeat_rate; 06546 06547 uint8_t tp_lite_min_clip; 06548 06549 06550 uint16_t tp_lite_long_sigma_thresh_mm; 06551 06552 uint16_t tp_lite_med_sigma_thresh_mm; 06553 06554 uint16_t tp_lite_short_sigma_thresh_mm; 06555 06556 06557 uint16_t tp_lite_long_min_count_rate_rtn_mcps; 06558 06559 uint16_t tp_lite_med_min_count_rate_rtn_mcps; 06560 06561 uint16_t tp_lite_short_min_count_rate_rtn_mcps; 06562 06563 06564 uint8_t tp_lite_sigma_est_pulse_width_ns; 06565 06566 uint8_t tp_lite_sigma_est_amb_width_ns; 06567 06568 uint8_t tp_lite_sigma_ref_mm; 06569 06570 uint8_t tp_lite_seed_cfg; 06571 06572 uint8_t tp_timed_seed_cfg; 06573 06574 06575 uint8_t tp_lite_quantifier; 06576 06577 uint8_t tp_lite_first_order_select; 06578 06579 06580 uint16_t tp_dss_target_lite_mcps; 06581 06582 uint16_t tp_dss_target_histo_mcps; 06583 06584 uint16_t tp_dss_target_histo_mz_mcps; 06585 06586 uint16_t tp_dss_target_timed_mcps; 06587 06588 uint16_t tp_dss_target_very_short_mcps; 06589 06590 06591 uint32_t tp_phasecal_timeout_lite_us; 06592 06593 uint32_t tp_phasecal_timeout_hist_long_us; 06594 06595 uint32_t tp_phasecal_timeout_hist_med_us; 06596 06597 uint32_t tp_phasecal_timeout_hist_short_us; 06598 06599 06600 uint32_t tp_phasecal_timeout_mz_long_us; 06601 06602 uint32_t tp_phasecal_timeout_mz_med_us; 06603 06604 uint32_t tp_phasecal_timeout_mz_short_us; 06605 06606 uint32_t tp_phasecal_timeout_timed_us; 06607 06608 06609 uint32_t tp_mm_timeout_lite_us; 06610 06611 uint32_t tp_mm_timeout_histo_us; 06612 06613 uint32_t tp_mm_timeout_mz_us; 06614 06615 uint32_t tp_mm_timeout_timed_us; 06616 06617 uint32_t tp_mm_timeout_lpa_us; 06618 06619 06620 uint32_t tp_range_timeout_lite_us; 06621 06622 uint32_t tp_range_timeout_histo_us; 06623 06624 uint32_t tp_range_timeout_mz_us; 06625 06626 uint32_t tp_range_timeout_timed_us; 06627 06628 uint32_t tp_range_timeout_lpa_us; 06629 06630 uint32_t tp_phasecal_patch_power; 06631 06632 uint32_t tp_hist_merge; 06633 06634 uint32_t tp_reset_merge_threshold; 06635 06636 uint32_t tp_hist_merge_max_size; 06637 06638 06639 } VL53LX_tuning_parm_storage_t; 06640 06641 06642 06643 06644 06645 typedef struct { 06646 06647 uint8_t x_centre; 06648 uint8_t y_centre; 06649 06650 } VL53LX_optical_centre_t; 06651 06652 06653 06654 06655 typedef struct { 06656 06657 uint8_t x_centre; 06658 uint8_t y_centre; 06659 uint8_t width; 06660 uint8_t height; 06661 06662 } VL53LX_user_zone_t; 06663 06664 06665 06666 06667 typedef struct { 06668 06669 uint8_t max_zones; 06670 uint8_t active_zones; 06671 06672 06673 06674 VL53LX_histogram_config_t multizone_hist_cfg; 06675 06676 VL53LX_user_zone_t user_zones[VL53LX_MAX_USER_ZONES]; 06677 06678 06679 uint8_t bin_config[VL53LX_MAX_USER_ZONES]; 06680 06681 06682 } VL53LX_zone_config_t; 06683 06684 06685 06686 typedef struct { 06687 06688 06689 VL53LX_GPIO_Interrupt_Mode intr_mode_distance; 06690 06691 06692 VL53LX_GPIO_Interrupt_Mode intr_mode_rate; 06693 06694 06695 uint8_t intr_new_measure_ready; 06696 06697 06698 uint8_t intr_no_target; 06699 06700 06701 uint8_t intr_combined_mode; 06702 06703 06704 06705 06706 06707 uint16_t threshold_distance_high; 06708 06709 06710 uint16_t threshold_distance_low; 06711 06712 06713 uint16_t threshold_rate_high; 06714 06715 06716 uint16_t threshold_rate_low; 06717 06718 } VL53LX_GPIO_interrupt_config_t; 06719 06720 06721 06722 06723 typedef struct { 06724 06725 06726 uint8_t vhv_loop_bound; 06727 06728 06729 uint8_t is_low_power_auto_mode; 06730 06731 06732 uint8_t low_power_auto_range_count; 06733 06734 06735 uint8_t saved_interrupt_config; 06736 06737 06738 uint8_t saved_vhv_init; 06739 06740 06741 uint8_t saved_vhv_timeout; 06742 06743 06744 uint8_t first_run_phasecal_result; 06745 06746 06747 uint32_t dss__total_rate_per_spad_mcps; 06748 06749 06750 uint16_t dss__required_spads; 06751 06752 } VL53LX_low_power_auto_data_t; 06753 06754 06755 06756 06757 06758 06759 06760 typedef struct { 06761 06762 06763 uint8_t smudge_corr_enabled; 06764 06765 06766 uint8_t smudge_corr_apply_enabled; 06767 06768 06769 uint8_t smudge_corr_single_apply; 06770 06771 06772 06773 06774 uint16_t smudge_margin; 06775 06776 06777 uint32_t noise_margin; 06778 06779 06780 uint32_t user_xtalk_offset_limit; 06781 06782 06783 uint8_t user_xtalk_offset_limit_hi; 06784 06785 06786 uint32_t sample_limit; 06787 06788 06789 uint32_t single_xtalk_delta; 06790 06791 06792 uint32_t averaged_xtalk_delta; 06793 06794 06795 uint32_t smudge_corr_clip_limit; 06796 06797 06798 uint32_t smudge_corr_ambient_threshold; 06799 06800 06801 uint8_t scaler_calc_method; 06802 06803 06804 int16_t x_gradient_scaler; 06805 06806 06807 int16_t y_gradient_scaler; 06808 06809 06810 uint8_t user_scaler_set; 06811 06812 06813 uint32_t nodetect_ambient_threshold; 06814 06815 06816 uint32_t nodetect_sample_limit; 06817 06818 06819 uint32_t nodetect_xtalk_offset; 06820 06821 06822 uint16_t nodetect_min_range_mm; 06823 06824 06825 uint32_t max_smudge_factor; 06826 06827 } VL53LX_smudge_corrector_config_t; 06828 06829 06830 06831 typedef struct { 06832 06833 06834 uint32_t current_samples; 06835 06836 06837 uint32_t required_samples; 06838 06839 06840 uint64_t accumulator; 06841 06842 06843 uint32_t nodetect_counter; 06844 06845 } VL53LX_smudge_corrector_internals_t; 06846 06847 06848 06849 typedef struct { 06850 06851 06852 uint8_t smudge_corr_valid; 06853 06854 06855 uint8_t smudge_corr_clipped; 06856 06857 06858 uint8_t single_xtalk_delta_flag; 06859 06860 06861 uint8_t averaged_xtalk_delta_flag; 06862 06863 06864 uint8_t sample_limit_exceeded_flag; 06865 06866 06867 uint8_t gradient_zero_flag; 06868 06869 06870 uint8_t new_xtalk_applied_flag; 06871 06872 06873 uint32_t algo__crosstalk_compensation_plane_offset_kcps; 06874 06875 06876 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps; 06877 06878 06879 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps; 06880 06881 06882 } VL53LX_smudge_corrector_data_t; 06883 06884 06885 06886 06887 06888 typedef struct { 06889 06890 06891 06892 uint8_t range_id; 06893 06894 uint32_t time_stamp; 06895 06896 uint8_t VL53LX_p_012; 06897 06898 uint8_t VL53LX_p_019; 06899 06900 uint8_t VL53LX_p_023; 06901 06902 uint8_t VL53LX_p_024; 06903 06904 uint8_t VL53LX_p_013; 06905 06906 uint8_t VL53LX_p_025; 06907 06908 06909 uint16_t width; 06910 06911 uint8_t VL53LX_p_029; 06912 06913 06914 uint16_t fast_osc_frequency; 06915 06916 uint16_t zero_distance_phase; 06917 06918 uint16_t VL53LX_p_004; 06919 06920 06921 uint32_t total_periods_elapsed; 06922 06923 06924 uint32_t peak_duration_us; 06925 06926 06927 uint32_t woi_duration_us; 06928 06929 06930 06931 06932 06933 uint32_t VL53LX_p_016; 06934 06935 uint32_t VL53LX_p_017; 06936 06937 int32_t VL53LX_p_010; 06938 06939 06940 06941 06942 uint16_t peak_signal_count_rate_mcps; 06943 06944 uint16_t avg_signal_count_rate_mcps; 06945 06946 uint16_t ambient_count_rate_mcps; 06947 06948 uint16_t total_rate_per_spad_mcps; 06949 06950 uint32_t VL53LX_p_009; 06951 06952 06953 06954 06955 uint16_t VL53LX_p_002; 06956 06957 06958 06959 06960 uint16_t VL53LX_p_026; 06961 06962 uint16_t VL53LX_p_011; 06963 06964 uint16_t VL53LX_p_027; 06965 06966 06967 06968 06969 int16_t min_range_mm; 06970 06971 int16_t median_range_mm; 06972 06973 int16_t max_range_mm; 06974 06975 06976 06977 06978 uint8_t range_status; 06979 06980 } VL53LX_range_data_t; 06981 06982 06983 06984 06985 typedef struct { 06986 06987 VL53LX_DeviceState cfg_device_state; 06988 06989 VL53LX_DeviceState rd_device_state; 06990 06991 uint8_t zone_id; 06992 06993 uint8_t stream_count; 06994 06995 06996 int16_t VL53LX_p_022[VL53LX_MAX_AMBIENT_DMAX_VALUES]; 06997 06998 int16_t wrap_dmax_mm; 06999 07000 07001 uint8_t device_status; 07002 07003 07004 uint8_t max_results; 07005 07006 uint8_t active_results; 07007 07008 VL53LX_range_data_t VL53LX_p_003[VL53LX_MAX_RANGE_RESULTS]; 07009 07010 VL53LX_range_data_t xmonitor; 07011 07012 VL53LX_smudge_corrector_data_t smudge_corrector_data; 07013 07014 07015 07016 } VL53LX_range_results_t; 07017 07018 07019 07020 07021 typedef struct { 07022 07023 uint8_t no_of_samples; 07024 07025 uint32_t rate_per_spad_kcps_sum; 07026 07027 uint32_t rate_per_spad_kcps_avg; 07028 07029 int32_t signal_total_events_sum; 07030 07031 int32_t signal_total_events_avg; 07032 07033 uint32_t sigma_mm_sum; 07034 07035 uint32_t sigma_mm_avg; 07036 07037 uint32_t median_phase_sum; 07038 07039 uint32_t median_phase_avg; 07040 07041 07042 } VL53LX_xtalk_range_data_t; 07043 07044 07045 07046 07047 typedef struct { 07048 07049 VL53LX_Error cal_status; 07050 07051 uint8_t num_of_samples_status; 07052 07053 uint8_t zero_samples_status; 07054 07055 uint8_t max_sigma_status; 07056 07057 uint8_t max_results; 07058 07059 uint8_t active_results; 07060 07061 07062 VL53LX_xtalk_range_data_t 07063 VL53LX_p_003[VL53LX_MAX_XTALK_RANGE_RESULTS]; 07064 07065 VL53LX_histogram_bin_data_t central_histogram_sum; 07066 07067 VL53LX_histogram_bin_data_t central_histogram_avg; 07068 07069 uint8_t central_histogram__window_start; 07070 07071 uint8_t central_histogram__window_end; 07072 07073 VL53LX_histogram_bin_data_t 07074 histogram_avg_1[VL53LX_MAX_XTALK_RANGE_RESULTS]; 07075 07076 VL53LX_histogram_bin_data_t 07077 histogram_avg_2[VL53LX_MAX_XTALK_RANGE_RESULTS]; 07078 07079 VL53LX_histogram_bin_data_t 07080 xtalk_avg[VL53LX_MAX_XTALK_RANGE_RESULTS]; 07081 07082 07083 } VL53LX_xtalk_range_results_t; 07084 07085 07086 07087 07088 typedef struct { 07089 07090 uint8_t preset_mode; 07091 07092 uint8_t dss_config__roi_mode_control; 07093 07094 uint16_t dss_config__manual_effective_spads_select; 07095 07096 uint8_t no_of_samples; 07097 07098 uint32_t effective_spads; 07099 07100 uint32_t peak_rate_mcps; 07101 07102 uint32_t VL53LX_p_002; 07103 07104 int32_t median_range_mm; 07105 07106 int32_t range_mm_offset; 07107 07108 07109 } VL53LX_offset_range_data_t; 07110 07111 07112 07113 07114 typedef struct { 07115 07116 int16_t cal_distance_mm; 07117 07118 uint16_t cal_reflectance_pc; 07119 07120 VL53LX_Error cal_status; 07121 07122 uint8_t cal_report; 07123 07124 uint8_t max_results; 07125 07126 uint8_t active_results; 07127 07128 VL53LX_offset_range_data_t 07129 VL53LX_p_003[VL53LX_MAX_OFFSET_RANGE_RESULTS]; 07130 07131 07132 } VL53LX_offset_range_results_t; 07133 07134 07135 07136 07137 typedef struct { 07138 07139 uint16_t result__mm_inner_actual_effective_spads; 07140 07141 uint16_t result__mm_outer_actual_effective_spads; 07142 07143 uint16_t result__mm_inner_peak_signal_count_rtn_mcps; 07144 07145 uint16_t result__mm_outer_peak_signal_count_rtn_mcps; 07146 07147 07148 } VL53LX_additional_offset_cal_data_t; 07149 07150 07151 07152 typedef struct { 07153 int16_t short_a_offset_mm; 07154 int16_t short_b_offset_mm; 07155 int16_t medium_a_offset_mm; 07156 int16_t medium_b_offset_mm; 07157 int16_t long_a_offset_mm; 07158 int16_t long_b_offset_mm; 07159 } VL53LX_per_vcsel_period_offset_cal_data_t; 07160 07161 07162 07163 07164 07165 typedef struct { 07166 07167 uint32_t VL53LX_p_016; 07168 07169 uint32_t VL53LX_p_017; 07170 07171 uint16_t VL53LX_p_011; 07172 07173 uint8_t range_status; 07174 07175 07176 } VL53LX_object_data_t; 07177 07178 07179 07180 07181 typedef struct { 07182 07183 VL53LX_DeviceState cfg_device_state; 07184 07185 VL53LX_DeviceState rd_device_state; 07186 07187 uint8_t zone_id; 07188 07189 uint8_t stream_count; 07190 07191 uint8_t max_objects; 07192 07193 uint8_t active_objects; 07194 07195 VL53LX_object_data_t VL53LX_p_003[VL53LX_MAX_RANGE_RESULTS]; 07196 07197 07198 VL53LX_object_data_t xmonitor; 07199 07200 07201 } VL53LX_zone_objects_t; 07202 07203 07204 07205 07206 07207 07208 typedef struct { 07209 07210 uint8_t max_zones; 07211 07212 uint8_t active_zones; 07213 07214 VL53LX_zone_objects_t VL53LX_p_003[VL53LX_MAX_USER_ZONES]; 07215 07216 07217 } VL53LX_zone_results_t; 07218 07219 07220 07221 07222 typedef struct { 07223 07224 VL53LX_DeviceState rd_device_state; 07225 07226 07227 uint8_t number_of_ambient_bins; 07228 07229 07230 uint16_t result__dss_actual_effective_spads; 07231 07232 uint8_t VL53LX_p_005; 07233 07234 uint32_t total_periods_elapsed; 07235 07236 07237 int32_t ambient_events_sum; 07238 07239 07240 } VL53LX_zone_hist_info_t; 07241 07242 07243 07244 07245 typedef struct { 07246 07247 uint8_t max_zones; 07248 07249 uint8_t active_zones; 07250 07251 VL53LX_zone_hist_info_t VL53LX_p_003[VL53LX_MAX_USER_ZONES]; 07252 07253 07254 } VL53LX_zone_histograms_t; 07255 07256 07257 07258 07259 typedef struct { 07260 07261 uint32_t no_of_samples; 07262 07263 uint32_t effective_spads; 07264 07265 uint32_t peak_rate_mcps; 07266 07267 uint32_t VL53LX_p_011; 07268 07269 uint32_t VL53LX_p_002; 07270 07271 int32_t median_range_mm; 07272 07273 int32_t range_mm_offset; 07274 07275 07276 } VL53LX_zone_calibration_data_t; 07277 07278 07279 07280 07281 07282 07283 typedef struct { 07284 07285 uint32_t struct_version; 07286 07287 VL53LX_DevicePresetModes preset_mode; 07288 07289 VL53LX_DeviceZonePreset zone_preset; 07290 07291 int16_t cal_distance_mm; 07292 07293 uint16_t cal_reflectance_pc; 07294 07295 uint16_t phasecal_result__reference_phase; 07296 07297 uint16_t zero_distance_phase; 07298 07299 VL53LX_Error cal_status; 07300 07301 uint8_t max_zones; 07302 07303 uint8_t active_zones; 07304 07305 VL53LX_zone_calibration_data_t VL53LX_p_003[VL53LX_MAX_USER_ZONES]; 07306 07307 07308 } VL53LX_zone_calibration_results_t; 07309 07310 07311 07312 07313 07314 typedef struct { 07315 07316 int16_t cal_distance_mm; 07317 07318 uint16_t cal_reflectance_pc; 07319 07320 uint16_t max_samples; 07321 07322 uint16_t width; 07323 07324 uint16_t height; 07325 07326 uint16_t peak_rate_mcps[VL53LX_NVM_PEAK_RATE_MAP_SAMPLES]; 07327 07328 07329 } VL53LX_cal_peak_rate_map_t; 07330 07331 07332 07333 07334 typedef struct { 07335 07336 uint8_t expected_stream_count; 07337 07338 uint8_t expected_gph_id; 07339 07340 uint8_t dss_mode; 07341 07342 uint16_t dss_requested_effective_spad_count; 07343 07344 uint8_t seed_cfg; 07345 07346 uint8_t initial_phase_seed; 07347 07348 07349 uint8_t roi_config__user_roi_centre_spad; 07350 07351 uint8_t roi_config__user_roi_requested_global_xy_size; 07352 07353 07354 } VL53LX_zone_private_dyn_cfg_t; 07355 07356 07357 07358 07359 typedef struct { 07360 07361 uint8_t max_zones; 07362 07363 uint8_t active_zones; 07364 07365 VL53LX_zone_private_dyn_cfg_t VL53LX_p_003[VL53LX_MAX_USER_ZONES]; 07366 07367 07368 } VL53LX_zone_private_dyn_cfgs_t; 07369 07370 07371 07372 typedef struct { 07373 07374 uint32_t algo__crosstalk_compensation_plane_offset_kcps; 07375 07376 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps; 07377 07378 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps; 07379 07380 uint32_t algo__xtalk_cpo_HistoMerge_kcps[VL53LX_BIN_REC_SIZE]; 07381 07382 07383 } VL53LX_xtalk_calibration_results_t; 07384 07385 07386 07387 07388 typedef struct { 07389 07390 07391 uint32_t sample_count; 07392 07393 07394 uint32_t pll_period_mm; 07395 07396 07397 uint32_t peak_duration_us_sum; 07398 07399 07400 uint32_t effective_spad_count_sum; 07401 07402 07403 uint32_t zero_distance_phase_sum; 07404 07405 07406 uint32_t zero_distance_phase_avg; 07407 07408 07409 int32_t event_scaler_sum; 07410 07411 07412 int32_t event_scaler_avg; 07413 07414 07415 int32_t signal_events_sum; 07416 07417 07418 uint32_t xtalk_rate_kcps_per_spad; 07419 07420 07421 int32_t xtalk_start_phase; 07422 07423 07424 int32_t xtalk_end_phase; 07425 07426 07427 int32_t xtalk_width_phase; 07428 07429 07430 int32_t target_start_phase; 07431 07432 07433 int32_t target_end_phase; 07434 07435 07436 int32_t target_width_phase; 07437 07438 07439 int32_t effective_width; 07440 07441 07442 int32_t event_scaler; 07443 07444 07445 uint8_t VL53LX_p_012; 07446 07447 07448 uint8_t VL53LX_p_013; 07449 07450 07451 uint8_t target_start; 07452 07453 07454 int32_t max_shape_value; 07455 07456 07457 int32_t bin_data_sums[VL53LX_XTALK_HISTO_BINS]; 07458 07459 } VL53LX_hist_xtalk_extract_data_t; 07460 07461 07462 07463 07464 typedef struct { 07465 07466 uint16_t standard_ranging_gain_factor; 07467 07468 uint16_t histogram_ranging_gain_factor; 07469 07470 07471 } VL53LX_gain_calibration_data_t; 07472 07473 07474 07475 07476 typedef struct { 07477 07478 VL53LX_DeviceState cfg_device_state; 07479 07480 uint8_t cfg_stream_count; 07481 07482 uint8_t cfg_internal_stream_count; 07483 07484 uint8_t cfg_internal_stream_count_val; 07485 07486 uint8_t cfg_gph_id; 07487 07488 uint8_t cfg_timing_status; 07489 07490 uint8_t cfg_zone_id; 07491 07492 07493 VL53LX_DeviceState rd_device_state; 07494 07495 uint8_t rd_stream_count; 07496 07497 uint8_t rd_internal_stream_count; 07498 07499 uint8_t rd_internal_stream_count_val; 07500 07501 uint8_t rd_gph_id; 07502 07503 uint8_t rd_timing_status; 07504 07505 uint8_t rd_zone_id; 07506 07507 07508 } VL53LX_ll_driver_state_t; 07509 07510 07511 07512 07513 typedef struct { 07514 07515 uint8_t wait_method; 07516 07517 VL53LX_DevicePresetModes preset_mode; 07518 07519 VL53LX_DeviceZonePreset zone_preset; 07520 07521 VL53LX_DeviceMeasurementModes measurement_mode; 07522 07523 VL53LX_OffsetCalibrationMode offset_calibration_mode; 07524 07525 VL53LX_OffsetCorrectionMode offset_correction_mode; 07526 07527 VL53LX_DeviceDmaxMode dmax_mode; 07528 07529 uint32_t phasecal_config_timeout_us; 07530 07531 uint32_t mm_config_timeout_us; 07532 07533 uint32_t range_config_timeout_us; 07534 07535 uint32_t inter_measurement_period_ms; 07536 07537 uint16_t dss_config__target_total_rate_mcps; 07538 07539 uint32_t fw_ready_poll_duration_ms; 07540 07541 uint8_t fw_ready; 07542 07543 uint8_t debug_mode; 07544 07545 07546 07547 VL53LX_ll_version_t version; 07548 07549 07550 VL53LX_ll_driver_state_t ll_state; 07551 07552 07553 VL53LX_GPIO_interrupt_config_t gpio_interrupt_config; 07554 07555 07556 VL53LX_customer_nvm_managed_t customer; 07557 VL53LX_cal_peak_rate_map_t cal_peak_rate_map; 07558 VL53LX_additional_offset_cal_data_t add_off_cal_data; 07559 VL53LX_dmax_calibration_data_t fmt_dmax_cal; 07560 VL53LX_dmax_calibration_data_t cust_dmax_cal; 07561 VL53LX_gain_calibration_data_t gain_cal; 07562 VL53LX_user_zone_t mm_roi; 07563 VL53LX_optical_centre_t optical_centre; 07564 VL53LX_zone_config_t zone_cfg; 07565 07566 07567 VL53LX_tuning_parm_storage_t tuning_parms; 07568 07569 07570 uint8_t rtn_good_spads[VL53LX_RTN_SPAD_BUFFER_SIZE]; 07571 07572 07573 VL53LX_refspadchar_config_t refspadchar; 07574 VL53LX_ssc_config_t ssc_cfg; 07575 VL53LX_hist_post_process_config_t histpostprocess; 07576 VL53LX_hist_gen3_dmax_config_t dmax_cfg; 07577 VL53LX_xtalkextract_config_t xtalk_extract_cfg; 07578 VL53LX_xtalk_config_t xtalk_cfg; 07579 VL53LX_offsetcal_config_t offsetcal_cfg; 07580 VL53LX_zonecal_config_t zonecal_cfg; 07581 07582 07583 VL53LX_static_nvm_managed_t stat_nvm; 07584 VL53LX_histogram_config_t hist_cfg; 07585 VL53LX_static_config_t stat_cfg; 07586 VL53LX_general_config_t gen_cfg; 07587 VL53LX_timing_config_t tim_cfg; 07588 VL53LX_dynamic_config_t dyn_cfg; 07589 VL53LX_system_control_t sys_ctrl; 07590 VL53LX_system_results_t sys_results; 07591 VL53LX_nvm_copy_data_t nvm_copy_data; 07592 07593 07594 VL53LX_histogram_bin_data_t hist_data; 07595 VL53LX_histogram_bin_data_t hist_xtalk; 07596 07597 07598 VL53LX_xtalk_histogram_data_t xtalk_shapes; 07599 VL53LX_xtalk_range_results_t xtalk_results; 07600 VL53LX_xtalk_calibration_results_t xtalk_cal; 07601 VL53LX_hist_xtalk_extract_data_t xtalk_extract; 07602 07603 07604 VL53LX_offset_range_results_t offset_results; 07605 07606 07607 VL53LX_core_results_t core_results; 07608 VL53LX_debug_results_t dbg_results; 07609 07610 VL53LX_smudge_corrector_config_t smudge_correct_config; 07611 07612 VL53LX_smudge_corrector_internals_t smudge_corrector_internals; 07613 07614 07615 07616 07617 VL53LX_low_power_auto_data_t low_power_auto_data; 07618 07619 uint8_t wArea1[1536]; 07620 uint8_t wArea2[512]; 07621 VL53LX_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data; 07622 07623 uint8_t bin_rec_pos; 07624 07625 uint8_t pos_before_next_recom; 07626 07627 int32_t multi_bins_rec[VL53LX_BIN_REC_SIZE] 07628 [VL53LX_TIMING_CONF_A_B_SIZE][VL53LX_HISTOGRAM_BUFFER_SIZE]; 07629 07630 } VL53LX_LLDriverData_t; 07631 07632 07633 07634 07635 typedef struct { 07636 07637 07638 VL53LX_range_results_t range_results; 07639 07640 07641 VL53LX_zone_private_dyn_cfgs_t zone_dyn_cfgs; 07642 07643 07644 VL53LX_zone_results_t zone_results; 07645 VL53LX_zone_histograms_t zone_hists; 07646 VL53LX_zone_calibration_results_t zone_cal; 07647 07648 } VL53LX_LLDriverResults_t; 07649 07650 07651 07652 07653 typedef struct { 07654 07655 uint32_t struct_version; 07656 VL53LX_customer_nvm_managed_t customer; 07657 VL53LX_dmax_calibration_data_t fmt_dmax_cal; 07658 VL53LX_dmax_calibration_data_t cust_dmax_cal; 07659 VL53LX_additional_offset_cal_data_t add_off_cal_data; 07660 VL53LX_optical_centre_t optical_centre; 07661 VL53LX_xtalk_histogram_data_t xtalkhisto; 07662 VL53LX_gain_calibration_data_t gain_cal; 07663 VL53LX_cal_peak_rate_map_t cal_peak_rate_map; 07664 VL53LX_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data; 07665 07666 } VL53LX_calibration_data_t; 07667 07668 07669 07670 07671 typedef struct { 07672 07673 VL53LX_customer_nvm_managed_t customer; 07674 VL53LX_xtalkextract_config_t xtalk_extract_cfg; 07675 VL53LX_xtalk_config_t xtalk_cfg; 07676 VL53LX_histogram_bin_data_t hist_data; 07677 VL53LX_xtalk_histogram_data_t xtalk_shapes; 07678 VL53LX_xtalk_range_results_t xtalk_results; 07679 07680 } VL53LX_xtalk_debug_data_t; 07681 07682 07683 07684 07685 typedef struct { 07686 07687 VL53LX_customer_nvm_managed_t customer; 07688 VL53LX_dmax_calibration_data_t fmt_dmax_cal; 07689 VL53LX_dmax_calibration_data_t cust_dmax_cal; 07690 VL53LX_additional_offset_cal_data_t add_off_cal_data; 07691 VL53LX_offset_range_results_t offset_results; 07692 07693 } VL53LX_offset_debug_data_t; 07694 07695 07696 07697 07698 typedef struct { 07699 uint16_t vl53lx_tuningparm_version; 07700 uint16_t vl53lx_tuningparm_key_table_version; 07701 uint16_t vl53lx_tuningparm_lld_version; 07702 uint8_t vl53lx_tuningparm_hist_algo_select; 07703 uint8_t vl53lx_tuningparm_hist_target_order; 07704 uint8_t vl53lx_tuningparm_hist_filter_woi_0; 07705 uint8_t vl53lx_tuningparm_hist_filter_woi_1; 07706 uint8_t vl53lx_tuningparm_hist_amb_est_method; 07707 uint8_t vl53lx_tuningparm_hist_amb_thresh_sigma_0; 07708 uint8_t vl53lx_tuningparm_hist_amb_thresh_sigma_1; 07709 int32_t vl53lx_tuningparm_hist_min_amb_thresh_events; 07710 uint16_t vl53lx_tuningparm_hist_amb_events_scaler; 07711 uint16_t vl53lx_tuningparm_hist_noise_threshold; 07712 int32_t vl53lx_tuningparm_hist_signal_total_events_limit; 07713 uint8_t vl53lx_tuningparm_hist_sigma_est_ref_mm; 07714 uint16_t vl53lx_tuningparm_hist_sigma_thresh_mm; 07715 uint16_t vl53lx_tuningparm_hist_gain_factor; 07716 uint8_t vl53lx_tuningparm_consistency_hist_phase_tolerance; 07717 uint16_t vl53lx_tuningparm_consistency_hist_min_max_tolerance_mm; 07718 uint8_t vl53lx_tuningparm_consistency_hist_event_sigma; 07719 uint16_t vl53lx_tuningparm_consistency_hist_event_sigma_min_spad_limit; 07720 uint8_t vl53lx_tuningparm_initial_phase_rtn_histo_long_range; 07721 uint8_t vl53lx_tuningparm_initial_phase_rtn_histo_med_range; 07722 uint8_t vl53lx_tuningparm_initial_phase_rtn_histo_short_range; 07723 uint8_t vl53lx_tuningparm_initial_phase_ref_histo_long_range; 07724 uint8_t vl53lx_tuningparm_initial_phase_ref_histo_med_range; 07725 uint8_t vl53lx_tuningparm_initial_phase_ref_histo_short_range; 07726 int16_t vl53lx_tuningparm_xtalk_detect_min_valid_range_mm; 07727 int16_t vl53lx_tuningparm_xtalk_detect_max_valid_range_mm; 07728 uint16_t vl53lx_tuningparm_xtalk_detect_max_sigma_mm; 07729 uint16_t vl53lx_tuningparm_xtalk_detect_min_max_tolerance; 07730 uint16_t vl53lx_tuningparm_xtalk_detect_max_valid_rate_kcps; 07731 uint8_t vl53lx_tuningparm_xtalk_detect_event_sigma; 07732 int16_t vl53lx_tuningparm_hist_xtalk_margin_kcps; 07733 uint8_t vl53lx_tuningparm_consistency_lite_phase_tolerance; 07734 uint8_t vl53lx_tuningparm_phasecal_target; 07735 uint16_t vl53lx_tuningparm_lite_cal_repeat_rate; 07736 uint16_t vl53lx_tuningparm_lite_ranging_gain_factor; 07737 uint8_t vl53lx_tuningparm_lite_min_clip_mm; 07738 uint16_t vl53lx_tuningparm_lite_long_sigma_thresh_mm; 07739 uint16_t vl53lx_tuningparm_lite_med_sigma_thresh_mm; 07740 uint16_t vl53lx_tuningparm_lite_short_sigma_thresh_mm; 07741 uint16_t vl53lx_tuningparm_lite_long_min_count_rate_rtn_mcps; 07742 uint16_t vl53lx_tuningparm_lite_med_min_count_rate_rtn_mcps; 07743 uint16_t vl53lx_tuningparm_lite_short_min_count_rate_rtn_mcps; 07744 uint8_t vl53lx_tuningparm_lite_sigma_est_pulse_width; 07745 uint8_t vl53lx_tuningparm_lite_sigma_est_amb_width_ns; 07746 uint8_t vl53lx_tuningparm_lite_sigma_ref_mm; 07747 uint8_t vl53lx_tuningparm_lite_rit_mult; 07748 uint8_t vl53lx_tuningparm_lite_seed_config; 07749 uint8_t vl53lx_tuningparm_lite_quantifier; 07750 uint8_t vl53lx_tuningparm_lite_first_order_select; 07751 int16_t vl53lx_tuningparm_lite_xtalk_margin_kcps; 07752 uint8_t vl53lx_tuningparm_initial_phase_rtn_lite_long_range; 07753 uint8_t vl53lx_tuningparm_initial_phase_rtn_lite_med_range; 07754 uint8_t vl53lx_tuningparm_initial_phase_rtn_lite_short_range; 07755 uint8_t vl53lx_tuningparm_initial_phase_ref_lite_long_range; 07756 uint8_t vl53lx_tuningparm_initial_phase_ref_lite_med_range; 07757 uint8_t vl53lx_tuningparm_initial_phase_ref_lite_short_range; 07758 uint8_t vl53lx_tuningparm_timed_seed_config; 07759 uint8_t vl53lx_tuningparm_dmax_cfg_signal_thresh_sigma; 07760 uint16_t vl53lx_tuningparm_dmax_cfg_reflectance_array_0; 07761 uint16_t vl53lx_tuningparm_dmax_cfg_reflectance_array_1; 07762 uint16_t vl53lx_tuningparm_dmax_cfg_reflectance_array_2; 07763 uint16_t vl53lx_tuningparm_dmax_cfg_reflectance_array_3; 07764 uint16_t vl53lx_tuningparm_dmax_cfg_reflectance_array_4; 07765 uint8_t vl53lx_tuningparm_vhv_loopbound; 07766 uint8_t vl53lx_tuningparm_refspadchar_device_test_mode; 07767 uint8_t vl53lx_tuningparm_refspadchar_vcsel_period; 07768 uint32_t vl53lx_tuningparm_refspadchar_phasecal_timeout_us; 07769 uint16_t vl53lx_tuningparm_refspadchar_target_count_rate_mcps; 07770 uint16_t vl53lx_tuningparm_refspadchar_min_countrate_limit_mcps; 07771 uint16_t vl53lx_tuningparm_refspadchar_max_countrate_limit_mcps; 07772 uint8_t vl53lx_tuningparm_xtalk_extract_num_of_samples; 07773 int16_t vl53lx_tuningparm_xtalk_extract_min_filter_thresh_mm; 07774 int16_t vl53lx_tuningparm_xtalk_extract_max_filter_thresh_mm; 07775 uint16_t vl53lx_tuningparm_xtalk_extract_dss_rate_mcps; 07776 uint32_t vl53lx_tuningparm_xtalk_extract_phasecal_timeout_us; 07777 uint16_t vl53lx_tuningparm_xtalk_extract_max_valid_rate_kcps; 07778 uint16_t vl53lx_tuningparm_xtalk_extract_sigma_threshold_mm; 07779 uint32_t vl53lx_tuningparm_xtalk_extract_dss_timeout_us; 07780 uint32_t vl53lx_tuningparm_xtalk_extract_bin_timeout_us; 07781 uint16_t vl53lx_tuningparm_offset_cal_dss_rate_mcps; 07782 uint32_t vl53lx_tuningparm_offset_cal_phasecal_timeout_us; 07783 uint32_t vl53lx_tuningparm_offset_cal_mm_timeout_us; 07784 uint32_t vl53lx_tuningparm_offset_cal_range_timeout_us; 07785 uint8_t vl53lx_tuningparm_offset_cal_pre_samples; 07786 uint8_t vl53lx_tuningparm_offset_cal_mm1_samples; 07787 uint8_t vl53lx_tuningparm_offset_cal_mm2_samples; 07788 uint16_t vl53lx_tuningparm_zone_cal_dss_rate_mcps; 07789 uint32_t vl53lx_tuningparm_zone_cal_phasecal_timeout_us; 07790 uint32_t vl53lx_tuningparm_zone_cal_dss_timeout_us; 07791 uint16_t vl53lx_tuningparm_zone_cal_phasecal_num_samples; 07792 uint32_t vl53lx_tuningparm_zone_cal_range_timeout_us; 07793 uint16_t vl53lx_tuningparm_zone_cal_zone_num_samples; 07794 uint8_t vl53lx_tuningparm_spadmap_vcsel_period; 07795 uint8_t vl53lx_tuningparm_spadmap_vcsel_start; 07796 uint16_t vl53lx_tuningparm_spadmap_rate_limit_mcps; 07797 uint16_t vl53lx_tuningparm_lite_dss_config_target_total_rate_mcps; 07798 uint16_t vl53lx_tuningparm_ranging_dss_config_target_total_rate_mcps; 07799 uint16_t vl53lx_tuningparm_mz_dss_config_target_total_rate_mcps; 07800 uint16_t vl53lx_tuningparm_timed_dss_config_target_total_rate_mcps; 07801 uint32_t vl53lx_tuningparm_lite_phasecal_config_timeout_us; 07802 uint32_t vl53lx_tuningparm_ranging_long_phasecal_config_timeout_us; 07803 uint32_t vl53lx_tuningparm_ranging_med_phasecal_config_timeout_us; 07804 uint32_t vl53lx_tuningparm_ranging_short_phasecal_config_timeout_us; 07805 uint32_t vl53lx_tuningparm_mz_long_phasecal_config_timeout_us; 07806 uint32_t vl53lx_tuningparm_mz_med_phasecal_config_timeout_us; 07807 uint32_t vl53lx_tuningparm_mz_short_phasecal_config_timeout_us; 07808 uint32_t vl53lx_tuningparm_timed_phasecal_config_timeout_us; 07809 uint32_t vl53lx_tuningparm_lite_mm_config_timeout_us; 07810 uint32_t vl53lx_tuningparm_ranging_mm_config_timeout_us; 07811 uint32_t vl53lx_tuningparm_mz_mm_config_timeout_us; 07812 uint32_t vl53lx_tuningparm_timed_mm_config_timeout_us; 07813 uint32_t vl53lx_tuningparm_lite_range_config_timeout_us; 07814 uint32_t vl53lx_tuningparm_ranging_range_config_timeout_us; 07815 uint32_t vl53lx_tuningparm_mz_range_config_timeout_us; 07816 uint32_t vl53lx_tuningparm_timed_range_config_timeout_us; 07817 uint16_t vl53lx_tuningparm_dynxtalk_smudge_margin; 07818 uint32_t vl53lx_tuningparm_dynxtalk_noise_margin; 07819 uint32_t vl53lx_tuningparm_dynxtalk_xtalk_offset_limit; 07820 uint8_t vl53lx_tuningparm_dynxtalk_xtalk_offset_limit_hi; 07821 uint32_t vl53lx_tuningparm_dynxtalk_sample_limit; 07822 uint32_t vl53lx_tuningparm_dynxtalk_single_xtalk_delta; 07823 uint32_t vl53lx_tuningparm_dynxtalk_averaged_xtalk_delta; 07824 uint32_t vl53lx_tuningparm_dynxtalk_clip_limit; 07825 uint8_t vl53lx_tuningparm_dynxtalk_scaler_calc_method; 07826 int16_t vl53lx_tuningparm_dynxtalk_xgradient_scaler; 07827 int16_t vl53lx_tuningparm_dynxtalk_ygradient_scaler; 07828 uint8_t vl53lx_tuningparm_dynxtalk_user_scaler_set; 07829 uint8_t vl53lx_tuningparm_dynxtalk_smudge_cor_single_apply; 07830 uint32_t vl53lx_tuningparm_dynxtalk_xtalk_amb_threshold; 07831 uint32_t vl53lx_tuningparm_dynxtalk_nodetect_amb_threshold_kcps; 07832 uint32_t vl53lx_tuningparm_dynxtalk_nodetect_sample_limit; 07833 uint32_t vl53lx_tuningparm_dynxtalk_nodetect_xtalk_offset_kcps; 07834 uint16_t vl53lx_tuningparm_dynxtalk_nodetect_min_range_mm; 07835 uint8_t vl53lx_tuningparm_lowpowerauto_vhv_loop_bound; 07836 uint32_t vl53lx_tuningparm_lowpowerauto_mm_config_timeout_us; 07837 uint32_t vl53lx_tuningparm_lowpowerauto_range_config_timeout_us; 07838 uint16_t vl53lx_tuningparm_very_short_dss_rate_mcps; 07839 uint32_t vl53lx_tuningparm_phasecal_patch_power; 07840 } VL53LX_tuning_parameters_t; 07841 07842 07843 07844 07845 07846 typedef struct { 07847 07848 uint16_t target_reflectance_for_dmax[VL53LX_MAX_AMBIENT_DMAX_VALUES]; 07849 07850 } VL53LX_dmax_reflectance_array_t; 07851 07852 07853 07854 07855 typedef struct { 07856 07857 uint8_t spad_type; 07858 07859 uint16_t VL53LX_p_020; 07860 07861 uint16_t rate_data[VL53LX_NO_OF_SPAD_ENABLES]; 07862 07863 uint16_t no_of_values; 07864 07865 uint8_t fractional_bits; 07866 07867 uint8_t error_status; 07868 07869 07870 } VL53LX_spad_rate_data_t; 07871 07872 07873 07874 07875 07876 07877 typedef struct { 07878 07879 VL53LX_DevicePresetModes preset_mode; 07880 07881 VL53LX_DeviceZonePreset zone_preset; 07882 07883 VL53LX_DeviceMeasurementModes measurement_mode; 07884 07885 VL53LX_OffsetCalibrationMode offset_calibration_mode; 07886 07887 VL53LX_OffsetCorrectionMode offset_correction_mode; 07888 07889 VL53LX_DeviceDmaxMode dmax_mode; 07890 07891 07892 uint32_t phasecal_config_timeout_us; 07893 07894 uint32_t mm_config_timeout_us; 07895 07896 uint32_t range_config_timeout_us; 07897 07898 uint32_t inter_measurement_period_ms; 07899 07900 uint16_t dss_config__target_total_rate_mcps; 07901 07902 07903 VL53LX_histogram_bin_data_t VL53LX_p_006; 07904 07905 07906 } VL53LX_additional_data_t; 07907 07908 07909 07910 /* vl53lx_def.h */ 07911 07912 07913 /** @defgroup VL53LX_globaldefine_group VL53LX Defines 07914 * @brief VL53LX Defines 07915 * @{ 07916 */ 07917 07918 07919 /** VL53LX IMPLEMENTATION major version */ 07920 #define VL53LX_IMPLEMENTATION_VER_MAJOR 1 07921 /** VL53LX IMPLEMENTATION minor version */ 07922 #define VL53LX_IMPLEMENTATION_VER_MINOR 1 07923 /** VL53LX IMPLEMENTATION sub version */ 07924 #define VL53LX_IMPLEMENTATION_VER_SUB 4 07925 /** VL53LX IMPLEMENTATION sub version */ 07926 #define VL53LX_IMPLEMENTATION_VER_REVISION 2352 07927 07928 /**************************************** 07929 * PRIVATE define do not edit 07930 ****************************************/ 07931 07932 /** @brief Defines the parameters of the Get Version Functions 07933 */ 07934 typedef struct { 07935 uint32_t revision; /*!< revision number */ 07936 uint8_t major; /*!< major number */ 07937 uint8_t minor; /*!< minor number */ 07938 uint8_t build; /*!< build number */ 07939 } VL53LX_Version_t; 07940 07941 07942 /** @brief Defines the parameters of the Get Device Info Functions 07943 */ 07944 typedef struct { 07945 uint8_t ProductType; 07946 /*!< Product Type, VL53LX = 0xAA 07947 * Stands as module_type in the datasheet 07948 */ 07949 uint8_t ProductRevisionMajor; 07950 /*!< Product revision major */ 07951 uint8_t ProductRevisionMinor; 07952 /*!< Product revision minor */ 07953 } VL53LX_DeviceInfo_t; 07954 07955 /** @defgroup VL53LX_define_DistanceModes_group Defines Distance modes 07956 * Defines all possible Distance modes for the device 07957 * @{ 07958 */ 07959 typedef uint8_t VL53LX_DistanceModes; 07960 07961 #define VL53LX_DISTANCEMODE_SHORT ((VL53LX_DistanceModes) 1) 07962 #define VL53LX_DISTANCEMODE_MEDIUM ((VL53LX_DistanceModes) 2) 07963 #define VL53LX_DISTANCEMODE_LONG ((VL53LX_DistanceModes) 3) 07964 /** @} VL53LX_define_DistanceModes_group */ 07965 07966 /** @defgroup VL53LX_define_OffsetCorrectionModes_group Defines Offset Correction modes 07967 * Device Offset Correction Mode 07968 * 07969 * @brief Defines all possible offset correction modes for the device 07970 * @{ 07971 */ 07972 typedef uint8_t VL53LX_OffsetCorrectionModes; 07973 07974 #define VL53LX_OFFSETCORRECTIONMODE_STANDARD ((VL53LX_OffsetCorrectionModes) 1) 07975 #define VL53LX_OFFSETCORRECTIONMODE_PERVCSEL ((VL53LX_OffsetCorrectionModes) 3) 07976 07977 /** @} VL53LX_define_OffsetCorrectionModes_group */ 07978 07979 /** @brief Defines all parameters for the device 07980 */ 07981 typedef struct { 07982 VL53LX_DistanceModes DistanceMode; 07983 /*!< Defines the operating mode to be used for the next measure */ 07984 uint32_t MeasurementTimingBudgetMicroSeconds; 07985 /*!< Defines the allowed total time for a single measurement */ 07986 } VL53LX_DeviceParameters_t; 07987 07988 07989 /** @defgroup VL53LX_define_Smudge_Mode_group Defines smudge correction modes 07990 * Defines the smudge correction modes 07991 * @{ 07992 */ 07993 07994 typedef uint8_t VL53LX_SmudgeCorrectionModes; 07995 07996 #define VL53LX_SMUDGE_CORRECTION_NONE ((VL53LX_SmudgeCorrectionModes) 0) 07997 /*!< Smudge correction is applied continuously across the rangings */ 07998 #define VL53LX_SMUDGE_CORRECTION_CONTINUOUS ((VL53LX_SmudgeCorrectionModes) 1) 07999 /*!< Smudge correction is applied continuously across the rangings */ 08000 #define VL53LX_SMUDGE_CORRECTION_SINGLE ((VL53LX_SmudgeCorrectionModes) 2) 08001 /*!< Smudge correction is applied only once across the rangings */ 08002 #define VL53LX_SMUDGE_CORRECTION_DEBUG ((VL53LX_SmudgeCorrectionModes) 3) 08003 /*!< Smudge detection is applied continuously but Xtalk values are not 08004 * updated automatically within the driver 08005 */ 08006 08007 /** @} VL53LX_define_Smudge_Correction_Mode_group */ 08008 08009 /** 08010 * @struct VL53LX_TargetRangeData_t 08011 * @brief One Range measurement data for each target. 08012 */ 08013 typedef struct { 08014 int16_t RangeMaxMilliMeter; 08015 /*!< Tells what is the maximum detection distance of the object 08016 * in current setup and environment conditions (Filled when 08017 * applicable) 08018 */ 08019 08020 int16_t RangeMinMilliMeter; 08021 /*!< Tells what is the minimum detection distance of the object 08022 * in current setup and environment conditions (Filled when 08023 * applicable) 08024 */ 08025 08026 FixPoint1616_t SignalRateRtnMegaCps; 08027 /*!< Return signal rate (MCPS)\n these is a 16.16 fix point 08028 * value, which is effectively a measure of target 08029 * reflectance. 08030 */ 08031 08032 FixPoint1616_t AmbientRateRtnMegaCps; 08033 /*!< Return ambient rate (MCPS)\n these is a 16.16 fix point 08034 * value, which is effectively a measure of the ambien 08035 * t light. 08036 */ 08037 08038 FixPoint1616_t SigmaMilliMeter; 08039 /*!< Return the Sigma value in millimeter */ 08040 08041 int16_t RangeMilliMeter; 08042 /*!< range distance in millimeter. This should be between 08043 * RangeMinMilliMeter and RangeMaxMilliMeter 08044 */ 08045 08046 uint8_t RangeStatus; 08047 /*!< Range Status for the current measurement. This is device 08048 * dependent. Value = 0 means value is valid. 08049 */ 08050 } VL53LX_TargetRangeData_t; 08051 /** 08052 * @struct VL53LX_MultiRangingData_t 08053 * @brief Structure for storing the set of range results 08054 * 08055 */ 08056 typedef struct { 08057 uint32_t TimeStamp; 08058 /*!< 32-bit time stamp. 08059 * @warning Not yet implemented 08060 */ 08061 08062 uint8_t StreamCount; 08063 /*!< 8-bit Stream Count. */ 08064 08065 uint8_t NumberOfObjectsFound; 08066 /*!< Indicate the number of objects found. 08067 * This is used to know how many ranging data should be get. 08068 * NumberOfObjectsFound is in the range 0 to 08069 * VL53LX_MAX_RANGE_RESULTS. 08070 */ 08071 VL53LX_TargetRangeData_t RangeData[VL53LX_MAX_RANGE_RESULTS]; 08072 /*!< Range data each target distance */ 08073 uint8_t HasXtalkValueChanged; 08074 /*!< set to 1 if a new Xtalk value has been computed whilst 08075 * smudge correction mode enable by with 08076 * VL53LX_SmudgeCorrectionEnable() function is either 08077 * VL53LX_SMUDGE_CORRECTION_CONTINUOUS or 08078 * VL53LX_SMUDGE_CORRECTION_SINGLE. 08079 */ 08080 uint16_t EffectiveSpadRtnCount; 08081 /*!< Return the effective SPAD count for the return signal. 08082 * To obtain Real value it should be divided by 256 08083 */ 08084 } VL53LX_MultiRangingData_t; 08085 08086 08087 08088 /** 08089 * @struct VL53LX_CustomerNvmManaged_t 08090 * 08091 */ 08092 08093 typedef struct { 08094 uint8_t global_config__spad_enables_ref_0; 08095 uint8_t global_config__spad_enables_ref_1; 08096 uint8_t global_config__spad_enables_ref_2; 08097 uint8_t global_config__spad_enables_ref_3; 08098 uint8_t global_config__spad_enables_ref_4; 08099 uint8_t global_config__spad_enables_ref_5; 08100 uint8_t global_config__ref_en_start_select; 08101 uint8_t ref_spad_man__num_requested_ref_spads; 08102 uint8_t ref_spad_man__ref_location; 08103 uint32_t algo__crosstalk_compensation_plane_offset_kcps; 08104 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps; 08105 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps; 08106 uint16_t ref_spad_char__total_rate_target_mcps; 08107 int16_t algo__part_to_part_range_offset_mm; 08108 int16_t mm_config__inner_offset_mm; 08109 int16_t mm_config__outer_offset_mm; 08110 } VL53LX_CustomerNvmManaged_t; 08111 08112 /** 08113 * @struct VL53LX_CalibrationData_t 08114 * @brief Structure for storing the Calibration Data 08115 * 08116 */ 08117 08118 typedef struct { 08119 08120 uint32_t struct_version; 08121 VL53LX_CustomerNvmManaged_t customer; 08122 VL53LX_additional_offset_cal_data_t add_off_cal_data; 08123 VL53LX_optical_centre_t optical_centre; 08124 VL53LX_xtalk_histogram_data_t xtalkhisto; 08125 VL53LX_gain_calibration_data_t gain_cal; 08126 VL53LX_cal_peak_rate_map_t cal_peak_rate_map; 08127 VL53LX_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data; 08128 uint32_t algo__xtalk_cpo_HistoMerge_kcps[VL53LX_BIN_REC_SIZE]; 08129 } VL53LX_CalibrationData_t; 08130 08131 #define VL53LX_ADDITIONAL_CALIBRATION_DATA_STRUCT_VERSION 0x20 08132 /** VL53LX additional Calibration Data struct version final struct version 08133 * is given by adding it to VL53LX_LL_CALIBRATION_DATA_STRUCT_VERSION 08134 */ 08135 08136 #define VL53LX_CALIBRATION_DATA_STRUCT_VERSION \ 08137 (VL53LX_LL_CALIBRATION_DATA_STRUCT_VERSION + \ 08138 VL53LX_ADDITIONAL_CALIBRATION_DATA_STRUCT_VERSION) 08139 /* VL53LX Calibration Data struct version */ 08140 08141 /** 08142 * @struct VL53LX_AdditionalData_t 08143 * @brief Structure for storing the Additional Data 08144 * 08145 */ 08146 typedef VL53LX_additional_data_t VL53LX_AdditionalData_t; 08147 08148 08149 /** @defgroup VL53LX_define_RangeStatus_group Defines the Range Status 08150 * @{ 08151 */ 08152 #define VL53LX_RANGESTATUS_RANGE_VALID 0 08153 /*!<The Range is valid. */ 08154 #define VL53LX_RANGESTATUS_SIGMA_FAIL 1 08155 /*!<Sigma Fail. */ 08156 #define VL53LX_RANGESTATUS_SIGNAL_FAIL 2 08157 /*!<Signal fail. */ 08158 #define VL53LX_RANGESTATUS_RANGE_VALID_MIN_RANGE_CLIPPED 3 08159 /*!<Target is below minimum detection threshold. */ 08160 #define VL53LX_RANGESTATUS_OUTOFBOUNDS_FAIL 4 08161 /*!<Phase out of valid limits - different to a wrap exit. */ 08162 #define VL53LX_RANGESTATUS_HARDWARE_FAIL 5 08163 /*!<Hardware fail. */ 08164 #define VL53LX_RANGESTATUS_RANGE_VALID_NO_WRAP_CHECK_FAIL 6 08165 /*!<The Range is valid but the wraparound check has not been done. */ 08166 #define VL53LX_RANGESTATUS_WRAP_TARGET_FAIL 7 08167 /*!<Wrapped target - no matching phase in other VCSEL period timing. */ 08168 #define VL53LX_RANGESTATUS_PROCESSING_FAIL 8 08169 /*!<Internal algo underflow or overflow in lite ranging. */ 08170 #define VL53LX_RANGESTATUS_XTALK_SIGNAL_FAIL 9 08171 /*!<Specific to lite ranging. */ 08172 #define VL53LX_RANGESTATUS_SYNCRONISATION_INT 10 08173 /*!<1st interrupt when starting ranging in back to back mode. Ignore data. */ 08174 #define VL53LX_RANGESTATUS_RANGE_VALID_MERGED_PULSE 11 08175 /*!<All Range ok but object is result of multiple pulses merging together. 08176 * Used by RQL for merged pulse detection 08177 */ 08178 #define VL53LX_RANGESTATUS_TARGET_PRESENT_LACK_OF_SIGNAL 12 08179 /*!<Used by RQL as different to phase fail. */ 08180 #define VL53LX_RANGESTATUS_MIN_RANGE_FAIL 13 08181 /*!<Unexpected error in SPAD Array.*/ 08182 #define VL53LX_RANGESTATUS_RANGE_INVALID 14 08183 /*!<lld returned valid range but negative value ! */ 08184 #define VL53LX_RANGESTATUS_NONE 255 08185 /*!<No Update. */ 08186 08187 /** @} VL53LX_define_RangeStatus_group */ 08188 08189 08190 /** @brief Contains the Internal data of the Bare Driver 08191 */ 08192 08193 typedef struct { 08194 VL53LX_LLDriverData_t LLData; 08195 /*!< Low Level Driver data structure */ 08196 08197 VL53LX_LLDriverResults_t llresults; 08198 /*!< Low Level Driver data structure */ 08199 08200 VL53LX_DeviceParameters_t CurrentParameters; 08201 /*!< Current Device Parameter */ 08202 08203 } VL53LX_DevData_t; 08204 08205 08206 /* MACRO Definitions */ 08207 /** @defgroup VL53LX_define_GeneralMacro_group General Macro Defines 08208 * General Macro Defines 08209 * @{ 08210 */ 08211 08212 /* Defines */ 08213 #define VL53LX_SETPARAMETERFIELD(Dev, field, value) \ 08214 (VL53LXDevDataSet(Dev, CurrentParameters.field, value)) 08215 08216 #define VL53LX_GETPARAMETERFIELD(Dev, field, variable) \ 08217 (variable = VL53LXDevDataGet(Dev, CurrentParameters).field) 08218 08219 #define VL53LX_SETARRAYPARAMETERFIELD(Dev, field, index, value) \ 08220 (VL53LXDevDataSet(Dev, CurrentParameters.field[index], value)) 08221 08222 #define VL53LX_GETARRAYPARAMETERFIELD(Dev, field, index, variable) \ 08223 (variable = VL53LXDevDataGet(Dev, CurrentParameters).field[index]) 08224 08225 #define VL53LX_SETDEVICESPECIFICPARAMETER(Dev, field, value) \ 08226 (VL53LXDevDataSet(Dev, DeviceSpecificParameters.field, value)) 08227 08228 #define VL53LX_GETDEVICESPECIFICPARAMETER(Dev, field) \ 08229 (VL53LXDevDataGet(Dev, DeviceSpecificParameters).field) 08230 08231 08232 #define VL53LX_FIXPOINT1616TOFIXPOINT44(Value) \ 08233 (uint16_t)((Value>>12)&0xFFFF) 08234 #define VL53LX_FIXPOINT44TOFIXPOINT1616(Value) \ 08235 (FixPoint1616_t)((uint32_t)Value<<12) 08236 08237 #define VL53LX_FIXPOINT1616TOFIXPOINT72(Value) \ 08238 (uint16_t)((Value>>14)&0xFFFF) 08239 #define VL53LX_FIXPOINT72TOFIXPOINT1616(Value) \ 08240 (FixPoint1616_t)((uint32_t)Value<<14) 08241 08242 #define VL53LX_FIXPOINT1616TOFIXPOINT97(Value) \ 08243 (uint16_t)((Value>>9)&0xFFFF) 08244 #define VL53LX_FIXPOINT97TOFIXPOINT1616(Value) \ 08245 (FixPoint1616_t)((uint32_t)Value<<9) 08246 08247 #define VL53LX_FIXPOINT1616TOFIXPOINT88(Value) \ 08248 (uint16_t)((Value>>8)&0xFFFF) 08249 #define VL53LX_FIXPOINT88TOFIXPOINT1616(Value) \ 08250 (FixPoint1616_t)((uint32_t)Value<<8) 08251 08252 #define VL53LX_FIXPOINT1616TOFIXPOINT412(Value) \ 08253 (uint16_t)((Value>>4)&0xFFFF) 08254 #define VL53LX_FIXPOINT412TOFIXPOINT1616(Value) \ 08255 (FixPoint1616_t)((uint32_t)Value<<4) 08256 08257 #define VL53LX_FIXPOINT1616TOFIXPOINT313(Value) \ 08258 (uint16_t)((Value>>3)&0xFFFF) 08259 #define VL53LX_FIXPOINT313TOFIXPOINT1616(Value) \ 08260 (FixPoint1616_t)((uint32_t)Value<<3) 08261 08262 #define VL53LX_FIXPOINT1616TOFIXPOINT08(Value) \ 08263 (uint8_t)((Value>>8)&0x00FF) 08264 #define VL53LX_FIXPOINT08TOFIXPOINT1616(Value) \ 08265 (FixPoint1616_t)((uint32_t)Value<<8) 08266 08267 #define VL53LX_FIXPOINT1616TOFIXPOINT53(Value) \ 08268 (uint8_t)((Value>>13)&0x00FF) 08269 #define VL53LX_FIXPOINT53TOFIXPOINT1616(Value) \ 08270 (FixPoint1616_t)((uint32_t)Value<<13) 08271 08272 #define VL53LX_FIXPOINT1616TOFIXPOINT102(Value) \ 08273 (uint16_t)((Value>>14)&0x0FFF) 08274 #define VL53LX_FIXPOINT102TOFIXPOINT1616(Value) \ 08275 (FixPoint1616_t)((uint32_t)Value<<14) 08276 08277 #define VL53LX_FIXPOINT1616TOFIXPOINT142(Value) \ 08278 (uint16_t)((Value>>14)&0xFFFF) 08279 #define VL53LX_FIXPOINT142TOFIXPOINT1616(Value) \ 08280 (FixPoint1616_t)((uint32_t)Value<<14) 08281 08282 #define VL53LX_FIXPOINT1616TOFIXPOINT160(Value) \ 08283 (uint16_t)((Value>>16)&0xFFFF) 08284 #define VL53LX_FIXPOINT160TOFIXPOINT1616(Value) \ 08285 (FixPoint1616_t)((uint32_t)Value<<16) 08286 08287 #define VL53LX_MAKEUINT16(lsb, msb) (uint16_t)((((uint16_t)msb)<<8) + \ 08288 (uint16_t)lsb) 08289 08290 #ifndef SUPPRESS_UNUSED_WARNING 08291 #define SUPPRESS_UNUSED_WARNING(x) ((void) (x)) 08292 #endif 08293 08294 /** @} VL53LX_define_GeneralMacro_group */ 08295 08296 /** @} VL53LX_globaldefine_group */ 08297 08298 08299 08300 08301 /* vl53lx_xtalk_private_structs.h */ 08302 08303 08304 #define VL53LX_D_012 4 08305 08306 08307 08308 08309 08310 08311 08312 08313 08314 typedef struct { 08315 08316 08317 08318 08319 08320 uint32_t VL53LX_p_061[VL53LX_D_012]; 08321 08322 08323 08324 int16_t VL53LX_p_059; 08325 08326 08327 int16_t VL53LX_p_060; 08328 08329 08330 08331 VL53LX_histogram_bin_data_t VL53LX_p_056; 08332 08333 08334 VL53LX_histogram_bin_data_t VL53LX_p_057; 08335 08336 08337 08338 08339 uint32_t VL53LX_p_058; 08340 08341 08342 08343 uint32_t VL53LX_p_062[VL53LX_XTALK_HISTO_BINS]; 08344 08345 08346 08347 } VL53LX_xtalk_algo_data_t; 08348 08349 08350 /*vl53lx_platform_user_data*/ 08351 08352 #include <stdlib.h> 08353 //#include "Wire.h" 08354 /* 08355 08356 typedef struct { 08357 VL53LX_DevData_t Data; 08358 //!< Low Level Driver data structure 08359 uint8_t i2c_slave_address; 08360 uint8_t comms_type; 08361 uint16_t comms_speed_khz; 08362 vl53L1X_DevI2C *I2cHandle; 08363 uint8_t I2cDevAddr; 08364 int Present; 08365 int Enabled; 08366 int LoopState; 08367 int FirstStreamCountZero; 08368 int Idle; 08369 int Ready; 08370 uint8_t RangeStatus; 08371 FixPoint1616_t SignalRateRtnMegaCps; 08372 VL53LX_DeviceState device_state; //!< Device State 08373 } VL53LX_Dev_t; 08374 08375 typedef VL53LX_Dev_t *VL53LX_DEV; 08376 */ 08377 /** 08378 * @def VL53LXDevDataGet 08379 * @brief Get ST private structure @a VL53LX_DevData_t data access 08380 * 08381 * @param Dev Device Handle 08382 * @param field ST structure field name 08383 * It maybe used and as real data "ref" not just as "get" for sub-structure item 08384 * like VL53L1DevDataGet(FilterData.field)[i] or 08385 * VL53L1DevDataGet(FilterData.MeasurementIndex)++ 08386 */ 08387 #define VL53LXDevDataGet(Dev, field) (Dev->Data.field) 08388 08389 /** 08390 * @def VL53LXDevDataSet(Dev, field, data) 08391 * @brief Set ST private structure @a VL53LX_DevData_t data field 08392 * @param Dev Device Handle 08393 * @param field ST structure field name 08394 * @param data Data to be set 08395 */ 08396 #define VL53LXDevDataSet(Dev, field, data) ((Dev->Data.field) = (data)) 08397 08398 #define PALDevDataGet(Dev, field) (Dev->Data.field) 08399 08400 #define PALDevDataSet(Dev, field, VL53LX_PRM_00005) (Dev->Data.field)=(VL53LX_PRM_00005) 08401 08402 #define VL53LXDevStructGetLLDriverHandle(Dev) (&Dev -> Data.LLData) 08403 08404 #define VL53LXDevStructGetLLResultsHandle(Dev) (&Dev -> Data.llresults) 08405 08406 08407 /* vl53lx_hist_map.h */ 08408 08409 08410 #define VL53LX_HISTOGRAM_CONFIG__OPCODE_SEQUENCE_0 \ 08411 VL53LX_SIGMA_ESTIMATOR__EFFECTIVE_PULSE_WIDTH_NS 08412 08413 #define VL53LX_HISTOGRAM_CONFIG__OPCODE_SEQUENCE_1 \ 08414 VL53LX_SIGMA_ESTIMATOR__EFFECTIVE_AMBIENT_WIDTH_NS 08415 08416 #define VL53LX_HISTOGRAM_CONFIG__OPCODE_SEQUENCE_2 \ 08417 VL53LX_SIGMA_ESTIMATOR__SIGMA_REF_MM 08418 08419 #define VL53LX_HISTOGRAM_CONFIG__AMB_THRESH_HIGH \ 08420 VL53LX_ALGO__RANGE_IGNORE_THRESHOLD_MCPS 08421 08422 08423 08424 08425 #define VL53LX_RESULT__HISTOGRAM_BIN_0_2 0x008E 08426 #define VL53LX_RESULT__HISTOGRAM_BIN_0_1 0x008F 08427 #define VL53LX_RESULT__HISTOGRAM_BIN_0_0 0x0090 08428 08429 #define VL53LX_RESULT__HISTOGRAM_BIN_23_2 0x00D3 08430 #define VL53LX_RESULT__HISTOGRAM_BIN_23_1 0x00D4 08431 #define VL53LX_RESULT__HISTOGRAM_BIN_23_0 0x00D5 08432 08433 #define VL53LX_RESULT__HISTOGRAM_BIN_23_0_MSB 0x00D9 08434 #define VL53LX_RESULT__HISTOGRAM_BIN_23_0_LSB 0x00DA 08435 08436 08437 08438 #define VL53LX_HISTOGRAM_BIN_DATA_I2C_INDEX \ 08439 VL53LX_RESULT__INTERRUPT_STATUS 08440 #define VL53LX_HISTOGRAM_BIN_DATA_I2C_SIZE_BYTES \ 08441 (VL53LX_RESULT__HISTOGRAM_BIN_23_0_LSB - \ 08442 VL53LX_RESULT__INTERRUPT_STATUS + 1) 08443 08444 08445 /* vl53lx_nvm_structs.h */ 08446 08447 typedef struct { 08448 08449 uint16_t result__actual_effective_rtn_spads; 08450 uint8_t ref_spad_array__num_requested_ref_spads; 08451 uint8_t ref_spad_array__ref_location; 08452 uint16_t result__peak_signal_count_rate_rtn_mcps; 08453 uint16_t result__ambient_count_rate_rtn_mcps; 08454 uint16_t result__peak_signal_count_rate_ref_mcps; 08455 uint16_t result__ambient_count_rate_ref_mcps; 08456 uint16_t measured_distance_mm; 08457 uint16_t measured_distance_stdev_mm; 08458 } VL53LX_decoded_nvm_fmt_range_data_t; 08459 08460 08461 typedef struct { 08462 08463 char nvm__fmt__fgc[19]; 08464 uint8_t nvm__fmt__test_program_major; 08465 uint8_t nvm__fmt__test_program_minor; 08466 uint8_t nvm__fmt__map_major; 08467 uint8_t nvm__fmt__map_minor; 08468 uint8_t nvm__fmt__year; 08469 uint8_t nvm__fmt__month; 08470 uint8_t nvm__fmt__day; 08471 uint8_t nvm__fmt__module_date_phase; 08472 uint16_t nvm__fmt__time; 08473 uint8_t nvm__fmt__tester_id; 08474 uint8_t nvm__fmt__site_id; 08475 uint8_t nvm__ews__test_program_major; 08476 uint8_t nvm__ews__test_program_minor; 08477 uint8_t nvm__ews__probe_card_major; 08478 uint8_t nvm__ews__probe_card_minor; 08479 uint8_t nvm__ews__tester_id; 08480 char nvm__ews__lot[8]; 08481 uint8_t nvm__ews__wafer; 08482 uint8_t nvm__ews__xcoord; 08483 uint8_t nvm__ews__ycoord; 08484 } VL53LX_decoded_nvm_fmt_info_t; 08485 08486 08487 typedef struct { 08488 08489 uint8_t nvm__ews__test_program_major; 08490 uint8_t nvm__ews__test_program_minor; 08491 uint8_t nvm__ews__probe_card_major; 08492 uint8_t nvm__ews__probe_card_minor; 08493 uint8_t nvm__ews__tester_id; 08494 char nvm__ews__lot[8]; 08495 uint8_t nvm__ews__wafer; 08496 uint8_t nvm__ews__xcoord; 08497 uint8_t nvm__ews__ycoord; 08498 } VL53LX_decoded_nvm_ews_info_t; 08499 08500 08501 typedef struct { 08502 uint8_t nvm__identification_model_id; 08503 uint8_t nvm__identification_module_type; 08504 uint8_t nvm__identification_revision_id; 08505 uint16_t nvm__identification_module_id; 08506 uint8_t nvm__i2c_valid; 08507 uint8_t nvm__i2c_device_address_ews; 08508 uint16_t nvm__ews__fast_osc_frequency; 08509 uint8_t nvm__ews__fast_osc_trim_max; 08510 uint8_t nvm__ews__fast_osc_freq_set; 08511 uint16_t nvm__ews__slow_osc_calibration; 08512 uint16_t nvm__fmt__fast_osc_frequency; 08513 uint8_t nvm__fmt__fast_osc_trim_max; 08514 uint8_t nvm__fmt__fast_osc_freq_set; 08515 uint16_t nvm__fmt__slow_osc_calibration; 08516 uint8_t nvm__vhv_config_unlock; 08517 uint8_t nvm__ref_selvddpix; 08518 uint8_t nvm__ref_selvquench; 08519 uint8_t nvm__regavdd1v2_sel; 08520 uint8_t nvm__regdvdd1v2_sel; 08521 uint8_t nvm__vhv_timeout__macrop; 08522 uint8_t nvm__vhv_loop_bound; 08523 uint8_t nvm__vhv_count_threshold; 08524 uint8_t nvm__vhv_offset; 08525 uint8_t nvm__vhv_init_enable; 08526 uint8_t nvm__vhv_init_value; 08527 uint8_t nvm__laser_safety_vcsel_trim_ll; 08528 uint8_t nvm__laser_safety_vcsel_selion_ll; 08529 uint8_t nvm__laser_safety_vcsel_selion_max_ll; 08530 uint8_t nvm__laser_safety_mult_ll; 08531 uint8_t nvm__laser_safety_clip_ll; 08532 uint8_t nvm__laser_safety_vcsel_trim_ld; 08533 uint8_t nvm__laser_safety_vcsel_selion_ld; 08534 uint8_t nvm__laser_safety_vcsel_selion_max_ld; 08535 uint8_t nvm__laser_safety_mult_ld; 08536 uint8_t nvm__laser_safety_clip_ld; 08537 uint8_t nvm__laser_safety_lock_byte; 08538 uint8_t nvm__laser_safety_unlock_byte; 08539 uint8_t nvm__ews__spad_enables_rtn[VL53LX_RTN_SPAD_BUFFER_SIZE]; 08540 uint8_t nvm__ews__spad_enables_ref__loc1[VL53LX_REF_SPAD_BUFFER_SIZE]; 08541 uint8_t nvm__ews__spad_enables_ref__loc2[VL53LX_REF_SPAD_BUFFER_SIZE]; 08542 uint8_t nvm__ews__spad_enables_ref__loc3[VL53LX_REF_SPAD_BUFFER_SIZE]; 08543 uint8_t nvm__fmt__spad_enables_rtn[VL53LX_RTN_SPAD_BUFFER_SIZE]; 08544 uint8_t nvm__fmt__spad_enables_ref__loc1[VL53LX_REF_SPAD_BUFFER_SIZE]; 08545 uint8_t nvm__fmt__spad_enables_ref__loc2[VL53LX_REF_SPAD_BUFFER_SIZE]; 08546 uint8_t nvm__fmt__spad_enables_ref__loc3[VL53LX_REF_SPAD_BUFFER_SIZE]; 08547 uint8_t nvm__fmt__roi_config__mode_roi_centre_spad; 08548 uint8_t nvm__fmt__roi_config__mode_roi_x_size; 08549 uint8_t nvm__fmt__roi_config__mode_roi_y_size; 08550 uint8_t nvm__fmt__ref_spad_apply__num_requested_ref_spad; 08551 uint8_t nvm__fmt__ref_spad_man__ref_location; 08552 uint16_t nvm__fmt__mm_config__inner_offset_mm; 08553 uint16_t nvm__fmt__mm_config__outer_offset_mm; 08554 uint16_t nvm__fmt__algo_part_to_part_range_offset_mm; 08555 uint16_t nvm__fmt__algo__crosstalk_compensation_plane_offset_kcps; 08556 uint16_t nvm__fmt__algo__crosstalk_compensation_x_plane_gradient_kcps; 08557 uint16_t nvm__fmt__algo__crosstalk_compensation_y_plane_gradient_kcps; 08558 uint8_t nvm__fmt__spare__host_config__nvm_config_spare_0; 08559 uint8_t nvm__fmt__spare__host_config__nvm_config_spare_1; 08560 uint8_t nvm__customer_space_programmed; 08561 uint8_t nvm__cust__i2c_device_address; 08562 uint8_t nvm__cust__ref_spad_apply__num_requested_ref_spad; 08563 uint8_t nvm__cust__ref_spad_man__ref_location; 08564 uint16_t nvm__cust__mm_config__inner_offset_mm; 08565 uint16_t nvm__cust__mm_config__outer_offset_mm; 08566 uint16_t nvm__cust__algo_part_to_part_range_offset_mm; 08567 uint16_t nvm__cust__algo__crosstalk_compensation_plane_offset_kcps; 08568 uint16_t nvm__cust__algo__crosstalk_compensation_x_plane_gradient_kcps; 08569 uint16_t nvm__cust__algo__crosstalk_compensation_y_plane_gradient_kcps; 08570 uint8_t nvm__cust__spare__host_config__nvm_config_spare_0; 08571 uint8_t nvm__cust__spare__host_config__nvm_config_spare_1; 08572 VL53LX_optical_centre_t fmt_optical_centre; 08573 VL53LX_cal_peak_rate_map_t fmt_peak_rate_map; 08574 VL53LX_additional_offset_cal_data_t fmt_add_offset_data; 08575 08576 VL53LX_decoded_nvm_fmt_range_data_t 08577 fmt_range_data[VL53LX_NVM_MAX_FMT_RANGE_DATA]; 08578 08579 VL53LX_decoded_nvm_fmt_info_t fmt_info; 08580 VL53LX_decoded_nvm_ews_info_t ews_info; 08581 08582 } VL53LX_decoded_nvm_data_t; 08583 08584 08585 08586 #ifdef __cplusplus 08587 } 08588 #endif 08589 08590 #endif /* _VL53LX_DEF_H_ */
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