Seunghee Jeong
/
controller_real
,
Diff: mbed_config.h
- Revision:
- 0:9d06cdd73bc7
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed_config.h Sat Dec 03 08:21:37 2022 +0000 @@ -0,0 +1,45 @@ +/* + * mbed SDK + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +// Automatically generated configuration file. +// DO NOT EDIT, content will be overwritten. + +#ifndef __MBED_CONFIG_DATA__ +#define __MBED_CONFIG_DATA__ + +// Configuration parameters +#define CLOCK_SOURCE USE_PLL_MSI // set by target:NUCLEO_L432KC +#define LPTICKER_DELAY_TICKS 0 // set by target:NUCLEO_L432KC +#define MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE 9600 // set by library:platform +#define MBED_CONF_PLATFORM_STDIO_BAUD_RATE 9600 // set by library:platform +#define MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES 0 // set by library:platform +#define MBED_CONF_PLATFORM_STDIO_FLUSH_AT_EXIT 1 // set by library:platform +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 // set by target:MCU_STM32_BAREMETAL +#define MBED_CONF_TARGET_CONSOLE_UART 1 // set by target:Target +#define MBED_CONF_TARGET_DEEP_SLEEP_LATENCY 4 // set by target:MCU_STM32 +#define MBED_CONF_TARGET_DEFAULT_ADC_VREF NAN // set by target:Target +#define MBED_CONF_TARGET_INIT_US_TICKER_AT_BOOT 1 // set by target:MCU_STM32 +#define MBED_CONF_TARGET_LPTICKER_LPTIM 1 // set by target:NUCLEO_L432KC +#define MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK 1 // set by target:MCU_STM32 +#define MBED_CONF_TARGET_LPUART_CLOCK_SOURCE USE_LPUART_CLK_LSE|USE_LPUART_CLK_PCLK1 // set by target:MCU_STM32 +#define MBED_CONF_TARGET_LSE_AVAILABLE 1 // set by target:MCU_STM32 +#define MBED_CONF_TARGET_MPU_ROM_END 0x0fffffff // set by target:Target +#define MBED_CONF_TARGET_TICKLESS_FROM_US_TICKER 0 // set by target:Target +#define MBED_CONF_TARGET_XIP_ENABLE 0 // set by target:Target + +#endif +