Diff: FPGA_bus.cpp

Revision:

7:c0bef9c1f5d5

Parent:

6:e68defb7b775

Child:

12:b9b4ff729fef

Child:

13:67382358d024

diff -r e68defb7b775 -r c0bef9c1f5d5 FPGA_bus.cpp
--- a/FPGA_bus.cpp	Wed May 08 16:41:44 2019 +0000
+++ b/FPGA_bus.cpp	Mon Apr 13 16:10:23 2020 +0000
@@ -13,25 +13,9 @@
  * Notes
  *      You can only change the defaults by recompiling the SystemVerilog code
  *      on the FPGA.
- */  
-FPGA_bus::FPGA_bus(int nos_PWM   = NOS_PWM_CHANNELS, 
-                   int nos_QE    = NOS_QE_CHANNELS, 
-                   int nos_servo = NOS_RC_CHANNELS)
-                   
-                :   async_uP_start(ASYNC_UP_START_PIN), 
-                    async_uP_handshake_1(ASYNC_UP_HANDSHAKE_1_PIN),
-                    async_uP_RW(ASYNC_UP_RW_PIN),
-                    async_uP_reset(ASYNC_UP_RESET_PIN),
-                    uP_ack(ASYNC_UP_ACK_PIN),
-                    uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN)                   
-{
-    _nos_PWM_units   = nos_PWM;
-    _nos_QE_units    = nos_QE;
-    _nos_servo_units = nos_servo;
-    
-    async_uP_start   = LOW;
-}
-
+ */ 
+ 
+ /*
 FPGA_bus::FPGA_bus(void)
                 :   async_uP_start(ASYNC_UP_START_PIN), 
                     async_uP_handshake_1(ASYNC_UP_HANDSHAKE_1_PIN),
@@ -46,7 +30,28 @@
     
     async_uP_start       = LOW;
 }
-
+ */
+FPGA_bus::FPGA_bus(int nos_PWM   /* = NOS_PWM_CHANNELS */, 
+                   int nos_QE    /* = NOS_QE_CHANNELS  */, 
+                   int nos_servo /* = NOS_RC_CHANNELS  */ )
+                   
+                :   async_uP_start(ASYNC_UP_START_PIN), 
+                    async_uP_handshake_1(ASYNC_UP_HANDSHAKE_1_PIN),
+                    async_uP_RW(ASYNC_UP_RW_PIN),
+                    async_uP_reset(ASYNC_UP_RESET_PIN),
+                    uP_ack(ASYNC_UP_ACK_PIN),
+                    uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN),
+                    
+                      _nos_PWM_units(nos_PWM),
+                      _nos_QE_units(nos_QE),
+                      _nos_servo_units(nos_servo)               
+{
+ /*   _nos_PWM_units   = nos_PWM;
+    _nos_QE_units    = nos_QE;
+    _nos_servo_units = nos_servo;  */
+    
+    async_uP_start   = LOW;
+}
 
 
 void  FPGA_bus::initialise(void)