Diff: FPGA_bus.cpp

Revision:

9:6fe95fb0c7ea

Parent:

8:65d1b1a7bfcc

Child:

10:56a045a02047

diff -r 65d1b1a7bfcc -r 6fe95fb0c7ea FPGA_bus.cpp
--- a/FPGA_bus.cpp	Sun May 12 21:10:50 2019 +0000
+++ b/FPGA_bus.cpp	Wed May 29 15:08:52 2019 +0000
@@ -23,7 +23,8 @@
                     async_uP_RW(ASYNC_UP_RW_PIN),
                     async_uP_reset(ASYNC_UP_RESET_PIN),
                     uP_ack(ASYNC_UP_ACK_PIN),
-                    uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN)                   
+                    uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN), 
+                    log_pin(LOG_PIN)                 
 {
     _nos_PWM_units   = nos_PWM;
     _nos_QE_units    = nos_QE;
@@ -38,7 +39,8 @@
                     async_uP_RW(ASYNC_UP_RW_PIN),
                     async_uP_reset(ASYNC_UP_RESET_PIN),
                     uP_ack(ASYNC_UP_ACK_PIN),
-                    uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN)                   
+                    uP_handshake_2(ASYNC_UP_HANDSHAKE_2_PIN),
+                    log_pin(LOG_PIN)                  
 {
     _nos_PWM_units   = NOS_PWM_CHANNELS;
     _nos_QE_units    = NOS_QE_CHANNELS;
@@ -67,6 +69,7 @@
     wait_us(20);
     
     global_FPGA_unit_error_flag = NO_ERROR;
+    log_pin = LOW;
 }
     
 void FPGA_bus::do_start(void)
@@ -135,17 +138,14 @@
                     uint32_t *data,
                     uint32_t *status)
 {
+    log_pin = HIGH;
     do_start();
- //   pc.printf("\n1");
     do_write(command, register_address, register_data);
- //   pc.printf(" 2");
     do_read(&in_pkt);
- //   pc.printf(" 3");
     do_end();
- //   pc.printf(" 4\n");
+    log_pin = LOW;
     *data = in_pkt.word_data[0];
     *status = in_pkt.word_data[1];
-   // pc.printf("data = %#08X  :: status = %#08X\n", in_pkt.word_data[0], in_pkt.word_data[1]);
 }
 
 uint32_t  FPGA_bus::do_command(FPGA_packet_t cmd_packet)
@@ -224,12 +224,23 @@
     global_FPGA_unit_error_flag = status;
 }
 
-void FPGA_bus::enable_speed_measure(uint32_t channel)
+void FPGA_bus::QE_config(uint32_t channel, uint32_t config_value)
+{
+    uint32_t register_address = ((PWM_BASE + (channel * NOS_PWM_REGISTERS)) + PWM_CONFIG);
+    do_transaction(WRITE_REGISTER_CMD, register_address , config_value, &data, &status);
+    global_FPGA_unit_error_flag = status;;
+}
+
+void FPGA_bus::enable_speed_measure(uint32_t channel, uint32_t config_value, uint32_t phase_time)
 {
-    uint32_t register_address = ((QE_BASE + (channel * NOS_QE_REGISTERS)) + QE_CONFIG);
-    uint32_t register_data = QE_SPEED_CALC_ENABLE;
-    do_transaction(WRITE_REGISTER_CMD, register_address, register_data, &data, &status);
+    uint32_t register_base = (QE_BASE + (channel * NOS_QE_REGISTERS));
+    do_transaction(WRITE_REGISTER_CMD, (register_base + QE_SIM_PHASE_TIME), phase_time, &data, &status);
     global_FPGA_unit_error_flag = status;
+ //   if (status != NO_ERROR) {
+ //       return;
+ //   }
+//    do_transaction(WRITE_REGISTER_CMD, (register_base + QE_CONFIG), config_value, &data, &status);
+//    global_FPGA_unit_error_flag = status;
 }
 
 uint32_t FPGA_bus::read_speed_measure(uint32_t channel)