Diff: FPGA_bus.cpp

Revision:

21:6b2b7a0e2d9a

Parent:

20:aacf2ebd93ff

Child:

22:c47d4177d59c

diff -r aacf2ebd93ff -r 6b2b7a0e2d9a FPGA_bus.cpp
--- a/FPGA_bus.cpp	Mon Jun 15 21:29:40 2020 +0000
+++ b/FPGA_bus.cpp	Tue Jun 16 23:06:04 2020 +0000
@@ -423,40 +423,31 @@
 // Notes
 //      Timeout on a first handshake after a RESET. Uses first part of
 //      'write_byte' handshake to test bus
-//      Three attempts are made before a fault is returned.
 // Return
 //      OK       = bus active and replying correctly
 //      BUS_FAIL = unable to get response from FPGA through bus
 //
 int32_t FPGA_bus::check_bus(void)
 {
+    do_reset();
+    wait_us(uS_DELAY_BEFORE_TEST_HANDSHAKE);
     
-    int32_t status = NO_ERROR;
-    for (uint32_t i=0 ; i < NOS_BUS_CHECKS ; i++) {
-        do_reset();
-        do_start();
-        SET_BUS_INPUT;
-        async_uP_RW = READ_BUS;
-        
-        SET_BUS_OUTPUT;
-        OUTPUT_BYTE_TO_BUS(0);
-        async_uP_RW = WRITE_BUS;
-        async_uP_handshake_1 = HIGH;
-        
-        
-        uint32_t timeout_count = BUS_TEST_TIMEOUT;
-        
-        while (uP_handshake_2 == LOW) {
-            timeout_count--;
-            if (timeout_count == 0) {
-                status = BUS_FAIL;
-                continue;           // try again
-            }
-        }
-        
-        status = NO_ERROR;
-        break;
+    if (uP_handshake_2 == HIGH) {
+        return  BUS_FAIL_1;       // handshake line in wrong init state
     }
+    
+    do_start();
+    SET_BUS_INPUT;
+    async_uP_RW = READ_BUS;
+    SET_BUS_OUTPUT;
+    OUTPUT_BYTE_TO_BUS(0);
+    async_uP_RW = WRITE_BUS;
+    async_uP_handshake_1 = HIGH;
+    wait_us(uS_DELAY_BEFORE_TEST_HANDSHAKE);
+    
+    if (uP_handshake_2 == LOW) {
+        return BUS_FAIL_2;
+    }  
 //
 // set system back to original state
 //
@@ -465,7 +456,7 @@
     async_uP_handshake_1 = LOW;
     async_uP_RW          = LOW;
     do_reset();
-    return status;
+    return NO_ERROR;
 }
 
     
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