Diff: FPGA_bus.h

Revision:

1:b819a72b3b5d

Parent:

0:9600ed6fd725

Child:

2:fd5c862b86db

--- a/FPGA_bus.h	Wed Feb 20 16:42:55 2019 +0000
+++ b/FPGA_bus.h	Wed Apr 17 14:32:22 2019 +0000
@@ -47,6 +47,17 @@
 #define INPUT_BYTE_FROM_BUS       (GPIOC->IDR & 0x000000FF)
 #define ENABLE_GPIO_SUBSYSTEM     (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
 
+// 
+// FPGA constants
+
+#define     nS_IN_uS                1000
+#define     FPGA_CLOCK_PERIOD_nS    20
+
+//
+// error codes
+
+#define  NO_ERROR   0
+
 #define LOOP_HERE     for(;;)
 
 typedef struct {
@@ -93,10 +104,16 @@
      
      void     initialise(void); 
      uint32_t do_command(FPGA_packet_t cmd_packet);
-     uint32_t set_PWM_period(uint32_t channel, float frequency);
-     uint32_t set_PWM_duty(uint32_t channel, float percentage);
-     uint32_t PWM_enable(uint32_t channel);
-     uint32_t PWM_config(uint32_t channel, uint32_t config_value);
+     void set_PWM_period(uint32_t channel, float frequency);
+     void set_PWM_duty(uint32_t channel, float percentage);
+     void PWM_enable(uint32_t channel);
+     void PWM_config(uint32_t channel, uint32_t config_value);
+     void set_RC_duty(void);
+     void set_RC_duty(uint32_t duty_uS);
+     void set_RC_pulse(uint32_t channel, uint32_t pulse_uS);
+     void enable_RC_channel(uint32_t channel);
+     
+     int32_t global_FPGA_unit_error_flag;
      
 protected:
     uint32_t    _nos_PWM_units;