Jeon byungchul / USBHOST

forked for unsupported target

Dependents:   stm32-disco-example DISCO-F469NI_BD_SD_Card_Control

Fork of USBHOST by ST

USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/userdef/usb0_host_dmacdrv.c@7:75f3e275934b, 2017-08-08 (annotated)

Committer:
bcjun@aname.co.kr
Date:
Tue Aug 08 16:20:39 2017 +0900
Revision:
7:75f3e275934b
Parent:
1:ab240722d7ef 
change usbhost library that forked in my account

Who changed what in which revision?

UserRevisionLine numberNew contents of line
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 1 /*******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 2 * DISCLAIMER
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 3 * This software is supplied by Renesas Electronics Corporation and is only
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 4 * intended for use with Renesas products. No other uses are authorized. This
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 5 * software is owned by Renesas Electronics Corporation and is protected under
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 6 * all applicable laws, including copyright laws.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 16 * Renesas reserves the right, without notice, to make changes to this software
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 17 * and to discontinue the availability of this software. By using this software,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 18 * you agree to the additional terms and conditions found by accessing the
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 19 * following link:
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 20 * http://www.renesas.com/disclaimer
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 22 *******************************************************************************/
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 23 /*******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 24 * File Name : usb0_host_dmacdrv.c
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 25 * $Rev: 1116 $
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 26 * $Date:: 2014-07-09 16:29:19 +0900#$
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 27 * Device(s) : RZ/A1H
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 28 * Tool-Chain :
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 29 * OS : None
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 30 * H/W Platform :
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 31 * Description : RZ/A1H R7S72100 USB Sample Program
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 32 * Operation :
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 33 * Limitations :
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 34 *******************************************************************************/
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 35
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 36
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 37 /*******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 38 Includes <System Includes> , "Project Includes"
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 39 *******************************************************************************/
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 40 #include "r_typedefs.h"
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 41 #include "iodefine.h"
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 42 #include "rza_io_regrw.h"
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 43 #include "usb0_host_dmacdrv.h"
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 44
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 45
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 46 /*******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 47 Typedef definitions
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 48 *******************************************************************************/
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 49
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 50
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 51 /*******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 52 Macro definitions
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 53 *******************************************************************************/
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 54 #define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 55
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 56 /* ==== Request setting information for on-chip peripheral module ==== */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 57 typedef enum dmac_peri_req_reg_type
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 58 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 59 DMAC_REQ_MID,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 60 DMAC_REQ_RID,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 61 DMAC_REQ_AM,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 62 DMAC_REQ_LVL,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 63 DMAC_REQ_REQD
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 64 } dmac_peri_req_reg_type_t;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 65
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 66
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 67 /*******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 68 Imported global variables and functions (from other files)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 69 *******************************************************************************/
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 70
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 71
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 72 /*******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 73 Exported global variables and functions (to be accessed by other files)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 74 *******************************************************************************/
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 75
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 76
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 77 /*******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 78 Private global variables and functions
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 79 *******************************************************************************/
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 80 /* ==== Prototype declaration ==== */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 81
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 82 /* ==== Global variable ==== */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 83 /* On-chip peripheral module request setting table */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 84 static const uint8_t usb0_host_dmac_peri_req_init_table[8][5] =
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 85 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 86 /* MID,RID, AM,LVL,REQD */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 87 { 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 88 { 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 89 { 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 90 { 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 91 { 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 92 { 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 93 { 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 94 { 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 95 };
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 96
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 97
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 98 /*******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 99 * Function Name: usb0_host_DMAC1_PeriReqInit
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 100 * Description : Sets the register mode for DMA mode and the on-chip peripheral
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 101 * : module request for transfer request for DMAC channel 1.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 102 * : Executes DMAC initial setting using the DMA information
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 103 * : specified by the argument *trans_info and the enabled/disabled
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 104 * : continuous transfer specified by the argument continuation.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 105 * : Registers DMAC channel 1 interrupt handler function and sets
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 106 * : the interrupt priority level. Then enables transfer completion
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 107 * : interrupt.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 108 * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 109 * : : register
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 110 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 111 * : uint32_t continuation : Set continuous transfer to be valid
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 112 * : : after DMA transfer has been completed
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 113 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 114 * : DMAC_SAMPLE_SINGLE : Do not execute continuous
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 115 * : : transfer
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 116 * : uint32_t request_factor : Factor for on-chip peripheral module
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 117 * : : request
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 118 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 119 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 120 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 121 * : :
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 122 * : uint32_t req_direction : Setting value of CHCFG_n register
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 123 * : : REQD bit
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 124 * Return Value : none
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 125 *******************************************************************************/
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 126 void usb0_host_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 127 uint32_t request_factor, uint32_t req_direction)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 128 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 129 /* ==== Register mode ==== */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 130 if (DMAC_MODE_REGISTER == dmamode)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 131 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 132 /* ==== Next0 register set ==== */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 133 DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 134 DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 135 DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 136
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 137 /* DAD : Transfer destination address counting direction */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 138 /* SAD : Transfer source address counting direction */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 139 /* DDS : Transfer destination transfer size */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 140 /* SDS : Transfer source transfer size */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 141 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 142 trans_info->daddr_dir,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 143 DMAC1_CHCFG_n_DAD_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 144 DMAC1_CHCFG_n_DAD);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 145 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 146 trans_info->saddr_dir,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 147 DMAC1_CHCFG_n_SAD_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 148 DMAC1_CHCFG_n_SAD);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 149 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 150 trans_info->dst_size,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 151 DMAC1_CHCFG_n_DDS_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 152 DMAC1_CHCFG_n_DDS);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 153 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 154 trans_info->src_size,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 155 DMAC1_CHCFG_n_SDS_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 156 DMAC1_CHCFG_n_SDS);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 157
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 158 /* DMS : Register mode */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 159 /* RSEL : Select Next0 register set */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 160 /* SBE : No discharge of buffer data when aborted */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 161 /* DEM : No DMA interrupt mask */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 162 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 163 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 164 DMAC1_CHCFG_n_DMS_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 165 DMAC1_CHCFG_n_DMS);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 166 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 167 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 168 DMAC1_CHCFG_n_RSEL_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 169 DMAC1_CHCFG_n_RSEL);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 170 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 171 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 172 DMAC1_CHCFG_n_SBE_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 173 DMAC1_CHCFG_n_SBE);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 174 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 175 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 176 DMAC1_CHCFG_n_DEM_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 177 DMAC1_CHCFG_n_DEM);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 178
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 179 /* ---- Continuous transfer ---- */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 180 if (DMAC_SAMPLE_CONTINUATION == continuation)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 181 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 182 /* REN : Execute continuous transfer */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 183 /* RSW : Change register set when DMA transfer is completed. */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 184 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 185 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 186 DMAC1_CHCFG_n_REN_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 187 DMAC1_CHCFG_n_REN);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 188 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 189 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 190 DMAC1_CHCFG_n_RSW_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 191 DMAC1_CHCFG_n_RSW);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 192 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 193 /* ---- Single transfer ---- */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 194 else
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 195 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 196 /* REN : Do not execute continuous transfer */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 197 /* RSW : Do not change register set when DMA transfer is completed. */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 198 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 199 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 200 DMAC1_CHCFG_n_REN_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 201 DMAC1_CHCFG_n_REN);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 202 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 203 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 204 DMAC1_CHCFG_n_RSW_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 205 DMAC1_CHCFG_n_RSW);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 206 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 207
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 208 /* TM : Single transfer */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 209 /* SEL : Channel setting */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 210 /* HIEN, LOEN : On-chip peripheral module request */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 211 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 212 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 213 DMAC1_CHCFG_n_TM_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 214 DMAC1_CHCFG_n_TM);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 215 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 216 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 217 DMAC1_CHCFG_n_SEL_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 218 DMAC1_CHCFG_n_SEL);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 219 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 220 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 221 DMAC1_CHCFG_n_HIEN_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 222 DMAC1_CHCFG_n_HIEN);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 223 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 224 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 225 DMAC1_CHCFG_n_LOEN_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 226 DMAC1_CHCFG_n_LOEN);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 227
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 228 /* ---- Set factor by specified on-chip peripheral module request ---- */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 229 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 230 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 231 DMAC1_CHCFG_n_AM_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 232 DMAC1_CHCFG_n_AM);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 233 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 234 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 235 DMAC1_CHCFG_n_LVL_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 236 DMAC1_CHCFG_n_LVL);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 237 if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 238 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 239 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 240 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 241 DMAC1_CHCFG_n_REQD_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 242 DMAC1_CHCFG_n_REQD);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 243 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 244 else
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 245 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 246 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 247 req_direction,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 248 DMAC1_CHCFG_n_REQD_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 249 DMAC1_CHCFG_n_REQD);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 250 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 251 RZA_IO_RegWrite_32(&DMAC01.DMARS,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 252 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 253 DMAC01_DMARS_CH1_RID_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 254 DMAC01_DMARS_CH1_RID);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 255 RZA_IO_RegWrite_32(&DMAC01.DMARS,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 256 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 257 DMAC01_DMARS_CH1_MID_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 258 DMAC01_DMARS_CH1_MID);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 259
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 260 /* PR : Round robin mode */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 261 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 262 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 263 DMAC07_DCTRL_0_7_PR_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 264 DMAC07_DCTRL_0_7_PR);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 265 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 266 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 267
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 268 /*******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 269 * Function Name: usb0_host_DMAC1_Open
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 270 * Description : Enables DMAC channel 1 transfer.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 271 * Arguments : uint32_t req : DMAC request mode
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 272 * Return Value : 0 : Succeeded in enabling DMA transfer
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 273 * : -1 : Failed to enable DMA transfer (due to DMA operation)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 274 *******************************************************************************/
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 275 int32_t usb0_host_DMAC1_Open (uint32_t req)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 276 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 277 int32_t ret;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 278 volatile uint8_t dummy;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 279
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 280 /* Transferable? */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 281 if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 282 DMAC1_CHSTAT_n_EN_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 283 DMAC1_CHSTAT_n_EN)) &&
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 284 (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 285 DMAC1_CHSTAT_n_TACT_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 286 DMAC1_CHSTAT_n_TACT)))
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 287 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 288 /* Clear Channel Status Register */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 289 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 290 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 291 DMAC1_CHCTRL_n_SWRST_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 292 DMAC1_CHCTRL_n_SWRST);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 293 dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 294 DMAC1_CHCTRL_n_SWRST_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 295 DMAC1_CHCTRL_n_SWRST);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 296 /* Enable DMA transfer */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 297 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 298 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 299 DMAC1_CHCTRL_n_SETEN_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 300 DMAC1_CHCTRL_n_SETEN);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 301
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 302 /* ---- Request by software ---- */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 303 if (DMAC_REQ_MODE_SOFT == req)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 304 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 305 /* DMA transfer Request by software */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 306 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 307 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 308 DMAC1_CHCTRL_n_STG_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 309 DMAC1_CHCTRL_n_STG);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 310 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 311
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 312 ret = 0;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 313 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 314 else
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 315 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 316 ret = -1;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 317 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 318
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 319 return ret;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 320 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 321
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 322 /*******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 323 * Function Name: usb0_host_DMAC1_Close
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 324 * Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 325 * : byte count at the time of DMA transfer abort to the argument
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 326 * : *remain.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 327 * Arguments : uint32_t * remain : Remaining transfer byte count when
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 328 * : : DMA transfer is aborted
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 329 * Return Value : none
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 330 *******************************************************************************/
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 331 void usb0_host_DMAC1_Close (uint32_t * remain)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 332 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 333
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 334 /* ==== Abort transfer ==== */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 335 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 336 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 337 DMAC1_CHCTRL_n_CLREN_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 338 DMAC1_CHCTRL_n_CLREN);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 339
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 340 while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 341 DMAC1_CHSTAT_n_TACT_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 342 DMAC1_CHSTAT_n_TACT))
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 343 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 344 /* Loop until transfer is aborted */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 345 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 346
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 347 while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 348 DMAC1_CHSTAT_n_EN_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 349 DMAC1_CHSTAT_n_EN))
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 350 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 351 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 352 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 353 /* ==== Obtain remaining transfer byte count ==== */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 354 *remain = DMAC1.CRTB_n;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 355 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 356
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 357 /*******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 358 * Function Name: usb0_host_DMAC1_Load_Set
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 359 * Description : Sets the transfer source address, transfer destination
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 360 * : address, and total transfer byte count respectively
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 361 * : specified by the argument src_addr, dst_addr, and count to
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 362 * : DMAC channel 1 as DMA transfer information.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 363 * : Sets the register set selected by the CHCFG_n register
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 364 * : RSEL bit from the Next0 or Next1 register set.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 365 * : This function should be called when DMA transfer of DMAC
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 366 * : channel 1 is aboted.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 367 * Arguments : uint32_t src_addr : Transfer source address
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 368 * : uint32_t dst_addr : Transfer destination address
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 369 * : uint32_t count : Total transfer byte count
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 370 * Return Value : none
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 371 *******************************************************************************/
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 372 void usb0_host_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 373 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 374 uint8_t reg_set;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 375
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 376 /* Obtain register set in use */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 377 reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 378 DMAC1_CHSTAT_n_SR_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 379 DMAC1_CHSTAT_n_SR);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 380
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 381 /* ==== Load ==== */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 382 if (0 == reg_set)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 383 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 384 /* ---- Next0 Register Set ---- */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 385 DMAC1.N0SA_n = src_addr; /* Start address of transfer source */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 386 DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 387 DMAC1.N0TB_n = count; /* Total transfer byte count */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 388 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 389 else
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 390 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 391 /* ---- Next1 Register Set ---- */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 392 DMAC1.N1SA_n = src_addr; /* Start address of transfer source */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 393 DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 394 DMAC1.N1TB_n = count; /* Total transfer byte count */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 395 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 396 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 397
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 398 /*******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 399 * Function Name: usb0_host_DMAC2_PeriReqInit
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 400 * Description : Sets the register mode for DMA mode and the on-chip peripheral
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 401 * : module request for transfer request for DMAC channel 2.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 402 * : Executes DMAC initial setting using the DMA information
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 403 * : specified by the argument *trans_info and the enabled/disabled
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 404 * : continuous transfer specified by the argument continuation.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 405 * : Registers DMAC channel 2 interrupt handler function and sets
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 406 * : the interrupt priority level. Then enables transfer completion
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 407 * : interrupt.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 408 * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 409 * : : register
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 410 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 411 * : uint32_t continuation : Set continuous transfer to be valid
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 412 * : : after DMA transfer has been completed
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 413 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 414 * : DMAC_SAMPLE_SINGLE : Do not execute continuous
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 415 * : : transfer
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 416 * : uint32_t request_factor : Factor for on-chip peripheral module
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 417 * : : request
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 418 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 419 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 420 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 421 * : :
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 422 * : uint32_t req_direction : Setting value of CHCFG_n register
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 423 * : : REQD bit
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 424 * Return Value : none
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 425 *******************************************************************************/
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 426 void usb0_host_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 427 uint32_t request_factor, uint32_t req_direction)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 428 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 429 /* ==== Register mode ==== */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 430 if (DMAC_MODE_REGISTER == dmamode)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 431 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 432 /* ==== Next0 register set ==== */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 433 DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 434 DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 435 DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 436
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 437 /* DAD : Transfer destination address counting direction */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 438 /* SAD : Transfer source address counting direction */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 439 /* DDS : Transfer destination transfer size */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 440 /* SDS : Transfer source transfer size */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 441 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 442 trans_info->daddr_dir,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 443 DMAC2_CHCFG_n_DAD_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 444 DMAC2_CHCFG_n_DAD);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 445 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 446 trans_info->saddr_dir,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 447 DMAC2_CHCFG_n_SAD_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 448 DMAC2_CHCFG_n_SAD);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 449 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 450 trans_info->dst_size,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 451 DMAC2_CHCFG_n_DDS_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 452 DMAC2_CHCFG_n_DDS);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 453 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 454 trans_info->src_size,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 455 DMAC2_CHCFG_n_SDS_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 456 DMAC2_CHCFG_n_SDS);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 457
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 458 /* DMS : Register mode */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 459 /* RSEL : Select Next0 register set */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 460 /* SBE : No discharge of buffer data when aborted */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 461 /* DEM : No DMA interrupt mask */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 462 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 463 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 464 DMAC2_CHCFG_n_DMS_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 465 DMAC2_CHCFG_n_DMS);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 466 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 467 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 468 DMAC2_CHCFG_n_RSEL_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 469 DMAC2_CHCFG_n_RSEL);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 470 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 471 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 472 DMAC2_CHCFG_n_SBE_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 473 DMAC2_CHCFG_n_SBE);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 474 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 475 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 476 DMAC2_CHCFG_n_DEM_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 477 DMAC2_CHCFG_n_DEM);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 478
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 479 /* ---- Continuous transfer ---- */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 480 if (DMAC_SAMPLE_CONTINUATION == continuation)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 481 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 482 /* REN : Execute continuous transfer */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 483 /* RSW : Change register set when DMA transfer is completed. */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 484 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 485 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 486 DMAC2_CHCFG_n_REN_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 487 DMAC2_CHCFG_n_REN);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 488 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 489 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 490 DMAC2_CHCFG_n_RSW_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 491 DMAC2_CHCFG_n_RSW);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 492 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 493 /* ---- Single transfer ---- */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 494 else
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 495 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 496 /* REN : Do not execute continuous transfer */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 497 /* RSW : Do not change register set when DMA transfer is completed. */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 498 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 499 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 500 DMAC2_CHCFG_n_REN_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 501 DMAC2_CHCFG_n_REN);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 502 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 503 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 504 DMAC2_CHCFG_n_RSW_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 505 DMAC2_CHCFG_n_RSW);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 506 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 507
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 508 /* TM : Single transfer */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 509 /* SEL : Channel setting */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 510 /* HIEN, LOEN : On-chip peripheral module request */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 511 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 512 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 513 DMAC2_CHCFG_n_TM_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 514 DMAC2_CHCFG_n_TM);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 515 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 516 2,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 517 DMAC2_CHCFG_n_SEL_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 518 DMAC2_CHCFG_n_SEL);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 519 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 520 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 521 DMAC2_CHCFG_n_HIEN_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 522 DMAC2_CHCFG_n_HIEN);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 523 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 524 0,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 525 DMAC2_CHCFG_n_LOEN_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 526 DMAC2_CHCFG_n_LOEN);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 527
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 528 /* ---- Set factor by specified on-chip peripheral module request ---- */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 529 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 530 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 531 DMAC2_CHCFG_n_AM_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 532 DMAC2_CHCFG_n_AM);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 533 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 534 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 535 DMAC2_CHCFG_n_LVL_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 536 DMAC2_CHCFG_n_LVL);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 537 if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 538 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 539 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 540 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 541 DMAC2_CHCFG_n_REQD_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 542 DMAC2_CHCFG_n_REQD);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 543 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 544 else
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 545 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 546 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 547 req_direction,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 548 DMAC2_CHCFG_n_REQD_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 549 DMAC2_CHCFG_n_REQD);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 550 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 551 RZA_IO_RegWrite_32(&DMAC23.DMARS,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 552 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 553 DMAC23_DMARS_CH2_RID_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 554 DMAC23_DMARS_CH2_RID);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 555 RZA_IO_RegWrite_32(&DMAC23.DMARS,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 556 usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 557 DMAC23_DMARS_CH2_MID_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 558 DMAC23_DMARS_CH2_MID);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 559
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 560 /* PR : Round robin mode */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 561 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 562 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 563 DMAC07_DCTRL_0_7_PR_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 564 DMAC07_DCTRL_0_7_PR);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 565 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 566 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 567
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 568 /*******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 569 * Function Name: usb0_host_DMAC2_Open
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 570 * Description : Enables DMAC channel 2 transfer.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 571 * Arguments : uint32_t req : DMAC request mode
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 572 * Return Value : 0 : Succeeded in enabling DMA transfer
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 573 * : -1 : Failed to enable DMA transfer (due to DMA operation)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 574 *******************************************************************************/
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 575 int32_t usb0_host_DMAC2_Open (uint32_t req)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 576 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 577 int32_t ret;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 578 volatile uint8_t dummy;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 579
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 580 /* Transferable? */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 581 if ((0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 582 DMAC2_CHSTAT_n_EN_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 583 DMAC2_CHSTAT_n_EN)) &&
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 584 (0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 585 DMAC2_CHSTAT_n_TACT_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 586 DMAC2_CHSTAT_n_TACT)))
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 587 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 588 /* Clear Channel Status Register */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 589 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 590 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 591 DMAC2_CHCTRL_n_SWRST_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 592 DMAC2_CHCTRL_n_SWRST);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 593 dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 594 DMAC2_CHCTRL_n_SWRST_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 595 DMAC2_CHCTRL_n_SWRST);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 596 /* Enable DMA transfer */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 597 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 598 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 599 DMAC2_CHCTRL_n_SETEN_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 600 DMAC2_CHCTRL_n_SETEN);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 601
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 602 /* ---- Request by software ---- */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 603 if (DMAC_REQ_MODE_SOFT == req)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 604 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 605 /* DMA transfer Request by software */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 606 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 607 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 608 DMAC2_CHCTRL_n_STG_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 609 DMAC2_CHCTRL_n_STG);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 610 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 611
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 612 ret = 0;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 613 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 614 else
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 615 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 616 ret = -1;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 617 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 618
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 619 return ret;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 620 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 621
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 622 /*******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 623 * Function Name: usb0_host_DMAC2_Close
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 624 * Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 625 * : byte count at the time of DMA transfer abort to the argument
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 626 * : *remain.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 627 * Arguments : uint32_t * remain : Remaining transfer byte count when
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 628 * : : DMA transfer is aborted
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 629 * Return Value : none
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 630 *******************************************************************************/
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 631 void usb0_host_DMAC2_Close (uint32_t * remain)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 632 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 633
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 634 /* ==== Abort transfer ==== */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 635 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 636 1,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 637 DMAC2_CHCTRL_n_CLREN_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 638 DMAC2_CHCTRL_n_CLREN);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 639
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 640 while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 641 DMAC2_CHSTAT_n_TACT_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 642 DMAC2_CHSTAT_n_TACT))
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 643 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 644 /* Loop until transfer is aborted */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 645 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 646
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 647 while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 648 DMAC2_CHSTAT_n_EN_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 649 DMAC2_CHSTAT_n_EN))
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 650 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 651 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 652 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 653 /* ==== Obtain remaining transfer byte count ==== */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 654 *remain = DMAC2.CRTB_n;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 655 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 656
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 657 /*******************************************************************************
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 658 * Function Name: usb0_host_DMAC2_Load_Set
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 659 * Description : Sets the transfer source address, transfer destination
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 660 * : address, and total transfer byte count respectively
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 661 * : specified by the argument src_addr, dst_addr, and count to
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 662 * : DMAC channel 2 as DMA transfer information.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 663 * : Sets the register set selected by the CHCFG_n register
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 664 * : RSEL bit from the Next0 or Next1 register set.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 665 * : This function should be called when DMA transfer of DMAC
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 666 * : channel 2 is aboted.
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 667 * Arguments : uint32_t src_addr : Transfer source address
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 668 * : uint32_t dst_addr : Transfer destination address
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 669 * : uint32_t count : Total transfer byte count
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 670 * Return Value : none
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 671 *******************************************************************************/
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 672 void usb0_host_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 673 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 674 uint8_t reg_set;
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 675
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 676 /* Obtain register set in use */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 677 reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 678 DMAC2_CHSTAT_n_SR_SHIFT,
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 679 DMAC2_CHSTAT_n_SR);
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 680
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 681 /* ==== Load ==== */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 682 if (0 == reg_set)
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 683 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 684 /* ---- Next0 Register Set ---- */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 685 DMAC2.N0SA_n = src_addr; /* Start address of transfer source */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 686 DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 687 DMAC2.N0TB_n = count; /* Total transfer byte count */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 688 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 689 else
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 690 {
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 691 /* ---- Next1 Register Set ---- */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 692 DMAC2.N1SA_n = src_addr; /* Start address of transfer source */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 693 DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 694 DMAC2.N1TB_n = count; /* Total transfer byte count */
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 695 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 696 }
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 697
frq08711@LMECWL0871.LME.ST.COM 1:ab240722d7ef 698 /* End of File */