Encapsulates access to the Cypress CY14B101P nvSRAM module.
CY14B101P.cpp@0:eec14545c442, 2011-07-11 (annotated)
- Committer:
- jeffcraighead
- Date:
- Mon Jul 11 16:41:25 2011 +0000
- Revision:
- 0:eec14545c442
- Child:
- 1:0f4063d68380
RTC functions not implemented. All other software features documented in the CY14B101P datasheet \"should\" work.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
jeffcraighead | 0:eec14545c442 | 1 | #include "CY14B101P.h" |
jeffcraighead | 0:eec14545c442 | 2 | |
jeffcraighead | 0:eec14545c442 | 3 | Serial pc_(USBTX,USBRX); |
jeffcraighead | 0:eec14545c442 | 4 | //Constructor - specify mbed pins for SPI connection to memory and the SPI clock rate |
jeffcraighead | 0:eec14545c442 | 5 | NVSRAM::NVSRAM(PinName mosi, PinName miso, PinName sclk, PinName csel, int spifrequency, int spibits, int spimode) : spi_(mosi, miso, sclk), chipSel_(csel) { |
jeffcraighead | 0:eec14545c442 | 6 | |
jeffcraighead | 0:eec14545c442 | 7 | //chipSel_(csel); |
jeffcraighead | 0:eec14545c442 | 8 | |
jeffcraighead | 0:eec14545c442 | 9 | spi_.format(spibits,spimode); |
jeffcraighead | 0:eec14545c442 | 10 | spi_.frequency(spifrequency); |
jeffcraighead | 0:eec14545c442 | 11 | spifreq = spifrequency; |
jeffcraighead | 0:eec14545c442 | 12 | chipSel_=1; |
jeffcraighead | 0:eec14545c442 | 13 | } |
jeffcraighead | 0:eec14545c442 | 14 | |
jeffcraighead | 0:eec14545c442 | 15 | void NVSRAM::init(){ |
jeffcraighead | 0:eec14545c442 | 16 | writeStatusRegister(0x00); |
jeffcraighead | 0:eec14545c442 | 17 | } |
jeffcraighead | 0:eec14545c442 | 18 | |
jeffcraighead | 0:eec14545c442 | 19 | void NVSRAM::writeBytes(char *bytes, unsigned int address, int length){ |
jeffcraighead | 0:eec14545c442 | 20 | chipSel_ = 0; |
jeffcraighead | 0:eec14545c442 | 21 | spi_.write(WREN); |
jeffcraighead | 0:eec14545c442 | 22 | chipSel_ = 1; |
jeffcraighead | 0:eec14545c442 | 23 | |
jeffcraighead | 0:eec14545c442 | 24 | chipSel_ = 0; |
jeffcraighead | 0:eec14545c442 | 25 | |
jeffcraighead | 0:eec14545c442 | 26 | spi_.write(WRITE); |
jeffcraighead | 0:eec14545c442 | 27 | |
jeffcraighead | 0:eec14545c442 | 28 | spi_.write( (char)(0x00010000 & address)>>16 ); |
jeffcraighead | 0:eec14545c442 | 29 | spi_.write( (char)(0x0000FF00 & address)>>8 ); |
jeffcraighead | 0:eec14545c442 | 30 | spi_.write( (char)(0x000000FF & address) ); |
jeffcraighead | 0:eec14545c442 | 31 | |
jeffcraighead | 0:eec14545c442 | 32 | for(int i=0; i<length; i++) spi_.write(bytes[i]); |
jeffcraighead | 0:eec14545c442 | 33 | |
jeffcraighead | 0:eec14545c442 | 34 | chipSel_ = 1; |
jeffcraighead | 0:eec14545c442 | 35 | } |
jeffcraighead | 0:eec14545c442 | 36 | |
jeffcraighead | 0:eec14545c442 | 37 | void NVSRAM::readBytes(char *bytes, unsigned int address, int length){ |
jeffcraighead | 0:eec14545c442 | 38 | chipSel_ = 0; |
jeffcraighead | 0:eec14545c442 | 39 | |
jeffcraighead | 0:eec14545c442 | 40 | spi_.write(READ); |
jeffcraighead | 0:eec14545c442 | 41 | |
jeffcraighead | 0:eec14545c442 | 42 | spi_.write( (char)(0x00010000 & address)>>16 ); |
jeffcraighead | 0:eec14545c442 | 43 | spi_.write( (char)(0x0000FF00 & address)>>8 ); |
jeffcraighead | 0:eec14545c442 | 44 | spi_.write( (char)(0x000000FF & address) ); |
jeffcraighead | 0:eec14545c442 | 45 | |
jeffcraighead | 0:eec14545c442 | 46 | for(int i=0; i<length; i++) bytes[i] = spi_.write(0x00); |
jeffcraighead | 0:eec14545c442 | 47 | |
jeffcraighead | 0:eec14545c442 | 48 | chipSel_ = 1; |
jeffcraighead | 0:eec14545c442 | 49 | } |
jeffcraighead | 0:eec14545c442 | 50 | |
jeffcraighead | 0:eec14545c442 | 51 | void NVSRAM::setRTC(int century, int year, int month, int dayofmonth, int dayofweek, int hour, int minute, int second){ |
jeffcraighead | 0:eec14545c442 | 52 | //RTC SPI frequency must be no greater than 25MHz, so just use half of the SRAM frequency since that has a max of 40MHz |
jeffcraighead | 0:eec14545c442 | 53 | spi_.frequency(spifreq/2); |
jeffcraighead | 0:eec14545c442 | 54 | chipSel_=0; |
jeffcraighead | 0:eec14545c442 | 55 | spi_.write(WREN); |
jeffcraighead | 0:eec14545c442 | 56 | chipSel_=1; |
jeffcraighead | 0:eec14545c442 | 57 | |
jeffcraighead | 0:eec14545c442 | 58 | |
jeffcraighead | 0:eec14545c442 | 59 | //Set the SPI frequency back to the requested rate for NVRAM access. |
jeffcraighead | 0:eec14545c442 | 60 | spi_.frequency(spifreq); |
jeffcraighead | 0:eec14545c442 | 61 | } |
jeffcraighead | 0:eec14545c442 | 62 | |
jeffcraighead | 0:eec14545c442 | 63 | int NVSRAM::readRTC(){ |
jeffcraighead | 0:eec14545c442 | 64 | //RTC SPI frequency must be no greater than 25MHz, so just use half of the SRAM frequency since that has a max of 40MHz |
jeffcraighead | 0:eec14545c442 | 65 | spi_.frequency(spifreq/2); |
jeffcraighead | 0:eec14545c442 | 66 | |
jeffcraighead | 0:eec14545c442 | 67 | |
jeffcraighead | 0:eec14545c442 | 68 | |
jeffcraighead | 0:eec14545c442 | 69 | //Set the SPI frequency back to the requested rate for NVRAM access. |
jeffcraighead | 0:eec14545c442 | 70 | spi_.frequency(spifreq); |
jeffcraighead | 0:eec14545c442 | 71 | |
jeffcraighead | 0:eec14545c442 | 72 | |
jeffcraighead | 0:eec14545c442 | 73 | return 0; |
jeffcraighead | 0:eec14545c442 | 74 | } |
jeffcraighead | 0:eec14545c442 | 75 | |
jeffcraighead | 0:eec14545c442 | 76 | void NVSRAM::nvStore(){ |
jeffcraighead | 0:eec14545c442 | 77 | chipSel_=0; |
jeffcraighead | 0:eec14545c442 | 78 | spi_.write(WREN); |
jeffcraighead | 0:eec14545c442 | 79 | chipSel_=1; |
jeffcraighead | 0:eec14545c442 | 80 | chipSel_=0; |
jeffcraighead | 0:eec14545c442 | 81 | spi_.write(STORE); |
jeffcraighead | 0:eec14545c442 | 82 | chipSel_=1; |
jeffcraighead | 0:eec14545c442 | 83 | } |
jeffcraighead | 0:eec14545c442 | 84 | |
jeffcraighead | 0:eec14545c442 | 85 | void NVSRAM::nvRecall(){ |
jeffcraighead | 0:eec14545c442 | 86 | chipSel_=0; |
jeffcraighead | 0:eec14545c442 | 87 | spi_.write(WREN); |
jeffcraighead | 0:eec14545c442 | 88 | chipSel_=1; |
jeffcraighead | 0:eec14545c442 | 89 | chipSel_=0; |
jeffcraighead | 0:eec14545c442 | 90 | spi_.write(RECALL); |
jeffcraighead | 0:eec14545c442 | 91 | chipSel_=1; |
jeffcraighead | 0:eec14545c442 | 92 | } |
jeffcraighead | 0:eec14545c442 | 93 | |
jeffcraighead | 0:eec14545c442 | 94 | void NVSRAM::enableAutoStore(bool enable){ |
jeffcraighead | 0:eec14545c442 | 95 | chipSel_=0; |
jeffcraighead | 0:eec14545c442 | 96 | spi_.write(WREN); |
jeffcraighead | 0:eec14545c442 | 97 | chipSel_=1; |
jeffcraighead | 0:eec14545c442 | 98 | chipSel_=0; |
jeffcraighead | 0:eec14545c442 | 99 | if(enable) spi_.write(ASENB); |
jeffcraighead | 0:eec14545c442 | 100 | else spi_.write(ASDISB); |
jeffcraighead | 0:eec14545c442 | 101 | chipSel_=1; |
jeffcraighead | 0:eec14545c442 | 102 | } |
jeffcraighead | 0:eec14545c442 | 103 | |
jeffcraighead | 0:eec14545c442 | 104 | void NVSRAM::writeStatusRegister(char status){ |
jeffcraighead | 0:eec14545c442 | 105 | chipSel_=0; |
jeffcraighead | 0:eec14545c442 | 106 | spi_.write(WREN); |
jeffcraighead | 0:eec14545c442 | 107 | chipSel_=1; |
jeffcraighead | 0:eec14545c442 | 108 | chipSel_=0; |
jeffcraighead | 0:eec14545c442 | 109 | spi_.write(WRSR); |
jeffcraighead | 0:eec14545c442 | 110 | spi_.write(status); |
jeffcraighead | 0:eec14545c442 | 111 | chipSel_=1; |
jeffcraighead | 0:eec14545c442 | 112 | } |
jeffcraighead | 0:eec14545c442 | 113 | |
jeffcraighead | 0:eec14545c442 | 114 | char NVSRAM::readStatusRegister(){ |
jeffcraighead | 0:eec14545c442 | 115 | chipSel_ = 0; |
jeffcraighead | 0:eec14545c442 | 116 | spi_.write(RDSR); |
jeffcraighead | 0:eec14545c442 | 117 | char out = spi_.write(0x00); |
jeffcraighead | 0:eec14545c442 | 118 | chipSel_ = 1; |
jeffcraighead | 0:eec14545c442 | 119 | |
jeffcraighead | 0:eec14545c442 | 120 | return out; |
jeffcraighead | 0:eec14545c442 | 121 | } |