Jeff Craighead / CY14B101P

Encapsulates access to the Cypress CY14B101P nvSRAM module.

CY14B101P.h@0:eec14545c442, 2011-07-11 (annotated)

Committer:
jeffcraighead
Date:
Mon Jul 11 16:41:25 2011 +0000
Revision:
0:eec14545c442
Child:
1:0f4063d68380
RTC functions not implemented. All other software features documented in the CY14B101P datasheet \"should\" work.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jeffcraighead 0:eec14545c442 1 /****************************
jeffcraighead 0:eec14545c442 2 / This library encapsulates (or will when completely implemented)
jeffcraighead 0:eec14545c442 3 / all software functions for reading and writing to the Cypress Semiconductor
jeffcraighead 0:eec14545c442 4 / CY14B101P nvSRAM module.
jeffcraighead 0:eec14545c442 5 /
jeffcraighead 0:eec14545c442 6 / As of July 11, 2011 RTC functions are not implemented.
jeffcraighead 0:eec14545c442 7 /
jeffcraighead 0:eec14545c442 8 / Author: Dr. Jeffrey Craighead
jeffcraighead 0:eec14545c442 9 *****************************/
jeffcraighead 0:eec14545c442 10
jeffcraighead 0:eec14545c442 11
jeffcraighead 0:eec14545c442 12 #ifndef CY14B101P
jeffcraighead 0:eec14545c442 13 #define CY14B101P
jeffcraighead 0:eec14545c442 14
jeffcraighead 0:eec14545c442 15 /*****
jeffcraighead 0:eec14545c442 16 * Includes
jeffcraighead 0:eec14545c442 17 *****/
jeffcraighead 0:eec14545c442 18 #include "mbed.h"
jeffcraighead 0:eec14545c442 19
jeffcraighead 0:eec14545c442 20
jeffcraighead 0:eec14545c442 21 /*****
jeffcraighead 0:eec14545c442 22 * Status Register Instructions
jeffcraighead 0:eec14545c442 23 *****/
jeffcraighead 0:eec14545c442 24 #define WREN 0x06 //Set Write Enable latch
jeffcraighead 0:eec14545c442 25 #define WRDI 0x04 //Reset Write Enable latch
jeffcraighead 0:eec14545c442 26 #define RDSR 0x05 //Read Status Register
jeffcraighead 0:eec14545c442 27 #define WRSR 0x01 //Write Status Register
jeffcraighead 0:eec14545c442 28
jeffcraighead 0:eec14545c442 29 /*****
jeffcraighead 0:eec14545c442 30 * SRAM Instructions
jeffcraighead 0:eec14545c442 31 *****/
jeffcraighead 0:eec14545c442 32 #define READ 0x03 //Read data from memory array
jeffcraighead 0:eec14545c442 33 #define WRITE 0x02 //Write data to memory array
jeffcraighead 0:eec14545c442 34
jeffcraighead 0:eec14545c442 35 /*****
jeffcraighead 0:eec14545c442 36 * RTC Instructions
jeffcraighead 0:eec14545c442 37 *****/
jeffcraighead 0:eec14545c442 38 #define WRTC 0x12 //Write Real Time Clock registers
jeffcraighead 0:eec14545c442 39 #define RDRTC 0x13 //Read Real Time Clock registers
jeffcraighead 0:eec14545c442 40
jeffcraighead 0:eec14545c442 41 /*****
jeffcraighead 0:eec14545c442 42 * Special NV Instructions
jeffcraighead 0:eec14545c442 43 *****/
jeffcraighead 0:eec14545c442 44 #define STORE 0x3C //Software Store (to NV memory)
jeffcraighead 0:eec14545c442 45 #define RECALL 0x60 //Software Recall (from NV memory)
jeffcraighead 0:eec14545c442 46 #define ASENB 0x59 //AutoStore Enable
jeffcraighead 0:eec14545c442 47 #define ASDISB 0x19 //AutoStore Disable
jeffcraighead 0:eec14545c442 48
jeffcraighead 0:eec14545c442 49 /*****
jeffcraighead 0:eec14545c442 50 * Other Definitions
jeffcraighead 0:eec14545c442 51 *****/
jeffcraighead 0:eec14545c442 52 #define MAXADDR 0x1FFF
jeffcraighead 0:eec14545c442 53
jeffcraighead 0:eec14545c442 54 /*****
jeffcraighead 0:eec14545c442 55 * Status Register Bits
jeffcraighead 0:eec14545c442 56 *****/
jeffcraighead 0:eec14545c442 57 #define READY 0x00 //Read Only, Active Low, bit is 1 while a STORE or RECALL is in progress
jeffcraighead 0:eec14545c442 58 #define WENABLE 0x01 //Write enabled bit
jeffcraighead 0:eec14545c442 59 #define BP0 0x02; //Block protection bit 0
jeffcraighead 0:eec14545c442 60 #define BP1 0x03; //Block protection bit 1
jeffcraighead 0:eec14545c442 61 #define WPENABLE 0x07; //Enabled the use of the hardware Write Protect pin.
jeffcraighead 0:eec14545c442 62
jeffcraighead 0:eec14545c442 63
jeffcraighead 0:eec14545c442 64 /*****
jeffcraighead 0:eec14545c442 65 * Cypress CY14B101P SPI nvSRAM Memory
jeffcraighead 0:eec14545c442 66 *****/
jeffcraighead 0:eec14545c442 67
jeffcraighead 0:eec14545c442 68 class NVSRAM {
jeffcraighead 0:eec14545c442 69
jeffcraighead 0:eec14545c442 70 public:
jeffcraighead 0:eec14545c442 71
jeffcraighead 0:eec14545c442 72 //Constructor - specify mbed pins for SPI connection to memory and the SPI clock rate
jeffcraighead 0:eec14545c442 73 NVSRAM(PinName mosi, PinName miso, PinName sclk, PinName csel, int spifrequency, int spibits, int spimode);
jeffcraighead 0:eec14545c442 74
jeffcraighead 0:eec14545c442 75 //Initialize the nvRAM status register allowing writes across the entire memory range.
jeffcraighead 0:eec14545c442 76 void init();
jeffcraighead 0:eec14545c442 77
jeffcraighead 0:eec14545c442 78 //Write bytes to the SRAM
jeffcraighead 0:eec14545c442 79 void writeBytes(char *bytes, unsigned int address, int length);
jeffcraighead 0:eec14545c442 80
jeffcraighead 0:eec14545c442 81 //Read bytes from the SRAM
jeffcraighead 0:eec14545c442 82 void readBytes(char *bytes, unsigned int address, int length);
jeffcraighead 0:eec14545c442 83
jeffcraighead 0:eec14545c442 84 //Set the Real Time Clock
jeffcraighead 0:eec14545c442 85 void setRTC(int century, int year, int month, int dayofmonth, int dayofweek, int hour, int minute, int second);
jeffcraighead 0:eec14545c442 86
jeffcraighead 0:eec14545c442 87 //Read the RTC
jeffcraighead 0:eec14545c442 88 int readRTC();
jeffcraighead 0:eec14545c442 89
jeffcraighead 0:eec14545c442 90 //Store the contents of SRAM to the NV memory
jeffcraighead 0:eec14545c442 91 void nvStore();
jeffcraighead 0:eec14545c442 92
jeffcraighead 0:eec14545c442 93 //Restore the contents of NV memory to the SRAM
jeffcraighead 0:eec14545c442 94 void nvRecall();
jeffcraighead 0:eec14545c442 95
jeffcraighead 0:eec14545c442 96 //Boolean to enable the AutoStore feature of the CY14B101P
jeffcraighead 0:eec14545c442 97 //When enabled, the contents of the SRAM will automatically be stored
jeffcraighead 0:eec14545c442 98 //to the NV memory on poweroff. Requires a capacitor between Vcap and Vss
jeffcraighead 0:eec14545c442 99 void enableAutoStore(bool enable);
jeffcraighead 0:eec14545c442 100
jeffcraighead 0:eec14545c442 101 //Write the status register
jeffcraighead 0:eec14545c442 102 void writeStatusRegister(char status);
jeffcraighead 0:eec14545c442 103
jeffcraighead 0:eec14545c442 104 //Read the status register
jeffcraighead 0:eec14545c442 105 char readStatusRegister();
jeffcraighead 0:eec14545c442 106
jeffcraighead 0:eec14545c442 107 private:
jeffcraighead 0:eec14545c442 108 int spifreq;
jeffcraighead 0:eec14545c442 109 SPI spi_;
jeffcraighead 0:eec14545c442 110 DigitalOut chipSel_;
jeffcraighead 0:eec14545c442 111 };
jeffcraighead 0:eec14545c442 112
jeffcraighead 0:eec14545c442 113 #endif /* CY14B101P */