Revision 9:6ffb85d69eaf, committed 2013-03-01

Comitter:

DavidEGrayson

Date:

Fri Mar 01 03:57:49 2013 +0000

Parent:

8:1578776ceac5

Child:

10:f1bb84b97788

Commit message:

Successfully transmitted colors on the M0.

Changed in this revision

--- a/PololuLedStrip.cpp	Fri Mar 01 02:05:21 2013 +0000
+++ b/PololuLedStrip.cpp	Fri Mar 01 03:57:49 2013 +0000
@@ -10,7 +10,7 @@
     int f_mhz = SystemCoreClock / 1000000;
     
     // Arrange for a 700 nanosecond delay between the rise time and the fall time for a 0 bit.
-    led_strip_write_delays[0] = 700*f_mhz/1000 - 25;
+    led_strip_write_delays[0] = 700*f_mhz/1000 - 25 - 5;
     
     // Arrange for a 600 nanosecond delay between the fall time for a 0 bit and the fall time for a 1 bit.
     // This means the pulses representing a 1 will be 700+600 = 1300 nanoseconds.
@@ -34,8 +34,9 @@
 
     while(count--)
     {
-        led_strip_write_color(colors++, gpio.reg_set, gpio.reg_clr, gpio.mask);
-     
+        led_strip_write_color(colors, gpio.reg_set, gpio.reg_clr, gpio.mask);
+        colors++;
+         
         if (interruptFriendly)
         {
             __enable_irq();
@@ -48,4 +49,8 @@
         
     __enable_irq();   // Re-enable interrupts now that we are done.
     wait_us(24);      // Hold the line low for 24 microseconds to send the reset signal.
+    
+    //*(gpio.reg_set) = gpio.mask;
+    //*(gpio.reg_clr) = gpio.mask;
+
 }
\ No newline at end of file

--- a/led_strip_write_color.s	Fri Mar 01 02:05:21 2013 +0000
+++ b/led_strip_write_color.s	Fri Mar 01 03:57:49 2013 +0000
@@ -6,9 +6,9 @@
     delay $id
     ldr r5, =led_strip_write_delays
     ldrb r5, [r5, $id]
-    lsl r5, r5, #1
+    lsls r5, r5, #1
     ldr r4, =delay_region_end
-    sub r4, r4, r5
+    subs r4, r4, r5
     blx r4
     MEND
 
@@ -26,34 +26,58 @@
     ;   R7:  the number of bits we still need to send
     ;   R13: Link Register, holds return addresses.
 
-    push {r4, r5, r6, r7, lr}  ; Push those registers so we can restore them later.
+    ; Push those registers so we can restore them later.
+    push {r4, r5, r6, r7}
+    mov r4, lr
+    push {r4}
     
-    ldr r6, [r0]       ; Read the color.  Now we have:     xxBbGgRr
-    rbit r6, r6        ; Reverse the order of the bits:    rRgGbBxx
-    rev r6, r6         ; Reverse the order of the bytes:   xxbBgGrR
-    mov r7, #24        ; Initialize the loop counter register.
+    ldrb r4, [r0, #0]  ; Load red.
+    lsls r4, r4, #24
+    mov r6, r4         ; Put red in MSB of r6.
+    ldrb r4, [r0, #1]  ; Load green.
+    lsls r4, r4, #16
+    orrs r6, r6, r4        ; Put green in r6.
+    ldrb r4, [r0, #2]  ; Load blue.
+    lsls r4, r4, #8
+    orrs r6, r6, r4        ; Put blue in MSB of r6.
+   
+    ; On the Cortex M0 we simply did:
+    ;    ldr r6, [r0]       ; Read the color.  Now we have:     xxBbGgRr
+    ;    rbit r6, r6        ; Reverse the order of the bits:    rRgGbBxx
+    ;    rev r6, r6         ; Reverse the order of the bytes:   xxbBgGrR
+    ; and then we used rrxs for shifting to the right through carry.
+    
+    ldr r7, =24        ; Initialize the loop counter register.
     
 send_led_strip_bit
     str r3, [r1]       ; Drive the line high.
-    rrxs r6, r6        ; Rotate right through carry.
     
     delay #0
     
-    it cc              ; If the bit to send it 0...
-    strcc r3, [r2]     ; Drive the line low.
+    ldr r4, =0x80000000
+    tst r6, r4
+    bne delay1
+    str r3, [r2]     ; If the bit to send it 0, drive the line low.
+delay1
 
     delay #1
 
-    it cs              ; If the bit to send is 1...
-    strcs r3, [r2]     ; Drive the line low.
+    ldr r4, =0x80000000
+    tst r6, r4
+    beq delay2
+    str r3, [r2]     ; If the bit to send is 1, drive the line low.
+delay2
     
     delay #2
     
+    lsls r6, r6, #1           ; Shift color bits.
     subs r7, r7, #1           ; Decrement the loop counter.
     bne send_led_strip_bit    ; Send another bit if we have not reached zero.
     
 led_strip_asm_end
-    pop {r4, r5, r6, r7, lr}
+    pop {r4}
+    mov lr, r4
+    pop {r4, r5, r6, r7}
     bx lr