fork of library for MAX14661 16:2 mux
Fork of max14661 by
max14661.h@12:f14ce75c0661, 2016-03-29 (annotated)
- Committer:
- j3
- Date:
- Tue Mar 29 00:58:54 2016 +0000
- Revision:
- 12:f14ce75c0661
- Parent:
- 11:d3971b4fbdd8
removed inheritance of I2C class and used private member var instead
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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j3 | 0:c770ad7363c8 | 1 | /******************************************************************//** |
j3 | 8:44257d87fa9e | 2 | * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. |
j3 | 0:c770ad7363c8 | 3 | * |
j3 | 0:c770ad7363c8 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
j3 | 0:c770ad7363c8 | 5 | * copy of this software and associated documentation files (the "Software"), |
j3 | 0:c770ad7363c8 | 6 | * to deal in the Software without restriction, including without limitation |
j3 | 0:c770ad7363c8 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
j3 | 0:c770ad7363c8 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
j3 | 0:c770ad7363c8 | 9 | * Software is furnished to do so, subject to the following conditions: |
j3 | 0:c770ad7363c8 | 10 | * |
j3 | 0:c770ad7363c8 | 11 | * The above copyright notice and this permission notice shall be included |
j3 | 0:c770ad7363c8 | 12 | * in all copies or substantial portions of the Software. |
j3 | 0:c770ad7363c8 | 13 | * |
j3 | 0:c770ad7363c8 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
j3 | 0:c770ad7363c8 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
j3 | 0:c770ad7363c8 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
j3 | 0:c770ad7363c8 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
j3 | 0:c770ad7363c8 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
j3 | 0:c770ad7363c8 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
j3 | 0:c770ad7363c8 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
j3 | 0:c770ad7363c8 | 21 | * |
j3 | 0:c770ad7363c8 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
j3 | 0:c770ad7363c8 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
j3 | 0:c770ad7363c8 | 24 | * Products, Inc. Branding Policy. |
j3 | 0:c770ad7363c8 | 25 | * |
j3 | 0:c770ad7363c8 | 26 | * The mere transfer of this software does not imply any licenses |
j3 | 0:c770ad7363c8 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
j3 | 0:c770ad7363c8 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
j3 | 0:c770ad7363c8 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
j3 | 0:c770ad7363c8 | 30 | * ownership rights. |
j3 | 0:c770ad7363c8 | 31 | **********************************************************************/ |
j3 | 0:c770ad7363c8 | 32 | |
j3 | 0:c770ad7363c8 | 33 | |
j3 | 0:c770ad7363c8 | 34 | #ifndef MAX14661_H |
j3 | 0:c770ad7363c8 | 35 | #define MAX14661_H |
j3 | 0:c770ad7363c8 | 36 | |
j3 | 0:c770ad7363c8 | 37 | |
j3 | 0:c770ad7363c8 | 38 | #include "mbed.h" |
j3 | 0:c770ad7363c8 | 39 | |
j3 | 0:c770ad7363c8 | 40 | |
j3 | 10:ccbe1afdab31 | 41 | class Max14661 |
j3 | 0:c770ad7363c8 | 42 | { |
j3 | 0:c770ad7363c8 | 43 | public: |
j3 | 9:27cfbbce3094 | 44 | |
j3 | 12:f14ce75c0661 | 45 | /** |
j3 | 12:f14ce75c0661 | 46 | * max14661_i2c_adrs_t - enumerated MAX14661 I2C Addresses |
j3 | 12:f14ce75c0661 | 47 | */ |
j3 | 12:f14ce75c0661 | 48 | typedef enum |
j3 | 12:f14ce75c0661 | 49 | { |
j3 | 12:f14ce75c0661 | 50 | MAX14661_I2C_ADRS0 = 0x4C, |
j3 | 12:f14ce75c0661 | 51 | MAX14661_I2C_ADRS1, |
j3 | 12:f14ce75c0661 | 52 | MAX14661_I2C_ADRS2, |
j3 | 12:f14ce75c0661 | 53 | MAX14661_I2C_ADRS3 |
j3 | 12:f14ce75c0661 | 54 | }max14661_i2c_adrs_t; |
j3 | 12:f14ce75c0661 | 55 | |
j3 | 12:f14ce75c0661 | 56 | |
j3 | 12:f14ce75c0661 | 57 | /** |
j3 | 12:f14ce75c0661 | 58 | * max14661_regs_t - enumerated MAX14661 register addresses |
j3 | 12:f14ce75c0661 | 59 | */ |
j3 | 12:f14ce75c0661 | 60 | typedef enum |
j3 | 12:f14ce75c0661 | 61 | { |
j3 | 12:f14ce75c0661 | 62 | DIR0, //Switches 8A–1A direct read/write access |
j3 | 12:f14ce75c0661 | 63 | DIR1, //Switches 16A–9A direct read/write access |
j3 | 12:f14ce75c0661 | 64 | DIR2, //Switches 8B–1B direct read/write access |
j3 | 12:f14ce75c0661 | 65 | DIR3, //Switches 16B–9B direct read/write access |
j3 | 12:f14ce75c0661 | 66 | SHDW0 = 0x10, //Switches 8A–1A shadow read/write access |
j3 | 12:f14ce75c0661 | 67 | SHDW1, //Switches 16A–9A shadow read/write access |
j3 | 12:f14ce75c0661 | 68 | SHDW2, //Switches 8B–1B shadow read/write access |
j3 | 12:f14ce75c0661 | 69 | SHDW3, //Switches 16B–9B shadow read/write access |
j3 | 12:f14ce75c0661 | 70 | CMD_A, //Set mux A command (reads 0x00) |
j3 | 12:f14ce75c0661 | 71 | CMD_B //Set mux B command (reads 0x00) |
j3 | 12:f14ce75c0661 | 72 | }max14661_regs_t; |
j3 | 12:f14ce75c0661 | 73 | |
j3 | 12:f14ce75c0661 | 74 | |
j3 | 12:f14ce75c0661 | 75 | /** |
j3 | 12:f14ce75c0661 | 76 | * max14661_cmds_t - enumerated MAX14661 commands |
j3 | 12:f14ce75c0661 | 77 | */ |
j3 | 12:f14ce75c0661 | 78 | typedef enum |
j3 | 12:f14ce75c0661 | 79 | { |
j3 | 12:f14ce75c0661 | 80 | ENABLE_SW01, //enables sw1 on bank only |
j3 | 12:f14ce75c0661 | 81 | ENABLE_SW02, //enables sw2 on bank only |
j3 | 12:f14ce75c0661 | 82 | ENABLE_SW03, //enables sw3 on bank only |
j3 | 12:f14ce75c0661 | 83 | ENABLE_SW04, //enables sw4 on bank only |
j3 | 12:f14ce75c0661 | 84 | ENABLE_SW05, //enables sw5 on bank only |
j3 | 12:f14ce75c0661 | 85 | ENABLE_SW06, //enables sw6 on bank only |
j3 | 12:f14ce75c0661 | 86 | ENABLE_SW07, //enables sw7 on bank only |
j3 | 12:f14ce75c0661 | 87 | ENABLE_SW08, //enables sw8 on bank only |
j3 | 12:f14ce75c0661 | 88 | ENABLE_SW09, //enables sw9 on bank only |
j3 | 12:f14ce75c0661 | 89 | ENABLE_SW10, //enables sw10 on bank only |
j3 | 12:f14ce75c0661 | 90 | ENABLE_SW11, //enables sw11 on bank only |
j3 | 12:f14ce75c0661 | 91 | ENABLE_SW12, //enables sw12 on bank only |
j3 | 12:f14ce75c0661 | 92 | ENABLE_SW13, //enables sw13 on bank only |
j3 | 12:f14ce75c0661 | 93 | ENABLE_SW14, //enables sw14 on bank only |
j3 | 12:f14ce75c0661 | 94 | ENABLE_SW15, //enables sw15 on bank only |
j3 | 12:f14ce75c0661 | 95 | ENABLE_SW16, //enables sw16 on bank only |
j3 | 12:f14ce75c0661 | 96 | DISABLE_BANK, //opens all switches on bank |
j3 | 12:f14ce75c0661 | 97 | COPY_SHADOW, //copies both shadow registers for bank |
j3 | 12:f14ce75c0661 | 98 | NO_CHANGE, |
j3 | 12:f14ce75c0661 | 99 | }max14661_cmds_t; |
j3 | 12:f14ce75c0661 | 100 | |
j3 | 12:f14ce75c0661 | 101 | |
j3 | 12:f14ce75c0661 | 102 | /** |
j3 | 12:f14ce75c0661 | 103 | * max14661_sw_t - enumerated MAX14661 switch bitmasks |
j3 | 12:f14ce75c0661 | 104 | */ |
j3 | 12:f14ce75c0661 | 105 | typedef enum |
j3 | 12:f14ce75c0661 | 106 | { |
j3 | 12:f14ce75c0661 | 107 | SW01 = (1 << 0), |
j3 | 12:f14ce75c0661 | 108 | SW02 = (1 << 1), |
j3 | 12:f14ce75c0661 | 109 | SW03 = (1 << 2), |
j3 | 12:f14ce75c0661 | 110 | SW04 = (1 << 3), |
j3 | 12:f14ce75c0661 | 111 | SW05 = (1 << 4), |
j3 | 12:f14ce75c0661 | 112 | SW06 = (1 << 5), |
j3 | 12:f14ce75c0661 | 113 | SW07 = (1 << 6), |
j3 | 12:f14ce75c0661 | 114 | SW08 = (1 << 7), |
j3 | 12:f14ce75c0661 | 115 | SW09 = (1 << 8), |
j3 | 12:f14ce75c0661 | 116 | SW10 = (1 << 9), |
j3 | 12:f14ce75c0661 | 117 | SW11 = (1 << 10), |
j3 | 12:f14ce75c0661 | 118 | SW12 = (1 << 11), |
j3 | 12:f14ce75c0661 | 119 | SW13 = (1 << 12), |
j3 | 12:f14ce75c0661 | 120 | SW14 = (1 << 13), |
j3 | 12:f14ce75c0661 | 121 | SW15 = (1 << 14), |
j3 | 12:f14ce75c0661 | 122 | SW16 = (1 << 15) |
j3 | 12:f14ce75c0661 | 123 | }max14661_sw_t; |
j3 | 12:f14ce75c0661 | 124 | |
j3 | 12:f14ce75c0661 | 125 | |
j3 | 12:f14ce75c0661 | 126 | /**********************************************************//** |
j3 | 12:f14ce75c0661 | 127 | * Constructor for Max14661 Class |
j3 | 12:f14ce75c0661 | 128 | * |
j3 | 12:f14ce75c0661 | 129 | * On Entry: |
j3 | 12:f14ce75c0661 | 130 | * @param[in] sda - sda pin of I2C bus |
j3 | 12:f14ce75c0661 | 131 | * @param[in] scl - scl pin of I2C bus |
j3 | 12:f14ce75c0661 | 132 | * @param[in] i2c_adrs - 7-bit slave address of MAX14661 |
j3 | 12:f14ce75c0661 | 133 | * |
j3 | 12:f14ce75c0661 | 134 | * On Exit: |
j3 | 12:f14ce75c0661 | 135 | * @return none |
j3 | 12:f14ce75c0661 | 136 | * |
j3 | 12:f14ce75c0661 | 137 | * Example: |
j3 | 12:f14ce75c0661 | 138 | * @code |
j3 | 12:f14ce75c0661 | 139 | * |
j3 | 12:f14ce75c0661 | 140 | * //declare mux object |
j3 | 12:f14ce75c0661 | 141 | * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0); |
j3 | 12:f14ce75c0661 | 142 | * |
j3 | 12:f14ce75c0661 | 143 | * @endcode |
j3 | 12:f14ce75c0661 | 144 | **************************************************************/ |
j3 | 12:f14ce75c0661 | 145 | Max14661(PinName sda, PinName scl, max14661_i2c_adrs_t i2c_adrs); |
j3 | 12:f14ce75c0661 | 146 | |
j3 | 12:f14ce75c0661 | 147 | |
j3 | 12:f14ce75c0661 | 148 | Max14661(I2C & i2c_bus, max14661_i2c_adrs_t i2c_adrs); |
j3 | 12:f14ce75c0661 | 149 | |
j3 | 12:f14ce75c0661 | 150 | |
j3 | 12:f14ce75c0661 | 151 | ~Max14661(); |
j3 | 12:f14ce75c0661 | 152 | |
j3 | 4:45fa0192f66d | 153 | |
j3 | 12:f14ce75c0661 | 154 | /******************************************************************//** |
j3 | 12:f14ce75c0661 | 155 | * Writes given commands to CMD_A and CMD_B |
j3 | 12:f14ce75c0661 | 156 | * |
j3 | 12:f14ce75c0661 | 157 | * On Entry: |
j3 | 12:f14ce75c0661 | 158 | * @param[in] cmdA - command for CMD_A |
j3 | 12:f14ce75c0661 | 159 | * @param[in] cmdB - command for CMD_B |
j3 | 12:f14ce75c0661 | 160 | * |
j3 | 12:f14ce75c0661 | 161 | * On Exit: |
j3 | 12:f14ce75c0661 | 162 | * @return return value = 0 on success, non-0 on failure |
j3 | 12:f14ce75c0661 | 163 | * |
j3 | 12:f14ce75c0661 | 164 | * Example: |
j3 | 12:f14ce75c0661 | 165 | * @code |
j3 | 12:f14ce75c0661 | 166 | * |
j3 | 12:f14ce75c0661 | 167 | * //declare mux object |
j3 | 12:f14ce75c0661 | 168 | * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0); |
j3 | 12:f14ce75c0661 | 169 | * |
j3 | 12:f14ce75c0661 | 170 | * uint16_t rtn_val; |
j3 | 12:f14ce75c0661 | 171 | * |
j3 | 12:f14ce75c0661 | 172 | * rtn_val = mux.wrt_cmd_registers(DISABLE_BANK, DISABLE_BANK); |
j3 | 12:f14ce75c0661 | 173 | * |
j3 | 12:f14ce75c0661 | 174 | * @endcode |
j3 | 12:f14ce75c0661 | 175 | **********************************************************************/ |
j3 | 12:f14ce75c0661 | 176 | uint16_t wrt_cmd_registers(max14661_cmds_t cmdA, max14661_cmds_t cmdB); |
j3 | 4:45fa0192f66d | 177 | |
j3 | 4:45fa0192f66d | 178 | |
j3 | 12:f14ce75c0661 | 179 | /******************************************************************//** |
j3 | 12:f14ce75c0661 | 180 | * Writes bankA and bankB to coresponding shadow registers |
j3 | 12:f14ce75c0661 | 181 | * |
j3 | 12:f14ce75c0661 | 182 | * On Entry: |
j3 | 12:f14ce75c0661 | 183 | * @param[in] bankA - binary representation of switch states |
j3 | 12:f14ce75c0661 | 184 | * @param[in] bankB - binary representation of switch states |
j3 | 12:f14ce75c0661 | 185 | * |
j3 | 12:f14ce75c0661 | 186 | * On Exit: |
j3 | 12:f14ce75c0661 | 187 | * @return return value = 0 on success, non-0 on failure |
j3 | 12:f14ce75c0661 | 188 | * |
j3 | 12:f14ce75c0661 | 189 | * Example: |
j3 | 12:f14ce75c0661 | 190 | * @code |
j3 | 12:f14ce75c0661 | 191 | * |
j3 | 12:f14ce75c0661 | 192 | * //declare mux object |
j3 | 12:f14ce75c0661 | 193 | * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0); |
j3 | 12:f14ce75c0661 | 194 | * |
j3 | 12:f14ce75c0661 | 195 | * uint16_t bankA = (SW12 | SW02); //example only |
j3 | 12:f14ce75c0661 | 196 | * uint16_t bankB = (SW11 | SW01); |
j3 | 12:f14ce75c0661 | 197 | * uint16_t rtn_val; |
j3 | 12:f14ce75c0661 | 198 | * |
j3 | 12:f14ce75c0661 | 199 | * //wite shadow registers |
j3 | 12:f14ce75c0661 | 200 | * rtn_val = mux.wrt_shadow_registers(bankA, bankB); |
j3 | 12:f14ce75c0661 | 201 | * |
j3 | 12:f14ce75c0661 | 202 | * @endcode |
j3 | 12:f14ce75c0661 | 203 | **********************************************************************/ |
j3 | 12:f14ce75c0661 | 204 | uint16_t wrt_shadow_registers(uint16_t bankA, uint16_t bankB); |
j3 | 4:45fa0192f66d | 205 | |
j3 | 4:45fa0192f66d | 206 | |
j3 | 12:f14ce75c0661 | 207 | /******************************************************************//** |
j3 | 12:f14ce75c0661 | 208 | * Writes bankA and bankB to coresponding direct access registers |
j3 | 12:f14ce75c0661 | 209 | * |
j3 | 12:f14ce75c0661 | 210 | * On Entry: |
j3 | 12:f14ce75c0661 | 211 | * @param[in] bankA - binary representation of switch states |
j3 | 12:f14ce75c0661 | 212 | * @param[in] bankB - binary representation of switch states |
j3 | 12:f14ce75c0661 | 213 | * |
j3 | 12:f14ce75c0661 | 214 | * On Exit: |
j3 | 12:f14ce75c0661 | 215 | * @return return value = 0 on success, non-0 on failure |
j3 | 12:f14ce75c0661 | 216 | * |
j3 | 12:f14ce75c0661 | 217 | * Example: |
j3 | 12:f14ce75c0661 | 218 | * @code |
j3 | 12:f14ce75c0661 | 219 | * |
j3 | 12:f14ce75c0661 | 220 | * //declare mux object |
j3 | 12:f14ce75c0661 | 221 | * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0); |
j3 | 12:f14ce75c0661 | 222 | * |
j3 | 12:f14ce75c0661 | 223 | * uint16_t bankA = (SW12 | SW02); //example only |
j3 | 12:f14ce75c0661 | 224 | * uint16_t bankB = (SW11 | SW01); |
j3 | 12:f14ce75c0661 | 225 | * uint16_t rtn_val; |
j3 | 12:f14ce75c0661 | 226 | * |
j3 | 12:f14ce75c0661 | 227 | * //wite shadow registers |
j3 | 12:f14ce75c0661 | 228 | * rtn_val = mux.wrt_dir_registers(bankA, bankB); |
j3 | 12:f14ce75c0661 | 229 | * |
j3 | 12:f14ce75c0661 | 230 | * @endcode |
j3 | 12:f14ce75c0661 | 231 | **********************************************************************/ |
j3 | 12:f14ce75c0661 | 232 | uint16_t wrt_dir_registers(uint16_t bankA, uint16_t bankB); |
j3 | 4:45fa0192f66d | 233 | |
j3 | 4:45fa0192f66d | 234 | |
j3 | 12:f14ce75c0661 | 235 | /******************************************************************//** |
j3 | 12:f14ce75c0661 | 236 | * Writes bankA and bankB to coresponding shadow register and then |
j3 | 12:f14ce75c0661 | 237 | * issues copy command for both banks |
j3 | 12:f14ce75c0661 | 238 | * |
j3 | 12:f14ce75c0661 | 239 | * On Entry: |
j3 | 12:f14ce75c0661 | 240 | * @param[in] bankA - binary representation of switch states |
j3 | 12:f14ce75c0661 | 241 | * @param[in] bankB - binary representation of switch states |
j3 | 12:f14ce75c0661 | 242 | * |
j3 | 12:f14ce75c0661 | 243 | * On Exit: |
j3 | 12:f14ce75c0661 | 244 | * @return return value = 0 on success, non-0 on failure |
j3 | 12:f14ce75c0661 | 245 | * |
j3 | 12:f14ce75c0661 | 246 | * Example: |
j3 | 12:f14ce75c0661 | 247 | * @code |
j3 | 12:f14ce75c0661 | 248 | * |
j3 | 12:f14ce75c0661 | 249 | * //declare mux object |
j3 | 12:f14ce75c0661 | 250 | * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0); |
j3 | 12:f14ce75c0661 | 251 | * |
j3 | 12:f14ce75c0661 | 252 | * uint16_t bankA = (SW12 | SW02); //example only |
j3 | 12:f14ce75c0661 | 253 | * uint16_t bankB = (SW11 | SW01); |
j3 | 12:f14ce75c0661 | 254 | * uint16_t rtn_val; |
j3 | 12:f14ce75c0661 | 255 | * |
j3 | 12:f14ce75c0661 | 256 | * //wite shadow registers |
j3 | 12:f14ce75c0661 | 257 | * rtn_val = mux.set_switches(bankA, bankB); |
j3 | 12:f14ce75c0661 | 258 | * |
j3 | 12:f14ce75c0661 | 259 | * @endcode |
j3 | 12:f14ce75c0661 | 260 | **********************************************************************/ |
j3 | 12:f14ce75c0661 | 261 | uint16_t set_switches(uint16_t bankA, uint16_t bankB); |
j3 | 4:45fa0192f66d | 262 | |
j3 | 4:45fa0192f66d | 263 | |
j3 | 12:f14ce75c0661 | 264 | /**********************************************************//** |
j3 | 12:f14ce75c0661 | 265 | * Reads data from direct access registers starting at DIR0 and |
j3 | 12:f14ce75c0661 | 266 | * stores it in byte array pointed at by 'data' |
j3 | 12:f14ce75c0661 | 267 | * |
j3 | 12:f14ce75c0661 | 268 | * On Entry: |
j3 | 12:f14ce75c0661 | 269 | * @param[in] data - pointer to byte array for storing data |
j3 | 12:f14ce75c0661 | 270 | * |
j3 | 12:f14ce75c0661 | 271 | * On Exit: |
j3 | 12:f14ce75c0661 | 272 | * @param[out] data - data buffer now contains data read |
j3 | 12:f14ce75c0661 | 273 | * from dir registers |
j3 | 12:f14ce75c0661 | 274 | * @return return value = 0 on success, non-0 on failure |
j3 | 12:f14ce75c0661 | 275 | * |
j3 | 12:f14ce75c0661 | 276 | * Example: |
j3 | 12:f14ce75c0661 | 277 | * @code |
j3 | 12:f14ce75c0661 | 278 | * |
j3 | 12:f14ce75c0661 | 279 | * //declare mux object |
j3 | 12:f14ce75c0661 | 280 | * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0); |
j3 | 12:f14ce75c0661 | 281 | * |
j3 | 12:f14ce75c0661 | 282 | * uint16_t rtn_val; |
j3 | 12:f14ce75c0661 | 283 | * uint8_t data[4]; |
j3 | 12:f14ce75c0661 | 284 | * |
j3 | 12:f14ce75c0661 | 285 | * //read direct access registers |
j3 | 12:f14ce75c0661 | 286 | * rtn_val = mux.rd_dir_registers(data); |
j3 | 12:f14ce75c0661 | 287 | * |
j3 | 12:f14ce75c0661 | 288 | * @endcode |
j3 | 12:f14ce75c0661 | 289 | **********************************************************************/ |
j3 | 12:f14ce75c0661 | 290 | uint16_t rd_dir_registers(uint8_t* data); |
j3 | 4:45fa0192f66d | 291 | |
j3 | 4:45fa0192f66d | 292 | |
j3 | 12:f14ce75c0661 | 293 | /**********************************************************//** |
j3 | 12:f14ce75c0661 | 294 | * Reads data from shadow registers starting at SHDW0 and stores |
j3 | 12:f14ce75c0661 | 295 | * it in byte array pointed at by 'data' |
j3 | 12:f14ce75c0661 | 296 | * |
j3 | 12:f14ce75c0661 | 297 | * On Entry: |
j3 | 12:f14ce75c0661 | 298 | * @param[in] data - pointer to byte array for storing data |
j3 | 12:f14ce75c0661 | 299 | * |
j3 | 12:f14ce75c0661 | 300 | * On Exit: |
j3 | 12:f14ce75c0661 | 301 | * @param[out] data - data buffer now contains data read |
j3 | 12:f14ce75c0661 | 302 | * from shadow registers |
j3 | 12:f14ce75c0661 | 303 | * @return return value = 0 on success, non-0 on failure |
j3 | 12:f14ce75c0661 | 304 | * |
j3 | 12:f14ce75c0661 | 305 | * Example: |
j3 | 12:f14ce75c0661 | 306 | * @code |
j3 | 12:f14ce75c0661 | 307 | * |
j3 | 12:f14ce75c0661 | 308 | * //declare mux object |
j3 | 12:f14ce75c0661 | 309 | * Max14661 mux(D14, D15, MAX14661_I2C_ADRS0); |
j3 | 12:f14ce75c0661 | 310 | * |
j3 | 12:f14ce75c0661 | 311 | * uint16_t rtn_val; |
j3 | 12:f14ce75c0661 | 312 | * uint8_t data[4]; |
j3 | 12:f14ce75c0661 | 313 | * |
j3 | 12:f14ce75c0661 | 314 | * //read shadow registers |
j3 | 12:f14ce75c0661 | 315 | * rtn_val = mux.rd_shadow_registers(data); |
j3 | 12:f14ce75c0661 | 316 | * |
j3 | 12:f14ce75c0661 | 317 | * @endcode |
j3 | 12:f14ce75c0661 | 318 | **************************************************************/ |
j3 | 12:f14ce75c0661 | 319 | uint16_t rd_shadow_registers(uint8_t* data); |
j3 | 12:f14ce75c0661 | 320 | |
j3 | 12:f14ce75c0661 | 321 | private: |
j3 | 12:f14ce75c0661 | 322 | |
j3 | 12:f14ce75c0661 | 323 | I2C * _i2c; |
j3 | 12:f14ce75c0661 | 324 | bool _i2c_owner; |
j3 | 12:f14ce75c0661 | 325 | uint8_t _w_adrs, _r_adrs; |
j3 | 0:c770ad7363c8 | 326 | }; |
j3 | 0:c770ad7363c8 | 327 | |
j3 | 0:c770ad7363c8 | 328 | |
j3 | 0:c770ad7363c8 | 329 | #endif /* MAX14661_H*/ |