Justin Jordan / ard2pmod

Fork of Library for MAXREFDES72# that supports configuration of shield for different PMOD types and the DS3231 RTC

Dependencies:   ds3231 max14661

Dependents:   ard2pmod_demo

Fork of ard2pmod by Maxim Integrated

ard2pmod.cpp@18:6d82914432e2, 2016-04-25 (annotated)

Committer:
j3
Date:
Mon Apr 25 17:26:53 2016 +0000
Revision:
18:6d82914432e2
Parent:
17:294c52822d28 
added OneWire support to ard2pmod

Who changed what in which revision?

UserRevisionLine numberNew contents of line
j3 0:bb62cd328247 1 /******************************************************************//**
j3 15:014ab2d734e0 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
j3 0:bb62cd328247 3 *
j3 0:bb62cd328247 4 * Permission is hereby granted, free of charge, to any person obtaining a
j3 0:bb62cd328247 5 * copy of this software and associated documentation files (the "Software"),
j3 0:bb62cd328247 6 * to deal in the Software without restriction, including without limitation
j3 0:bb62cd328247 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
j3 0:bb62cd328247 8 * and/or sell copies of the Software, and to permit persons to whom the
j3 0:bb62cd328247 9 * Software is furnished to do so, subject to the following conditions:
j3 0:bb62cd328247 10 *
j3 0:bb62cd328247 11 * The above copyright notice and this permission notice shall be included
j3 0:bb62cd328247 12 * in all copies or substantial portions of the Software.
j3 0:bb62cd328247 13 *
j3 0:bb62cd328247 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
j3 0:bb62cd328247 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
j3 0:bb62cd328247 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
j3 0:bb62cd328247 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
j3 0:bb62cd328247 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
j3 0:bb62cd328247 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
j3 0:bb62cd328247 20 * OTHER DEALINGS IN THE SOFTWARE.
j3 0:bb62cd328247 21 *
j3 0:bb62cd328247 22 * Except as contained in this notice, the name of Maxim Integrated
j3 0:bb62cd328247 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
j3 0:bb62cd328247 24 * Products, Inc. Branding Policy.
j3 0:bb62cd328247 25 *
j3 0:bb62cd328247 26 * The mere transfer of this software does not imply any licenses
j3 0:bb62cd328247 27 * of trade secrets, proprietary technology, copyrights, patents,
j3 0:bb62cd328247 28 * trademarks, maskwork rights, or any other form of intellectual
j3 0:bb62cd328247 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
j3 0:bb62cd328247 30 * ownership rights.
j3 0:bb62cd328247 31 **********************************************************************/
j3 0:bb62cd328247 32
j3 0:bb62cd328247 33
j3 0:bb62cd328247 34 #include "ard2pmod.h"
j3 0:bb62cd328247 35
j3 0:bb62cd328247 36
j3 17:294c52822d28 37 //*********************************************************************
j3 18:6d82914432e2 38 Ard2Pmod::Ard2Pmod(PmodType pmod_type, PinName ow_pin):
j3 17:294c52822d28 39 _mux(D14, D15, Max14661::MAX14661_I2C_ADRS0)
j3 0:bb62cd328247 40 {
j3 0:bb62cd328247 41 switch(pmod_type)
j3 0:bb62cd328247 42 {
j3 3:64d54fa4dd3c 43 case PMOD_TYPE_I2C_A:
j3 17:294c52822d28 44 _mux.set_switches((Max14661::SW12 | Max14661::SW09), (Max14661::SW11 | Max14661::SW10));
j3 18:6d82914432e2 45 break;
j3 3:64d54fa4dd3c 46
j3 3:64d54fa4dd3c 47 case PMOD_TYPE_I2C_B:
j3 17:294c52822d28 48 _mux.set_switches((Max14661::SW09 | Max14661::SW07), (Max14661::SW10 | Max14661::SW08));
j3 18:6d82914432e2 49 break;
j3 3:64d54fa4dd3c 50
j3 3:64d54fa4dd3c 51 case PMOD_TYPE_I2C_AB:
j3 17:294c52822d28 52 _mux.set_switches((Max14661::SW12 | Max14661::SW09 | Max14661::SW07), (Max14661::SW11 | Max14661::SW10 | Max14661::SW08));
j3 18:6d82914432e2 53 break;
j3 0:bb62cd328247 54
j3 0:bb62cd328247 55 case PMOD_TYPE_1_GPIO:
j3 17:294c52822d28 56 _mux.wrt_cmd_registers(Max14661::DISABLE_BANK, Max14661::DISABLE_BANK);
j3 18:6d82914432e2 57 break;
j3 0:bb62cd328247 58
j3 0:bb62cd328247 59 case PMOD_TYPE_2_SPI:
j3 17:294c52822d28 60 _mux.wrt_cmd_registers(Max14661::DISABLE_BANK, Max14661::DISABLE_BANK);
j3 18:6d82914432e2 61 break;
j3 0:bb62cd328247 62
j3 0:bb62cd328247 63 case PMOD_TYPE_3_UART:
j3 17:294c52822d28 64 _mux.set_switches((Max14661::SW12 | Max14661::SW01), (Max14661::SW11 | Max14661::SW02));
j3 18:6d82914432e2 65 break;
j3 0:bb62cd328247 66
j3 0:bb62cd328247 67 case PMOD_TYPE_4_UART:
j3 17:294c52822d28 68 _mux.set_switches((Max14661::SW13 | Max14661::SW02), (Max14661::SW12 | Max14661::SW01));
j3 0:bb62cd328247 69 break;
j3 0:bb62cd328247 70
j3 0:bb62cd328247 71 case PMOD_TYPE_5_HBRIDGE:
j3 17:294c52822d28 72 _mux.wrt_cmd_registers(Max14661::DISABLE_BANK, Max14661::DISABLE_BANK);
j3 18:6d82914432e2 73 break;
j3 0:bb62cd328247 74
j3 0:bb62cd328247 75 case PMOD_TYPE_6_HBRIDGE:
j3 17:294c52822d28 76 _mux.wrt_cmd_registers(Max14661::DISABLE_BANK, Max14661::DISABLE_BANK);
j3 18:6d82914432e2 77 break;
j3 18:6d82914432e2 78
j3 18:6d82914432e2 79 case PMOD_TYPE_7_ONEWIRE_A:
j3 18:6d82914432e2 80
j3 18:6d82914432e2 81 //set switches for owm_A
j3 18:6d82914432e2 82 switch(ow_pin)
j3 18:6d82914432e2 83 {
j3 18:6d82914432e2 84 case D0:
j3 18:6d82914432e2 85 _mux.set_switches((Max14661::SW01 | Max14661::SW11), 0);
j3 18:6d82914432e2 86 break;
j3 18:6d82914432e2 87
j3 18:6d82914432e2 88 case D1:
j3 18:6d82914432e2 89 _mux.set_switches((Max14661::SW02 | Max14661::SW11), 0);
j3 18:6d82914432e2 90 break;
j3 18:6d82914432e2 91
j3 18:6d82914432e2 92 case D2:
j3 18:6d82914432e2 93 _mux.set_switches((Max14661::SW03 | Max14661::SW11), 0);
j3 18:6d82914432e2 94 break;
j3 18:6d82914432e2 95
j3 18:6d82914432e2 96 case D3:
j3 18:6d82914432e2 97 _mux.set_switches((Max14661::SW04 | Max14661::SW11), 0);
j3 18:6d82914432e2 98 break;
j3 18:6d82914432e2 99
j3 18:6d82914432e2 100 case D4:
j3 18:6d82914432e2 101 _mux.set_switches((Max14661::SW05 | Max14661::SW11), 0);
j3 18:6d82914432e2 102 break;
j3 18:6d82914432e2 103
j3 18:6d82914432e2 104 case D5:
j3 18:6d82914432e2 105 _mux.set_switches((Max14661::SW06 | Max14661::SW11), 0);
j3 18:6d82914432e2 106 break;
j3 18:6d82914432e2 107
j3 18:6d82914432e2 108 case D6:
j3 18:6d82914432e2 109 _mux.set_switches((Max14661::SW07 | Max14661::SW11), 0);
j3 18:6d82914432e2 110 break;
j3 18:6d82914432e2 111
j3 18:6d82914432e2 112 case D7:
j3 18:6d82914432e2 113 _mux.set_switches((Max14661::SW08 | Max14661::SW11), 0);
j3 18:6d82914432e2 114 break;
j3 18:6d82914432e2 115
j3 18:6d82914432e2 116 case D8:
j3 18:6d82914432e2 117 _mux.set_switches((Max14661::SW16 | Max14661::SW11), 0);
j3 18:6d82914432e2 118 break;
j3 18:6d82914432e2 119
j3 18:6d82914432e2 120 case D9:
j3 18:6d82914432e2 121 _mux.set_switches((Max14661::SW15 | Max14661::SW11), 0);
j3 18:6d82914432e2 122 break;
j3 18:6d82914432e2 123
j3 18:6d82914432e2 124 case D10:
j3 18:6d82914432e2 125 _mux.set_switches((Max14661::SW14 | Max14661::SW11), 0);
j3 18:6d82914432e2 126 break;
j3 18:6d82914432e2 127
j3 18:6d82914432e2 128 case D11:
j3 18:6d82914432e2 129 _mux.set_switches((Max14661::SW13 | Max14661::SW11), 0);
j3 18:6d82914432e2 130 break;
j3 18:6d82914432e2 131
j3 18:6d82914432e2 132 case D12:
j3 18:6d82914432e2 133 _mux.set_switches((Max14661::SW12 | Max14661::SW11), 0);
j3 18:6d82914432e2 134 break;
j3 18:6d82914432e2 135
j3 18:6d82914432e2 136 default:
j3 18:6d82914432e2 137 _mux.wrt_cmd_registers(Max14661::DISABLE_BANK, Max14661::DISABLE_BANK);
j3 18:6d82914432e2 138 break;
j3 18:6d82914432e2 139 }
j3 18:6d82914432e2 140
j3 18:6d82914432e2 141 break;
j3 18:6d82914432e2 142
j3 18:6d82914432e2 143 case PMOD_TYPE_8_ONEWIRE_B:
j3 18:6d82914432e2 144
j3 18:6d82914432e2 145 //set switches for owm_B
j3 18:6d82914432e2 146 switch(ow_pin)
j3 18:6d82914432e2 147 {
j3 18:6d82914432e2 148 case D0:
j3 18:6d82914432e2 149 _mux.set_switches(0, (Max14661::SW01 | Max14661::SW08));
j3 18:6d82914432e2 150 break;
j3 18:6d82914432e2 151
j3 18:6d82914432e2 152 case D1:
j3 18:6d82914432e2 153 _mux.set_switches(0, (Max14661::SW02 | Max14661::SW08));
j3 18:6d82914432e2 154 break;
j3 18:6d82914432e2 155
j3 18:6d82914432e2 156 case D2:
j3 18:6d82914432e2 157 _mux.set_switches(0, (Max14661::SW03 | Max14661::SW08));
j3 18:6d82914432e2 158 break;
j3 18:6d82914432e2 159
j3 18:6d82914432e2 160 case D3:
j3 18:6d82914432e2 161 _mux.set_switches(0, (Max14661::SW04 | Max14661::SW08));
j3 18:6d82914432e2 162 break;
j3 18:6d82914432e2 163
j3 18:6d82914432e2 164 case D4:
j3 18:6d82914432e2 165 _mux.set_switches(0, (Max14661::SW05 | Max14661::SW08));
j3 18:6d82914432e2 166 break;
j3 18:6d82914432e2 167
j3 18:6d82914432e2 168 case D5:
j3 18:6d82914432e2 169 _mux.set_switches(0, (Max14661::SW06 | Max14661::SW08));
j3 18:6d82914432e2 170 break;
j3 18:6d82914432e2 171
j3 18:6d82914432e2 172 case D6:
j3 18:6d82914432e2 173 _mux.set_switches(0, (Max14661::SW07 | Max14661::SW08));
j3 18:6d82914432e2 174 break;
j3 18:6d82914432e2 175
j3 18:6d82914432e2 176 case D7:
j3 18:6d82914432e2 177 _mux.wrt_cmd_registers(Max14661::DISABLE_BANK, Max14661::DISABLE_BANK);
j3 18:6d82914432e2 178 break;
j3 18:6d82914432e2 179
j3 18:6d82914432e2 180 case D8:
j3 18:6d82914432e2 181 _mux.set_switches(0, (Max14661::SW16 | Max14661::SW08));
j3 18:6d82914432e2 182 break;
j3 18:6d82914432e2 183
j3 18:6d82914432e2 184 case D9:
j3 18:6d82914432e2 185 _mux.set_switches(0, (Max14661::SW15 | Max14661::SW08));
j3 18:6d82914432e2 186 break;
j3 18:6d82914432e2 187
j3 18:6d82914432e2 188 case D10:
j3 18:6d82914432e2 189 _mux.set_switches(0, (Max14661::SW14 | Max14661::SW08));
j3 18:6d82914432e2 190 break;
j3 18:6d82914432e2 191
j3 18:6d82914432e2 192 case D11:
j3 18:6d82914432e2 193 _mux.set_switches(0, (Max14661::SW13 | Max14661::SW08));
j3 18:6d82914432e2 194 break;
j3 18:6d82914432e2 195
j3 18:6d82914432e2 196 case D12:
j3 18:6d82914432e2 197 _mux.set_switches(0, (Max14661::SW12 | Max14661::SW08));
j3 18:6d82914432e2 198 break;
j3 18:6d82914432e2 199
j3 18:6d82914432e2 200 case D13:
j3 18:6d82914432e2 201 _mux.set_switches(0, (Max14661::SW11 | Max14661::SW08));
j3 18:6d82914432e2 202 break;
j3 18:6d82914432e2 203
j3 18:6d82914432e2 204 default:
j3 18:6d82914432e2 205 _mux.wrt_cmd_registers(Max14661::DISABLE_BANK, Max14661::DISABLE_BANK);
j3 18:6d82914432e2 206 break;
j3 18:6d82914432e2 207 }
j3 18:6d82914432e2 208
j3 18:6d82914432e2 209 break;
j3 0:bb62cd328247 210
j3 0:bb62cd328247 211 default:
j3 17:294c52822d28 212 _mux.wrt_cmd_registers(Max14661::DISABLE_BANK, Max14661::DISABLE_BANK);
j3 18:6d82914432e2 213 break;
j3 17:294c52822d28 214 }
j3 0:bb62cd328247 215 }
j3 0:bb62cd328247 216
j3 0:bb62cd328247 217