SC16IS752.h

00001 #ifndef SC16IS752_H
00002 #define SC16IS752_H
00003 
00004 #include "Stream.h"
00005 
00006 //I2C Slaveaddresses                     A1  A0 
00007 #define SC16IS752_SA0            0x90  /* VDD VDD */
00008 #define SC16IS752_SA1            0x92  /* VDD VSS */
00009 #define SC16IS752_SA2            0x94  /* VDD SCL */
00010 #define SC16IS752_SA3            0x95  /* VDD SDA */
00011 #define SC16IS752_SA4            0x98  /* VSS VDD */
00012 #define SC16IS752_SA5            0x9A  /* VSS VSS */
00013 #define SC16IS752_SA6            0x9C  /* VSS SCL */
00014 #define SC16IS752_SA7            0x9E  /* VSS SDA */
00015 #define SC16IS752_SA8            0xA0  /* SCL VDD */
00016 #define SC16IS752_SA9            0xA2  /* SCL VSS */
00017 #define SC16IS752_SA10           0xA4  /* SCL SCL */
00018 #define SC16IS752_SA11           0xA6  /* SCL SDA */
00019 #define SC16IS752_SA12           0xA8  /* SDA VDD */
00020 #define SC16IS752_SA13           0xAA  /* SDA VSS */
00021 #define SC16IS752_SA14           0xAC  /* SDA SCL */
00022 #define SC16IS752_SA15           0xAE  /* SDA SDA */
00023 
00024 /** See datasheet section 7.8 for configuring the
00025   * "Programmable baud rate generator"
00026   */
00027 #define SC16IS752_XTAL_FREQ                     1843200 /* On-board crystal (New mid-2010 Version) */
00028 #define SC16IS752_PRESCALER_1                   1       /* Default prescaler after reset           */
00029 #define SC16IS752_PRESCALER_4                   4       /* Selectable by setting MCR[7]            */
00030 #define SC16IS752_PRESCALER                     SC16IS752_PRESCALER_1  
00031 #define SC16IS752_BAUDRATE_DIVISOR(baud)        ((SC16IS752_XTAL_FREQ/SC16IS752_PRESCALER)/(baud*16))
00032 
00033 /** See section 8.3 of the datasheet for definitions
00034   * of bits in the FIFO Control Register (FCR)
00035   */
00036 #define FCR_RX_IRQ_60                 (3 << 6)
00037 #define FCR_RX_IRQ_56                 (2 << 6)
00038 #define FCR_RX_IRQ_16                 (1 << 6)
00039 #define FCR_RX_IRQ_8                  (0 << 6)
00040 //TX Level only accessible when EFR[4] is set
00041 #define FCR_TX_IRQ_56                 (3 << 4)
00042 #define FCR_TX_IRQ_32                 (2 << 4)
00043 #define FCR_TX_IRQ_16                 (1 << 4)
00044 #define FCR_TX_IRQ_8                  (0 << 4)
00045 //#define FCR_RESERVED                  (1 << 3)
00046 #define FCR_TX_FIFO_RST               (1 << 2)
00047 #define FCR_RX_FIFO_RST               (1 << 1)
00048 #define FCR_ENABLE_FIFO               (1 << 0)
00049 
00050 //FIFO size
00051 #define SC16IS752_FIFO_RX                  64
00052 #define SC16IS752_FIFO_TX                  64
00053 
00054 
00055 /** See section 8.4 of the datasheet for definitions
00056   * of bits in the Line Control Register (LCR)
00057   */
00058 #define LCR_BITS5                      0x00
00059 #define LCR_BITS6                      0x01
00060 #define LCR_BITS7                      0x02
00061 #define LCR_BITS8                      0x03
00062 
00063 #define LCR_BITS1                      0x00
00064 #define LCR_BITS2                      0x04
00065 
00066 #define LCR_NONE                       0x00
00067 #define LCR_ODD                        0x08
00068 #define LCR_EVEN                       0x18
00069 #define LCR_FORCED1                    0x28
00070 #define LCR_FORCED0                    0x38
00071 
00072 #define LCR_BRK_ENA                    0x40
00073 #define LCR_BRK_DIS                    0x00
00074 
00075 #define LCR_ENABLE_DIV                 0x80
00076 #define LCR_DISABLE_DIV                0x00
00077 
00078 #define LCR_ENABLE_ENHANCED_FUNCTIONS (0xBF)
00079 
00080 
00081 /** See section 8.5 of the datasheet for definitions
00082   * of bits in the Line status register (LSR)
00083   */
00084 #define LSR_DR   (0x01) /* Data ready in RX FIFO                       */
00085 #define LSR_OE   (0x02) /* Overrun error                               */
00086 #define LSR_PE   (0x04) /* Parity error                                */
00087 #define LSR_FE   (0x08) /* Framing error                               */
00088 #define LSR_BI   (0x10) /* Break interrupt                             */
00089 #define LSR_THRE (0x20) /* Transmitter holding register (FIFO empty)   */
00090 #define LSR_TEMT (0x40) /* Transmitter empty (FIFO and TSR both empty) */
00091 #define LSR_FFE  (0x80) /* At least one PE, FE or BI in FIFO           */
00092 
00093 
00094 /** See section 8.6 of the datasheet for definitions
00095   * of bits in the Modem control register (MCR)
00096   */
00097 #define MCR_MDTR                      (1 << 0) /* Data Terminal Ready pin control. */
00098 #define MCR_MRTS                      (1 << 1) /* Request to Send pin control when not in Auto RTS mode.*/
00099 //MCR[2] only accessible when EFR[4] is set
00100 #define MCR_ENABLE_TCR_TLR            (1 << 2)
00101 #define MCR_ENABLE_LOOPBACK           (1 << 4)
00102 //MCR[7:5] only accessible when EFR[4] is set
00103 #define MCR_ENABLE_XON_ANY_CHAR       (1 << 5)
00104 #define MCR_ENABLE_IRDA               (1 << 6)
00105 #define MCR_PRESCALE_1                (0 << 7)
00106 #define MCR_PRESCALE_4                (1 << 7)
00107 
00108 
00109 /** See section 8.7 of the datasheet for definitions
00110   * of bits in the Modem status register (MSR)
00111   */
00112 #define MSR_DCTS                      (1 << 0) /* Delta CTS - CTS Changed State      */
00113 #define MSR_DDSR                      (1 << 1) /* Delta DSR - DSR Changed State      */
00114 #define MSR_DDI                       (1 << 2) /* Delta DI  - DI  Changed State      */
00115 #define MSR_DCD                       (1 << 3) /* Delta CD  - CD  Changed State      */
00116 #define MSR_CTS                       (1 << 4) /* CTS State - Complement of NCTS pin */
00117 //MSR[7:5] only accessible when GPIO[7:4] are set as modem pin
00118 #define MSR_DSR                       (1 << 5) /* DSR State - Complement of NDSR pin */
00119 #define MSR_RI                        (1 << 6) /* RI State  - Complement of  NRI pin */
00120 #define MSR_CD                        (1 << 7) /* CD State  - Complement of  NCD pin */
00121 
00122 
00123 /** See section 8.8 of the datasheet for definitions
00124   * of bits in the Interrupt enable register (IER)
00125   */
00126 #define IER_ERHRI (0x01) /* Enable received data available interrupt            */
00127 #define IER_ETHRI (0x02) /* Enable transmitter holding register empty interrupt */
00128 #define IER_ELSI  (0x04) /* Enable receiver line status interrupt               */
00129 #define IER_EMSI  (0x08) /* Enable modem status interrupt                       */
00130 //IER[7:5] only accessible when EFR[4] is set
00131 #define IER_SLEEP (0x10) /* Enable sleep mode                                   */
00132 #define IER_XOFFI (0x20) /* Enable XOFF interrupt                               */
00133 #define IER_RTSI  (0x40) /* Enable RTS interrupt                                */
00134 #define IER_CTSI  (0x80) /* Enable CTS interrupt                                */
00135 
00136 
00137 /** See section 8.9 of the datasheet for definitions
00138   * of bits in the Interrupt identification register (IIR)
00139   * Bit 0 is set to 0 if an IRQ is pending.
00140   * Bits 1..5 are used to identify the IRQ source.
00141   */
00142 #define IIR_IRQ_NOT_PENDING             (0x01)  /* IRQ Not Pending              */
00143 #define IIR_TX_EMPTY                    (0x02)  /* THR Interrupt                */
00144 #define IIR_RX_DATA                     (0x04)  /* RHR Interrupt                */
00145 #define IIR_RX_ERROR                    (0x06)  /* Line Status Error Interrupt  */
00146 #define IIR_RX_TIMEOUT                  (0x0B)  /* RX Timeout Interrupt         */
00147 #define IIR_RX_XOFF                     (0x10)  /* RX XOff Interrupt            */
00148 #define IIR_DCTS_DRTS                   (0x20)  /* Delta CTS or RTS Interrupt   */
00149 #define IIR_DIO                         (0x30)  /* Delta GPIO pin Interrupt     */
00150 
00151 #define IIR_BITS_USED                   (0x07)
00152 
00153 
00154 /** See section 8.10 of the datasheet for definitions
00155   * of bits in the Enhanced Features Register (EFR)
00156   */
00157 #define EFR_ENABLE_CTS                  (1 << 7)
00158 #define EFR_ENABLE_RTS                  (1 << 6)
00159 #define EFR_ENABLE_XOFF2_CHAR_DETECT    (1 << 5)
00160 #define EFR_ENABLE_ENHANCED_FUNCTIONS   (1 << 4)
00161 // EFR[3:0] are used to define Software Flow Control mode
00162 // See section 7.3
00163 #define EFR_DISABLE_TX_FLOW_CTRL        (0x0 << 2)
00164 #define EFR_TX_XON2_XOFF2               (0x1 << 2)
00165 #define EFR_TX_XON1_XOFF1               (0x2 << 2)
00166 #define EFR_TX_XON2_1_XOFF2_1           (0x3 << 2)
00167 
00168 #define EFR_DISABLE_RX_FLOW_CTRL        (0x0 << 0)
00169 #define EFR_RX_XON2_XOFF2               (0x1 << 0)
00170 #define EFR_RX_XON1_XOFF1               (0x2 << 0)
00171 #define EFR_RX_XON2_1_XOFF2_1           (0x3 << 0)
00172 
00173 #define EFR_TX_XON2_XOFF2_RX_FLOW       (0x1 << 2) | (0x3 << 0)
00174 #define EFR_TX_XON1_XOFF1_RX_FLOW       (0x2 << 2) | (0x3 << 0)
00175 #define EFR_TX_XON2_1_XOFF2_1_RX_FLOW   (0x3 << 2) | (0x3 << 0)
00176 
00177 
00178 
00179 /** See section 8.12 of the datasheet for definitions
00180   * of bits in the Transmission Control Register (TCR)
00181   * These levels control when RTS is asserted or de-asserted and auto RTS is enabled. Note that XON/XOFF is not supported in this lib.
00182   *   Trigger level to halt transmission to the device   : 0..15 (meaning 0-60 with a granularity of 4) 
00183   *     RTS is de-asserted when RX FIFO is above the set trigger level (i.e. buffer is getting full)  
00184   *   Trigger level to resume transmission to the device : 0..15 (meaning 0-60 with a granularity of 4) 
00185   *     RTS is asserted again when RX FIFO drops below the set trigger level (i.e. buffer has room again)    
00186   */
00187 #define TCR_HALT_DEFAULT                (0x0E)
00188 #define TCR_RESUME_DEFAULT              (0x08)  
00189 
00190 /** See section 8.12 of the datasheet for definitions
00191   * Note: The device will stop transmissions from the TX FIFO when CTS is de-asserted by external receiver and 
00192   *       auto CTS is enabled. Note that XON/XOFF is not supported in this lib.
00193   */
00194   
00195     
00196 /** See section 7.5 and 8.13 of the datasheet for definitions
00197   * of bits in the Trigger Level Register (TLR) control when an IRQ is generated.
00198   *   Trigger level for TX interrupt: 0..15 (meaning 0-60 with a granularity of 4) 
00199   *     IRQ when TX FIFO is above the set trigger level (i.e. buffer is getting full)
00200   *   Trigger level for RX interrupt: 0..15 (meaning 0-60 with a granularity of 4) 
00201   *     IRQ when RX FIFO is above the set trigger level (i.e. data is waiting to be read)
00202   */
00203 #define TLR_TX_DEFAULT                  (0x0E)
00204 #define TLR_RX_DEFAULT                  (0x04)  
00205 
00206 
00207 /**
00208   * See section 8.16, 8.17, 8.18 of the datasheet for definitions
00209   * of bits in the IO Direction (IODIR), IO State (IOSTATE) and IO Interrupt Enable register (IOINTENA)
00210   * 
00211   * Basically a direct mapping of register bits to GPIO pin.
00212   */
00213 
00214 
00215 /**
00216   * See section 8.19 of the datasheet for definitions
00217   * of bits in the IO Control register (IOC)
00218   * 
00219   * Bit 0 is set to 0 to enable latch of IO inputs.
00220   * Bit 1 is set to enable GPIO[7-4] as /RI, /CD, /DTR, /DST.
00221   * Bit 2 is set to enable software reset.
00222   */
00223 #define IOC_ENA_LATCH                   (0x01)
00224 #define IOC_ENA_MODEM                   (0x02) /* Set GPIO[7:4] pins to modem functions */
00225 #define IOC_SW_RST                      (0x04) 
00226 
00227 
00228 /**
00229   * See section 8.20 of the datasheet for definitions
00230   * of bits in the Extra Features Control register (EFCR)
00231   * 
00232   */
00233 #define EFCR_ENA_RS485                  (0x01)  
00234 #define EFCR_DIS_RX                     (0x02)    
00235 #define EFCR_DIS_TX                     (0x04)    
00236 #define EFCR_ENA_TX_RTS                 (0x10)    
00237 #define EFCR_INV_RTS_RS485              (0x20)    
00238 #define EFCR_ENA_IRDA                   (0x80)
00239 
00240 class SC16IS752 : public Stream
00241 {
00242 public:
00243     enum RegisterName
00244     { 
00245         RHR         = 0x00 << 3, /* Rx buffer register     - Read access  */
00246         THR         = 0x00 << 3, /* Tx holding register    - Write access */
00247         IER         = 0x01 << 3, /* Interrupt enable reg   - RD/WR access */
00248         
00249         DLL         = 0x00 << 3, /* Divisor latch (LSB)    - RD/WR access */
00250         DLH         = 0x01 << 3, /* Divisor latch (MSB)    - RD/WR access */
00251         
00252         IIR         = 0x02 << 3, /* Interrupt id. register - Read only    */
00253         FCR         = 0x02 << 3, /* FIFO control register  - Write only   */
00254 
00255         EFR         = 0x02 << 3, /* Enhanced features reg  - RD/WR access */     
00256 
00257         LCR         = 0x03 << 3, /* Line control register  - RD/WR access */
00258 
00259         MCR         = 0x04 << 3, /* Modem control register - RD/WR access */
00260         LSR         = 0x05 << 3, /* Line status register   - Read only    */
00261  
00262         MSR         = 0x06 << 3, /* Modem status register  - Read only    */
00263         SPR         = 0x07 << 3, /* Scratchpad register    - RD/WR access */
00264 
00265         TCR         = 0x06 << 3, /* Transmission control register - RD/WR access */
00266         TLR         = 0x07 << 3, /* Trigger level register        - RD/WR access */
00267 
00268         XON1        = 0x04 << 3, /* XON1 register          - RD/WR access */
00269         XON2        = 0x05 << 3, /* XON2 register          - RD/WR access */
00270         XOFF1       = 0x06 << 3, /* XOFF1 register         - RD/WR access */
00271         XOFF2       = 0x07 << 3, /* XOFF2 register         - RD/WR access */
00272 
00273         TXLVL       = 0x08 << 3, /* TX FIFO Level register - Read only    */
00274         RXLVL       = 0x09 << 3, /* RX FIFO Level register - Read only    */
00275         IODIR       = 0x0A << 3, /* IO Pin Direction reg   - RD/WR access */
00276         IOSTATE     = 0x0B << 3, /* IO Pin State reg       - RD/WR access */
00277         IOINTENA    = 0x0C << 3, /* IO Interrupt Enable    - RD/WR access */
00278 //        reserved    = 0x0D << 3,
00279         IOCTRL      = 0x0E << 3, /* IO Control register    - RD/WR access */
00280         EFCR        = 0x0F << 3, /* Extra features reg     - RD/WR access */
00281     } ;
00282     
00283     enum Flow {
00284         Disabled = 0,
00285         RTS,
00286         CTS,
00287         RTSCTS
00288     };
00289     
00290     enum ChannelName { 
00291       Channel_A     = 0x00 << 1,   
00292       Channel_B     = 0x01 << 1         
00293     };
00294     
00295     struct SC16IS752_cfg {
00296       char baudrate;
00297       char dataformat;  
00298       char flowctrl;  
00299       char fifoformat;
00300       bool fifoenable;      
00301     };
00302     
00303     bool readable();
00304     int readableCount();
00305     int writeable();
00306     int writeableCount();
00307     int get();  
00308     int put(int value);
00309     void writeString(const char *str);
00310     void writeBytes(const char *data, int len);
00311     bool swReset();
00312     bool baud(int baudrate = 9600);
00313     bool format(int bits=8, Serial::Parity parity=Serial::None, int stop_bits=1);
00314     bool set_flow_control(Flow type=Disabled, PinName flow1=NC, PinName flow2=NC);
00315     bool set_flow_triggers(int resume = TCR_RESUME_DEFAULT, int halt = TCR_HALT_DEFAULT);
00316     bool set_modem_control();
00317     bool connected();
00318     bool set_fifo_control(bool stat = true);
00319     bool flush();
00320     bool init(int baudrate = 9600);
00321     bool wr(char adr, char data);
00322     void wrblock (const char *data, int len );
00323     void wrblock (const uint8_t *data, int len );
00324     char rd(char adr);
00325     
00326     SC16IS752(PinName sda, PinName scl, uint8_t deviceAddress = SC16IS752_SA0, PinName rst = NC, ChannelName channel = SC16IS752::Channel_A);
00327     virtual ~SC16IS752();
00328 
00329 private:
00330     I2C _i2c;
00331     uint8_t _slaveAddress;
00332     DigitalOut* _reset;
00333     ChannelName _channel;
00334     char data[64];
00335     char w[32];
00336     char r[32];
00337     
00338 protected:
00339     virtual int _getc()
00340     {
00341         return getc();
00342     }
00343     
00344     virtual int _putc(int c)
00345     {
00346         return putc(c); 
00347     }
00348     
00349     virtual int peek() {return 0;};
00350     SC16IS752_cfg _config;
00351 };
00352 
00353 #endif