Igor Skochinsky
NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip
include/lpc17xx_uart.h@0:1063a091a062, 2010-02-17 (annotated)
- Committer:
- igorsk
- Date:
- Wed Feb 17 16:22:39 2010 +0000
- Revision:
- 0:1063a091a062
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| igorsk | 0:1063a091a062 | 1 | /***********************************************************************//** |
| igorsk | 0:1063a091a062 | 2 | * @file : lpc17xx_uart.h |
| igorsk | 0:1063a091a062 | 3 | * @brief : Contains all macro definitions and function prototypes |
| igorsk | 0:1063a091a062 | 4 | * support for UART firmware library on LPC17xx |
| igorsk | 0:1063a091a062 | 5 | * @version : 1.0 |
| igorsk | 0:1063a091a062 | 6 | * @date : 18. Mar. 2009 |
| igorsk | 0:1063a091a062 | 7 | * @author : HieuNguyen |
| igorsk | 0:1063a091a062 | 8 | ************************************************************************** |
| igorsk | 0:1063a091a062 | 9 | * Software that is described herein is for illustrative purposes only |
| igorsk | 0:1063a091a062 | 10 | * which provides customers with programming information regarding the |
| igorsk | 0:1063a091a062 | 11 | * products. This software is supplied "AS IS" without any warranties. |
| igorsk | 0:1063a091a062 | 12 | * NXP Semiconductors assumes no responsibility or liability for the |
| igorsk | 0:1063a091a062 | 13 | * use of the software, conveys no license or title under any patent, |
| igorsk | 0:1063a091a062 | 14 | * copyright, or mask work right to the product. NXP Semiconductors |
| igorsk | 0:1063a091a062 | 15 | * reserves the right to make changes in the software without |
| igorsk | 0:1063a091a062 | 16 | * notification. NXP Semiconductors also make no representation or |
| igorsk | 0:1063a091a062 | 17 | * warranty that such application will be suitable for the specified |
| igorsk | 0:1063a091a062 | 18 | * use without further testing or modification. |
| igorsk | 0:1063a091a062 | 19 | **************************************************************************/ |
| igorsk | 0:1063a091a062 | 20 | |
| igorsk | 0:1063a091a062 | 21 | /* Peripheral group ----------------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 22 | /** @defgroup UART |
| igorsk | 0:1063a091a062 | 23 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
| igorsk | 0:1063a091a062 | 24 | * @{ |
| igorsk | 0:1063a091a062 | 25 | */ |
| igorsk | 0:1063a091a062 | 26 | |
| igorsk | 0:1063a091a062 | 27 | #ifndef __LPC17XX_UART_H |
| igorsk | 0:1063a091a062 | 28 | #define __LPC17XX_UART_H |
| igorsk | 0:1063a091a062 | 29 | |
| igorsk | 0:1063a091a062 | 30 | /* Includes ------------------------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 31 | #include "cmsis.h" |
| igorsk | 0:1063a091a062 | 32 | #include "lpc_types.h" |
| igorsk | 0:1063a091a062 | 33 | |
| igorsk | 0:1063a091a062 | 34 | |
| igorsk | 0:1063a091a062 | 35 | #ifdef __cplusplus |
| igorsk | 0:1063a091a062 | 36 | extern "C" |
| igorsk | 0:1063a091a062 | 37 | { |
| igorsk | 0:1063a091a062 | 38 | #endif |
| igorsk | 0:1063a091a062 | 39 | |
| igorsk | 0:1063a091a062 | 40 | |
| igorsk | 0:1063a091a062 | 41 | /* Private Macros ------------------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 42 | /** @defgroup UART_Private_Macros |
| igorsk | 0:1063a091a062 | 43 | * @{ |
| igorsk | 0:1063a091a062 | 44 | */ |
| igorsk | 0:1063a091a062 | 45 | |
| igorsk | 0:1063a091a062 | 46 | |
| igorsk | 0:1063a091a062 | 47 | /** @defgroup UART_REGISTER_BIT_DEFINITIONS |
| igorsk | 0:1063a091a062 | 48 | * @{ |
| igorsk | 0:1063a091a062 | 49 | */ |
| igorsk | 0:1063a091a062 | 50 | |
| igorsk | 0:1063a091a062 | 51 | /* Accepted Error baud rate value (in percent unit) */ |
| igorsk | 0:1063a091a062 | 52 | #define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */ |
| igorsk | 0:1063a091a062 | 53 | |
| igorsk | 0:1063a091a062 | 54 | /* Macro defines for UARTn Receiver Buffer Register */ |
| igorsk | 0:1063a091a062 | 55 | #define UART_RBR_MASKBIT ((uint8_t)0xFF) /*!< UART Received Buffer mask bit (8 bits) */ |
| igorsk | 0:1063a091a062 | 56 | |
| igorsk | 0:1063a091a062 | 57 | /* Macro defines for UARTn Transmit Holding Register */ |
| igorsk | 0:1063a091a062 | 58 | #define UART_THR_MASKBIT ((uint8_t)0xFF) /*!< UART Transmit Holding mask bit (8 bits) */ |
| igorsk | 0:1063a091a062 | 59 | |
| igorsk | 0:1063a091a062 | 60 | /* Macro defines for UARTn Divisor Latch LSB register */ |
| igorsk | 0:1063a091a062 | 61 | #define UART_LOAD_DLL(div) ((div) & 0xFF) /**< Macro for loading least significant halfs of divisors */ |
| igorsk | 0:1063a091a062 | 62 | #define UART_DLL_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch LSB bit mask */ |
| igorsk | 0:1063a091a062 | 63 | |
| igorsk | 0:1063a091a062 | 64 | /* Macro defines for UARTn Divisor Latch MSB register */ |
| igorsk | 0:1063a091a062 | 65 | #define UART_DLM_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch MSB bit mask */ |
| igorsk | 0:1063a091a062 | 66 | #define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /**< Macro for loading most significant halfs of divisors */ |
| igorsk | 0:1063a091a062 | 67 | |
| igorsk | 0:1063a091a062 | 68 | |
| igorsk | 0:1063a091a062 | 69 | /* Macro defines for UART interrupt enable register */ |
| igorsk | 0:1063a091a062 | 70 | #define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /*!< RBR Interrupt enable*/ |
| igorsk | 0:1063a091a062 | 71 | #define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /*!< THR Interrupt enable*/ |
| igorsk | 0:1063a091a062 | 72 | #define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /*!< RX line status interrupt enable*/ |
| igorsk | 0:1063a091a062 | 73 | #define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /*!< Modem status interrupt enable */ |
| igorsk | 0:1063a091a062 | 74 | #define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /*!< CTS1 signal transition interrupt enable */ |
| igorsk | 0:1063a091a062 | 75 | #define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /*!< Enables the end of auto-baud interrupt */ |
| igorsk | 0:1063a091a062 | 76 | #define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /*!< Enables the auto-baud time-out interrupt */ |
| igorsk | 0:1063a091a062 | 77 | #define UART_IER_BITMASK ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */ |
| igorsk | 0:1063a091a062 | 78 | #define UART1_IER_BITMASK ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */ |
| igorsk | 0:1063a091a062 | 79 | |
| igorsk | 0:1063a091a062 | 80 | |
| igorsk | 0:1063a091a062 | 81 | /* UART interrupt identification register defines */ |
| igorsk | 0:1063a091a062 | 82 | #define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /*!<Interrupt Status - Active low */ |
| igorsk | 0:1063a091a062 | 83 | #define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /*!<Interrupt identification: Receive line status*/ |
| igorsk | 0:1063a091a062 | 84 | #define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /*!<Interrupt identification: Receive data available*/ |
| igorsk | 0:1063a091a062 | 85 | #define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /*!<Interrupt identification: Character time-out indicator*/ |
| igorsk | 0:1063a091a062 | 86 | #define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) /*!<Interrupt identification: THRE interrupt*/ |
| igorsk | 0:1063a091a062 | 87 | #define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /*!<Interrupt identification: Modem interrupt*/ |
| igorsk | 0:1063a091a062 | 88 | #define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /*!<Interrupt identification: Interrupt ID mask */ |
| igorsk | 0:1063a091a062 | 89 | #define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /*!<These bits are equivalent to UnFCR[0] */ |
| igorsk | 0:1063a091a062 | 90 | #define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) /*!< End of auto-baud interrupt */ |
| igorsk | 0:1063a091a062 | 91 | #define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) /*!< Auto-baud time-out interrupt */ |
| igorsk | 0:1063a091a062 | 92 | #define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /*!< UART interrupt identification register bit mask */ |
| igorsk | 0:1063a091a062 | 93 | |
| igorsk | 0:1063a091a062 | 94 | |
| igorsk | 0:1063a091a062 | 95 | /* Macro defines for UART FIFO control register */ |
| igorsk | 0:1063a091a062 | 96 | #define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) /*!< UART FIFO enable */ |
| igorsk | 0:1063a091a062 | 97 | #define UART_FCR_RX_RS ((uint8_t)(1<<1)) /*!< UART FIFO RX reset */ |
| igorsk | 0:1063a091a062 | 98 | #define UART_FCR_TX_RS ((uint8_t)(1<<2)) /*!< UART FIFO TX reset */ |
| igorsk | 0:1063a091a062 | 99 | #define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) /*!< UART DMA mode selection */ |
| igorsk | 0:1063a091a062 | 100 | #define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /*!< UART FIFO trigger level 0: 1 character */ |
| igorsk | 0:1063a091a062 | 101 | #define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) /*!< UART FIFO trigger level 1: 4 character */ |
| igorsk | 0:1063a091a062 | 102 | #define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /*!< UART FIFO trigger level 2: 8 character */ |
| igorsk | 0:1063a091a062 | 103 | #define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /*!< UART FIFO trigger level 3: 14 character */ |
| igorsk | 0:1063a091a062 | 104 | #define UART_FCR_BITMASK ((uint8_t)(0xCF)) /*!< UART FIFO control bit mask */ |
| igorsk | 0:1063a091a062 | 105 | #define UART_TX_FIFO_SIZE (16) |
| igorsk | 0:1063a091a062 | 106 | |
| igorsk | 0:1063a091a062 | 107 | /* Macro defines for UART line control register */ |
| igorsk | 0:1063a091a062 | 108 | #define UART_LCR_WLEN5 ((uint8_t)(0)) /*!< UART 5 bit data mode */ |
| igorsk | 0:1063a091a062 | 109 | #define UART_LCR_WLEN6 ((uint8_t)(1<<0)) /*!< UART 6 bit data mode */ |
| igorsk | 0:1063a091a062 | 110 | #define UART_LCR_WLEN7 ((uint8_t)(2<<0)) /*!< UART 7 bit data mode */ |
| igorsk | 0:1063a091a062 | 111 | #define UART_LCR_WLEN8 ((uint8_t)(3<<0)) /*!< UART 8 bit data mode */ |
| igorsk | 0:1063a091a062 | 112 | #define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) /*!< UART Two Stop Bits Select */ |
| igorsk | 0:1063a091a062 | 113 | #define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) /*!< UART Parity Enable */ |
| igorsk | 0:1063a091a062 | 114 | #define UART_LCR_PARITY_ODD ((uint8_t)(0)) /*!< UART Odd Parity Select */ |
| igorsk | 0:1063a091a062 | 115 | #define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) /*!< UART Even Parity Select */ |
| igorsk | 0:1063a091a062 | 116 | #define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) /*!< UART force 1 stick parity */ |
| igorsk | 0:1063a091a062 | 117 | #define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) /*!< UART force 0 stick parity */ |
| igorsk | 0:1063a091a062 | 118 | #define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) /*!< UART Transmission Break enable */ |
| igorsk | 0:1063a091a062 | 119 | #define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) /*!< UART Divisor Latches Access bit enable */ |
| igorsk | 0:1063a091a062 | 120 | #define UART_LCR_BITMASK ((uint8_t)(0xFF)) /*!< UART line control bit mask */ |
| igorsk | 0:1063a091a062 | 121 | |
| igorsk | 0:1063a091a062 | 122 | |
| igorsk | 0:1063a091a062 | 123 | /* Macro defines for UART1 Modem Control Register */ |
| igorsk | 0:1063a091a062 | 124 | #define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) /*!< Source for modem output pin DTR */ |
| igorsk | 0:1063a091a062 | 125 | #define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) /*!< Source for modem output pin RTS */ |
| igorsk | 0:1063a091a062 | 126 | #define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) /*!< Loop back mode select */ |
| igorsk | 0:1063a091a062 | 127 | #define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) /*!< Enable Auto RTS flow-control */ |
| igorsk | 0:1063a091a062 | 128 | #define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) /*!< Enable Auto CTS flow-control */ |
| igorsk | 0:1063a091a062 | 129 | #define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) /*!< UART1 bit mask value */ |
| igorsk | 0:1063a091a062 | 130 | |
| igorsk | 0:1063a091a062 | 131 | |
| igorsk | 0:1063a091a062 | 132 | /* Macro defines for UART line status register */ |
| igorsk | 0:1063a091a062 | 133 | #define UART_LSR_RDR ((uint8_t)(1<<0)) /*!<Line status register: Receive data ready*/ |
| igorsk | 0:1063a091a062 | 134 | #define UART_LSR_OE ((uint8_t)(1<<1)) /*!<Line status register: Overrun error*/ |
| igorsk | 0:1063a091a062 | 135 | #define UART_LSR_PE ((uint8_t)(1<<2)) /*!<Line status register: Parity error*/ |
| igorsk | 0:1063a091a062 | 136 | #define UART_LSR_FE ((uint8_t)(1<<3)) /*!<Line status register: Framing error*/ |
| igorsk | 0:1063a091a062 | 137 | #define UART_LSR_BI ((uint8_t)(1<<4)) /*!<Line status register: Break interrupt*/ |
| igorsk | 0:1063a091a062 | 138 | #define UART_LSR_THRE ((uint8_t)(1<<5)) /*!<Line status register: Transmit holding register empty*/ |
| igorsk | 0:1063a091a062 | 139 | #define UART_LSR_TEMT ((uint8_t)(1<<6)) /*!<Line status register: Transmitter empty*/ |
| igorsk | 0:1063a091a062 | 140 | #define UART_LSR_RXFE ((uint8_t)(1<<7)) /*!<Error in RX FIFO*/ |
| igorsk | 0:1063a091a062 | 141 | #define UART_LSR_BITMASK ((uint8_t)(0xFF)) /*!<UART Line status bit mask */ |
| igorsk | 0:1063a091a062 | 142 | |
| igorsk | 0:1063a091a062 | 143 | |
| igorsk | 0:1063a091a062 | 144 | /* Macro defines for UART Modem (UART1 only) status register */ |
| igorsk | 0:1063a091a062 | 145 | #define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) /*!< Set upon state change of input CTS */ |
| igorsk | 0:1063a091a062 | 146 | #define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) /*!< Set upon state change of input DSR */ |
| igorsk | 0:1063a091a062 | 147 | #define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) /*!< Set upon low to high transition of input RI */ |
| igorsk | 0:1063a091a062 | 148 | #define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) /*!< Set upon state change of input DCD */ |
| igorsk | 0:1063a091a062 | 149 | #define UART1_MSR_CTS ((uint8_t)(1<<4)) /*!< Clear To Send State */ |
| igorsk | 0:1063a091a062 | 150 | #define UART1_MSR_DSR ((uint8_t)(1<<5)) /*!< Data Set Ready State */ |
| igorsk | 0:1063a091a062 | 151 | #define UART1_MSR_RI ((uint8_t)(1<<6)) /*!< Ring Indicator State */ |
| igorsk | 0:1063a091a062 | 152 | #define UART1_MSR_DCD ((uint8_t)(1<<7)) /*!< Data Carrier Detect State */ |
| igorsk | 0:1063a091a062 | 153 | #define UART1_MSR_BITMASK ((uint8_t)(0xFF)) /*!< MSR register bit-mask value */ |
| igorsk | 0:1063a091a062 | 154 | |
| igorsk | 0:1063a091a062 | 155 | |
| igorsk | 0:1063a091a062 | 156 | /* Macro defines for UART Scratch Pad Register */ |
| igorsk | 0:1063a091a062 | 157 | #define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*!< UART Scratch Pad bit mask */ |
| igorsk | 0:1063a091a062 | 158 | |
| igorsk | 0:1063a091a062 | 159 | /* Macro defines for UART Auto baudrate control register */ |
| igorsk | 0:1063a091a062 | 160 | #define UART_ACR_START ((uint32_t)(1<<0)) /**< UART Auto-baud start */ |
| igorsk | 0:1063a091a062 | 161 | #define UART_ACR_MODE ((uint32_t)(1<<1)) /**< UART Auto baudrate Mode 1 */ |
| igorsk | 0:1063a091a062 | 162 | #define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) /**< UART Auto baudrate restart */ |
| igorsk | 0:1063a091a062 | 163 | #define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) /**< UART End of auto-baud interrupt clear */ |
| igorsk | 0:1063a091a062 | 164 | #define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) /**< UART Auto-baud time-out interrupt clear */ |
| igorsk | 0:1063a091a062 | 165 | #define UART_ACR_BITMASK ((uint32_t)(0x307)) /**< UART Auto Baudrate register bit mask */ |
| igorsk | 0:1063a091a062 | 166 | |
| igorsk | 0:1063a091a062 | 167 | /* UART IrDA control register defines */ |
| igorsk | 0:1063a091a062 | 168 | #define UART_ICR_IRDAEN ((uint32_t)(1<<0)) /**< IrDA mode enable */ |
| igorsk | 0:1063a091a062 | 169 | #define UART_ICR_IRDAINV ((uint32_t)(1<<1)) /**< IrDA serial input inverted */ |
| igorsk | 0:1063a091a062 | 170 | #define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) /**< IrDA fixed pulse width mode */ |
| igorsk | 0:1063a091a062 | 171 | #define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */ |
| igorsk | 0:1063a091a062 | 172 | #define UART_ICR_BITMASK ((uint32_t)(0x3F)) /*!< UART IRDA bit mask */ |
| igorsk | 0:1063a091a062 | 173 | |
| igorsk | 0:1063a091a062 | 174 | /* Macro defines for UART Fractional divider register */ |
| igorsk | 0:1063a091a062 | 175 | #define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /**< Baud-rate generation pre-scaler divisor */ |
| igorsk | 0:1063a091a062 | 176 | #define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /**< Baud-rate pre-scaler multiplier value */ |
| igorsk | 0:1063a091a062 | 177 | #define UART_FDR_BITMASK ((uint32_t)(0xFF)) /**< UART Fractional Divider register bit mask */ |
| igorsk | 0:1063a091a062 | 178 | |
| igorsk | 0:1063a091a062 | 179 | /* Macro defines for UART Tx Enable register */ |
| igorsk | 0:1063a091a062 | 180 | #define UART_TER_TXEN ((uint8_t)(1<<7)) /*!< Transmit enable bit */ |
| igorsk | 0:1063a091a062 | 181 | #define UART_TER_BITMASK ((uint8_t)(0x80)) /**< UART Transmit Enable Register bit mask */ |
| igorsk | 0:1063a091a062 | 182 | |
| igorsk | 0:1063a091a062 | 183 | |
| igorsk | 0:1063a091a062 | 184 | /* Macro defines for UART1 RS485 Control register */ |
| igorsk | 0:1063a091a062 | 185 | #define UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM) |
| igorsk | 0:1063a091a062 | 186 | is disabled */ |
| igorsk | 0:1063a091a062 | 187 | #define UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) /*!< The receiver is disabled */ |
| igorsk | 0:1063a091a062 | 188 | #define UART1_RS485CTRL_AADEN ((uint32_t)(1<<2)) /*!< Auto Address Detect (AAD) is enabled */ |
| igorsk | 0:1063a091a062 | 189 | #define UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) /*!< If direction control is enabled |
| igorsk | 0:1063a091a062 | 190 | (bit DCTRL = 1), pin DTR is used for direction control */ |
| igorsk | 0:1063a091a062 | 191 | #define UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) /*!< Enable Auto Direction Control */ |
| igorsk | 0:1063a091a062 | 192 | #define UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) /*!< This bit reverses the polarity of the direction |
| igorsk | 0:1063a091a062 | 193 | control signal on the RTS (or DTR) pin. The direction control pin |
| igorsk | 0:1063a091a062 | 194 | will be driven to logic "1" when the transmitter has data to be sent */ |
| igorsk | 0:1063a091a062 | 195 | #define UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F)) /**< RS485 control bit-mask value */ |
| igorsk | 0:1063a091a062 | 196 | |
| igorsk | 0:1063a091a062 | 197 | |
| igorsk | 0:1063a091a062 | 198 | /* Macro defines for UART1 RS-485 Address Match register */ |
| igorsk | 0:1063a091a062 | 199 | #define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */ |
| igorsk | 0:1063a091a062 | 200 | |
| igorsk | 0:1063a091a062 | 201 | /* Macro defines for UART1 RS-485 Delay value register */ |
| igorsk | 0:1063a091a062 | 202 | #define UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */ |
| igorsk | 0:1063a091a062 | 203 | |
| igorsk | 0:1063a091a062 | 204 | |
| igorsk | 0:1063a091a062 | 205 | /* Macro defines for UART FIFO Level register */ |
| igorsk | 0:1063a091a062 | 206 | #define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) /**< Reflects the current level of the UART receiver FIFO */ |
| igorsk | 0:1063a091a062 | 207 | #define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) /**< Reflects the current level of the UART transmitter FIFO */ |
| igorsk | 0:1063a091a062 | 208 | #define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /**< UART FIFO Level Register bit mask */ |
| igorsk | 0:1063a091a062 | 209 | |
| igorsk | 0:1063a091a062 | 210 | /** |
| igorsk | 0:1063a091a062 | 211 | * @} |
| igorsk | 0:1063a091a062 | 212 | */ |
| igorsk | 0:1063a091a062 | 213 | |
| igorsk | 0:1063a091a062 | 214 | /** |
| igorsk | 0:1063a091a062 | 215 | * @} |
| igorsk | 0:1063a091a062 | 216 | */ |
| igorsk | 0:1063a091a062 | 217 | |
| igorsk | 0:1063a091a062 | 218 | |
| igorsk | 0:1063a091a062 | 219 | /* Public Types --------------------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 220 | /** @defgroup UART_Public_Types |
| igorsk | 0:1063a091a062 | 221 | * @{ |
| igorsk | 0:1063a091a062 | 222 | */ |
| igorsk | 0:1063a091a062 | 223 | |
| igorsk | 0:1063a091a062 | 224 | |
| igorsk | 0:1063a091a062 | 225 | /** |
| igorsk | 0:1063a091a062 | 226 | * @brief UART Databit type definitions |
| igorsk | 0:1063a091a062 | 227 | */ |
| igorsk | 0:1063a091a062 | 228 | typedef enum { |
| igorsk | 0:1063a091a062 | 229 | UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */ |
| igorsk | 0:1063a091a062 | 230 | UART_DATABIT_6, /*!< UART 6 bit data mode */ |
| igorsk | 0:1063a091a062 | 231 | UART_DATABIT_7, /*!< UART 7 bit data mode */ |
| igorsk | 0:1063a091a062 | 232 | UART_DATABIT_8 /*!< UART 8 bit data mode */ |
| igorsk | 0:1063a091a062 | 233 | } UART_DATABIT_Type; |
| igorsk | 0:1063a091a062 | 234 | |
| igorsk | 0:1063a091a062 | 235 | /** Macro to check the input UART_DATABIT parameters */ |
| igorsk | 0:1063a091a062 | 236 | #define PARAM_UART_DATABIT(databit) ((databit==UART_DATABIT_5) || (databit==UART_DATABIT_6)\ |
| igorsk | 0:1063a091a062 | 237 | || (databit==UART_DATABIT_7) || (databit==UART_DATABIT_8)) |
| igorsk | 0:1063a091a062 | 238 | |
| igorsk | 0:1063a091a062 | 239 | /** |
| igorsk | 0:1063a091a062 | 240 | * @brief UART Stop bit type definitions |
| igorsk | 0:1063a091a062 | 241 | */ |
| igorsk | 0:1063a091a062 | 242 | typedef enum { |
| igorsk | 0:1063a091a062 | 243 | UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */ |
| igorsk | 0:1063a091a062 | 244 | UART_STOPBIT_2, /*!< UART Two Stop Bits Select */ |
| igorsk | 0:1063a091a062 | 245 | } UART_STOPBIT_Type; |
| igorsk | 0:1063a091a062 | 246 | |
| igorsk | 0:1063a091a062 | 247 | /** Macro to check the input UART_STOPBIT parameters */ |
| igorsk | 0:1063a091a062 | 248 | #define PARAM_UART_STOPBIT(stopbit) ((stopbit==UART_STOPBIT_1) || (stopbit==UART_STOPBIT_2)) |
| igorsk | 0:1063a091a062 | 249 | |
| igorsk | 0:1063a091a062 | 250 | /** |
| igorsk | 0:1063a091a062 | 251 | * @brief UART Parity type definitions |
| igorsk | 0:1063a091a062 | 252 | */ |
| igorsk | 0:1063a091a062 | 253 | typedef enum { |
| igorsk | 0:1063a091a062 | 254 | UART_PARITY_NONE = 0, /*!< No parity */ |
| igorsk | 0:1063a091a062 | 255 | UART_PARITY_ODD, /*!< Odd parity */ |
| igorsk | 0:1063a091a062 | 256 | UART_PARITY_EVEN, /*!< Even parity */ |
| igorsk | 0:1063a091a062 | 257 | UART_PARITY_SP_1, /*!< Forced "1" stick parity */ |
| igorsk | 0:1063a091a062 | 258 | UART_PARITY_SP_0 /*!< Forced "0" stick parity */ |
| igorsk | 0:1063a091a062 | 259 | } UART_PARITY_Type; |
| igorsk | 0:1063a091a062 | 260 | |
| igorsk | 0:1063a091a062 | 261 | /** Macro to check the input UART_PARITY parameters */ |
| igorsk | 0:1063a091a062 | 262 | #define PARAM_UART_PARITY(parity) ((parity==UART_PARITY_NONE) || (parity==UART_PARITY_ODD) \ |
| igorsk | 0:1063a091a062 | 263 | || (parity==UART_PARITY_EVEN) || (parity==UART_PARITY_SP_1) \ |
| igorsk | 0:1063a091a062 | 264 | || (parity==UART_PARITY_SP_0)) |
| igorsk | 0:1063a091a062 | 265 | |
| igorsk | 0:1063a091a062 | 266 | /** |
| igorsk | 0:1063a091a062 | 267 | * @brief FIFO Level type definitions |
| igorsk | 0:1063a091a062 | 268 | */ |
| igorsk | 0:1063a091a062 | 269 | typedef enum { |
| igorsk | 0:1063a091a062 | 270 | UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */ |
| igorsk | 0:1063a091a062 | 271 | UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */ |
| igorsk | 0:1063a091a062 | 272 | UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */ |
| igorsk | 0:1063a091a062 | 273 | UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */ |
| igorsk | 0:1063a091a062 | 274 | } UART_FITO_LEVEL_Type; |
| igorsk | 0:1063a091a062 | 275 | |
| igorsk | 0:1063a091a062 | 276 | /** Macro to check the input UART_FIFO parameters */ |
| igorsk | 0:1063a091a062 | 277 | #define PARAM_UART_FIFO_LEVEL(fifo) ((fifo==UART_FIFO_TRGLEV0) \ |
| igorsk | 0:1063a091a062 | 278 | || (fifo==UART_FIFO_TRGLEV1) || (fifo==UART_FIFO_TRGLEV2) \ |
| igorsk | 0:1063a091a062 | 279 | || (fifo==UART_FIFO_TRGLEV3)) |
| igorsk | 0:1063a091a062 | 280 | |
| igorsk | 0:1063a091a062 | 281 | /********************************************************************//** |
| igorsk | 0:1063a091a062 | 282 | * @brief UART Interrupt Type definitions |
| igorsk | 0:1063a091a062 | 283 | **********************************************************************/ |
| igorsk | 0:1063a091a062 | 284 | typedef enum { |
| igorsk | 0:1063a091a062 | 285 | UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/ |
| igorsk | 0:1063a091a062 | 286 | UART_INTCFG_THRE, /*!< THR Interrupt enable*/ |
| igorsk | 0:1063a091a062 | 287 | UART_INTCFG_RLS, /*!< RX line status interrupt enable*/ |
| igorsk | 0:1063a091a062 | 288 | UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */ |
| igorsk | 0:1063a091a062 | 289 | UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */ |
| igorsk | 0:1063a091a062 | 290 | UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */ |
| igorsk | 0:1063a091a062 | 291 | UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */ |
| igorsk | 0:1063a091a062 | 292 | } UART_INT_Type; |
| igorsk | 0:1063a091a062 | 293 | |
| igorsk | 0:1063a091a062 | 294 | /** Macro to check the input UART_INTCFG parameters */ |
| igorsk | 0:1063a091a062 | 295 | #define PARAM_UART_INTCFG(IntCfg) ((IntCfg==UART_INTCFG_RBR) || (IntCfg==UART_INTCFG_THRE) \ |
| igorsk | 0:1063a091a062 | 296 | || (IntCfg==UART_INTCFG_RLS) || (IntCfg==UART_INTCFG_ABEO) \ |
| igorsk | 0:1063a091a062 | 297 | || (IntCfg==UART_INTCFG_ABTO)) |
| igorsk | 0:1063a091a062 | 298 | |
| igorsk | 0:1063a091a062 | 299 | /** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */ |
| igorsk | 0:1063a091a062 | 300 | #define PARAM_UART1_INTCFG(IntCfg) ((IntCfg==UART1_INTCFG_MS) || (IntCfg==UART1_INTCFG_CTS)) |
| igorsk | 0:1063a091a062 | 301 | |
| igorsk | 0:1063a091a062 | 302 | |
| igorsk | 0:1063a091a062 | 303 | /** |
| igorsk | 0:1063a091a062 | 304 | * @brief UART Line Status Type definition |
| igorsk | 0:1063a091a062 | 305 | */ |
| igorsk | 0:1063a091a062 | 306 | typedef enum { |
| igorsk | 0:1063a091a062 | 307 | UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/ |
| igorsk | 0:1063a091a062 | 308 | UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/ |
| igorsk | 0:1063a091a062 | 309 | UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/ |
| igorsk | 0:1063a091a062 | 310 | UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/ |
| igorsk | 0:1063a091a062 | 311 | UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/ |
| igorsk | 0:1063a091a062 | 312 | UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/ |
| igorsk | 0:1063a091a062 | 313 | UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/ |
| igorsk | 0:1063a091a062 | 314 | UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/ |
| igorsk | 0:1063a091a062 | 315 | } UART_LS_Type; |
| igorsk | 0:1063a091a062 | 316 | |
| igorsk | 0:1063a091a062 | 317 | |
| igorsk | 0:1063a091a062 | 318 | /** |
| igorsk | 0:1063a091a062 | 319 | * @brief UART Auto-baudrate mode type definition |
| igorsk | 0:1063a091a062 | 320 | */ |
| igorsk | 0:1063a091a062 | 321 | typedef enum { |
| igorsk | 0:1063a091a062 | 322 | UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */ |
| igorsk | 0:1063a091a062 | 323 | UART_AUTOBAUD_MODE1, /**< UART Auto baudrate Mode 1 */ |
| igorsk | 0:1063a091a062 | 324 | } UART_AB_MODE_Type; |
| igorsk | 0:1063a091a062 | 325 | |
| igorsk | 0:1063a091a062 | 326 | /** Macro to check the input UART_AUTOBAUD_MODE parameters */ |
| igorsk | 0:1063a091a062 | 327 | #define PARAM_UART_AUTOBAUD_MODE(ABmode) ((ABmode==UART_AUTOBAUD_MODE0) || (ABmode==UART_AUTOBAUD_MODE1)) |
| igorsk | 0:1063a091a062 | 328 | |
| igorsk | 0:1063a091a062 | 329 | /** |
| igorsk | 0:1063a091a062 | 330 | * @brief Auto Baudrate mode configuration type definition |
| igorsk | 0:1063a091a062 | 331 | */ |
| igorsk | 0:1063a091a062 | 332 | typedef struct { |
| igorsk | 0:1063a091a062 | 333 | UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */ |
| igorsk | 0:1063a091a062 | 334 | FunctionalState AutoRestart; /**< Auto Restart state */ |
| igorsk | 0:1063a091a062 | 335 | } UART_AB_CFG_Type; |
| igorsk | 0:1063a091a062 | 336 | |
| igorsk | 0:1063a091a062 | 337 | |
| igorsk | 0:1063a091a062 | 338 | /** |
| igorsk | 0:1063a091a062 | 339 | * @brief UART End of Auto-baudrate type definition |
| igorsk | 0:1063a091a062 | 340 | */ |
| igorsk | 0:1063a091a062 | 341 | typedef enum { |
| igorsk | 0:1063a091a062 | 342 | UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */ |
| igorsk | 0:1063a091a062 | 343 | UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */ |
| igorsk | 0:1063a091a062 | 344 | }UART_ABEO_Type; |
| igorsk | 0:1063a091a062 | 345 | |
| igorsk | 0:1063a091a062 | 346 | /** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */ |
| igorsk | 0:1063a091a062 | 347 | #define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat) ((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) || (ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO)) |
| igorsk | 0:1063a091a062 | 348 | |
| igorsk | 0:1063a091a062 | 349 | /** |
| igorsk | 0:1063a091a062 | 350 | * UART IrDA Control type Definition |
| igorsk | 0:1063a091a062 | 351 | */ |
| igorsk | 0:1063a091a062 | 352 | typedef enum { |
| igorsk | 0:1063a091a062 | 353 | UART_IrDA_PULSEDIV2 = 0, /**< Pulse width = 2 * Tpclk |
| igorsk | 0:1063a091a062 | 354 | - Configures the pulse when FixPulseEn = 1 */ |
| igorsk | 0:1063a091a062 | 355 | UART_IrDA_PULSEDIV4, /**< Pulse width = 4 * Tpclk |
| igorsk | 0:1063a091a062 | 356 | - Configures the pulse when FixPulseEn = 1 */ |
| igorsk | 0:1063a091a062 | 357 | UART_IrDA_PULSEDIV8, /**< Pulse width = 8 * Tpclk |
| igorsk | 0:1063a091a062 | 358 | - Configures the pulse when FixPulseEn = 1 */ |
| igorsk | 0:1063a091a062 | 359 | UART_IrDA_PULSEDIV16, /**< Pulse width = 16 * Tpclk |
| igorsk | 0:1063a091a062 | 360 | - Configures the pulse when FixPulseEn = 1 */ |
| igorsk | 0:1063a091a062 | 361 | UART_IrDA_PULSEDIV32, /**< Pulse width = 32 * Tpclk |
| igorsk | 0:1063a091a062 | 362 | - Configures the pulse when FixPulseEn = 1 */ |
| igorsk | 0:1063a091a062 | 363 | UART_IrDA_PULSEDIV64, /**< Pulse width = 64 * Tpclk |
| igorsk | 0:1063a091a062 | 364 | - Configures the pulse when FixPulseEn = 1 */ |
| igorsk | 0:1063a091a062 | 365 | UART_IrDA_PULSEDIV128, /**< Pulse width = 128 * Tpclk |
| igorsk | 0:1063a091a062 | 366 | - Configures the pulse when FixPulseEn = 1 */ |
| igorsk | 0:1063a091a062 | 367 | UART_IrDA_PULSEDIV256 /**< Pulse width = 256 * Tpclk |
| igorsk | 0:1063a091a062 | 368 | - Configures the pulse when FixPulseEn = 1 */ |
| igorsk | 0:1063a091a062 | 369 | } UART_IrDA_PULSE_Type; |
| igorsk | 0:1063a091a062 | 370 | |
| igorsk | 0:1063a091a062 | 371 | |
| igorsk | 0:1063a091a062 | 372 | /** Macro to check the input UART_IrDA_PULSEDIV parameters */ |
| igorsk | 0:1063a091a062 | 373 | #define PARAM_UART_IrDA_PULSEDIV(PulseDiv) ((PulseDiv==UART_IrDA_PULSEDIV2) || (PulseDiv==UART_IrDA_PULSEDIV4) \ |
| igorsk | 0:1063a091a062 | 374 | || (PulseDiv==UART_IrDA_PULSEDIV8) || (PulseDiv==UART_IrDA_PULSEDIV16) \ |
| igorsk | 0:1063a091a062 | 375 | || (PulseDiv==UART_IrDA_PULSEDIV32) || (PulseDiv==UART_IrDA_PULSEDIV64) \ |
| igorsk | 0:1063a091a062 | 376 | || (PulseDiv==UART_IrDA_PULSEDIV128) || (PulseDiv==UART_IrDA_PULSEDIV256)) |
| igorsk | 0:1063a091a062 | 377 | |
| igorsk | 0:1063a091a062 | 378 | /********************************************************************//** |
| igorsk | 0:1063a091a062 | 379 | * @brief UART1 Full modem - Signal states definition |
| igorsk | 0:1063a091a062 | 380 | **********************************************************************/ |
| igorsk | 0:1063a091a062 | 381 | typedef enum { |
| igorsk | 0:1063a091a062 | 382 | INACTIVE = 0, /* In-active state */ |
| igorsk | 0:1063a091a062 | 383 | ACTIVE = !INACTIVE /* Active state */ |
| igorsk | 0:1063a091a062 | 384 | }UART1_SignalState; |
| igorsk | 0:1063a091a062 | 385 | |
| igorsk | 0:1063a091a062 | 386 | /* Macro to check the input UART1_SignalState parameters */ |
| igorsk | 0:1063a091a062 | 387 | #define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) || (x==ACTIVE)) |
| igorsk | 0:1063a091a062 | 388 | |
| igorsk | 0:1063a091a062 | 389 | /** |
| igorsk | 0:1063a091a062 | 390 | * @brief UART modem status type definition |
| igorsk | 0:1063a091a062 | 391 | */ |
| igorsk | 0:1063a091a062 | 392 | typedef enum { |
| igorsk | 0:1063a091a062 | 393 | UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */ |
| igorsk | 0:1063a091a062 | 394 | UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */ |
| igorsk | 0:1063a091a062 | 395 | UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */ |
| igorsk | 0:1063a091a062 | 396 | UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */ |
| igorsk | 0:1063a091a062 | 397 | UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */ |
| igorsk | 0:1063a091a062 | 398 | UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */ |
| igorsk | 0:1063a091a062 | 399 | UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */ |
| igorsk | 0:1063a091a062 | 400 | UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */ |
| igorsk | 0:1063a091a062 | 401 | } UART_MODEM_STAT_type; |
| igorsk | 0:1063a091a062 | 402 | |
| igorsk | 0:1063a091a062 | 403 | /** |
| igorsk | 0:1063a091a062 | 404 | * @brief Modem output pin type definition |
| igorsk | 0:1063a091a062 | 405 | */ |
| igorsk | 0:1063a091a062 | 406 | typedef enum { |
| igorsk | 0:1063a091a062 | 407 | UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */ |
| igorsk | 0:1063a091a062 | 408 | UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */ |
| igorsk | 0:1063a091a062 | 409 | } UART_MODEM_PIN_Type; |
| igorsk | 0:1063a091a062 | 410 | |
| igorsk | 0:1063a091a062 | 411 | /** Macro to check the input PARAM_UART1_MODEM_PIN parameters */ |
| igorsk | 0:1063a091a062 | 412 | #define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) || (x==UART1_MODEM_PIN_RTS)) |
| igorsk | 0:1063a091a062 | 413 | |
| igorsk | 0:1063a091a062 | 414 | |
| igorsk | 0:1063a091a062 | 415 | /** |
| igorsk | 0:1063a091a062 | 416 | * @brief UART Modem mode type definition |
| igorsk | 0:1063a091a062 | 417 | */ |
| igorsk | 0:1063a091a062 | 418 | typedef enum { |
| igorsk | 0:1063a091a062 | 419 | UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */ |
| igorsk | 0:1063a091a062 | 420 | UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */ |
| igorsk | 0:1063a091a062 | 421 | UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */ |
| igorsk | 0:1063a091a062 | 422 | } UART_MODEM_MODE_Type; |
| igorsk | 0:1063a091a062 | 423 | |
| igorsk | 0:1063a091a062 | 424 | /** Macro to check the input PARAM_UART1_MODEM_MODE parameters */ |
| igorsk | 0:1063a091a062 | 425 | #define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) || (x==UART1_MODEM_MODE_AUTO_RTS) \ |
| igorsk | 0:1063a091a062 | 426 | || (x==UART1_MODEM_MODE_AUTO_CTS)) |
| igorsk | 0:1063a091a062 | 427 | |
| igorsk | 0:1063a091a062 | 428 | |
| igorsk | 0:1063a091a062 | 429 | /** |
| igorsk | 0:1063a091a062 | 430 | * @brief UART Direction Control Pin type definition |
| igorsk | 0:1063a091a062 | 431 | */ |
| igorsk | 0:1063a091a062 | 432 | typedef enum { |
| igorsk | 0:1063a091a062 | 433 | UART1_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */ |
| igorsk | 0:1063a091a062 | 434 | UART1_RS485_DIRCTRL_DTR /**< Pin DTR is used for direction control */ |
| igorsk | 0:1063a091a062 | 435 | } UART_RS485_DIRCTRL_PIN_Type; |
| igorsk | 0:1063a091a062 | 436 | |
| igorsk | 0:1063a091a062 | 437 | /** Macro to check the direction control pin type */ |
| igorsk | 0:1063a091a062 | 438 | #define PARAM_UART_RS485_DIRCTRL_PIN(x) ((x==UART1_RS485_DIRCTRL_RTS) || (x==UART1_RS485_DIRCTRL_DTR)) |
| igorsk | 0:1063a091a062 | 439 | |
| igorsk | 0:1063a091a062 | 440 | |
| igorsk | 0:1063a091a062 | 441 | /********************************************************************//** |
| igorsk | 0:1063a091a062 | 442 | * @brief UART Configuration Structure definition |
| igorsk | 0:1063a091a062 | 443 | **********************************************************************/ |
| igorsk | 0:1063a091a062 | 444 | typedef struct { |
| igorsk | 0:1063a091a062 | 445 | uint32_t Baud_rate; /**< UART baud rate */ |
| igorsk | 0:1063a091a062 | 446 | UART_PARITY_Type Parity; /**< Parity selection, should be: |
| igorsk | 0:1063a091a062 | 447 | - UART_PARITY_NONE: No parity |
| igorsk | 0:1063a091a062 | 448 | - UART_PARITY_ODD: Odd parity |
| igorsk | 0:1063a091a062 | 449 | - UART_PARITY_EVEN: Even parity |
| igorsk | 0:1063a091a062 | 450 | - UART_PARITY_SP_1: Forced "1" stick parity |
| igorsk | 0:1063a091a062 | 451 | - UART_PARITY_SP_0: Forced "0" stick parity |
| igorsk | 0:1063a091a062 | 452 | */ |
| igorsk | 0:1063a091a062 | 453 | UART_DATABIT_Type Databits; /**< Number of data bits, should be: |
| igorsk | 0:1063a091a062 | 454 | - UART_DATABIT_5: UART 5 bit data mode |
| igorsk | 0:1063a091a062 | 455 | - UART_DATABIT_6: UART 6 bit data mode |
| igorsk | 0:1063a091a062 | 456 | - UART_DATABIT_7: UART 7 bit data mode |
| igorsk | 0:1063a091a062 | 457 | - UART_DATABIT_8: UART 8 bit data mode |
| igorsk | 0:1063a091a062 | 458 | */ |
| igorsk | 0:1063a091a062 | 459 | UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be: |
| igorsk | 0:1063a091a062 | 460 | - UART_STOPBIT_1: UART 1 Stop Bits Select |
| igorsk | 0:1063a091a062 | 461 | - UART_STOPBIT_2: UART 2 Stop Bits Select |
| igorsk | 0:1063a091a062 | 462 | */ |
| igorsk | 0:1063a091a062 | 463 | } UART_CFG_Type; |
| igorsk | 0:1063a091a062 | 464 | |
| igorsk | 0:1063a091a062 | 465 | /********************************************************************//** |
| igorsk | 0:1063a091a062 | 466 | * @brief UART FIFO Configuration Structure definition |
| igorsk | 0:1063a091a062 | 467 | **********************************************************************/ |
| igorsk | 0:1063a091a062 | 468 | |
| igorsk | 0:1063a091a062 | 469 | typedef struct { |
| igorsk | 0:1063a091a062 | 470 | FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be: |
| igorsk | 0:1063a091a062 | 471 | - ENABLE: Reset Rx FIFO in UART |
| igorsk | 0:1063a091a062 | 472 | - DISABLE: Do not reset Rx FIFO in UART |
| igorsk | 0:1063a091a062 | 473 | */ |
| igorsk | 0:1063a091a062 | 474 | FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be: |
| igorsk | 0:1063a091a062 | 475 | - ENABLE: Reset Tx FIFO in UART |
| igorsk | 0:1063a091a062 | 476 | - DISABLE: Do not reset Tx FIFO in UART |
| igorsk | 0:1063a091a062 | 477 | */ |
| igorsk | 0:1063a091a062 | 478 | FunctionalState FIFO_DMAMode; /**< DMA mode, should be: |
| igorsk | 0:1063a091a062 | 479 | - ENABLE: Enable DMA mode in UART |
| igorsk | 0:1063a091a062 | 480 | - DISABLE: Disable DMA mode in UART |
| igorsk | 0:1063a091a062 | 481 | */ |
| igorsk | 0:1063a091a062 | 482 | UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be: |
| igorsk | 0:1063a091a062 | 483 | - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character |
| igorsk | 0:1063a091a062 | 484 | - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character |
| igorsk | 0:1063a091a062 | 485 | - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character |
| igorsk | 0:1063a091a062 | 486 | - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character |
| igorsk | 0:1063a091a062 | 487 | */ |
| igorsk | 0:1063a091a062 | 488 | } UART_FIFO_CFG_Type; |
| igorsk | 0:1063a091a062 | 489 | |
| igorsk | 0:1063a091a062 | 490 | |
| igorsk | 0:1063a091a062 | 491 | /********************************************************************//** |
| igorsk | 0:1063a091a062 | 492 | * @brief UART1 Full modem - RS485 Control configuration type |
| igorsk | 0:1063a091a062 | 493 | **********************************************************************/ |
| igorsk | 0:1063a091a062 | 494 | typedef struct { |
| igorsk | 0:1063a091a062 | 495 | FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State: |
| igorsk | 0:1063a091a062 | 496 | - ENABLE: Enable this function. |
| igorsk | 0:1063a091a062 | 497 | - DISABLE: Disable this function. */ |
| igorsk | 0:1063a091a062 | 498 | FunctionalState Rx_State; /*!< Receiver State: |
| igorsk | 0:1063a091a062 | 499 | - ENABLE: Enable Receiver. |
| igorsk | 0:1063a091a062 | 500 | - DISABLE: Disable Receiver. */ |
| igorsk | 0:1063a091a062 | 501 | FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state: |
| igorsk | 0:1063a091a062 | 502 | - ENABLE: ENABLE this function. |
| igorsk | 0:1063a091a062 | 503 | - DISABLE: Disable this function. */ |
| igorsk | 0:1063a091a062 | 504 | FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State: |
| igorsk | 0:1063a091a062 | 505 | - ENABLE: Enable this function. |
| igorsk | 0:1063a091a062 | 506 | - DISABLE: Disable this function. */ |
| igorsk | 0:1063a091a062 | 507 | UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state: |
| igorsk | 0:1063a091a062 | 508 | - UART1_RS485_DIRCTRL_RTS: |
| igorsk | 0:1063a091a062 | 509 | pin RTS is used for direction control. |
| igorsk | 0:1063a091a062 | 510 | - UART1_RS485_DIRCTRL_DTR: |
| igorsk | 0:1063a091a062 | 511 | pin DTR is used for direction control. */ |
| igorsk | 0:1063a091a062 | 512 | SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on |
| igorsk | 0:1063a091a062 | 513 | the RTS (or DTR) pin: |
| igorsk | 0:1063a091a062 | 514 | - RESET: The direction control pin will be driven |
| igorsk | 0:1063a091a062 | 515 | to logic "0" when the transmitter has data to be sent. |
| igorsk | 0:1063a091a062 | 516 | - SET: The direction control pin will be driven |
| igorsk | 0:1063a091a062 | 517 | to logic "1" when the transmitter has data to be sent. */ |
| igorsk | 0:1063a091a062 | 518 | uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */ |
| igorsk | 0:1063a091a062 | 519 | uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */ |
| igorsk | 0:1063a091a062 | 520 | } UART1_RS485_CTRLCFG_Type; |
| igorsk | 0:1063a091a062 | 521 | |
| igorsk | 0:1063a091a062 | 522 | |
| igorsk | 0:1063a091a062 | 523 | /* UART call-back function type definitions */ |
| igorsk | 0:1063a091a062 | 524 | /** UART Receive Call-back function type */ |
| igorsk | 0:1063a091a062 | 525 | typedef void (fnRxCbs_Type)(void); |
| igorsk | 0:1063a091a062 | 526 | /** UART Transmit Call-back function type */ |
| igorsk | 0:1063a091a062 | 527 | typedef void (fnTxCbs_Type)(void); |
| igorsk | 0:1063a091a062 | 528 | /** UART Auto-Baudrate Call-back function type */ |
| igorsk | 0:1063a091a062 | 529 | typedef void (fnABCbs_Type)(uint32_t bABIntType); |
| igorsk | 0:1063a091a062 | 530 | /** UART Error Call-back function type */ |
| igorsk | 0:1063a091a062 | 531 | typedef void (fnErrCbs_Type)(uint8_t bError); |
| igorsk | 0:1063a091a062 | 532 | /** UART1 modem status interrupt callback type */ |
| igorsk | 0:1063a091a062 | 533 | typedef void (fnModemCbs_Type)(uint8_t ModemStatus); |
| igorsk | 0:1063a091a062 | 534 | |
| igorsk | 0:1063a091a062 | 535 | |
| igorsk | 0:1063a091a062 | 536 | /** |
| igorsk | 0:1063a091a062 | 537 | * @} |
| igorsk | 0:1063a091a062 | 538 | */ |
| igorsk | 0:1063a091a062 | 539 | |
| igorsk | 0:1063a091a062 | 540 | |
| igorsk | 0:1063a091a062 | 541 | /* Public Macros -------------------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 542 | /** @defgroup UART_Public_Macros |
| igorsk | 0:1063a091a062 | 543 | * @{ |
| igorsk | 0:1063a091a062 | 544 | */ |
| igorsk | 0:1063a091a062 | 545 | |
| igorsk | 0:1063a091a062 | 546 | |
| igorsk | 0:1063a091a062 | 547 | /* Macro to determine if it is valid UART port number */ |
| igorsk | 0:1063a091a062 | 548 | #define PARAM_UARTx(x) ((((uint32_t *)x)==((uint32_t *)LPC_UART0)) \ |
| igorsk | 0:1063a091a062 | 549 | || (((uint32_t *)x)==((uint32_t *)LPC_UART1)) \ |
| igorsk | 0:1063a091a062 | 550 | || (((uint32_t *)x)==((uint32_t *)LPC_UART2)) \ |
| igorsk | 0:1063a091a062 | 551 | || (((uint32_t *)x)==((uint32_t *)LPC_UART3))) |
| igorsk | 0:1063a091a062 | 552 | #define PARAM_UART_IrDA(x) (((uint32_t *)x)==((uint32_t *)LPC_UART3)) |
| igorsk | 0:1063a091a062 | 553 | #define PARAM_UART1_MODEM(x) (((uint32_t *)x)==((uint32_t *)LPC_UART1)) |
| igorsk | 0:1063a091a062 | 554 | |
| igorsk | 0:1063a091a062 | 555 | |
| igorsk | 0:1063a091a062 | 556 | /** Macro to check the input value for UART1_RS485_CFG_MATCHADDRVALUE parameter */ |
| igorsk | 0:1063a091a062 | 557 | #define PARAM_UART1_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF)) |
| igorsk | 0:1063a091a062 | 558 | |
| igorsk | 0:1063a091a062 | 559 | /** Macro to check the input value for UART1_RS485_CFG_DELAYVALUE parameter */ |
| igorsk | 0:1063a091a062 | 560 | #define PARAM_UART1_RS485_CFG_DELAYVALUE(x) ((x<0xFF)) |
| igorsk | 0:1063a091a062 | 561 | |
| igorsk | 0:1063a091a062 | 562 | |
| igorsk | 0:1063a091a062 | 563 | /** UART time-out definitions in case of using Read() and Write function |
| igorsk | 0:1063a091a062 | 564 | * with Blocking Flag mode |
| igorsk | 0:1063a091a062 | 565 | */ |
| igorsk | 0:1063a091a062 | 566 | |
| igorsk | 0:1063a091a062 | 567 | #define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL) |
| igorsk | 0:1063a091a062 | 568 | |
| igorsk | 0:1063a091a062 | 569 | /** |
| igorsk | 0:1063a091a062 | 570 | * @} |
| igorsk | 0:1063a091a062 | 571 | */ |
| igorsk | 0:1063a091a062 | 572 | |
| igorsk | 0:1063a091a062 | 573 | |
| igorsk | 0:1063a091a062 | 574 | /* Public Functions ----------------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 575 | /** @defgroup UART_Public_Functions |
| igorsk | 0:1063a091a062 | 576 | * @{ |
| igorsk | 0:1063a091a062 | 577 | */ |
| igorsk | 0:1063a091a062 | 578 | |
| igorsk | 0:1063a091a062 | 579 | void UART_DeInit(LPC_UART_TypeDef* UARTx); |
| igorsk | 0:1063a091a062 | 580 | void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct); |
| igorsk | 0:1063a091a062 | 581 | void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct); |
| igorsk | 0:1063a091a062 | 582 | void UART_SendData(LPC_UART_TypeDef* UARTx, uint8_t Data); |
| igorsk | 0:1063a091a062 | 583 | uint8_t UART_ReceiveData(LPC_UART_TypeDef* UARTx); |
| igorsk | 0:1063a091a062 | 584 | void UART_ForceBreak(LPC_UART_TypeDef* UARTx); |
| igorsk | 0:1063a091a062 | 585 | void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState); |
| igorsk | 0:1063a091a062 | 586 | void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState); |
| igorsk | 0:1063a091a062 | 587 | void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv); |
| igorsk | 0:1063a091a062 | 588 | void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, \ |
| igorsk | 0:1063a091a062 | 589 | FunctionalState NewState); |
| igorsk | 0:1063a091a062 | 590 | uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx); |
| igorsk | 0:1063a091a062 | 591 | FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx); |
| igorsk | 0:1063a091a062 | 592 | void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg); |
| igorsk | 0:1063a091a062 | 593 | void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct); |
| igorsk | 0:1063a091a062 | 594 | void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \ |
| igorsk | 0:1063a091a062 | 595 | FunctionalState NewState); |
| igorsk | 0:1063a091a062 | 596 | void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState); |
| igorsk | 0:1063a091a062 | 597 | void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \ |
| igorsk | 0:1063a091a062 | 598 | UART1_SignalState NewState); |
| igorsk | 0:1063a091a062 | 599 | void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \ |
| igorsk | 0:1063a091a062 | 600 | FunctionalState NewState); |
| igorsk | 0:1063a091a062 | 601 | uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx); |
| igorsk | 0:1063a091a062 | 602 | void UART_RS485Config(LPC_UART1_TypeDef *UARTx, \ |
| igorsk | 0:1063a091a062 | 603 | UART1_RS485_CTRLCFG_Type *RS485ConfigStruct); |
| igorsk | 0:1063a091a062 | 604 | void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState); |
| igorsk | 0:1063a091a062 | 605 | void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr); |
| igorsk | 0:1063a091a062 | 606 | uint32_t UART_RS485SendData(LPC_UART1_TypeDef *UARTx, uint8_t *pData, uint32_t size); |
| igorsk | 0:1063a091a062 | 607 | uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf, |
| igorsk | 0:1063a091a062 | 608 | uint32_t buflen, TRANSFER_BLOCK_Type flag); |
| igorsk | 0:1063a091a062 | 609 | uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \ |
| igorsk | 0:1063a091a062 | 610 | uint32_t buflen, TRANSFER_BLOCK_Type flag); |
| igorsk | 0:1063a091a062 | 611 | void UART_SetupCbs(LPC_UART_TypeDef *UARTx, uint8_t CbType, void *pfnCbs); |
| igorsk | 0:1063a091a062 | 612 | void UART0_StdIntHandler(void); |
| igorsk | 0:1063a091a062 | 613 | void UART1_StdIntHandler(void); |
| igorsk | 0:1063a091a062 | 614 | void UART2_StdIntHandler(void); |
| igorsk | 0:1063a091a062 | 615 | void UART3_StdIntHandler(void); |
| igorsk | 0:1063a091a062 | 616 | |
| igorsk | 0:1063a091a062 | 617 | /** |
| igorsk | 0:1063a091a062 | 618 | * @} |
| igorsk | 0:1063a091a062 | 619 | */ |
| igorsk | 0:1063a091a062 | 620 | |
| igorsk | 0:1063a091a062 | 621 | |
| igorsk | 0:1063a091a062 | 622 | #ifdef __cplusplus |
| igorsk | 0:1063a091a062 | 623 | } |
| igorsk | 0:1063a091a062 | 624 | #endif |
| igorsk | 0:1063a091a062 | 625 | |
| igorsk | 0:1063a091a062 | 626 | |
| igorsk | 0:1063a091a062 | 627 | #endif /* __LPC17XX_UART_H */ |
| igorsk | 0:1063a091a062 | 628 | |
| igorsk | 0:1063a091a062 | 629 | /** |
| igorsk | 0:1063a091a062 | 630 | * @} |
| igorsk | 0:1063a091a062 | 631 | */ |
| igorsk | 0:1063a091a062 | 632 | |
| igorsk | 0:1063a091a062 | 633 | /* --------------------------------- End Of File ------------------------------ */ |