NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip
include/lpc17xx_ssp.h@0:1063a091a062, 2010-02-17 (annotated)
- Committer:
- igorsk
- Date:
- Wed Feb 17 16:22:39 2010 +0000
- Revision:
- 0:1063a091a062
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
igorsk | 0:1063a091a062 | 1 | /***********************************************************************//** |
igorsk | 0:1063a091a062 | 2 | * @file : lpc17xx_ssp.h |
igorsk | 0:1063a091a062 | 3 | * @brief : Contains all macro definitions and function prototypes |
igorsk | 0:1063a091a062 | 4 | * support for SSP firmware library on LPC17xx |
igorsk | 0:1063a091a062 | 5 | * @version : 1.0 |
igorsk | 0:1063a091a062 | 6 | * @date : 9. April. 2009 |
igorsk | 0:1063a091a062 | 7 | * @author : HieuNguyen |
igorsk | 0:1063a091a062 | 8 | ************************************************************************** |
igorsk | 0:1063a091a062 | 9 | * Software that is described herein is for illustrative purposes only |
igorsk | 0:1063a091a062 | 10 | * which provides customers with programming information regarding the |
igorsk | 0:1063a091a062 | 11 | * products. This software is supplied "AS IS" without any warranties. |
igorsk | 0:1063a091a062 | 12 | * NXP Semiconductors assumes no responsibility or liability for the |
igorsk | 0:1063a091a062 | 13 | * use of the software, conveys no license or title under any patent, |
igorsk | 0:1063a091a062 | 14 | * copyright, or mask work right to the product. NXP Semiconductors |
igorsk | 0:1063a091a062 | 15 | * reserves the right to make changes in the software without |
igorsk | 0:1063a091a062 | 16 | * notification. NXP Semiconductors also make no representation or |
igorsk | 0:1063a091a062 | 17 | * warranty that such application will be suitable for the specified |
igorsk | 0:1063a091a062 | 18 | * use without further testing or modification. |
igorsk | 0:1063a091a062 | 19 | **************************************************************************/ |
igorsk | 0:1063a091a062 | 20 | |
igorsk | 0:1063a091a062 | 21 | /* Peripheral group ----------------------------------------------------------- */ |
igorsk | 0:1063a091a062 | 22 | /** @defgroup SSP |
igorsk | 0:1063a091a062 | 23 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
igorsk | 0:1063a091a062 | 24 | * @{ |
igorsk | 0:1063a091a062 | 25 | */ |
igorsk | 0:1063a091a062 | 26 | |
igorsk | 0:1063a091a062 | 27 | #ifndef LPC17XX_SSP_H_ |
igorsk | 0:1063a091a062 | 28 | #define LPC17XX_SSP_H_ |
igorsk | 0:1063a091a062 | 29 | |
igorsk | 0:1063a091a062 | 30 | /* Includes ------------------------------------------------------------------- */ |
igorsk | 0:1063a091a062 | 31 | #include "cmsis.h" |
igorsk | 0:1063a091a062 | 32 | #include "lpc_types.h" |
igorsk | 0:1063a091a062 | 33 | |
igorsk | 0:1063a091a062 | 34 | |
igorsk | 0:1063a091a062 | 35 | #ifdef __cplusplus |
igorsk | 0:1063a091a062 | 36 | extern "C" |
igorsk | 0:1063a091a062 | 37 | { |
igorsk | 0:1063a091a062 | 38 | #endif |
igorsk | 0:1063a091a062 | 39 | |
igorsk | 0:1063a091a062 | 40 | |
igorsk | 0:1063a091a062 | 41 | /* Private Macros ------------------------------------------------------------- */ |
igorsk | 0:1063a091a062 | 42 | /** @defgroup SSP_Private_Macros |
igorsk | 0:1063a091a062 | 43 | * @{ |
igorsk | 0:1063a091a062 | 44 | */ |
igorsk | 0:1063a091a062 | 45 | |
igorsk | 0:1063a091a062 | 46 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 47 | * Macro defines for CR0 register |
igorsk | 0:1063a091a062 | 48 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 49 | |
igorsk | 0:1063a091a062 | 50 | /** @defgroup SSP_REGISTER_BIT_DEFINITION |
igorsk | 0:1063a091a062 | 51 | * @{ |
igorsk | 0:1063a091a062 | 52 | */ |
igorsk | 0:1063a091a062 | 53 | |
igorsk | 0:1063a091a062 | 54 | /** SSP data size select, must be 4 bits to 16 bits */ |
igorsk | 0:1063a091a062 | 55 | #define SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF)) |
igorsk | 0:1063a091a062 | 56 | /** SSP control 0 Motorola SPI mode */ |
igorsk | 0:1063a091a062 | 57 | #define SSP_CR0_FRF_SPI ((uint32_t)(0<<4)) |
igorsk | 0:1063a091a062 | 58 | /** SSP control 0 TI synchronous serial mode */ |
igorsk | 0:1063a091a062 | 59 | #define SSP_CR0_FRF_TI ((uint32_t)(1<<4)) |
igorsk | 0:1063a091a062 | 60 | /** SSP control 0 National Micro-wire mode */ |
igorsk | 0:1063a091a062 | 61 | #define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4)) |
igorsk | 0:1063a091a062 | 62 | /** SPI clock polarity bit (used in SPI mode only), (1) = maintains the |
igorsk | 0:1063a091a062 | 63 | bus clock high between frames, (0) = low */ |
igorsk | 0:1063a091a062 | 64 | #define SSP_CR0_CPOL_HI ((uint32_t)(1<<6)) |
igorsk | 0:1063a091a062 | 65 | /** SPI clock out phase bit (used in SPI mode only), (1) = captures data |
igorsk | 0:1063a091a062 | 66 | on the second clock transition of the frame, (0) = first */ |
igorsk | 0:1063a091a062 | 67 | #define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7)) |
igorsk | 0:1063a091a062 | 68 | /** SSP serial clock rate value load macro, divider rate is |
igorsk | 0:1063a091a062 | 69 | PERIPH_CLK / (cpsr * (SCR + 1)) */ |
igorsk | 0:1063a091a062 | 70 | #define SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8)) |
igorsk | 0:1063a091a062 | 71 | /** SSP CR0 bit mask */ |
igorsk | 0:1063a091a062 | 72 | #define SSP_CR0_BITMASK ((uint32_t)(0xFFFF)) |
igorsk | 0:1063a091a062 | 73 | |
igorsk | 0:1063a091a062 | 74 | |
igorsk | 0:1063a091a062 | 75 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 76 | * Macro defines for CR1 register |
igorsk | 0:1063a091a062 | 77 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 78 | /** SSP control 1 loopback mode enable bit */ |
igorsk | 0:1063a091a062 | 79 | #define SSP_CR1_LBM_EN ((uint32_t)(1<<0)) |
igorsk | 0:1063a091a062 | 80 | /** SSP control 1 enable bit */ |
igorsk | 0:1063a091a062 | 81 | #define SSP_CR1_SSP_EN ((uint32_t)(1<<1)) |
igorsk | 0:1063a091a062 | 82 | /** SSP control 1 slave enable */ |
igorsk | 0:1063a091a062 | 83 | #define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2)) |
igorsk | 0:1063a091a062 | 84 | /** SSP control 1 slave out disable bit, disables transmit line in slave |
igorsk | 0:1063a091a062 | 85 | mode */ |
igorsk | 0:1063a091a062 | 86 | #define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3)) |
igorsk | 0:1063a091a062 | 87 | /** SSP CR1 bit mask */ |
igorsk | 0:1063a091a062 | 88 | #define SSP_CR1_BITMASK ((uint32_t)(0x0F)) |
igorsk | 0:1063a091a062 | 89 | |
igorsk | 0:1063a091a062 | 90 | |
igorsk | 0:1063a091a062 | 91 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 92 | * Macro defines for DR register |
igorsk | 0:1063a091a062 | 93 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 94 | /** SSP data bit mask */ |
igorsk | 0:1063a091a062 | 95 | #define SSP_DR_BITMASK(n) ((n)&0xFFFF) |
igorsk | 0:1063a091a062 | 96 | |
igorsk | 0:1063a091a062 | 97 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 98 | * Macro defines for SR register |
igorsk | 0:1063a091a062 | 99 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 100 | /** SSP status TX FIFO Empty bit */ |
igorsk | 0:1063a091a062 | 101 | #define SSP_SR_TFE ((uint32_t)(1<<0)) |
igorsk | 0:1063a091a062 | 102 | /** SSP status TX FIFO not full bit */ |
igorsk | 0:1063a091a062 | 103 | #define SSP_SR_TNF ((uint32_t)(1<<1)) |
igorsk | 0:1063a091a062 | 104 | /** SSP status RX FIFO not empty bit */ |
igorsk | 0:1063a091a062 | 105 | #define SSP_SR_RNE ((uint32_t)(1<<2)) |
igorsk | 0:1063a091a062 | 106 | /** SSP status RX FIFO full bit */ |
igorsk | 0:1063a091a062 | 107 | #define SSP_SR_RFF ((uint32_t)(1<<3)) |
igorsk | 0:1063a091a062 | 108 | /** SSP status SSP Busy bit */ |
igorsk | 0:1063a091a062 | 109 | #define SSP_SR_BSY ((uint32_t)(1<<4)) |
igorsk | 0:1063a091a062 | 110 | /** SSP SR bit mask */ |
igorsk | 0:1063a091a062 | 111 | #define SSP_SR_BITMASK ((uint32_t)(0x1F)) |
igorsk | 0:1063a091a062 | 112 | |
igorsk | 0:1063a091a062 | 113 | |
igorsk | 0:1063a091a062 | 114 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 115 | * Macro defines for CPSR register |
igorsk | 0:1063a091a062 | 116 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 117 | /** SSP clock prescaler */ |
igorsk | 0:1063a091a062 | 118 | #define SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF)) |
igorsk | 0:1063a091a062 | 119 | /** SSP CPSR bit mask */ |
igorsk | 0:1063a091a062 | 120 | #define SSP_CPSR_BITMASK ((uint32_t)(0xFF)) |
igorsk | 0:1063a091a062 | 121 | |
igorsk | 0:1063a091a062 | 122 | |
igorsk | 0:1063a091a062 | 123 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 124 | * Macro define for (IMSC) Interrupt Mask Set/Clear registers |
igorsk | 0:1063a091a062 | 125 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 126 | /** Receive Overrun */ |
igorsk | 0:1063a091a062 | 127 | #define SSP_IMSC_ROR ((uint32_t)(1<<0)) |
igorsk | 0:1063a091a062 | 128 | /** Receive TimeOut */ |
igorsk | 0:1063a091a062 | 129 | #define SSP_IMSC_RT ((uint32_t)(1<<1)) |
igorsk | 0:1063a091a062 | 130 | /** Rx FIFO is at least half full */ |
igorsk | 0:1063a091a062 | 131 | #define SSP_IMSC_RX ((uint32_t)(1<<2)) |
igorsk | 0:1063a091a062 | 132 | /** Tx FIFO is at least half empty */ |
igorsk | 0:1063a091a062 | 133 | #define SSP_IMSC_TX ((uint32_t)(1<<3)) |
igorsk | 0:1063a091a062 | 134 | /** IMSC bit mask */ |
igorsk | 0:1063a091a062 | 135 | #define SSP_IMSC_BITMASK ((uint32_t)(0x0F)) |
igorsk | 0:1063a091a062 | 136 | |
igorsk | 0:1063a091a062 | 137 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 138 | * Macro define for (RIS) Raw Interrupt Status registers |
igorsk | 0:1063a091a062 | 139 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 140 | /** Receive Overrun */ |
igorsk | 0:1063a091a062 | 141 | #define SSP_RIS_ROR ((uint32_t)(1<<0)) |
igorsk | 0:1063a091a062 | 142 | /** Receive TimeOut */ |
igorsk | 0:1063a091a062 | 143 | #define SSP_RIS_RT ((uint32_t)(1<<1)) |
igorsk | 0:1063a091a062 | 144 | /** Rx FIFO is at least half full */ |
igorsk | 0:1063a091a062 | 145 | #define SSP_RIS_RX ((uint32_t)(1<<2)) |
igorsk | 0:1063a091a062 | 146 | /** Tx FIFO is at least half empty */ |
igorsk | 0:1063a091a062 | 147 | #define SSP_RIS_TX ((uint32_t)(1<<3)) |
igorsk | 0:1063a091a062 | 148 | /** RIS bit mask */ |
igorsk | 0:1063a091a062 | 149 | #define SSP_RIS_BITMASK ((uint32_t)(0x0F)) |
igorsk | 0:1063a091a062 | 150 | |
igorsk | 0:1063a091a062 | 151 | |
igorsk | 0:1063a091a062 | 152 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 153 | * Macro define for (MIS) Masked Interrupt Status registers |
igorsk | 0:1063a091a062 | 154 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 155 | /** Receive Overrun */ |
igorsk | 0:1063a091a062 | 156 | #define SSP_MIS_ROR ((uint32_t)(1<<0)) |
igorsk | 0:1063a091a062 | 157 | /** Receive TimeOut */ |
igorsk | 0:1063a091a062 | 158 | #define SSP_MIS_RT ((uint32_t)(1<<1)) |
igorsk | 0:1063a091a062 | 159 | /** Rx FIFO is at least half full */ |
igorsk | 0:1063a091a062 | 160 | #define SSP_MIS_RX ((uint32_t)(1<<2)) |
igorsk | 0:1063a091a062 | 161 | /** Tx FIFO is at least half empty */ |
igorsk | 0:1063a091a062 | 162 | #define SSP_MIS_TX ((uint32_t)(1<<3)) |
igorsk | 0:1063a091a062 | 163 | /** MIS bit mask */ |
igorsk | 0:1063a091a062 | 164 | #define SSP_MIS_BITMASK ((uint32_t)(0x0F)) |
igorsk | 0:1063a091a062 | 165 | |
igorsk | 0:1063a091a062 | 166 | |
igorsk | 0:1063a091a062 | 167 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 168 | * Macro define for (ICR) Interrupt Clear registers |
igorsk | 0:1063a091a062 | 169 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 170 | /** Writing a 1 to this bit clears the "frame was received when |
igorsk | 0:1063a091a062 | 171 | * RxFIFO was full" interrupt */ |
igorsk | 0:1063a091a062 | 172 | #define SSP_ICR_ROR ((uint32_t)(1<<0)) |
igorsk | 0:1063a091a062 | 173 | /** Writing a 1 to this bit clears the "Rx FIFO was not empty and |
igorsk | 0:1063a091a062 | 174 | * has not been read for a timeout period" interrupt */ |
igorsk | 0:1063a091a062 | 175 | #define SSP_ICR_RT ((uint32_t)(1<<1)) |
igorsk | 0:1063a091a062 | 176 | /** ICR bit mask */ |
igorsk | 0:1063a091a062 | 177 | #define SSP_ICR_BITMASK ((uint32_t)(0x03)) |
igorsk | 0:1063a091a062 | 178 | |
igorsk | 0:1063a091a062 | 179 | |
igorsk | 0:1063a091a062 | 180 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 181 | * Macro defines for DMACR register |
igorsk | 0:1063a091a062 | 182 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 183 | /** SSP bit for enabling RX DMA */ |
igorsk | 0:1063a091a062 | 184 | #define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0)) |
igorsk | 0:1063a091a062 | 185 | /** SSP bit for enabling TX DMA */ |
igorsk | 0:1063a091a062 | 186 | #define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1)) |
igorsk | 0:1063a091a062 | 187 | /** DMACR bit mask */ |
igorsk | 0:1063a091a062 | 188 | #define SSP_DMA_BITMASK ((uint32_t)(0x03)) |
igorsk | 0:1063a091a062 | 189 | |
igorsk | 0:1063a091a062 | 190 | /** |
igorsk | 0:1063a091a062 | 191 | * @} |
igorsk | 0:1063a091a062 | 192 | */ |
igorsk | 0:1063a091a062 | 193 | |
igorsk | 0:1063a091a062 | 194 | /** |
igorsk | 0:1063a091a062 | 195 | * @} |
igorsk | 0:1063a091a062 | 196 | */ |
igorsk | 0:1063a091a062 | 197 | |
igorsk | 0:1063a091a062 | 198 | |
igorsk | 0:1063a091a062 | 199 | /* Public Types --------------------------------------------------------------- */ |
igorsk | 0:1063a091a062 | 200 | /** @defgroup SSP_Public_Types |
igorsk | 0:1063a091a062 | 201 | * @{ |
igorsk | 0:1063a091a062 | 202 | */ |
igorsk | 0:1063a091a062 | 203 | |
igorsk | 0:1063a091a062 | 204 | /** @brief SSP configuration structure */ |
igorsk | 0:1063a091a062 | 205 | typedef struct { |
igorsk | 0:1063a091a062 | 206 | uint32_t Databit; /** Databit number, should be SSP_DATABIT_x, |
igorsk | 0:1063a091a062 | 207 | where x is in range from 4 - 16 */ |
igorsk | 0:1063a091a062 | 208 | uint32_t CPHA; /** Clock phase, should be: |
igorsk | 0:1063a091a062 | 209 | - SSP_CPHA_FIRST: first clock edge |
igorsk | 0:1063a091a062 | 210 | - SSP_CPHA_SECOND: second clock edge */ |
igorsk | 0:1063a091a062 | 211 | uint32_t CPOL; /** Clock polarity, should be: |
igorsk | 0:1063a091a062 | 212 | - SSP_CPOL_HI: high level |
igorsk | 0:1063a091a062 | 213 | - SSP_CPOL_LO: low level */ |
igorsk | 0:1063a091a062 | 214 | uint32_t Mode; /** SSP mode, should be: |
igorsk | 0:1063a091a062 | 215 | - SSP_MASTER_MODE: Master mode |
igorsk | 0:1063a091a062 | 216 | - SSP_SLAVE_MODE: Slave mode */ |
igorsk | 0:1063a091a062 | 217 | uint32_t FrameFormat; /** Frame Format: |
igorsk | 0:1063a091a062 | 218 | - SSP_FRAME_SPI: Motorola SPI frame format |
igorsk | 0:1063a091a062 | 219 | - SSP_FRAME_TI: TI frame format |
igorsk | 0:1063a091a062 | 220 | - SSP_FRAME_MICROWIRE: National Microwire frame format */ |
igorsk | 0:1063a091a062 | 221 | uint32_t ClockRate; /** Clock rate,in Hz */ |
igorsk | 0:1063a091a062 | 222 | } SSP_CFG_Type; |
igorsk | 0:1063a091a062 | 223 | |
igorsk | 0:1063a091a062 | 224 | /** |
igorsk | 0:1063a091a062 | 225 | * @brief SSP Transfer Type definitions |
igorsk | 0:1063a091a062 | 226 | */ |
igorsk | 0:1063a091a062 | 227 | typedef enum { |
igorsk | 0:1063a091a062 | 228 | SSP_TRANSFER_POLLING = 0, /**< Polling transfer */ |
igorsk | 0:1063a091a062 | 229 | SSP_TRANSFER_INTERRUPT /**< Interrupt transfer */ |
igorsk | 0:1063a091a062 | 230 | } SSP_TRANSFER_Type; |
igorsk | 0:1063a091a062 | 231 | |
igorsk | 0:1063a091a062 | 232 | /** |
igorsk | 0:1063a091a062 | 233 | * @brief SPI Data configuration structure definitions |
igorsk | 0:1063a091a062 | 234 | */ |
igorsk | 0:1063a091a062 | 235 | typedef struct { |
igorsk | 0:1063a091a062 | 236 | void *tx_data; /**< Pointer to transmit data */ |
igorsk | 0:1063a091a062 | 237 | uint32_t tx_cnt; /**< Transmit counter */ |
igorsk | 0:1063a091a062 | 238 | void *rx_data; /**< Pointer to transmit data */ |
igorsk | 0:1063a091a062 | 239 | uint32_t rx_cnt; /**< Receive counter */ |
igorsk | 0:1063a091a062 | 240 | uint32_t length; /**< Length of transfer data */ |
igorsk | 0:1063a091a062 | 241 | uint32_t status; /**< Current status of SSP activity */ |
igorsk | 0:1063a091a062 | 242 | void (*callback)(void); /**< Pointer to Call back function when transmission complete |
igorsk | 0:1063a091a062 | 243 | used in interrupt transfer mode */ |
igorsk | 0:1063a091a062 | 244 | } SSP_DATA_SETUP_Type; |
igorsk | 0:1063a091a062 | 245 | |
igorsk | 0:1063a091a062 | 246 | |
igorsk | 0:1063a091a062 | 247 | /** |
igorsk | 0:1063a091a062 | 248 | * @} |
igorsk | 0:1063a091a062 | 249 | */ |
igorsk | 0:1063a091a062 | 250 | |
igorsk | 0:1063a091a062 | 251 | |
igorsk | 0:1063a091a062 | 252 | /* Public Macros -------------------------------------------------------------- */ |
igorsk | 0:1063a091a062 | 253 | /** @defgroup SSP_Public_Macros |
igorsk | 0:1063a091a062 | 254 | * @{ |
igorsk | 0:1063a091a062 | 255 | */ |
igorsk | 0:1063a091a062 | 256 | |
igorsk | 0:1063a091a062 | 257 | /** Macro to determine if it is valid SSP port number */ |
igorsk | 0:1063a091a062 | 258 | #define PARAM_SSPx(n) ((((uint32_t *)n)==((uint32_t *)LPC_SSP0)) \ |
igorsk | 0:1063a091a062 | 259 | || (((uint32_t *)n)==((uint32_t *)LPC_SSP1))) |
igorsk | 0:1063a091a062 | 260 | |
igorsk | 0:1063a091a062 | 261 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 262 | * SSP configuration parameter defines |
igorsk | 0:1063a091a062 | 263 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 264 | /** Clock phase control bit */ |
igorsk | 0:1063a091a062 | 265 | #define SSP_CPHA_FIRST ((uint32_t)(0)) |
igorsk | 0:1063a091a062 | 266 | #define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND |
igorsk | 0:1063a091a062 | 267 | #define PARAM_SSP_CPHA(n) ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND)) |
igorsk | 0:1063a091a062 | 268 | |
igorsk | 0:1063a091a062 | 269 | /** Clock polarity control bit */ |
igorsk | 0:1063a091a062 | 270 | /* There's no bug here!!! |
igorsk | 0:1063a091a062 | 271 | * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames. |
igorsk | 0:1063a091a062 | 272 | * That means the active clock is in HI state. |
igorsk | 0:1063a091a062 | 273 | * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock |
igorsk | 0:1063a091a062 | 274 | * high between frames. That means the active clock is in LO state. |
igorsk | 0:1063a091a062 | 275 | */ |
igorsk | 0:1063a091a062 | 276 | #define SSP_CPOL_HI ((uint32_t)(0)) |
igorsk | 0:1063a091a062 | 277 | #define SSP_CPOL_LO SSP_CR0_CPOL_HI |
igorsk | 0:1063a091a062 | 278 | #define PARAM_SSP_CPOL(n) ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO)) |
igorsk | 0:1063a091a062 | 279 | |
igorsk | 0:1063a091a062 | 280 | /** SSP master mode enable */ |
igorsk | 0:1063a091a062 | 281 | #define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN |
igorsk | 0:1063a091a062 | 282 | #define SSP_MASTER_MODE ((uint32_t)(0)) |
igorsk | 0:1063a091a062 | 283 | #define PARAM_SSP_MODE(n) ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE)) |
igorsk | 0:1063a091a062 | 284 | |
igorsk | 0:1063a091a062 | 285 | /** SSP data bit number defines */ |
igorsk | 0:1063a091a062 | 286 | #define SSP_DATABIT_4 SSP_CR0_DSS(4) /*!< Databit number = 4 */ |
igorsk | 0:1063a091a062 | 287 | #define SSP_DATABIT_5 SSP_CR0_DSS(5) /*!< Databit number = 5 */ |
igorsk | 0:1063a091a062 | 288 | #define SSP_DATABIT_6 SSP_CR0_DSS(6) /*!< Databit number = 6 */ |
igorsk | 0:1063a091a062 | 289 | #define SSP_DATABIT_7 SSP_CR0_DSS(7) /*!< Databit number = 7 */ |
igorsk | 0:1063a091a062 | 290 | #define SSP_DATABIT_8 SSP_CR0_DSS(8) /*!< Databit number = 8 */ |
igorsk | 0:1063a091a062 | 291 | #define SSP_DATABIT_9 SSP_CR0_DSS(9) /*!< Databit number = 9 */ |
igorsk | 0:1063a091a062 | 292 | #define SSP_DATABIT_10 SSP_CR0_DSS(10) /*!< Databit number = 10 */ |
igorsk | 0:1063a091a062 | 293 | #define SSP_DATABIT_11 SSP_CR0_DSS(11) /*!< Databit number = 11 */ |
igorsk | 0:1063a091a062 | 294 | #define SSP_DATABIT_12 SSP_CR0_DSS(12) /*!< Databit number = 12 */ |
igorsk | 0:1063a091a062 | 295 | #define SSP_DATABIT_13 SSP_CR0_DSS(13) /*!< Databit number = 13 */ |
igorsk | 0:1063a091a062 | 296 | #define SSP_DATABIT_14 SSP_CR0_DSS(14) /*!< Databit number = 14 */ |
igorsk | 0:1063a091a062 | 297 | #define SSP_DATABIT_15 SSP_CR0_DSS(15) /*!< Databit number = 15 */ |
igorsk | 0:1063a091a062 | 298 | #define SSP_DATABIT_16 SSP_CR0_DSS(16) /*!< Databit number = 16 */ |
igorsk | 0:1063a091a062 | 299 | #define PARAM_SSP_DATABIT(n) ((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \ |
igorsk | 0:1063a091a062 | 300 | || (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \ |
igorsk | 0:1063a091a062 | 301 | || (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \ |
igorsk | 0:1063a091a062 | 302 | || (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \ |
igorsk | 0:1063a091a062 | 303 | || (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \ |
igorsk | 0:1063a091a062 | 304 | || (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \ |
igorsk | 0:1063a091a062 | 305 | || (n==SSP_DATABIT_15)) |
igorsk | 0:1063a091a062 | 306 | |
igorsk | 0:1063a091a062 | 307 | /** SSP Frame Format definition */ |
igorsk | 0:1063a091a062 | 308 | /** Motorola SPI mode */ |
igorsk | 0:1063a091a062 | 309 | #define SSP_FRAME_SPI SSP_CR0_FRF_SPI |
igorsk | 0:1063a091a062 | 310 | /** TI synchronous serial mode */ |
igorsk | 0:1063a091a062 | 311 | #define SSP_FRAME_TI SSP_CR0_FRF_TI |
igorsk | 0:1063a091a062 | 312 | /** National Micro-wire mode */ |
igorsk | 0:1063a091a062 | 313 | #define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE |
igorsk | 0:1063a091a062 | 314 | |
igorsk | 0:1063a091a062 | 315 | #define PARAM_SSP_FRAME(n) ((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\ |
igorsk | 0:1063a091a062 | 316 | || (n==SSP_FRAME_MICROWIRE)) |
igorsk | 0:1063a091a062 | 317 | |
igorsk | 0:1063a091a062 | 318 | |
igorsk | 0:1063a091a062 | 319 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 320 | * SSP Status defines |
igorsk | 0:1063a091a062 | 321 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 322 | /** SSP status TX FIFO Empty bit */ |
igorsk | 0:1063a091a062 | 323 | #define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE |
igorsk | 0:1063a091a062 | 324 | /** SSP status TX FIFO not full bit */ |
igorsk | 0:1063a091a062 | 325 | #define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF |
igorsk | 0:1063a091a062 | 326 | /** SSP status RX FIFO not empty bit */ |
igorsk | 0:1063a091a062 | 327 | #define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE |
igorsk | 0:1063a091a062 | 328 | /** SSP status RX FIFO full bit */ |
igorsk | 0:1063a091a062 | 329 | #define SSP_STAT_RXFIFO_FULL SSP_SR_RFF |
igorsk | 0:1063a091a062 | 330 | /** SSP status SSP Busy bit */ |
igorsk | 0:1063a091a062 | 331 | #define SSP_STAT_BUSY SSP_SR_BSY |
igorsk | 0:1063a091a062 | 332 | |
igorsk | 0:1063a091a062 | 333 | #define PARAM_SSP_STAT(n) ((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \ |
igorsk | 0:1063a091a062 | 334 | || (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \ |
igorsk | 0:1063a091a062 | 335 | || (n==SSP_STAT_BUSY)) |
igorsk | 0:1063a091a062 | 336 | |
igorsk | 0:1063a091a062 | 337 | |
igorsk | 0:1063a091a062 | 338 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 339 | * SSP Interrupt Configuration defines |
igorsk | 0:1063a091a062 | 340 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 341 | /** Receive Overrun */ |
igorsk | 0:1063a091a062 | 342 | #define SSP_INTCFG_ROR SSP_IMSC_ROR |
igorsk | 0:1063a091a062 | 343 | /** Receive TimeOut */ |
igorsk | 0:1063a091a062 | 344 | #define SSP_INTCFG_RT SSP_IMSC_RT |
igorsk | 0:1063a091a062 | 345 | /** Rx FIFO is at least half full */ |
igorsk | 0:1063a091a062 | 346 | #define SSP_INTCFG_RX SSP_IMSC_RX |
igorsk | 0:1063a091a062 | 347 | /** Tx FIFO is at least half empty */ |
igorsk | 0:1063a091a062 | 348 | #define SSP_INTCFG_TX SSP_IMSC_TX |
igorsk | 0:1063a091a062 | 349 | |
igorsk | 0:1063a091a062 | 350 | #define PARAM_SSP_INTCFG(n) ((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \ |
igorsk | 0:1063a091a062 | 351 | || (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX)) |
igorsk | 0:1063a091a062 | 352 | |
igorsk | 0:1063a091a062 | 353 | |
igorsk | 0:1063a091a062 | 354 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 355 | * SSP Configured Interrupt Status defines |
igorsk | 0:1063a091a062 | 356 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 357 | /** Receive Overrun */ |
igorsk | 0:1063a091a062 | 358 | #define SSP_INTSTAT_ROR SSP_MIS_ROR |
igorsk | 0:1063a091a062 | 359 | /** Receive TimeOut */ |
igorsk | 0:1063a091a062 | 360 | #define SSP_INTSTAT_RT SSP_MIS_RT |
igorsk | 0:1063a091a062 | 361 | /** Rx FIFO is at least half full */ |
igorsk | 0:1063a091a062 | 362 | #define SSP_INTSTAT_RX SSP_MIS_RX |
igorsk | 0:1063a091a062 | 363 | /** Tx FIFO is at least half empty */ |
igorsk | 0:1063a091a062 | 364 | #define SSP_INTSTAT_TX SSP_MIS_TX |
igorsk | 0:1063a091a062 | 365 | |
igorsk | 0:1063a091a062 | 366 | #define PARAM_SSP_INTSTAT(n) ((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \ |
igorsk | 0:1063a091a062 | 367 | || (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX)) |
igorsk | 0:1063a091a062 | 368 | |
igorsk | 0:1063a091a062 | 369 | |
igorsk | 0:1063a091a062 | 370 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 371 | * SSP Raw Interrupt Status defines |
igorsk | 0:1063a091a062 | 372 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 373 | /** Receive Overrun */ |
igorsk | 0:1063a091a062 | 374 | #define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR |
igorsk | 0:1063a091a062 | 375 | /** Receive TimeOut */ |
igorsk | 0:1063a091a062 | 376 | #define SSP_INTSTAT_RAW_RT SSP_RIS_RT |
igorsk | 0:1063a091a062 | 377 | /** Rx FIFO is at least half full */ |
igorsk | 0:1063a091a062 | 378 | #define SSP_INTSTAT_RAW_RX SSP_RIS_RX |
igorsk | 0:1063a091a062 | 379 | /** Tx FIFO is at least half empty */ |
igorsk | 0:1063a091a062 | 380 | #define SSP_INTSTAT_RAW_TX SSP_RIS_TX |
igorsk | 0:1063a091a062 | 381 | |
igorsk | 0:1063a091a062 | 382 | #define PARAM_SSP_INTSTAT_RAW(n) ((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \ |
igorsk | 0:1063a091a062 | 383 | || (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX)) |
igorsk | 0:1063a091a062 | 384 | |
igorsk | 0:1063a091a062 | 385 | |
igorsk | 0:1063a091a062 | 386 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 387 | * SSP Interrupt Clear defines |
igorsk | 0:1063a091a062 | 388 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 389 | /** Writing a 1 to this bit clears the "frame was received when |
igorsk | 0:1063a091a062 | 390 | * RxFIFO was full" interrupt */ |
igorsk | 0:1063a091a062 | 391 | #define SSP_INTCLR_ROR SSP_ICR_ROR |
igorsk | 0:1063a091a062 | 392 | /** Writing a 1 to this bit clears the "Rx FIFO was not empty and |
igorsk | 0:1063a091a062 | 393 | * has not been read for a timeout period" interrupt */ |
igorsk | 0:1063a091a062 | 394 | #define SSP_INTCLR_RT SSP_ICR_RT |
igorsk | 0:1063a091a062 | 395 | |
igorsk | 0:1063a091a062 | 396 | #define PARAM_SSP_INTCLR(n) ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT)) |
igorsk | 0:1063a091a062 | 397 | |
igorsk | 0:1063a091a062 | 398 | |
igorsk | 0:1063a091a062 | 399 | /*********************************************************************//** |
igorsk | 0:1063a091a062 | 400 | * SSP DMA defines |
igorsk | 0:1063a091a062 | 401 | **********************************************************************/ |
igorsk | 0:1063a091a062 | 402 | /** SSP bit for enabling RX DMA */ |
igorsk | 0:1063a091a062 | 403 | #define SSP_DMA_TX SSP_DMA_RXDMA_EN |
igorsk | 0:1063a091a062 | 404 | /** SSP bit for enabling TX DMA */ |
igorsk | 0:1063a091a062 | 405 | #define SSP_DMA_RX SSP_DMA_TXDMA_EN |
igorsk | 0:1063a091a062 | 406 | |
igorsk | 0:1063a091a062 | 407 | #define PARAM_SSP_DMA(n) ((n==SSP_DMA_TX) || (n==SSP_DMA_RX)) |
igorsk | 0:1063a091a062 | 408 | |
igorsk | 0:1063a091a062 | 409 | /* SSP Status Implementation definitions */ |
igorsk | 0:1063a091a062 | 410 | #define SSP_STAT_DONE (1UL<<8) /**< Done */ |
igorsk | 0:1063a091a062 | 411 | #define SSP_STAT_ERROR (1UL<<9) /**< Error */ |
igorsk | 0:1063a091a062 | 412 | |
igorsk | 0:1063a091a062 | 413 | /** |
igorsk | 0:1063a091a062 | 414 | * @} |
igorsk | 0:1063a091a062 | 415 | */ |
igorsk | 0:1063a091a062 | 416 | |
igorsk | 0:1063a091a062 | 417 | |
igorsk | 0:1063a091a062 | 418 | /* Public Functions ----------------------------------------------------------- */ |
igorsk | 0:1063a091a062 | 419 | /** @defgroup SSP_Public_Functions |
igorsk | 0:1063a091a062 | 420 | * @{ |
igorsk | 0:1063a091a062 | 421 | */ |
igorsk | 0:1063a091a062 | 422 | |
igorsk | 0:1063a091a062 | 423 | void SSP_SetClock (LPC_SSP_TypeDef *SSPx, uint32_t target_clock); |
igorsk | 0:1063a091a062 | 424 | void SSP_DeInit(LPC_SSP_TypeDef* SSPx); |
igorsk | 0:1063a091a062 | 425 | void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct); |
igorsk | 0:1063a091a062 | 426 | void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct); |
igorsk | 0:1063a091a062 | 427 | void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState); |
igorsk | 0:1063a091a062 | 428 | void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState); |
igorsk | 0:1063a091a062 | 429 | void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState); |
igorsk | 0:1063a091a062 | 430 | void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data); |
igorsk | 0:1063a091a062 | 431 | uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx); |
igorsk | 0:1063a091a062 | 432 | int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \ |
igorsk | 0:1063a091a062 | 433 | SSP_TRANSFER_Type xfType); |
igorsk | 0:1063a091a062 | 434 | FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType); |
igorsk | 0:1063a091a062 | 435 | void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState); |
igorsk | 0:1063a091a062 | 436 | IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType); |
igorsk | 0:1063a091a062 | 437 | IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType); |
igorsk | 0:1063a091a062 | 438 | void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType); |
igorsk | 0:1063a091a062 | 439 | void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState); |
igorsk | 0:1063a091a062 | 440 | void SSP0_StdIntHandler(void); |
igorsk | 0:1063a091a062 | 441 | void SSP1_StdIntHandler(void); |
igorsk | 0:1063a091a062 | 442 | |
igorsk | 0:1063a091a062 | 443 | /** |
igorsk | 0:1063a091a062 | 444 | * @} |
igorsk | 0:1063a091a062 | 445 | */ |
igorsk | 0:1063a091a062 | 446 | |
igorsk | 0:1063a091a062 | 447 | #ifdef __cplusplus |
igorsk | 0:1063a091a062 | 448 | } |
igorsk | 0:1063a091a062 | 449 | #endif |
igorsk | 0:1063a091a062 | 450 | |
igorsk | 0:1063a091a062 | 451 | #endif /* LPC17XX_SSP_H_ */ |
igorsk | 0:1063a091a062 | 452 | |
igorsk | 0:1063a091a062 | 453 | /** |
igorsk | 0:1063a091a062 | 454 | * @} |
igorsk | 0:1063a091a062 | 455 | */ |
igorsk | 0:1063a091a062 | 456 | |
igorsk | 0:1063a091a062 | 457 | /* --------------------------------- End Of File ------------------------------ */ |