Igor Skochinsky
NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip
include/lpc17xx_mcpwm.h@0:1063a091a062, 2010-02-17 (annotated)
- Committer:
- igorsk
- Date:
- Wed Feb 17 16:22:39 2010 +0000
- Revision:
- 0:1063a091a062
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| igorsk | 0:1063a091a062 | 1 | /***********************************************************************//** |
| igorsk | 0:1063a091a062 | 2 | * @file : lpc17xx_mcpwm.h |
| igorsk | 0:1063a091a062 | 3 | * @brief : Contains all macro definitions and function prototypes |
| igorsk | 0:1063a091a062 | 4 | * support for Motor Control PWM firmware library on LPC17xx |
| igorsk | 0:1063a091a062 | 5 | * @version : 1.0 |
| igorsk | 0:1063a091a062 | 6 | * @date : 28. May. 2009 |
| igorsk | 0:1063a091a062 | 7 | * @author : HieuNguyen |
| igorsk | 0:1063a091a062 | 8 | ************************************************************************** |
| igorsk | 0:1063a091a062 | 9 | * Software that is described herein is for illustrative purposes only |
| igorsk | 0:1063a091a062 | 10 | * which provides customers with programming information regarding the |
| igorsk | 0:1063a091a062 | 11 | * products. This software is supplied "AS IS" without any warranties. |
| igorsk | 0:1063a091a062 | 12 | * NXP Semiconductors assumes no responsibility or liability for the |
| igorsk | 0:1063a091a062 | 13 | * use of the software, conveys no license or title under any patent, |
| igorsk | 0:1063a091a062 | 14 | * copyright, or mask work right to the product. NXP Semiconductors |
| igorsk | 0:1063a091a062 | 15 | * reserves the right to make changes in the software without |
| igorsk | 0:1063a091a062 | 16 | * notification. NXP Semiconductors also make no representation or |
| igorsk | 0:1063a091a062 | 17 | * warranty that such application will be suitable for the specified |
| igorsk | 0:1063a091a062 | 18 | * use without further testing or modification. |
| igorsk | 0:1063a091a062 | 19 | **************************************************************************/ |
| igorsk | 0:1063a091a062 | 20 | |
| igorsk | 0:1063a091a062 | 21 | /* Peripheral group ----------------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 22 | /** @defgroup MCPWM |
| igorsk | 0:1063a091a062 | 23 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
| igorsk | 0:1063a091a062 | 24 | * @{ |
| igorsk | 0:1063a091a062 | 25 | */ |
| igorsk | 0:1063a091a062 | 26 | |
| igorsk | 0:1063a091a062 | 27 | #ifndef LPC17XX_MCPWM_H_ |
| igorsk | 0:1063a091a062 | 28 | #define LPC17XX_MCPWM_H_ |
| igorsk | 0:1063a091a062 | 29 | |
| igorsk | 0:1063a091a062 | 30 | /* Includes ------------------------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 31 | #include "cmsis.h" |
| igorsk | 0:1063a091a062 | 32 | #include "lpc_types.h" |
| igorsk | 0:1063a091a062 | 33 | |
| igorsk | 0:1063a091a062 | 34 | |
| igorsk | 0:1063a091a062 | 35 | #ifdef __cplusplus |
| igorsk | 0:1063a091a062 | 36 | extern "C" |
| igorsk | 0:1063a091a062 | 37 | { |
| igorsk | 0:1063a091a062 | 38 | #endif |
| igorsk | 0:1063a091a062 | 39 | |
| igorsk | 0:1063a091a062 | 40 | |
| igorsk | 0:1063a091a062 | 41 | /* Private Macros ------------------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 42 | /** @defgroup MCPWM_Private_Macros |
| igorsk | 0:1063a091a062 | 43 | * @{ |
| igorsk | 0:1063a091a062 | 44 | */ |
| igorsk | 0:1063a091a062 | 45 | |
| igorsk | 0:1063a091a062 | 46 | /** @defgroup MCPWM_REGISTER_BIT_DEFINITIONS |
| igorsk | 0:1063a091a062 | 47 | * @{ |
| igorsk | 0:1063a091a062 | 48 | */ |
| igorsk | 0:1063a091a062 | 49 | |
| igorsk | 0:1063a091a062 | 50 | /* MCPWM Control register, these macro definitions below can be applied for these |
| igorsk | 0:1063a091a062 | 51 | * register type: |
| igorsk | 0:1063a091a062 | 52 | * - MCPWM Control read address |
| igorsk | 0:1063a091a062 | 53 | * - MCPWM Control set address |
| igorsk | 0:1063a091a062 | 54 | * - MCPWM Control clear address |
| igorsk | 0:1063a091a062 | 55 | */ |
| igorsk | 0:1063a091a062 | 56 | #define MCPWM_CON_RUN(n) (((n<=2)) ? ((uint32_t)(1UL<<((n*8)+0))) : (0)) /**< Stops/starts timer channel n */ |
| igorsk | 0:1063a091a062 | 57 | #define MCPWM_CON_CENTER(n) (((n<=2)) ? ((uint32_t)(1UL<<((n*8)+1))) : (0)) /**< Edge/center aligned operation for channel n */ |
| igorsk | 0:1063a091a062 | 58 | #define MCPWM_CON_POLAR(n) (((n<=2)) ? ((uint32_t)(1UL<<((n*8)+2))) : (0)) /**< Select polarity of the MCOAn and MCOBn pin */ |
| igorsk | 0:1063a091a062 | 59 | #define MCPWM_CON_DTE(n) (((n<=2)) ? ((uint32_t)(1UL<<((n*8)+3))) : (0)) /**< Control the dead-time feature for channel n */ |
| igorsk | 0:1063a091a062 | 60 | #define MCPWM_CON_DISUP(n) (((n<=2)) ? ((uint32_t)(1UL<<((n*8)+4))) : (0)) /**< Enable/Disable update of functional register for channel n */ |
| igorsk | 0:1063a091a062 | 61 | #define MCPWM_CON_INVBDC ((uint32_t)(1<<29)) /**< Control the polarity for all 3 channels */ |
| igorsk | 0:1063a091a062 | 62 | #define MCPWM_CON_ACMODE ((uint32_t)(1<<30)) /**< 3-phase AC mode select */ |
| igorsk | 0:1063a091a062 | 63 | #define MCPWM_CON_DCMODE ((uint32_t)(1UL<<31)) /**< 3-phase DC mode select */ |
| igorsk | 0:1063a091a062 | 64 | |
| igorsk | 0:1063a091a062 | 65 | /* Capture Control register, these macro definitions below can be applied for these |
| igorsk | 0:1063a091a062 | 66 | * register type: |
| igorsk | 0:1063a091a062 | 67 | * - MCPWM Capture Control read address |
| igorsk | 0:1063a091a062 | 68 | * - MCPWM Capture Control set address |
| igorsk | 0:1063a091a062 | 69 | * - MCPWM Capture control clear address |
| igorsk | 0:1063a091a062 | 70 | */ |
| igorsk | 0:1063a091a062 | 71 | /** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */ |
| igorsk | 0:1063a091a062 | 72 | #define MCPWM_CAPCON_CAPMCI_RE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1UL<<((cap*6)+(mci*2)+0))) : (0)) |
| igorsk | 0:1063a091a062 | 73 | /** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */ |
| igorsk | 0:1063a091a062 | 74 | #define MCPWM_CAPCON_CAPMCI_FE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1UL<<((cap*6)+(mci*2)+1))) : (0)) |
| igorsk | 0:1063a091a062 | 75 | /** TC(n) is reset by channel (n) capture event */ |
| igorsk | 0:1063a091a062 | 76 | #define MCPWM_CAPCON_RT(n) (((n<=2)) ? ((uint32_t)(1<<(18+(n)))) : (0)) |
| igorsk | 0:1063a091a062 | 77 | /** Hardware noise filter: channel (n) capture events are delayed */ |
| igorsk | 0:1063a091a062 | 78 | #define MCPWM_CAPCON_HNFCAP(n) (((n<=2)) ? ((uint32_t)(1<<(21+(n)))) : (0)) |
| igorsk | 0:1063a091a062 | 79 | |
| igorsk | 0:1063a091a062 | 80 | /* Interrupt registers, these macro definitions below can be applied for these |
| igorsk | 0:1063a091a062 | 81 | * register type: |
| igorsk | 0:1063a091a062 | 82 | * - MCPWM Interrupt Enable read address |
| igorsk | 0:1063a091a062 | 83 | * - MCPWM Interrupt Enable set address |
| igorsk | 0:1063a091a062 | 84 | * - MCPWM Interrupt Enable clear address |
| igorsk | 0:1063a091a062 | 85 | * - MCPWM Interrupt Flags read address |
| igorsk | 0:1063a091a062 | 86 | * - MCPWM Interrupt Flags set address |
| igorsk | 0:1063a091a062 | 87 | * - MCPWM Interrupt Flags clear address |
| igorsk | 0:1063a091a062 | 88 | */ |
| igorsk | 0:1063a091a062 | 89 | /** Limit interrupt for channel (n) */ |
| igorsk | 0:1063a091a062 | 90 | #define MCPWM_INT_ILIM(n) (((n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0)) |
| igorsk | 0:1063a091a062 | 91 | /** Match interrupt for channel (n) */ |
| igorsk | 0:1063a091a062 | 92 | #define MCPWM_INT_IMAT(n) (((n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0)) |
| igorsk | 0:1063a091a062 | 93 | /** Capture interrupt for channel (n) */ |
| igorsk | 0:1063a091a062 | 94 | #define MCPWM_INT_ICAP(n) (((n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0)) |
| igorsk | 0:1063a091a062 | 95 | /** Fast abort interrupt */ |
| igorsk | 0:1063a091a062 | 96 | #define MCPWM_INT_ABORT ((uint32_t)(1<<15)) |
| igorsk | 0:1063a091a062 | 97 | |
| igorsk | 0:1063a091a062 | 98 | /* MCPWM Count Control register, these macro definitions below can be applied for these |
| igorsk | 0:1063a091a062 | 99 | * register type: |
| igorsk | 0:1063a091a062 | 100 | * - MCPWM Count Control read address |
| igorsk | 0:1063a091a062 | 101 | * - MCPWM Count Control set address |
| igorsk | 0:1063a091a062 | 102 | * - MCPWM Count Control clear address |
| igorsk | 0:1063a091a062 | 103 | */ |
| igorsk | 0:1063a091a062 | 104 | /** Counter(tc) advances on a rising edge on MCI(mci) pin */ |
| igorsk | 0:1063a091a062 | 105 | #define MCPWM_CNTCON_TCMCI_RE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0)) |
| igorsk | 0:1063a091a062 | 106 | /** Counter(cnt) advances on a falling edge on MCI(mci) pin */ |
| igorsk | 0:1063a091a062 | 107 | #define MCPWM_CNTCON_TCMCI_FE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0)) |
| igorsk | 0:1063a091a062 | 108 | /** Channel (n) is in counter mode */ |
| igorsk | 0:1063a091a062 | 109 | #define MCPWM_CNTCON_CNTR(n) (((n<=2)) ? ((uint32_t)(1<<(29+n))) : (0)) |
| igorsk | 0:1063a091a062 | 110 | |
| igorsk | 0:1063a091a062 | 111 | /* MCPWM Timer/Counter 0-2 registers --------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 112 | /* MCPWM Limit 0-2 registers ----------------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 113 | /* MCPWM Match 0-2 registers ----------------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 114 | |
| igorsk | 0:1063a091a062 | 115 | /* MCPWM Dead-time register ------------------------------------------------------------ */ |
| igorsk | 0:1063a091a062 | 116 | /** Dead time value x for channel n */ |
| igorsk | 0:1063a091a062 | 117 | #define MCPWM_DT(n,x) (((n<=2)) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0)) |
| igorsk | 0:1063a091a062 | 118 | |
| igorsk | 0:1063a091a062 | 119 | /* MCPWM Communication Pattern register ------------------------------------------------ */ |
| igorsk | 0:1063a091a062 | 120 | #define MCPWM_CP_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */ |
| igorsk | 0:1063a091a062 | 121 | #define MCPWM_CP_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */ |
| igorsk | 0:1063a091a062 | 122 | #define MCPWM_CP_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */ |
| igorsk | 0:1063a091a062 | 123 | #define MCPWM_CP_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */ |
| igorsk | 0:1063a091a062 | 124 | #define MCPWM_CP_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */ |
| igorsk | 0:1063a091a062 | 125 | #define MCPWM_CP_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */ |
| igorsk | 0:1063a091a062 | 126 | |
| igorsk | 0:1063a091a062 | 127 | /* MCPWM Capture Registers ------------------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 128 | /* MCPWM Capture read addresses */ |
| igorsk | 0:1063a091a062 | 129 | |
| igorsk | 0:1063a091a062 | 130 | /* MCPWM Capture clear address --------------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 131 | /** Clear the MCCAP (n) register */ |
| igorsk | 0:1063a091a062 | 132 | #define MCPWM_CAPCLR_CAP(n) (((n<=2)) ? ((uint32_t)(1UL<<n)) : (0)) |
| igorsk | 0:1063a091a062 | 133 | |
| igorsk | 0:1063a091a062 | 134 | |
| igorsk | 0:1063a091a062 | 135 | /** |
| igorsk | 0:1063a091a062 | 136 | * @} |
| igorsk | 0:1063a091a062 | 137 | */ |
| igorsk | 0:1063a091a062 | 138 | |
| igorsk | 0:1063a091a062 | 139 | /** |
| igorsk | 0:1063a091a062 | 140 | * @} |
| igorsk | 0:1063a091a062 | 141 | */ |
| igorsk | 0:1063a091a062 | 142 | |
| igorsk | 0:1063a091a062 | 143 | |
| igorsk | 0:1063a091a062 | 144 | /* Public Types --------------------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 145 | /** @defgroup MCPWM_Public_Types |
| igorsk | 0:1063a091a062 | 146 | * @{ |
| igorsk | 0:1063a091a062 | 147 | */ |
| igorsk | 0:1063a091a062 | 148 | |
| igorsk | 0:1063a091a062 | 149 | /** |
| igorsk | 0:1063a091a062 | 150 | * @brief Motor Control PWM Channel Configuration structure type definition |
| igorsk | 0:1063a091a062 | 151 | */ |
| igorsk | 0:1063a091a062 | 152 | typedef struct { |
| igorsk | 0:1063a091a062 | 153 | uint32_t channelType; /**< Edge/center aligned mode for this channel, |
| igorsk | 0:1063a091a062 | 154 | should be: |
| igorsk | 0:1063a091a062 | 155 | - MCPWM_CHANNEL_EDGE_MODE: Channel is in Edge mode |
| igorsk | 0:1063a091a062 | 156 | - MCPWM_CHANNEL_CENTER_MODE: Channel is in Center mode |
| igorsk | 0:1063a091a062 | 157 | */ |
| igorsk | 0:1063a091a062 | 158 | uint32_t channelPolarity; /**< Polarity of the MCOA and MCOB pins, should be: |
| igorsk | 0:1063a091a062 | 159 | - MCPWM_CHANNEL_PASSIVE_LO: Passive state is LOW, active state is HIGH |
| igorsk | 0:1063a091a062 | 160 | - MCPWM_CHANNEL_PASSIVE_HI: Passive state is HIGH, active state is LOW |
| igorsk | 0:1063a091a062 | 161 | */ |
| igorsk | 0:1063a091a062 | 162 | uint32_t channelDeadtimeEnable; /**< Enable/Disable DeadTime function for channel, should be: |
| igorsk | 0:1063a091a062 | 163 | - ENABLE. |
| igorsk | 0:1063a091a062 | 164 | - DISABLE. |
| igorsk | 0:1063a091a062 | 165 | */ |
| igorsk | 0:1063a091a062 | 166 | uint32_t channelDeadtimeValue; /**< DeadTime value, should be less than 0x3FF */ |
| igorsk | 0:1063a091a062 | 167 | uint32_t channelUpdateEnable; /**< Enable/Disable updates of functional registers, |
| igorsk | 0:1063a091a062 | 168 | should be: |
| igorsk | 0:1063a091a062 | 169 | - ENABLE. |
| igorsk | 0:1063a091a062 | 170 | - DISABLE. |
| igorsk | 0:1063a091a062 | 171 | */ |
| igorsk | 0:1063a091a062 | 172 | uint32_t channelTimercounterValue; /**< MCPWM Timer Counter value */ |
| igorsk | 0:1063a091a062 | 173 | uint32_t channelPeriodValue; /**< MCPWM Period value */ |
| igorsk | 0:1063a091a062 | 174 | uint32_t channelPulsewidthValue; /**< MCPWM Pulse Width value */ |
| igorsk | 0:1063a091a062 | 175 | } MCPWM_CHANNEL_CFG_Type; |
| igorsk | 0:1063a091a062 | 176 | |
| igorsk | 0:1063a091a062 | 177 | /** |
| igorsk | 0:1063a091a062 | 178 | * @brief MCPWM Capture Configuration type definition |
| igorsk | 0:1063a091a062 | 179 | */ |
| igorsk | 0:1063a091a062 | 180 | typedef struct { |
| igorsk | 0:1063a091a062 | 181 | uint32_t captureChannel; /**< Capture Channel Number, should be in range from 0 to 2 */ |
| igorsk | 0:1063a091a062 | 182 | uint32_t captureRising; /**< Enable/Disable Capture on Rising Edge event, should be: |
| igorsk | 0:1063a091a062 | 183 | - ENABLE. |
| igorsk | 0:1063a091a062 | 184 | - DISABLE. |
| igorsk | 0:1063a091a062 | 185 | */ |
| igorsk | 0:1063a091a062 | 186 | uint32_t captureFalling; /**< Enable/Disable Capture on Falling Edge event, should be: |
| igorsk | 0:1063a091a062 | 187 | - ENABLE. |
| igorsk | 0:1063a091a062 | 188 | - DISABLE. |
| igorsk | 0:1063a091a062 | 189 | */ |
| igorsk | 0:1063a091a062 | 190 | uint32_t timerReset; /**< Enable/Disable Timer reset function an capture, should be: |
| igorsk | 0:1063a091a062 | 191 | - ENABLE. |
| igorsk | 0:1063a091a062 | 192 | - DISABLE. |
| igorsk | 0:1063a091a062 | 193 | */ |
| igorsk | 0:1063a091a062 | 194 | uint32_t hnfEnable; /**< Enable/Disable Hardware noise filter function, should be: |
| igorsk | 0:1063a091a062 | 195 | - ENABLE. |
| igorsk | 0:1063a091a062 | 196 | - DISABLE. |
| igorsk | 0:1063a091a062 | 197 | */ |
| igorsk | 0:1063a091a062 | 198 | } MCPWM_CAPTURE_CFG_Type; |
| igorsk | 0:1063a091a062 | 199 | |
| igorsk | 0:1063a091a062 | 200 | |
| igorsk | 0:1063a091a062 | 201 | /** |
| igorsk | 0:1063a091a062 | 202 | * @brief MCPWM Count Control Configuration type definition |
| igorsk | 0:1063a091a062 | 203 | */ |
| igorsk | 0:1063a091a062 | 204 | typedef struct { |
| igorsk | 0:1063a091a062 | 205 | uint32_t counterChannel; /**< Counter Channel Number, should be in range from 0 to 2 */ |
| igorsk | 0:1063a091a062 | 206 | uint32_t countRising; /**< Enable/Disable Capture on Rising Edge event, should be: |
| igorsk | 0:1063a091a062 | 207 | - ENABLE. |
| igorsk | 0:1063a091a062 | 208 | - DISABLE. |
| igorsk | 0:1063a091a062 | 209 | */ |
| igorsk | 0:1063a091a062 | 210 | uint32_t countFalling; /**< Enable/Disable Capture on Falling Edge event, should be: |
| igorsk | 0:1063a091a062 | 211 | - ENABLE. |
| igorsk | 0:1063a091a062 | 212 | - DISABLE. |
| igorsk | 0:1063a091a062 | 213 | */ |
| igorsk | 0:1063a091a062 | 214 | } MCPWM_COUNT_CFG_Type; |
| igorsk | 0:1063a091a062 | 215 | |
| igorsk | 0:1063a091a062 | 216 | /** |
| igorsk | 0:1063a091a062 | 217 | * @} |
| igorsk | 0:1063a091a062 | 218 | */ |
| igorsk | 0:1063a091a062 | 219 | |
| igorsk | 0:1063a091a062 | 220 | |
| igorsk | 0:1063a091a062 | 221 | /* Public Macros -------------------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 222 | /** @defgroup MCPWM_Public_Macros |
| igorsk | 0:1063a091a062 | 223 | * @{ |
| igorsk | 0:1063a091a062 | 224 | */ |
| igorsk | 0:1063a091a062 | 225 | |
| igorsk | 0:1063a091a062 | 226 | |
| igorsk | 0:1063a091a062 | 227 | /** Edge aligned mode for channel in MCPWM */ |
| igorsk | 0:1063a091a062 | 228 | #define MCPWM_CHANNEL_EDGE_MODE ((uint32_t)(0)) |
| igorsk | 0:1063a091a062 | 229 | /** Center aligned mode for channel in MCPWM */ |
| igorsk | 0:1063a091a062 | 230 | #define MCPWM_CHANNEL_CENTER_MODE ((uint32_t)(1)) |
| igorsk | 0:1063a091a062 | 231 | |
| igorsk | 0:1063a091a062 | 232 | /** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */ |
| igorsk | 0:1063a091a062 | 233 | #define MCPWM_CHANNEL_PASSIVE_LO ((uint32_t)(0)) |
| igorsk | 0:1063a091a062 | 234 | /** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */ |
| igorsk | 0:1063a091a062 | 235 | #define MCPWM_CHANNEL_PASSIVE_HI ((uint32_t)(1)) |
| igorsk | 0:1063a091a062 | 236 | |
| igorsk | 0:1063a091a062 | 237 | /* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of |
| igorsk | 0:1063a091a062 | 238 | * the six output pins under the control of the bits in this register */ |
| igorsk | 0:1063a091a062 | 239 | #define MCPWM_PATENT_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */ |
| igorsk | 0:1063a091a062 | 240 | #define MCPWM_PATENT_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */ |
| igorsk | 0:1063a091a062 | 241 | #define MCPWM_PATENT_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */ |
| igorsk | 0:1063a091a062 | 242 | #define MCPWM_PATENT_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */ |
| igorsk | 0:1063a091a062 | 243 | #define MCPWM_PATENT_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */ |
| igorsk | 0:1063a091a062 | 244 | #define MCPWM_PATENT_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */ |
| igorsk | 0:1063a091a062 | 245 | |
| igorsk | 0:1063a091a062 | 246 | /* Interrupt type in MCPWM */ |
| igorsk | 0:1063a091a062 | 247 | /** Limit interrupt for channel (0) */ |
| igorsk | 0:1063a091a062 | 248 | #define MCPWM_INTFLAG_LIM0 MCPWM_INT_ILIM(0) |
| igorsk | 0:1063a091a062 | 249 | /** Match interrupt for channel (0) */ |
| igorsk | 0:1063a091a062 | 250 | #define MCPWM_INTFLAG_MAT0 MCPWM_INT_IMAT(0) |
| igorsk | 0:1063a091a062 | 251 | /** Capture interrupt for channel (0) */ |
| igorsk | 0:1063a091a062 | 252 | #define MCPWM_INTFLAG_CAP0 MCPWM_INT_ICAP(0) |
| igorsk | 0:1063a091a062 | 253 | |
| igorsk | 0:1063a091a062 | 254 | /** Limit interrupt for channel (1) */ |
| igorsk | 0:1063a091a062 | 255 | #define MCPWM_INTFLAG_LIM1 MCPWM_INT_ILIM(1) |
| igorsk | 0:1063a091a062 | 256 | /** Match interrupt for channel (1) */ |
| igorsk | 0:1063a091a062 | 257 | #define MCPWM_INTFLAG_MAT1 MCPWM_INT_IMAT(1) |
| igorsk | 0:1063a091a062 | 258 | /** Capture interrupt for channel (1) */ |
| igorsk | 0:1063a091a062 | 259 | #define MCPWM_INTFLAG_CAP1 MCPWM_INT_ICAP(1) |
| igorsk | 0:1063a091a062 | 260 | |
| igorsk | 0:1063a091a062 | 261 | /** Limit interrupt for channel (2) */ |
| igorsk | 0:1063a091a062 | 262 | #define MCPWM_INTFLAG_LIM2 MCPWM_INT_ILIM(2) |
| igorsk | 0:1063a091a062 | 263 | /** Match interrupt for channel (2) */ |
| igorsk | 0:1063a091a062 | 264 | #define MCPWM_INTFLAG_MAT2 MCPWM_INT_IMAT(2) |
| igorsk | 0:1063a091a062 | 265 | /** Capture interrupt for channel (2) */ |
| igorsk | 0:1063a091a062 | 266 | #define MCPWM_INTFLAG_CAP2 MCPWM_INT_ICAP(2) |
| igorsk | 0:1063a091a062 | 267 | |
| igorsk | 0:1063a091a062 | 268 | /** Fast abort interrupt */ |
| igorsk | 0:1063a091a062 | 269 | #define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT |
| igorsk | 0:1063a091a062 | 270 | |
| igorsk | 0:1063a091a062 | 271 | |
| igorsk | 0:1063a091a062 | 272 | /** |
| igorsk | 0:1063a091a062 | 273 | * @} |
| igorsk | 0:1063a091a062 | 274 | */ |
| igorsk | 0:1063a091a062 | 275 | |
| igorsk | 0:1063a091a062 | 276 | |
| igorsk | 0:1063a091a062 | 277 | /* Public Functions ----------------------------------------------------------- */ |
| igorsk | 0:1063a091a062 | 278 | /** @defgroup MCPWM_Public_Functions |
| igorsk | 0:1063a091a062 | 279 | * @{ |
| igorsk | 0:1063a091a062 | 280 | */ |
| igorsk | 0:1063a091a062 | 281 | |
| igorsk | 0:1063a091a062 | 282 | void MCPWM_Init(LPC_MCPWM_TypeDef *MCPWMx); |
| igorsk | 0:1063a091a062 | 283 | void MCPWM_ConfigChannel(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, |
| igorsk | 0:1063a091a062 | 284 | MCPWM_CHANNEL_CFG_Type * channelSetup); |
| igorsk | 0:1063a091a062 | 285 | void MCPWM_WriteToShadow(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, |
| igorsk | 0:1063a091a062 | 286 | MCPWM_CHANNEL_CFG_Type *channelSetup); |
| igorsk | 0:1063a091a062 | 287 | void MCPWM_ConfigCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, |
| igorsk | 0:1063a091a062 | 288 | MCPWM_CAPTURE_CFG_Type *captureConfig); |
| igorsk | 0:1063a091a062 | 289 | void MCPWM_ClearCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel); |
| igorsk | 0:1063a091a062 | 290 | uint32_t MCPWM_GetCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel); |
| igorsk | 0:1063a091a062 | 291 | void MCPWM_CountConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, |
| igorsk | 0:1063a091a062 | 292 | uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig); |
| igorsk | 0:1063a091a062 | 293 | void MCPWM_Start(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2); |
| igorsk | 0:1063a091a062 | 294 | void MCPWM_Stop(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2); |
| igorsk | 0:1063a091a062 | 295 | void MCPWM_ACMode(LPC_MCPWM_TypeDef *MCPWMx,uint32_t acMode); |
| igorsk | 0:1063a091a062 | 296 | void MCPWM_DCMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t dcMode, |
| igorsk | 0:1063a091a062 | 297 | uint32_t outputInvered, uint32_t outputPattern); |
| igorsk | 0:1063a091a062 | 298 | void MCPWM_IntConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType, FunctionalState NewState); |
| igorsk | 0:1063a091a062 | 299 | void MCPWM_IntSet(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType); |
| igorsk | 0:1063a091a062 | 300 | void MCPWM_IntClear(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType); |
| igorsk | 0:1063a091a062 | 301 | FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType); |
| igorsk | 0:1063a091a062 | 302 | |
| igorsk | 0:1063a091a062 | 303 | /** |
| igorsk | 0:1063a091a062 | 304 | * @} |
| igorsk | 0:1063a091a062 | 305 | */ |
| igorsk | 0:1063a091a062 | 306 | |
| igorsk | 0:1063a091a062 | 307 | #ifdef __cplusplus |
| igorsk | 0:1063a091a062 | 308 | } |
| igorsk | 0:1063a091a062 | 309 | #endif |
| igorsk | 0:1063a091a062 | 310 | |
| igorsk | 0:1063a091a062 | 311 | #endif /* LPC17XX_MCPWM_H_ */ |
| igorsk | 0:1063a091a062 | 312 | |
| igorsk | 0:1063a091a062 | 313 | /** |
| igorsk | 0:1063a091a062 | 314 | * @} |
| igorsk | 0:1063a091a062 | 315 | */ |
| igorsk | 0:1063a091a062 | 316 | |
| igorsk | 0:1063a091a062 | 317 | /* --------------------------------- End Of File ------------------------------ */ |