DriverLibrary - NXP's driver library for LPC17xx, ported to mbed'…

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Igor Skochinsky / Mbed 2 deprecated DriverLibrary

NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip

Dependencies: mbed

include/lpc17xx_adc.h@0:1063a091a062, 2010-02-17 (annotated)

Committer:: igorsk
Date:: Wed Feb 17 16:22:39 2010 +0000
Revision:: 0:1063a091a062

Who changed what in which revision?

User	Revision	Line number	New contents of line
igorsk	0:1063a091a062	1	/*********************************************************************//
igorsk	0:1063a091a062	2	* @file : lpc17xx_adc.h
igorsk	0:1063a091a062	3	* @brief : Contains all macro definitions and function prototypes
igorsk	0:1063a091a062	4	* support for ADC firmware library on LPC17xx
igorsk	0:1063a091a062	5	* @version : 1.0
igorsk	0:1063a091a062	6	* @date : 3. April. 2009
igorsk	0:1063a091a062	7	* @author : NgaDinh
igorsk	0:1063a091a062	8	**************************************************************************
igorsk	0:1063a091a062	9	* Software that is described herein is for illustrative purposes only
igorsk	0:1063a091a062	10	* which provides customers with programming information regarding the
igorsk	0:1063a091a062	11	* products. This software is supplied "AS IS" without any warranties.
igorsk	0:1063a091a062	12	* NXP Semiconductors assumes no responsibility or liability for the
igorsk	0:1063a091a062	13	* use of the software, conveys no license or title under any patent,
igorsk	0:1063a091a062	14	* copyright, or mask work right to the product. NXP Semiconductors
igorsk	0:1063a091a062	15	* reserves the right to make changes in the software without
igorsk	0:1063a091a062	16	* notification. NXP Semiconductors also make no representation or
igorsk	0:1063a091a062	17	* warranty that such application will be suitable for the specified
igorsk	0:1063a091a062	18	* use without further testing or modification.
igorsk	0:1063a091a062	19	**************************************************************************/
igorsk	0:1063a091a062	20
igorsk	0:1063a091a062	21	/* Peripheral group ----------------------------------------------------------- */
igorsk	0:1063a091a062	22	/** @defgroup ADC
igorsk	0:1063a091a062	23	* @ingroup LPC1700CMSIS_FwLib_Drivers
igorsk	0:1063a091a062	24	* @{
igorsk	0:1063a091a062	25	*/
igorsk	0:1063a091a062	26
igorsk	0:1063a091a062	27	#ifndef LPC17XX_ADC_H_
igorsk	0:1063a091a062	28	#define LPC17XX_ADC_H_
igorsk	0:1063a091a062	29
igorsk	0:1063a091a062	30	/* Includes ------------------------------------------------------------------- */
igorsk	0:1063a091a062	31	#include "cmsis.h"
igorsk	0:1063a091a062	32	#include "lpc_types.h"
igorsk	0:1063a091a062	33
igorsk	0:1063a091a062	34
igorsk	0:1063a091a062	35	#ifdef __cplusplus
igorsk	0:1063a091a062	36	extern "C"
igorsk	0:1063a091a062	37	{
igorsk	0:1063a091a062	38	#endif
igorsk	0:1063a091a062	39
igorsk	0:1063a091a062	40
igorsk	0:1063a091a062	41	/* Private Macros ------------------------------------------------------------- */
igorsk	0:1063a091a062	42	/** @defgroup ADC_Private_Macros ADC_Private_Macros
igorsk	0:1063a091a062	43	* @{
igorsk	0:1063a091a062	44	*/
igorsk	0:1063a091a062	45
igorsk	0:1063a091a062	46
igorsk	0:1063a091a062	47	/** @defgroup group3 ADC_REGISTER_BIT_DEFINITIONS
igorsk	0:1063a091a062	48	* @{
igorsk	0:1063a091a062	49	*/
igorsk	0:1063a091a062	50
igorsk	0:1063a091a062	51	/*******************************************************************//
igorsk	0:1063a091a062	52	* Macro defines for ADC control register
igorsk	0:1063a091a062	53	**********************************************************************/
igorsk	0:1063a091a062	54	/** Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
igorsk	0:1063a091a062	55	#define ADC_CR_CH_SEL(n) ((1UL << n))
igorsk	0:1063a091a062	56	/** The APB clock (PCLK) is divided by (this value plus one)
igorsk	0:1063a091a062	57	* to produce the clock for the A/D */
igorsk	0:1063a091a062	58	#define ADC_CR_CLKDIV(n) ((n<<8))
igorsk	0:1063a091a062	59	/** Repeated conversions A/D enable bit */
igorsk	0:1063a091a062	60	#define ADC_CR_BURST ((1UL<<16))
igorsk	0:1063a091a062	61	/** ADC convert in power down mode */
igorsk	0:1063a091a062	62	#define ADC_CR_PDN ((1UL<<21))
igorsk	0:1063a091a062	63	/** Start mask bits */
igorsk	0:1063a091a062	64	#define ADC_CR_START_MASK ((7UL<<24))
igorsk	0:1063a091a062	65	/** Select Start Mode */
igorsk	0:1063a091a062	66	#define ADC_CR_START_MODE_SEL(SEL) ((SEL<<24))
igorsk	0:1063a091a062	67	/** Start conversion now */
igorsk	0:1063a091a062	68	#define ADC_CR_START_NOW ((1UL<<24))
igorsk	0:1063a091a062	69	/** Start conversion when the edge selected by bit 27 occurs on P2.10/EINT0 */
igorsk	0:1063a091a062	70	#define ADC_CR_START_EINT0 ((2UL<<24))
igorsk	0:1063a091a062	71	/** Start conversion when the edge selected by bit 27 occurs on P1.27/CAP0.1 */
igorsk	0:1063a091a062	72	#define ADC_CR_START_CAP01 ((3UL<<24))
igorsk	0:1063a091a062	73	/** Start conversion when the edge selected by bit 27 occurs on MAT0.1 */
igorsk	0:1063a091a062	74	#define ADC_CR_START_MAT01 ((4UL<<24))
igorsk	0:1063a091a062	75	/** Start conversion when the edge selected by bit 27 occurs on MAT0.3 */
igorsk	0:1063a091a062	76	#define ADC_CR_START_MAT03 ((5UL<<24))
igorsk	0:1063a091a062	77	/** Start conversion when the edge selected by bit 27 occurs on MAT1.0 */
igorsk	0:1063a091a062	78	#define ADC_CR_START_MAT10 ((6UL<<24))
igorsk	0:1063a091a062	79	/** Start conversion when the edge selected by bit 27 occurs on MAT1.1 */
igorsk	0:1063a091a062	80	#define ADC_CR_START_MAT11 ((7UL<<24))
igorsk	0:1063a091a062	81	/** Start conversion on a falling edge on the selected CAP/MAT signal */
igorsk	0:1063a091a062	82	#define ADC_CR_EDGE ((1UL<<27))
igorsk	0:1063a091a062	83
igorsk	0:1063a091a062	84	/*******************************************************************//
igorsk	0:1063a091a062	85	* Macro defines for ADC Global Data register
igorsk	0:1063a091a062	86	**********************************************************************/
igorsk	0:1063a091a062	87	/** When DONE is 1, this field contains result value of ADC conversion */
igorsk	0:1063a091a062	88	#define ADC_GDR_RESULT(n) (((n>>4)&0xFFF))
igorsk	0:1063a091a062	89	/** These bits contain the channel from which the LS bits were converted */
igorsk	0:1063a091a062	90	#define ADC_GDR_CH(n) (((n>>24)&0x7))
igorsk	0:1063a091a062	91	/** This bit is 1 in burst mode if the results of one or
igorsk	0:1063a091a062	92	* more conversions was (were) lost */
igorsk	0:1063a091a062	93	#define ADC_GDR_OVERRUN_FLAG ((1UL<<30))
igorsk	0:1063a091a062	94	/** This bit is set to 1 when an A/D conversion completes */
igorsk	0:1063a091a062	95	#define ADC_GDR_DONE_FLAG ((1UL<<31))
igorsk	0:1063a091a062	96
igorsk	0:1063a091a062	97	/** This bits is used to mask for Channel */
igorsk	0:1063a091a062	98	#define ADC_GDR_CH_MASK ((7UL<<24))
igorsk	0:1063a091a062	99	/*******************************************************************//
igorsk	0:1063a091a062	100	* Macro defines for ADC Interrupt register
igorsk	0:1063a091a062	101	**********************************************************************/
igorsk	0:1063a091a062	102	/** These bits allow control over which A/D channels generate
igorsk	0:1063a091a062	103	* interrupts for conversion completion */
igorsk	0:1063a091a062	104	#define ADC_INTEN_CH(n) ((1UL<<n))
igorsk	0:1063a091a062	105	/** When 1, enables the global DONE flag in ADDR to generate an interrupt */
igorsk	0:1063a091a062	106	#define ADC_INTEN_GLOBAL ((1UL<<8))
igorsk	0:1063a091a062	107
igorsk	0:1063a091a062	108	/*******************************************************************//
igorsk	0:1063a091a062	109	* Macro defines for ADC Data register
igorsk	0:1063a091a062	110	**********************************************************************/
igorsk	0:1063a091a062	111	/** When DONE is 1, this field contains result value of ADC conversion */
igorsk	0:1063a091a062	112	#define ADC_DR_RESULT(n) (((n>>4)&0xFFF))
igorsk	0:1063a091a062	113	/** These bits mirror the OVERRRUN status flags that appear in the
igorsk	0:1063a091a062	114	* result register for each A/D channel */
igorsk	0:1063a091a062	115	#define ADC_DR_OVERRUN_FLAG ((1UL<<30))
igorsk	0:1063a091a062	116	/** This bit is set to 1 when an A/D conversion completes. It is cleared
igorsk	0:1063a091a062	117	* when this register is read */
igorsk	0:1063a091a062	118	#define ADC_DR_DONE_FLAG ((1UL<<31))
igorsk	0:1063a091a062	119
igorsk	0:1063a091a062	120	/*******************************************************************//
igorsk	0:1063a091a062	121	* Macro defines for ADC Status register
igorsk	0:1063a091a062	122	**********************************************************************/
igorsk	0:1063a091a062	123	/** These bits mirror the DONE status flags that appear in the result
igorsk	0:1063a091a062	124	* register for each A/D channel */
igorsk	0:1063a091a062	125	#define ADC_STAT_CH_DONE_FLAG(n) ((n&0xFF))
igorsk	0:1063a091a062	126	/** These bits mirror the OVERRRUN status flags that appear in the
igorsk	0:1063a091a062	127	* result register for each A/D channel */
igorsk	0:1063a091a062	128	#define ADC_STAT_CH_OVERRUN_FLAG(n) (((n>>8)&0xFF))
igorsk	0:1063a091a062	129	/** This bit is the A/D interrupt flag */
igorsk	0:1063a091a062	130	#define ADC_STAT_INT_FLAG ((1UL<<16))
igorsk	0:1063a091a062	131
igorsk	0:1063a091a062	132	/*******************************************************************//
igorsk	0:1063a091a062	133	* Macro defines for ADC Trim register
igorsk	0:1063a091a062	134	**********************************************************************/
igorsk	0:1063a091a062	135	/** Offset trim bits for ADC operation */
igorsk	0:1063a091a062	136	#define ADC_ADCOFFS(n) (((n&0xF)<<4))
igorsk	0:1063a091a062	137	/** Written to boot code*/
igorsk	0:1063a091a062	138	#define ADC_TRIM(n) (((n&0xF)<<8))
igorsk	0:1063a091a062	139
igorsk	0:1063a091a062	140	/**
igorsk	0:1063a091a062	141	* @}
igorsk	0:1063a091a062	142	*/
igorsk	0:1063a091a062	143
igorsk	0:1063a091a062	144	/**
igorsk	0:1063a091a062	145	* @}
igorsk	0:1063a091a062	146	*/
igorsk	0:1063a091a062	147
igorsk	0:1063a091a062	148
igorsk	0:1063a091a062	149	/* Public Types --------------------------------------------------------------- */
igorsk	0:1063a091a062	150	/** @defgroup ADC_Public_Types
igorsk	0:1063a091a062	151	* @{
igorsk	0:1063a091a062	152	*/
igorsk	0:1063a091a062	153
igorsk	0:1063a091a062	154	/*******************************************************************//
igorsk	0:1063a091a062	155	* @brief ADC enumeration
igorsk	0:1063a091a062	156	**********************************************************************/
igorsk	0:1063a091a062	157	/** @brief Channel Selection */
igorsk	0:1063a091a062	158	typedef enum
igorsk	0:1063a091a062	159	{
igorsk	0:1063a091a062	160	ADC_CHANNEL_0 = 0, /!< Channel 0 /
igorsk	0:1063a091a062	161	ADC_CHANNEL_1, /!< Channel 1 /
igorsk	0:1063a091a062	162	ADC_CHANNEL_2, /!< Channel 2 /
igorsk	0:1063a091a062	163	ADC_CHANNEL_3, /!< Channel 3 /
igorsk	0:1063a091a062	164	ADC_CHANNEL_4, /!< Channel 4 /
igorsk	0:1063a091a062	165	ADC_CHANNEL_5, /!< Channel 5 /
igorsk	0:1063a091a062	166	ADC_CHANNEL_6, /!< Channel 6 /
igorsk	0:1063a091a062	167	ADC_CHANNEL_7 /!< Channel 7 /
igorsk	0:1063a091a062	168	}ADC_CHANNEL_SELECTION;
igorsk	0:1063a091a062	169
igorsk	0:1063a091a062	170
igorsk	0:1063a091a062	171
igorsk	0:1063a091a062	172	/** @brief Type of start option */
igorsk	0:1063a091a062	173
igorsk	0:1063a091a062	174	/** @brief Type of start option */
igorsk	0:1063a091a062	175
igorsk	0:1063a091a062	176	typedef enum
igorsk	0:1063a091a062	177	{
igorsk	0:1063a091a062	178	ADC_START_CONTINUOUS =0, /!< Continuous mode /
igorsk	0:1063a091a062	179	ADC_START_NOW, /!< Start conversion now /
igorsk	0:1063a091a062	180	ADC_START_ON_EINT0, /*!< Start conversion when the edge selected
igorsk	0:1063a091a062	181	* by bit 27 occurs on P2.10/EINT0 */
igorsk	0:1063a091a062	182	ADC_START_ON_CAP01, /*!< Start conversion when the edge selected
igorsk	0:1063a091a062	183	* by bit 27 occurs on P1.27/CAP0.1 */
igorsk	0:1063a091a062	184	ADC_START_ON_MAT01, /*!< Start conversion when the edge selected
igorsk	0:1063a091a062	185	* by bit 27 occurs on MAT0.1 */
igorsk	0:1063a091a062	186	ADC_START_ON_MAT03, /*!< Start conversion when the edge selected
igorsk	0:1063a091a062	187	* by bit 27 occurs on MAT0.3 */
igorsk	0:1063a091a062	188	ADC_START_ON_MAT10, /*!< Start conversion when the edge selected
igorsk	0:1063a091a062	189	* by bit 27 occurs on MAT1.0 */
igorsk	0:1063a091a062	190	ADC_START_ON_MAT11 /*!< Start conversion when the edge selected
igorsk	0:1063a091a062	191	* by bit 27 occurs on MAT1.1 */
igorsk	0:1063a091a062	192	} ADC_START_OPT;
igorsk	0:1063a091a062	193
igorsk	0:1063a091a062	194
igorsk	0:1063a091a062	195	/** @brief Type of edge when start conversion on the selected CAP/MAT signal */
igorsk	0:1063a091a062	196
igorsk	0:1063a091a062	197	typedef enum
igorsk	0:1063a091a062	198	{
igorsk	0:1063a091a062	199	ADC_START_ON_RISING = 0, /*!< Start conversion on a rising edge
igorsk	0:1063a091a062	200	on the selected CAP/MAT signal /
igorsk	0:1063a091a062	201	ADC_START_ON_FALLING /*!< Start conversion on a falling edge
igorsk	0:1063a091a062	202	on the selected CAP/MAT signal /
igorsk	0:1063a091a062	203	} ADC_START_ON_EDGE_OPT;
igorsk	0:1063a091a062	204
igorsk	0:1063a091a062	205	/** @brief* ADC type interrupt enum */
igorsk	0:1063a091a062	206	typedef enum
igorsk	0:1063a091a062	207	{
igorsk	0:1063a091a062	208	ADC_ADINTEN0 = 0, /!< Interrupt channel 0 /
igorsk	0:1063a091a062	209	ADC_ADINTEN1, /!< Interrupt channel 1 /
igorsk	0:1063a091a062	210	ADC_ADINTEN2, /!< Interrupt channel 2 /
igorsk	0:1063a091a062	211	ADC_ADINTEN3, /!< Interrupt channel 3 /
igorsk	0:1063a091a062	212	ADC_ADINTEN4, /!< Interrupt channel 4 /
igorsk	0:1063a091a062	213	ADC_ADINTEN5, /!< Interrupt channel 5 /
igorsk	0:1063a091a062	214	ADC_ADINTEN6, /!< Interrupt channel 6 /
igorsk	0:1063a091a062	215	ADC_ADINTEN7, /!< Interrupt channel 7 /
igorsk	0:1063a091a062	216	ADC_ADGINTEN /!< Individual channel/global flag done generate an interrupt /
igorsk	0:1063a091a062	217	}ADC_TYPE_INT_OPT;
igorsk	0:1063a091a062	218
igorsk	0:1063a091a062	219	/** Macro to determine if it is valid interrupt type */
igorsk	0:1063a091a062	220	#define PARAM_ADC_TYPE_INT_OPT(OPT) ((OPT == ADC_ADINTEN0)\|\|(OPT == ADC_ADINTEN1)\
igorsk	0:1063a091a062	221	\|\|(OPT == ADC_ADINTEN2)\|\|(OPT == ADC_ADINTEN3)\
igorsk	0:1063a091a062	222	\|\|(OPT == ADC_ADINTEN4)\|\|(OPT == ADC_ADINTEN5)\
igorsk	0:1063a091a062	223	\|\|(OPT == ADC_ADINTEN6)\|\|(OPT == ADC_ADINTEN7)\
igorsk	0:1063a091a062	224	\|\|(OPT == ADC_ADGINTEN))
igorsk	0:1063a091a062	225
igorsk	0:1063a091a062	226
igorsk	0:1063a091a062	227	/** @brief ADC Data status */
igorsk	0:1063a091a062	228	typedef enum
igorsk	0:1063a091a062	229	{
igorsk	0:1063a091a062	230	ADC_DATA_BURST = 0, /Burst bit/
igorsk	0:1063a091a062	231	ADC_DATA_DONE /Done bit/
igorsk	0:1063a091a062	232	}ADC_DATA_STATUS;
igorsk	0:1063a091a062	233
igorsk	0:1063a091a062	234
igorsk	0:1063a091a062	235	#define PARAM_ADC_START_ON_EDGE_OPT(OPT) ((OPT == ADC_START_ON_RISING)\|\|(OPT == ADC_START_ON_FALLING))
igorsk	0:1063a091a062	236
igorsk	0:1063a091a062	237	#define PARAM_ADC_DATA_STATUS(OPT) ((OPT== ADC_DATA_BURST)\|\|(OPT== ADC_DATA_DONE))
igorsk	0:1063a091a062	238
igorsk	0:1063a091a062	239	#define PARAM_ADC_FREQUENCY(FRE) (FRE <= 13000000 )
igorsk	0:1063a091a062	240
igorsk	0:1063a091a062	241	#define PARAM_ADC_CHANNEL_SELECTION(SEL) ((SEL == ADC_CHANNEL_0)\|\|(ADC_CHANNEL_1)\
igorsk	0:1063a091a062	242	\|\|(SEL == ADC_CHANNEL_2)\|(ADC_CHANNEL_3)\
igorsk	0:1063a091a062	243	\|\|(SEL == ADC_CHANNEL_4)\|\|(ADC_CHANNEL_5)\
igorsk	0:1063a091a062	244	\|\|(SEL == ADC_CHANNEL_6)\|\|(ADC_CHANNEL_7))
igorsk	0:1063a091a062	245
igorsk	0:1063a091a062	246	#define PARAM_ADC_START_OPT(OPT) ((OPT == ADC_START_CONTINUOUS)\|\|(OPT == ADC_START_NOW)\
igorsk	0:1063a091a062	247	\|\|(OPT == ADC_START_ON_EINT0)\|\|(OPT == ADC_START_ON_CAP01)\
igorsk	0:1063a091a062	248	\|\|(OPT == ADC_START_ON_MAT01)\|\|(OPT == ADC_START_ON_MAT03)\
igorsk	0:1063a091a062	249	\|\|(OPT == ADC_START_ON_MAT10)\|\|(OPT == ADC_START_ON_MAT11))
igorsk	0:1063a091a062	250
igorsk	0:1063a091a062	251	#define PARAM_ADC_TYPE_INT_OPT(OPT) ((OPT == ADC_ADINTEN0)\|\|(OPT == ADC_ADINTEN1)\
igorsk	0:1063a091a062	252	\|\|(OPT == ADC_ADINTEN2)\|\|(OPT == ADC_ADINTEN3)\
igorsk	0:1063a091a062	253	\|\|(OPT == ADC_ADINTEN4)\|\|(OPT == ADC_ADINTEN5)\
igorsk	0:1063a091a062	254	\|\|(OPT == ADC_ADINTEN6)\|\|(OPT == ADC_ADINTEN7)\
igorsk	0:1063a091a062	255	\|\|(OPT == ADC_ADGINTEN))
igorsk	0:1063a091a062	256
igorsk	0:1063a091a062	257	#define PARAM_ADCx(n) (((uint32_t )n)==((uint32_t )LPC_ADC))
igorsk	0:1063a091a062	258
igorsk	0:1063a091a062	259	/**
igorsk	0:1063a091a062	260	* @}
igorsk	0:1063a091a062	261	*/
igorsk	0:1063a091a062	262
igorsk	0:1063a091a062	263
igorsk	0:1063a091a062	264
igorsk	0:1063a091a062	265	/* Public Functions ----------------------------------------------------------- */
igorsk	0:1063a091a062	266	/** @defgroup ADC_Public_Functions
igorsk	0:1063a091a062	267	* @{
igorsk	0:1063a091a062	268	*/
igorsk	0:1063a091a062	269
igorsk	0:1063a091a062	270	void ADC_Init(LPC_ADC_TypeDef *ADCx, uint32_t ConvFreq);
igorsk	0:1063a091a062	271	void ADC_DeInit(LPC_ADC_TypeDef *ADCx);
igorsk	0:1063a091a062	272	void ADC_BurstCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState);
igorsk	0:1063a091a062	273	void ADC_PowerdownCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState);
igorsk	0:1063a091a062	274	void ADC_StartCmd(LPC_ADC_TypeDef *ADCx, uint8_t start_mode);
igorsk	0:1063a091a062	275	void ADC_EdgeStartConfig(LPC_ADC_TypeDef *ADCx, uint8_t EdgeOption);
igorsk	0:1063a091a062	276	void ADC_IntConfig (LPC_ADC_TypeDef *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState);
igorsk	0:1063a091a062	277	void ADC_ChannelCmd (LPC_ADC_TypeDef *ADCx, uint8_t Channel, FunctionalState NewState);
igorsk	0:1063a091a062	278	uint16_t ADC_ChannelGetData(LPC_ADC_TypeDef *ADCx, uint8_t channel);
igorsk	0:1063a091a062	279	FlagStatus ADC_ChannelGetStatus(LPC_ADC_TypeDef *ADCx, uint8_t channel, uint32_t StatusType);
igorsk	0:1063a091a062	280	uint16_t ADC_GlobalGetData(LPC_ADC_TypeDef *ADCx, uint8_t channel);
igorsk	0:1063a091a062	281	FlagStatus ADC_GlobalGetStatus(LPC_ADC_TypeDef *ADCx, uint32_t StatusType);
igorsk	0:1063a091a062	282
igorsk	0:1063a091a062	283	/**
igorsk	0:1063a091a062	284	* @}
igorsk	0:1063a091a062	285	*/
igorsk	0:1063a091a062	286
igorsk	0:1063a091a062	287
igorsk	0:1063a091a062	288	#ifdef __cplusplus
igorsk	0:1063a091a062	289	}
igorsk	0:1063a091a062	290	#endif
igorsk	0:1063a091a062	291
igorsk	0:1063a091a062	292
igorsk	0:1063a091a062	293	#endif /* LPC17XX_ADC_H_ */
igorsk	0:1063a091a062	294
igorsk	0:1063a091a062	295	/**
igorsk	0:1063a091a062	296	* @}
igorsk	0:1063a091a062	297	*/
igorsk	0:1063a091a062	298
igorsk	0:1063a091a062	299	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	17 Feb 2010
Imports:	121
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	5

include/lpc17xx_adc.h@0:1063a091a062, 2010-02-17 (annotated)

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