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DeviceSSP.c@197:7a05523bf588, 2016-10-19 (annotated)

Committer:
Kovalev_D
Date:
Wed Oct 19 10:55:05 2016 +0000
Revision:
197:7a05523bf588
Parent:
173:7f938afb0447 
modul

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Diletant 149:abbf7663d27d 1 #include "Device.h"
Diletant 156:e68ee0bcdcda 2
Diletant 156:e68ee0bcdcda 3 #define SSPCR1_SSE 0x00000002
Diletant 156:e68ee0bcdcda 4
Diletant 156:e68ee0bcdcda 5 #define TX_SSP_EMPT 0x00000001
Diletant 156:e68ee0bcdcda 6 #define RX_SSP_notEMPT 0x00000004
Diletant 156:e68ee0bcdcda 7 #define TX_SSP_notFULL 0x00000002
Diletant 156:e68ee0bcdcda 8 #define RX_SSP_FULL 0x00000008
Diletant 156:e68ee0bcdcda 9 #define SSP_BUSY 0x00000010
Diletant 156:e68ee0bcdcda 10
Diletant 156:e68ee0bcdcda 11 #define ADC_ERR_MSK 0x00000001
Diletant 156:e68ee0bcdcda 12 #define DAC_ERR_MSK 0x00000002
Diletant 156:e68ee0bcdcda 13
Diletant 149:abbf7663d27d 14 extern Device device;
Diletant 149:abbf7663d27d 15
Diletant 167:bedc0a9d559a 16 void InitSSPDefaultSettings(void){
Diletant 149:abbf7663d27d 17 }
Diletant 149:abbf7663d27d 18
Diletant 167:bedc0a9d559a 19 void InitSSPState(void){
Diletant 167:bedc0a9d559a 20 }
Diletant 167:bedc0a9d559a 21
Diletant 167:bedc0a9d559a 22 void DeviceStartSSP(void){
Diletant 156:e68ee0bcdcda 23 uint32_t Dummy;
Diletant 156:e68ee0bcdcda 24
Diletant 156:e68ee0bcdcda 25 LPC_SC->PCONP |= (1<<21); //Power on SSP0
Diletant 156:e68ee0bcdcda 26
Diletant 156:e68ee0bcdcda 27 /* выбор частоты для переферии используем по умолчания с делителем основной на 4 */
Diletant 156:e68ee0bcdcda 28 LPC_SC->PCLKSEL1 &= ~(0x3<<10); //00 CLK/4; 1 CLK; 2 CLK/2; 3 CLK/8
Diletant 156:e68ee0bcdcda 29 LPC_SC->PCLKSEL1 |= (0x0<<10); //00 CLK/4; 1 CLK; 2 CLK/2; 3 CLK/
Diletant 156:e68ee0bcdcda 30
Diletant 156:e68ee0bcdcda 31 // P0.15~0.18 as SSP0
Diletant 156:e68ee0bcdcda 32 LPC_PINCON->PINSEL0 &= ~(0x3UL<<30); //установит Р 0.15
Diletant 156:e68ee0bcdcda 33 LPC_PINCON->PINSEL0 |= (0x2UL<<30); //частота для синхронизациии Master - slave
Diletant 156:e68ee0bcdcda 34
Diletant 156:e68ee0bcdcda 35 LPC_PINCON->PINSEL1 &= ~((0x3<<0)|(0x3<<2)|(0x3<<4)); // устанивоить Р 0.17 и Р 0.18
Diletant 156:e68ee0bcdcda 36 LPC_PINCON->PINSEL1 |= ((0x2<<2)|(0x2<<4)); // как MISO0 и MOSI0
Diletant 156:e68ee0bcdcda 37
Diletant 156:e68ee0bcdcda 38 LPC_PINCON->PINMODE0 &= ~(0x3UL<<30);// ? установление на Р 0.15 режима On-Chip pull-down resistor enabled
Diletant 156:e68ee0bcdcda 39 LPC_PINCON->PINMODE0 |= (0x3UL<<30);// ? установление на Р 0.15 режима On-Chip pull-down resistor enabled
Diletant 156:e68ee0bcdcda 40
Diletant 156:e68ee0bcdcda 41 LPC_PINCON->PINMODE1 &= ~((0x3<<2)|(0x3<<4));// ? установление на Р 0.17 и Р 0.18 режима On-Chip pull-down resistor enabled
Diletant 156:e68ee0bcdcda 42 LPC_PINCON->PINMODE1 |= ((0x3<<2)|(0x3<<4));// ? установление на Р 0.17 и Р 0.18 режима On-Chip pull-down resistor enabled
Diletant 156:e68ee0bcdcda 43
Diletant 156:e68ee0bcdcda 44 LPC_SSP0->CR0 = ((3<<8)|(0<<7)|(0<<4) |0xF); // (0xF)-установление DSS(Data sise select) в 16-битный формат, (3<<8 scr - выбор частоты),
Diletant 156:e68ee0bcdcda 45 // низкий уровень линии тактирования между кадрами, прикрепление передачи к первому нарастанию тактового мигнала
Diletant 156:e68ee0bcdcda 46 // формат кадра TI.
Diletant 156:e68ee0bcdcda 47
Diletant 156:e68ee0bcdcda 48 /* SSPCPSR clock prescale register, master mode, minimum divisor is 0x02 */
Diletant 156:e68ee0bcdcda 49 LPC_SSP0->CPSR = 0x2; // freq = CLK/(cpsdvr*(scr+1)) = 1.6 MHz
Diletant 156:e68ee0bcdcda 50
Diletant 156:e68ee0bcdcda 51 /*SSP enable, master mode */
Diletant 156:e68ee0bcdcda 52 LPC_SSP0->CR1 = SSPCR1_SSE;
Diletant 156:e68ee0bcdcda 53 while (LPC_SSP0->SR & SSP_BUSY); //wait until busy
Diletant 156:e68ee0bcdcda 54 while (LPC_SSP0->SR & RX_SSP_notEMPT) /* clear the RxFIFO */
Diletant 156:e68ee0bcdcda 55 Dummy = LPC_SSP0->DR;
Diletant 156:e68ee0bcdcda 56 //all pins after reset is in GPIO mode, so CS pins needn't to configure
Diletant 156:e68ee0bcdcda 57 LPC_GPIO0->FIODIR |= (1<<16); // P0.16 defined as CS for ADC
Diletant 156:e68ee0bcdcda 58 LPC_GPIO0->FIOSET |= (1<<16); // set CS for ADC
Diletant 156:e68ee0bcdcda 59
Diletant 156:e68ee0bcdcda 60 LPC_GPIO0->FIODIR |= (1<<23); // P defined as CS for DAC
Diletant 156:e68ee0bcdcda 61 LPC_GPIO0->FIOCLR |= (1<<23); // set CS for DAC
Diletant 156:e68ee0bcdcda 62 while (LPC_SSP1->SR & RX_SSP_notEMPT)
Diletant 156:e68ee0bcdcda 63 Dummy = LPC_SSP1->DR; /* clear the RxFIFO */
Diletant 149:abbf7663d27d 64 }
Diletant 149:abbf7663d27d 65
Diletant 173:7f938afb0447 66 void sspReceive(void){
Diletant 149:abbf7663d27d 67 //Prepare ADCs for sampling
Diletant 149:abbf7663d27d 68 LPC_GPIO0->FIOCLR = 1<<16; //reset SSEL signal for ADCs
Diletant 149:abbf7663d27d 69 //Start ADCs sampling
Diletant 149:abbf7663d27d 70 LPC_GPIO0->FIOSET = 1<<16; //set SSEL signal for ADCs
Diletant 149:abbf7663d27d 71 //Get samples
Diletant 166:c3c0b8a90d81 72
Diletant 166:c3c0b8a90d81 73 device.controller.SSP.in[4] += LPC_SSP0->DR;
Diletant 166:c3c0b8a90d81 74 device.controller.SSP.in[3] += LPC_SSP0->DR;
Diletant 166:c3c0b8a90d81 75 device.controller.SSP.in[2] += LPC_SSP0->DR;
Diletant 166:c3c0b8a90d81 76 device.controller.SSP.in[1] += LPC_SSP0->DR;
Diletant 166:c3c0b8a90d81 77 device.controller.SSP.in[0] += LPC_SSP0->DR;
Diletant 166:c3c0b8a90d81 78
Diletant 166:c3c0b8a90d81 79 /*
Diletant 156:e68ee0bcdcda 80 device.controller.SSP.accumulator[4] += LPC_SSP0->DR;
Diletant 156:e68ee0bcdcda 81 device.controller.SSP.accumulator[3] += LPC_SSP0->DR;
Diletant 156:e68ee0bcdcda 82 device.controller.SSP.accumulator[2] += LPC_SSP0->DR;
Diletant 156:e68ee0bcdcda 83 device.controller.SSP.accumulator[1] += LPC_SSP0->DR;
Diletant 156:e68ee0bcdcda 84 device.controller.SSP.accumulator[0] += LPC_SSP0->DR;
Diletant 166:c3c0b8a90d81 85 */
Diletant 166:c3c0b8a90d81 86
Diletant 166:c3c0b8a90d81 87 //Clear input queue
Diletant 173:7f938afb0447 88 uint32_t value;
Diletant 149:abbf7663d27d 89 while (LPC_SSP0->SR & 0x00000004) value = LPC_SSP0->DR;
Diletant 166:c3c0b8a90d81 90 /*
Diletant 149:abbf7663d27d 91 //Average samples for dither period
Diletant 166:c3c0b8a90d81 92 if (device.measurement.counter == 31) {
Diletant 149:abbf7663d27d 93 for (uint8_t i = 0; i < 5; i++){
Diletant 156:e68ee0bcdcda 94 device.controller.SSP.in[i] = device.controller.SSP.accumulator[i] >> 5;
Diletant 166:c3c0b8a90d81 95 device.controller.SSP.accumulator[i] = 0;
Diletant 149:abbf7663d27d 96 }
Diletant 149:abbf7663d27d 97 }
Diletant 166:c3c0b8a90d81 98 */
Diletant 149:abbf7663d27d 99 }
Diletant 149:abbf7663d27d 100
Diletant 173:7f938afb0447 101 void sspTransmit(uint8_t index){
Diletant 149:abbf7663d27d 102 LPC_GPIO0->FIOSET = 1<<23; //set SSEL signal for DACs
Diletant 149:abbf7663d27d 103 LPC_GPIO0->FIOCLR = 1<<23; //reset SSEL signal for DACs
Diletant 149:abbf7663d27d 104
Diletant 149:abbf7663d27d 105 LPC_SSP0->DR=0x5555;
Diletant 149:abbf7663d27d 106 LPC_SSP0->DR=0x5555;
Diletant 149:abbf7663d27d 107 LPC_SSP0->DR=0x5555;
Diletant 149:abbf7663d27d 108
Diletant 149:abbf7663d27d 109 if (index){
Diletant 149:abbf7663d27d 110 LPC_SSP0->DR = 0x00000030; //Write DAC0
Diletant 156:e68ee0bcdcda 111 LPC_SSP0->DR = device.controller.SSP.out[0];
Diletant 149:abbf7663d27d 112 } else {
Diletant 149:abbf7663d27d 113 LPC_SSP0->DR = 0x00000031; //Write DAC1
Diletant 156:e68ee0bcdcda 114 LPC_SSP0->DR = device.controller.SSP.out[1];
Diletant 149:abbf7663d27d 115 }
Diletant 149:abbf7663d27d 116 }