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DeviceSSP.c@156:e68ee0bcdcda, 2016-05-09 (annotated)

Committer:
Diletant
Date:
Mon May 09 20:03:26 2016 +0000
Revision:
156:e68ee0bcdcda
Parent:
149:abbf7663d27d
Child:
166:c3c0b8a90d81
Device & ... update. Not final!!!

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Diletant 149:abbf7663d27d 1 #include "Device.h"
Diletant 156:e68ee0bcdcda 2
Diletant 156:e68ee0bcdcda 3 #define SSPCR1_SSE 0x00000002
Diletant 156:e68ee0bcdcda 4
Diletant 156:e68ee0bcdcda 5 #define TX_SSP_EMPT 0x00000001
Diletant 156:e68ee0bcdcda 6 #define RX_SSP_notEMPT 0x00000004
Diletant 156:e68ee0bcdcda 7 #define TX_SSP_notFULL 0x00000002
Diletant 156:e68ee0bcdcda 8 #define RX_SSP_FULL 0x00000008
Diletant 156:e68ee0bcdcda 9 #define SSP_BUSY 0x00000010
Diletant 156:e68ee0bcdcda 10
Diletant 156:e68ee0bcdcda 11 #define ADC_ERR_MSK 0x00000001
Diletant 156:e68ee0bcdcda 12 #define DAC_ERR_MSK 0x00000002
Diletant 156:e68ee0bcdcda 13
Diletant 149:abbf7663d27d 14 extern Device device;
Diletant 149:abbf7663d27d 15
Diletant 149:abbf7663d27d 16 void InitSSPWithDefaults(void){
Diletant 149:abbf7663d27d 17 }
Diletant 149:abbf7663d27d 18
Diletant 149:abbf7663d27d 19 void InitSSP(void){
Diletant 156:e68ee0bcdcda 20 uint32_t Dummy;
Diletant 156:e68ee0bcdcda 21
Diletant 156:e68ee0bcdcda 22 LPC_SC->PCONP |= (1<<21); //Power on SSP0
Diletant 156:e68ee0bcdcda 23
Diletant 156:e68ee0bcdcda 24 /* выбор частоты для переферии используем по умолчания с делителем основной на 4 */
Diletant 156:e68ee0bcdcda 25 LPC_SC->PCLKSEL1 &= ~(0x3<<10); //00 CLK/4; 1 CLK; 2 CLK/2; 3 CLK/8
Diletant 156:e68ee0bcdcda 26 LPC_SC->PCLKSEL1 |= (0x0<<10); //00 CLK/4; 1 CLK; 2 CLK/2; 3 CLK/
Diletant 156:e68ee0bcdcda 27
Diletant 156:e68ee0bcdcda 28 // P0.15~0.18 as SSP0
Diletant 156:e68ee0bcdcda 29 LPC_PINCON->PINSEL0 &= ~(0x3UL<<30); //установит Р 0.15
Diletant 156:e68ee0bcdcda 30 LPC_PINCON->PINSEL0 |= (0x2UL<<30); //частота для синхронизациии Master - slave
Diletant 156:e68ee0bcdcda 31
Diletant 156:e68ee0bcdcda 32 LPC_PINCON->PINSEL1 &= ~((0x3<<0)|(0x3<<2)|(0x3<<4)); // устанивоить Р 0.17 и Р 0.18
Diletant 156:e68ee0bcdcda 33 LPC_PINCON->PINSEL1 |= ((0x2<<2)|(0x2<<4)); // как MISO0 и MOSI0
Diletant 156:e68ee0bcdcda 34
Diletant 156:e68ee0bcdcda 35 LPC_PINCON->PINMODE0 &= ~(0x3UL<<30);// ? установление на Р 0.15 режима On-Chip pull-down resistor enabled
Diletant 156:e68ee0bcdcda 36 LPC_PINCON->PINMODE0 |= (0x3UL<<30);// ? установление на Р 0.15 режима On-Chip pull-down resistor enabled
Diletant 156:e68ee0bcdcda 37
Diletant 156:e68ee0bcdcda 38 LPC_PINCON->PINMODE1 &= ~((0x3<<2)|(0x3<<4));// ? установление на Р 0.17 и Р 0.18 режима On-Chip pull-down resistor enabled
Diletant 156:e68ee0bcdcda 39 LPC_PINCON->PINMODE1 |= ((0x3<<2)|(0x3<<4));// ? установление на Р 0.17 и Р 0.18 режима On-Chip pull-down resistor enabled
Diletant 156:e68ee0bcdcda 40
Diletant 156:e68ee0bcdcda 41 LPC_SSP0->CR0 = ((3<<8)|(0<<7)|(0<<4) |0xF); // (0xF)-установление DSS(Data sise select) в 16-битный формат, (3<<8 scr - выбор частоты),
Diletant 156:e68ee0bcdcda 42 // низкий уровень линии тактирования между кадрами, прикрепление передачи к первому нарастанию тактового мигнала
Diletant 156:e68ee0bcdcda 43 // формат кадра TI.
Diletant 156:e68ee0bcdcda 44
Diletant 156:e68ee0bcdcda 45 /* SSPCPSR clock prescale register, master mode, minimum divisor is 0x02 */
Diletant 156:e68ee0bcdcda 46 LPC_SSP0->CPSR = 0x2; // freq = CLK/(cpsdvr*(scr+1)) = 1.6 MHz
Diletant 156:e68ee0bcdcda 47
Diletant 156:e68ee0bcdcda 48 /*SSP enable, master mode */
Diletant 156:e68ee0bcdcda 49 LPC_SSP0->CR1 = SSPCR1_SSE;
Diletant 156:e68ee0bcdcda 50 while (LPC_SSP0->SR & SSP_BUSY); //wait until busy
Diletant 156:e68ee0bcdcda 51 while (LPC_SSP0->SR & RX_SSP_notEMPT) /* clear the RxFIFO */
Diletant 156:e68ee0bcdcda 52 Dummy = LPC_SSP0->DR;
Diletant 156:e68ee0bcdcda 53 //all pins after reset is in GPIO mode, so CS pins needn't to configure
Diletant 156:e68ee0bcdcda 54 LPC_GPIO0->FIODIR |= (1<<16); // P0.16 defined as CS for ADC
Diletant 156:e68ee0bcdcda 55 LPC_GPIO0->FIOSET |= (1<<16); // set CS for ADC
Diletant 156:e68ee0bcdcda 56
Diletant 156:e68ee0bcdcda 57 LPC_GPIO0->FIODIR |= (1<<23); // P defined as CS for DAC
Diletant 156:e68ee0bcdcda 58 LPC_GPIO0->FIOCLR |= (1<<23); // set CS for DAC
Diletant 156:e68ee0bcdcda 59 while (LPC_SSP1->SR & RX_SSP_notEMPT)
Diletant 156:e68ee0bcdcda 60 Dummy = LPC_SSP1->DR; /* clear the RxFIFO */
Diletant 149:abbf7663d27d 61 }
Diletant 149:abbf7663d27d 62
Diletant 149:abbf7663d27d 63 void DeviceSSPReceive(void){
Diletant 149:abbf7663d27d 64 //Prepare ADCs for sampling
Diletant 149:abbf7663d27d 65 LPC_GPIO0->FIOCLR = 1<<16; //reset SSEL signal for ADCs
Diletant 149:abbf7663d27d 66 //Start ADCs sampling
Diletant 149:abbf7663d27d 67 LPC_GPIO0->FIOSET = 1<<16; //set SSEL signal for ADCs
Diletant 149:abbf7663d27d 68 //Get samples
Diletant 149:abbf7663d27d 69 uint32_t value;
Diletant 156:e68ee0bcdcda 70 device.controller.SSP.accumulator[4] += LPC_SSP0->DR;
Diletant 156:e68ee0bcdcda 71 device.controller.SSP.accumulator[3] += LPC_SSP0->DR;
Diletant 156:e68ee0bcdcda 72 device.controller.SSP.accumulator[2] += LPC_SSP0->DR;
Diletant 156:e68ee0bcdcda 73 device.controller.SSP.accumulator[1] += LPC_SSP0->DR;
Diletant 156:e68ee0bcdcda 74 device.controller.SSP.accumulator[0] += LPC_SSP0->DR;
Diletant 149:abbf7663d27d 75 while (LPC_SSP0->SR & 0x00000004) value = LPC_SSP0->DR;
Diletant 149:abbf7663d27d 76 //Average samples for dither period
Diletant 156:e68ee0bcdcda 77 if (device.measurement.counter == 0) {
Diletant 149:abbf7663d27d 78 for (uint8_t i = 0; i < 5; i++){
Diletant 156:e68ee0bcdcda 79 device.controller.SSP.in[i] = device.controller.SSP.accumulator[i] >> 5;
Diletant 156:e68ee0bcdcda 80 device.controller.SSP.accumulator[i] = 0;
Diletant 156:e68ee0bcdcda 81 device.controller.SSP.dataReady = 1;
Diletant 149:abbf7663d27d 82 }
Diletant 149:abbf7663d27d 83 }
Diletant 149:abbf7663d27d 84 }
Diletant 149:abbf7663d27d 85
Diletant 149:abbf7663d27d 86 void DeviceSSPTransmit(uint8_t index){
Diletant 149:abbf7663d27d 87 LPC_GPIO0->FIOSET = 1<<23; //set SSEL signal for DACs
Diletant 149:abbf7663d27d 88 LPC_GPIO0->FIOCLR = 1<<23; //reset SSEL signal for DACs
Diletant 149:abbf7663d27d 89
Diletant 149:abbf7663d27d 90 LPC_SSP0->DR=0x5555;
Diletant 149:abbf7663d27d 91 LPC_SSP0->DR=0x5555;
Diletant 149:abbf7663d27d 92 LPC_SSP0->DR=0x5555;
Diletant 149:abbf7663d27d 93
Diletant 149:abbf7663d27d 94 if (index){
Diletant 149:abbf7663d27d 95 LPC_SSP0->DR = 0x00000030; //Write DAC0
Diletant 156:e68ee0bcdcda 96 LPC_SSP0->DR = device.controller.SSP.out[0];
Diletant 149:abbf7663d27d 97 } else {
Diletant 149:abbf7663d27d 98 LPC_SSP0->DR = 0x00000031; //Write DAC1
Diletant 156:e68ee0bcdcda 99 LPC_SSP0->DR = device.controller.SSP.out[1];
Diletant 149:abbf7663d27d 100 }
Diletant 149:abbf7663d27d 101 }