iforce2d Chris / Mbed 2 deprecated ubxDistanceMeter

Displays distance to start location on OLED screen.

Dependencies:   mbed

u8g_dev_uc1610_dogxl160.c@0:972874f31c98, 2018-03-07 (annotated)

Committer:
iforce2d
Date:
Wed Mar 07 12:49:14 2018 +0000
Revision:
0:972874f31c98
First commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
iforce2d 0:972874f31c98 1 /*
iforce2d 0:972874f31c98 2
iforce2d 0:972874f31c98 3 u8g_dev_uc1610_dogxl160.c
iforce2d 0:972874f31c98 4
iforce2d 0:972874f31c98 5 Universal 8bit Graphics Library
iforce2d 0:972874f31c98 6
iforce2d 0:972874f31c98 7 Copyright (c) 2011, olikraus@gmail.com
iforce2d 0:972874f31c98 8 All rights reserved.
iforce2d 0:972874f31c98 9
iforce2d 0:972874f31c98 10 Redistribution and use in source and binary forms, with or without modification,
iforce2d 0:972874f31c98 11 are permitted provided that the following conditions are met:
iforce2d 0:972874f31c98 12
iforce2d 0:972874f31c98 13 * Redistributions of source code must retain the above copyright notice, this list
iforce2d 0:972874f31c98 14 of conditions and the following disclaimer.
iforce2d 0:972874f31c98 15
iforce2d 0:972874f31c98 16 * Redistributions in binary form must reproduce the above copyright notice, this
iforce2d 0:972874f31c98 17 list of conditions and the following disclaimer in the documentation and/or other
iforce2d 0:972874f31c98 18 materials provided with the distribution.
iforce2d 0:972874f31c98 19
iforce2d 0:972874f31c98 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
iforce2d 0:972874f31c98 21 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
iforce2d 0:972874f31c98 22 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
iforce2d 0:972874f31c98 23 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
iforce2d 0:972874f31c98 24 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
iforce2d 0:972874f31c98 25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
iforce2d 0:972874f31c98 26 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
iforce2d 0:972874f31c98 27 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
iforce2d 0:972874f31c98 28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
iforce2d 0:972874f31c98 29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
iforce2d 0:972874f31c98 30 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
iforce2d 0:972874f31c98 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
iforce2d 0:972874f31c98 32 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
iforce2d 0:972874f31c98 33
iforce2d 0:972874f31c98 34
iforce2d 0:972874f31c98 35 */
iforce2d 0:972874f31c98 36
iforce2d 0:972874f31c98 37 #include "u8g.h"
iforce2d 0:972874f31c98 38
iforce2d 0:972874f31c98 39 #define WIDTH 160
iforce2d 0:972874f31c98 40 #define HEIGHT 104
iforce2d 0:972874f31c98 41
iforce2d 0:972874f31c98 42 static const uint8_t u8g_dev_uc1610_dogxl160_init_seq[] PROGMEM = {
iforce2d 0:972874f31c98 43 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 44 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 45 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
iforce2d 0:972874f31c98 46 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 47 0x0f1, /* set display height-1 */
iforce2d 0:972874f31c98 48 0x067, /* */
iforce2d 0:972874f31c98 49 0x0c0, /* SEG & COM normal */
iforce2d 0:972874f31c98 50 0x040, /* set display start line */
iforce2d 0:972874f31c98 51 0x050, /* */
iforce2d 0:972874f31c98 52 0x02b, /* set panelloading */
iforce2d 0:972874f31c98 53 0x0eb, /* set bias 1/2 */
iforce2d 0:972874f31c98 54 0x081, /* set contrast */
iforce2d 0:972874f31c98 55 0x05f, /* */
iforce2d 0:972874f31c98 56 0x089, /* set auto increment */
iforce2d 0:972874f31c98 57 0x0a6, /* normal pixel mode */
iforce2d 0:972874f31c98 58 0x0d3, /* 0xd3=40% RMS separation for gray levels */
iforce2d 0:972874f31c98 59 0x0af, /* display on */
iforce2d 0:972874f31c98 60 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 61 0x0a5, /* display all points, ST7565, UC1610 */
iforce2d 0:972874f31c98 62 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 63 U8G_ESC_DLY(100), /* delay 100 ms */
iforce2d 0:972874f31c98 64 0x0a4, /* normal display */
iforce2d 0:972874f31c98 65
iforce2d 0:972874f31c98 66
iforce2d 0:972874f31c98 67 U8G_ESC_CS(0), /* disable chip */
iforce2d 0:972874f31c98 68 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 69 };
iforce2d 0:972874f31c98 70
iforce2d 0:972874f31c98 71 static const uint8_t u8g_dev_uc1610_dogxl160_data_start[] PROGMEM = {
iforce2d 0:972874f31c98 72 U8G_ESC_ADR(0), /* instruction mode */
iforce2d 0:972874f31c98 73 U8G_ESC_CS(1), /* enable chip */
iforce2d 0:972874f31c98 74 0x010, /* set upper 4 bit of the col adr to 0 */
iforce2d 0:972874f31c98 75 0x000, /* set lower 4 bit of the col adr to 0 */
iforce2d 0:972874f31c98 76 U8G_ESC_END /* end of sequence */
iforce2d 0:972874f31c98 77 };
iforce2d 0:972874f31c98 78
iforce2d 0:972874f31c98 79 static uint8_t u8g_dev_1to2(uint8_t n)
iforce2d 0:972874f31c98 80 {
iforce2d 0:972874f31c98 81 register uint8_t a,b,c;
iforce2d 0:972874f31c98 82 a = n;
iforce2d 0:972874f31c98 83 a &= 1;
iforce2d 0:972874f31c98 84 n <<= 1;
iforce2d 0:972874f31c98 85 b = n;
iforce2d 0:972874f31c98 86 b &= 4;
iforce2d 0:972874f31c98 87 n <<= 1;
iforce2d 0:972874f31c98 88 c = n;
iforce2d 0:972874f31c98 89 c &= 16;
iforce2d 0:972874f31c98 90 n <<= 1;
iforce2d 0:972874f31c98 91 n &= 64;
iforce2d 0:972874f31c98 92 n |= a;
iforce2d 0:972874f31c98 93 n |= b;
iforce2d 0:972874f31c98 94 n |= c;
iforce2d 0:972874f31c98 95 n |= n << 1;
iforce2d 0:972874f31c98 96 return n;
iforce2d 0:972874f31c98 97 }
iforce2d 0:972874f31c98 98
iforce2d 0:972874f31c98 99 uint8_t u8g_dev_uc1610_dogxl160_bw_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 100 {
iforce2d 0:972874f31c98 101 switch(msg)
iforce2d 0:972874f31c98 102 {
iforce2d 0:972874f31c98 103 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 104 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
iforce2d 0:972874f31c98 105 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1610_dogxl160_init_seq);
iforce2d 0:972874f31c98 106 break;
iforce2d 0:972874f31c98 107 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 108 break;
iforce2d 0:972874f31c98 109 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 110 {
iforce2d 0:972874f31c98 111 int i;
iforce2d 0:972874f31c98 112 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 113 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1610_dogxl160_data_start);
iforce2d 0:972874f31c98 114 u8g_WriteByte(u8g, dev, 0x060 | (pb->p.page*2) ); /* select current page 1/2 (UC1610) */
iforce2d 0:972874f31c98 115 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 116 for( i = 0; i < WIDTH; i++ )
iforce2d 0:972874f31c98 117 {
iforce2d 0:972874f31c98 118 u8g_WriteByte(u8g, dev, u8g_dev_1to2( ((uint8_t *)(pb->buf))[i] ) );
iforce2d 0:972874f31c98 119 }
iforce2d 0:972874f31c98 120
iforce2d 0:972874f31c98 121 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1610_dogxl160_data_start);
iforce2d 0:972874f31c98 122 u8g_WriteByte(u8g, dev, 0x060 | (pb->p.page*2+1) ); /* select current page 2/2 (UC1610) */
iforce2d 0:972874f31c98 123 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 124 for( i = 0; i < WIDTH; i++ )
iforce2d 0:972874f31c98 125 {
iforce2d 0:972874f31c98 126 u8g_WriteByte(u8g, dev, u8g_dev_1to2( ((uint8_t *)(pb->buf))[i] >> 4 ) );
iforce2d 0:972874f31c98 127 }
iforce2d 0:972874f31c98 128
iforce2d 0:972874f31c98 129 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 130 }
iforce2d 0:972874f31c98 131 break;
iforce2d 0:972874f31c98 132 case U8G_DEV_MSG_CONTRAST:
iforce2d 0:972874f31c98 133 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 134 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
iforce2d 0:972874f31c98 135 u8g_WriteByte(u8g, dev, 0x081);
iforce2d 0:972874f31c98 136 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
iforce2d 0:972874f31c98 137 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 138 return 1;
iforce2d 0:972874f31c98 139 }
iforce2d 0:972874f31c98 140 return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 141 }
iforce2d 0:972874f31c98 142
iforce2d 0:972874f31c98 143 uint8_t u8g_dev_uc1610_dogxl160_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 144 {
iforce2d 0:972874f31c98 145 switch(msg)
iforce2d 0:972874f31c98 146 {
iforce2d 0:972874f31c98 147 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 148 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
iforce2d 0:972874f31c98 149 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1610_dogxl160_init_seq);
iforce2d 0:972874f31c98 150 break;
iforce2d 0:972874f31c98 151 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 152 break;
iforce2d 0:972874f31c98 153 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 154 {
iforce2d 0:972874f31c98 155 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 156 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1610_dogxl160_data_start);
iforce2d 0:972874f31c98 157 u8g_WriteByte(u8g, dev, 0x060 | (pb->p.page) ); /* select current page (UC1610) */
iforce2d 0:972874f31c98 158 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 159 if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
iforce2d 0:972874f31c98 160 return 0;
iforce2d 0:972874f31c98 161 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 162 }
iforce2d 0:972874f31c98 163 break;
iforce2d 0:972874f31c98 164 case U8G_DEV_MSG_CONTRAST:
iforce2d 0:972874f31c98 165 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 166 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
iforce2d 0:972874f31c98 167 u8g_WriteByte(u8g, dev, 0x081);
iforce2d 0:972874f31c98 168 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
iforce2d 0:972874f31c98 169 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 170 return 1;
iforce2d 0:972874f31c98 171 }
iforce2d 0:972874f31c98 172 return u8g_dev_pb8v2_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 173 }
iforce2d 0:972874f31c98 174
iforce2d 0:972874f31c98 175 uint8_t u8g_dev_uc1610_dogxl160_2x_bw_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 176 {
iforce2d 0:972874f31c98 177 switch(msg)
iforce2d 0:972874f31c98 178 {
iforce2d 0:972874f31c98 179 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 180 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
iforce2d 0:972874f31c98 181 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1610_dogxl160_init_seq);
iforce2d 0:972874f31c98 182 break;
iforce2d 0:972874f31c98 183 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 184 break;
iforce2d 0:972874f31c98 185 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 186 {
iforce2d 0:972874f31c98 187 int i;
iforce2d 0:972874f31c98 188 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 189
iforce2d 0:972874f31c98 190 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1610_dogxl160_data_start);
iforce2d 0:972874f31c98 191 u8g_WriteByte(u8g, dev, 0x060 | (pb->p.page*4) ); /* select current page 1/2 (UC1610) */
iforce2d 0:972874f31c98 192 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 193 for( i = 0; i < WIDTH; i++ )
iforce2d 0:972874f31c98 194 {
iforce2d 0:972874f31c98 195 u8g_WriteByte(u8g, dev, u8g_dev_1to2( ((uint8_t *)(pb->buf))[i] ) );
iforce2d 0:972874f31c98 196 }
iforce2d 0:972874f31c98 197
iforce2d 0:972874f31c98 198 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1610_dogxl160_data_start);
iforce2d 0:972874f31c98 199 u8g_WriteByte(u8g, dev, 0x060 | (pb->p.page*4+1) ); /* select current page 2/2 (UC1610) */
iforce2d 0:972874f31c98 200 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 201 for( i = 0; i < WIDTH; i++ )
iforce2d 0:972874f31c98 202 {
iforce2d 0:972874f31c98 203 u8g_WriteByte(u8g, dev, u8g_dev_1to2( ((uint8_t *)(pb->buf))[i] >> 4 ) );
iforce2d 0:972874f31c98 204 }
iforce2d 0:972874f31c98 205
iforce2d 0:972874f31c98 206 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1610_dogxl160_data_start);
iforce2d 0:972874f31c98 207 u8g_WriteByte(u8g, dev, 0x060 | (pb->p.page*4+2) ); /* select current page 1/2 (UC1610) */
iforce2d 0:972874f31c98 208 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 209 for( i = 0; i < WIDTH; i++ )
iforce2d 0:972874f31c98 210 {
iforce2d 0:972874f31c98 211 u8g_WriteByte(u8g, dev, u8g_dev_1to2( ((uint8_t *)((uint8_t *)(pb->buf)+WIDTH))[i] ) );
iforce2d 0:972874f31c98 212 }
iforce2d 0:972874f31c98 213
iforce2d 0:972874f31c98 214 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1610_dogxl160_data_start);
iforce2d 0:972874f31c98 215 u8g_WriteByte(u8g, dev, 0x060 | (pb->p.page*4+3) ); /* select current page 2/2 (UC1610) */
iforce2d 0:972874f31c98 216 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 217 for( i = 0; i < WIDTH; i++ )
iforce2d 0:972874f31c98 218 {
iforce2d 0:972874f31c98 219 u8g_WriteByte(u8g, dev, u8g_dev_1to2( ((uint8_t *)((uint8_t *)(pb->buf)+WIDTH))[i] >> 4 ) );
iforce2d 0:972874f31c98 220 }
iforce2d 0:972874f31c98 221
iforce2d 0:972874f31c98 222 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 223 }
iforce2d 0:972874f31c98 224 break;
iforce2d 0:972874f31c98 225 case U8G_DEV_MSG_CONTRAST:
iforce2d 0:972874f31c98 226 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 227 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
iforce2d 0:972874f31c98 228 u8g_WriteByte(u8g, dev, 0x081);
iforce2d 0:972874f31c98 229 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
iforce2d 0:972874f31c98 230 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 231 return 1;
iforce2d 0:972874f31c98 232 }
iforce2d 0:972874f31c98 233 return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 234 }
iforce2d 0:972874f31c98 235
iforce2d 0:972874f31c98 236 uint8_t u8g_dev_uc1610_dogxl160_2x_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
iforce2d 0:972874f31c98 237 {
iforce2d 0:972874f31c98 238 switch(msg)
iforce2d 0:972874f31c98 239 {
iforce2d 0:972874f31c98 240 case U8G_DEV_MSG_INIT:
iforce2d 0:972874f31c98 241 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
iforce2d 0:972874f31c98 242 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1610_dogxl160_init_seq);
iforce2d 0:972874f31c98 243 break;
iforce2d 0:972874f31c98 244 case U8G_DEV_MSG_STOP:
iforce2d 0:972874f31c98 245 break;
iforce2d 0:972874f31c98 246 case U8G_DEV_MSG_PAGE_NEXT:
iforce2d 0:972874f31c98 247 {
iforce2d 0:972874f31c98 248 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
iforce2d 0:972874f31c98 249
iforce2d 0:972874f31c98 250 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1610_dogxl160_data_start);
iforce2d 0:972874f31c98 251 u8g_WriteByte(u8g, dev, 0x060 | (pb->p.page*2) ); /* select current page (UC1610) */
iforce2d 0:972874f31c98 252 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 253 if ( u8g_WriteSequence(u8g, dev, WIDTH, pb->buf) == 0 )
iforce2d 0:972874f31c98 254 return 0;
iforce2d 0:972874f31c98 255
iforce2d 0:972874f31c98 256 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1610_dogxl160_data_start);
iforce2d 0:972874f31c98 257 u8g_WriteByte(u8g, dev, 0x060 | (pb->p.page*2+1) ); /* select current page (UC1610) */
iforce2d 0:972874f31c98 258 u8g_SetAddress(u8g, dev, 1); /* data mode */
iforce2d 0:972874f31c98 259 if ( u8g_WriteSequence(u8g, dev, WIDTH, (uint8_t *)(pb->buf)+WIDTH) == 0 )
iforce2d 0:972874f31c98 260 return 0;
iforce2d 0:972874f31c98 261
iforce2d 0:972874f31c98 262 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 263 }
iforce2d 0:972874f31c98 264 break;
iforce2d 0:972874f31c98 265 case U8G_DEV_MSG_CONTRAST:
iforce2d 0:972874f31c98 266 u8g_SetChipSelect(u8g, dev, 1);
iforce2d 0:972874f31c98 267 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
iforce2d 0:972874f31c98 268 u8g_WriteByte(u8g, dev, 0x081);
iforce2d 0:972874f31c98 269 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
iforce2d 0:972874f31c98 270 u8g_SetChipSelect(u8g, dev, 0);
iforce2d 0:972874f31c98 271 return 1;
iforce2d 0:972874f31c98 272 }
iforce2d 0:972874f31c98 273 return u8g_dev_pb16v2_base_fn(u8g, dev, msg, arg);
iforce2d 0:972874f31c98 274 }
iforce2d 0:972874f31c98 275
iforce2d 0:972874f31c98 276 U8G_PB_DEV(u8g_dev_uc1610_dogxl160_bw_sw_spi, WIDTH, HEIGHT, 8, u8g_dev_uc1610_dogxl160_bw_fn, U8G_COM_SW_SPI);
iforce2d 0:972874f31c98 277 U8G_PB_DEV(u8g_dev_uc1610_dogxl160_bw_hw_spi, WIDTH, HEIGHT, 8, u8g_dev_uc1610_dogxl160_bw_fn, U8G_COM_HW_SPI);
iforce2d 0:972874f31c98 278
iforce2d 0:972874f31c98 279 U8G_PB_DEV(u8g_dev_uc1610_dogxl160_gr_sw_spi, WIDTH, HEIGHT, 4, u8g_dev_uc1610_dogxl160_gr_fn, U8G_COM_SW_SPI);
iforce2d 0:972874f31c98 280 U8G_PB_DEV(u8g_dev_uc1610_dogxl160_gr_hw_spi, WIDTH, HEIGHT, 4, u8g_dev_uc1610_dogxl160_gr_fn, U8G_COM_HW_SPI);
iforce2d 0:972874f31c98 281
iforce2d 0:972874f31c98 282 uint8_t u8g_dev_uc1610_dogxl160_2x_bw_buf[WIDTH*2] U8G_NOCOMMON ;
iforce2d 0:972874f31c98 283 u8g_pb_t u8g_dev_uc1610_dogxl160_2x_bw_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_uc1610_dogxl160_2x_bw_buf};
iforce2d 0:972874f31c98 284 u8g_dev_t u8g_dev_uc1610_dogxl160_2x_bw_sw_spi = { u8g_dev_uc1610_dogxl160_2x_bw_fn, &u8g_dev_uc1610_dogxl160_2x_bw_pb, U8G_COM_SW_SPI };
iforce2d 0:972874f31c98 285 u8g_dev_t u8g_dev_uc1610_dogxl160_2x_bw_hw_spi = { u8g_dev_uc1610_dogxl160_2x_bw_fn, &u8g_dev_uc1610_dogxl160_2x_bw_pb, U8G_COM_HW_SPI };
iforce2d 0:972874f31c98 286
iforce2d 0:972874f31c98 287 uint8_t u8g_dev_uc1610_dogxl160_2x_gr_buf[WIDTH*2] U8G_NOCOMMON ;
iforce2d 0:972874f31c98 288 u8g_pb_t u8g_dev_uc1610_dogxl160_2x_gr_pb = { {8, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_uc1610_dogxl160_2x_gr_buf};
iforce2d 0:972874f31c98 289 u8g_dev_t u8g_dev_uc1610_dogxl160_2x_gr_sw_spi = { u8g_dev_uc1610_dogxl160_2x_gr_fn, &u8g_dev_uc1610_dogxl160_2x_gr_pb, U8G_COM_SW_SPI };
iforce2d 0:972874f31c98 290 u8g_dev_t u8g_dev_uc1610_dogxl160_2x_gr_hw_spi = { u8g_dev_uc1610_dogxl160_2x_gr_fn, &u8g_dev_uc1610_dogxl160_2x_gr_pb, U8G_COM_HW_SPI };
iforce2d 0:972874f31c98 291