iforce2d Chris / Mbed 2 deprecated ubxDistanceMeter

Displays distance to start location on OLED screen.

Dependencies:   mbed

u8g_com_atmega_st7920_hw_spi.c@0:972874f31c98, 2018-03-07 (annotated)

Committer:
iforce2d
Date:
Wed Mar 07 12:49:14 2018 +0000
Revision:
0:972874f31c98
First commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
iforce2d 0:972874f31c98 1 /*
iforce2d 0:972874f31c98 2
iforce2d 0:972874f31c98 3 u8g_com_atmega_st7920_hw_spi.c
iforce2d 0:972874f31c98 4
iforce2d 0:972874f31c98 5 Universal 8bit Graphics Library
iforce2d 0:972874f31c98 6
iforce2d 0:972874f31c98 7 Copyright (c) 2011, olikraus@gmail.com
iforce2d 0:972874f31c98 8 All rights reserved.
iforce2d 0:972874f31c98 9
iforce2d 0:972874f31c98 10 Redistribution and use in source and binary forms, with or without modification,
iforce2d 0:972874f31c98 11 are permitted provided that the following conditions are met:
iforce2d 0:972874f31c98 12
iforce2d 0:972874f31c98 13 * Redistributions of source code must retain the above copyright notice, this list
iforce2d 0:972874f31c98 14 of conditions and the following disclaimer.
iforce2d 0:972874f31c98 15
iforce2d 0:972874f31c98 16 * Redistributions in binary form must reproduce the above copyright notice, this
iforce2d 0:972874f31c98 17 list of conditions and the following disclaimer in the documentation and/or other
iforce2d 0:972874f31c98 18 materials provided with the distribution.
iforce2d 0:972874f31c98 19
iforce2d 0:972874f31c98 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
iforce2d 0:972874f31c98 21 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
iforce2d 0:972874f31c98 22 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
iforce2d 0:972874f31c98 23 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
iforce2d 0:972874f31c98 24 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
iforce2d 0:972874f31c98 25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
iforce2d 0:972874f31c98 26 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
iforce2d 0:972874f31c98 27 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
iforce2d 0:972874f31c98 28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
iforce2d 0:972874f31c98 29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
iforce2d 0:972874f31c98 30 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
iforce2d 0:972874f31c98 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
iforce2d 0:972874f31c98 32 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
iforce2d 0:972874f31c98 33
iforce2d 0:972874f31c98 34 A special SPI interface for ST7920 controller with HW SPI Support
iforce2d 0:972874f31c98 35
iforce2d 0:972874f31c98 36 Assumes, that
iforce2d 0:972874f31c98 37 MOSI is at PORTB, Pin 3
iforce2d 0:972874f31c98 38 and
iforce2d 0:972874f31c98 39 SCK is at PORTB, Pin 5
iforce2d 0:972874f31c98 40
iforce2d 0:972874f31c98 41 Update for ATOMIC operation done (01 Jun 2013)
iforce2d 0:972874f31c98 42 U8G_ATOMIC_OR(ptr, val)
iforce2d 0:972874f31c98 43 U8G_ATOMIC_AND(ptr, val)
iforce2d 0:972874f31c98 44 U8G_ATOMIC_START()
iforce2d 0:972874f31c98 45 U8G_ATOMIC_END()
iforce2d 0:972874f31c98 46
iforce2d 0:972874f31c98 47
iforce2d 0:972874f31c98 48 */
iforce2d 0:972874f31c98 49
iforce2d 0:972874f31c98 50 #include "u8g.h"
iforce2d 0:972874f31c98 51
iforce2d 0:972874f31c98 52 #if defined(__AVR__)
iforce2d 0:972874f31c98 53 #define U8G_ATMEGA_HW_SPI
iforce2d 0:972874f31c98 54
iforce2d 0:972874f31c98 55 /* remove the definition for attiny */
iforce2d 0:972874f31c98 56 #if __AVR_ARCH__ == 2
iforce2d 0:972874f31c98 57 #undef U8G_ATMEGA_HW_SPI
iforce2d 0:972874f31c98 58 #endif
iforce2d 0:972874f31c98 59 #if __AVR_ARCH__ == 25
iforce2d 0:972874f31c98 60 #undef U8G_ATMEGA_HW_SPI
iforce2d 0:972874f31c98 61 #endif
iforce2d 0:972874f31c98 62
iforce2d 0:972874f31c98 63 #endif
iforce2d 0:972874f31c98 64
iforce2d 0:972874f31c98 65 #if defined(U8G_ATMEGA_HW_SPI)
iforce2d 0:972874f31c98 66
iforce2d 0:972874f31c98 67 #include <avr/interrupt.h>
iforce2d 0:972874f31c98 68 #include <avr/io.h>
iforce2d 0:972874f31c98 69
iforce2d 0:972874f31c98 70 static uint8_t u8g_atmega_st7920_hw_spi_shift_out(u8g_t *u8g, uint8_t val) U8G_NOINLINE;
iforce2d 0:972874f31c98 71 static uint8_t u8g_atmega_st7920_hw_spi_shift_out(u8g_t *u8g, uint8_t val)
iforce2d 0:972874f31c98 72 {
iforce2d 0:972874f31c98 73 /* send data */
iforce2d 0:972874f31c98 74 SPDR = val;
iforce2d 0:972874f31c98 75 /* wait for transmission */
iforce2d 0:972874f31c98 76 while (!(SPSR & (1<<SPIF)))
iforce2d 0:972874f31c98 77 ;
iforce2d 0:972874f31c98 78 /* clear the SPIF flag by reading SPDR */
iforce2d 0:972874f31c98 79 return SPDR;
iforce2d 0:972874f31c98 80 }
iforce2d 0:972874f31c98 81
iforce2d 0:972874f31c98 82
iforce2d 0:972874f31c98 83 static void u8g_com_atmega_st7920_write_byte_hw_spi(u8g_t *u8g, uint8_t rs, uint8_t val) U8G_NOINLINE;
iforce2d 0:972874f31c98 84 static void u8g_com_atmega_st7920_write_byte_hw_spi(u8g_t *u8g, uint8_t rs, uint8_t val)
iforce2d 0:972874f31c98 85 {
iforce2d 0:972874f31c98 86 uint8_t i;
iforce2d 0:972874f31c98 87
iforce2d 0:972874f31c98 88 if ( rs == 0 )
iforce2d 0:972874f31c98 89 {
iforce2d 0:972874f31c98 90 /* command */
iforce2d 0:972874f31c98 91 u8g_atmega_st7920_hw_spi_shift_out(u8g, 0x0f8);
iforce2d 0:972874f31c98 92 }
iforce2d 0:972874f31c98 93 else if ( rs == 1 )
iforce2d 0:972874f31c98 94 {
iforce2d 0:972874f31c98 95 /* data */
iforce2d 0:972874f31c98 96 u8g_atmega_st7920_hw_spi_shift_out(u8g, 0x0fa);
iforce2d 0:972874f31c98 97 }
iforce2d 0:972874f31c98 98
iforce2d 0:972874f31c98 99 u8g_atmega_st7920_hw_spi_shift_out(u8g, val & 0x0f0);
iforce2d 0:972874f31c98 100 u8g_atmega_st7920_hw_spi_shift_out(u8g, val << 4);
iforce2d 0:972874f31c98 101
iforce2d 0:972874f31c98 102 for( i = 0; i < 4; i++ )
iforce2d 0:972874f31c98 103 u8g_10MicroDelay();
iforce2d 0:972874f31c98 104 }
iforce2d 0:972874f31c98 105
iforce2d 0:972874f31c98 106
iforce2d 0:972874f31c98 107 uint8_t u8g_com_atmega_st7920_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
iforce2d 0:972874f31c98 108 {
iforce2d 0:972874f31c98 109 switch(msg)
iforce2d 0:972874f31c98 110 {
iforce2d 0:972874f31c98 111 case U8G_COM_MSG_INIT:
iforce2d 0:972874f31c98 112 u8g_SetPIOutput(u8g, U8G_PI_CS);
iforce2d 0:972874f31c98 113 //u8g_SetPIOutput(u8g, U8G_PI_A0);
iforce2d 0:972874f31c98 114
iforce2d 0:972874f31c98 115 U8G_ATOMIC_START();
iforce2d 0:972874f31c98 116
iforce2d 0:972874f31c98 117 DDRB |= _BV(3); /* D0, MOSI */
iforce2d 0:972874f31c98 118 DDRB |= _BV(5); /* SCK */
iforce2d 0:972874f31c98 119 DDRB |= _BV(2); /* slave select */
iforce2d 0:972874f31c98 120
iforce2d 0:972874f31c98 121 PORTB &= ~_BV(3); /* D0, MOSI = 0 */
iforce2d 0:972874f31c98 122 PORTB &= ~_BV(5); /* SCK = 0 */
iforce2d 0:972874f31c98 123 U8G_ATOMIC_END();
iforce2d 0:972874f31c98 124
iforce2d 0:972874f31c98 125 u8g_SetPILevel(u8g, U8G_PI_CS, 1);
iforce2d 0:972874f31c98 126
iforce2d 0:972874f31c98 127 /*
iforce2d 0:972874f31c98 128 SPR1 SPR0
iforce2d 0:972874f31c98 129 0 0 fclk/4
iforce2d 0:972874f31c98 130 0 1 fclk/16
iforce2d 0:972874f31c98 131 1 0 fclk/64
iforce2d 0:972874f31c98 132 1 1 fclk/128
iforce2d 0:972874f31c98 133 */
iforce2d 0:972874f31c98 134 SPCR = 0;
iforce2d 0:972874f31c98 135
iforce2d 0:972874f31c98 136 /* maybe set CPOL and CPHA to 1 */
iforce2d 0:972874f31c98 137 /* 20 Dez 2012: did set CPOL and CPHA to 1 in Arduino variant! */
iforce2d 0:972874f31c98 138 SPCR = (1<<SPE) | (1<<MSTR)|(0<<SPR1)|(0<<SPR0)|(0<<CPOL)|(0<<CPHA);
iforce2d 0:972874f31c98 139 #ifdef U8G_HW_SPI_2X
iforce2d 0:972874f31c98 140 SPSR = (1 << SPI2X); /* double speed, issue 89 */
iforce2d 0:972874f31c98 141 #endif
iforce2d 0:972874f31c98 142 u8g->pin_list[U8G_PI_A0_STATE] = 0; /* inital RS state: command mode */
iforce2d 0:972874f31c98 143 break;
iforce2d 0:972874f31c98 144
iforce2d 0:972874f31c98 145 case U8G_COM_MSG_STOP:
iforce2d 0:972874f31c98 146 break;
iforce2d 0:972874f31c98 147
iforce2d 0:972874f31c98 148 case U8G_COM_MSG_RESET:
iforce2d 0:972874f31c98 149 u8g_SetPILevel(u8g, U8G_PI_RESET, arg_val);
iforce2d 0:972874f31c98 150 break;
iforce2d 0:972874f31c98 151
iforce2d 0:972874f31c98 152 case U8G_COM_MSG_ADDRESS: /* define cmd (arg_val = 0) or data mode (arg_val = 1) */
iforce2d 0:972874f31c98 153 u8g->pin_list[U8G_PI_A0_STATE] = arg_val;
iforce2d 0:972874f31c98 154 break;
iforce2d 0:972874f31c98 155
iforce2d 0:972874f31c98 156 case U8G_COM_MSG_CHIP_SELECT:
iforce2d 0:972874f31c98 157 if ( arg_val == 0 )
iforce2d 0:972874f31c98 158 {
iforce2d 0:972874f31c98 159 /* disable, note: the st7920 has an active high chip select */
iforce2d 0:972874f31c98 160 u8g_SetPILevel(u8g, U8G_PI_CS, 0);
iforce2d 0:972874f31c98 161 }
iforce2d 0:972874f31c98 162 else
iforce2d 0:972874f31c98 163 {
iforce2d 0:972874f31c98 164 /* u8g_SetPILevel(u8g, U8G_PI_SCK, 0 ); */
iforce2d 0:972874f31c98 165 /* enable */
iforce2d 0:972874f31c98 166 u8g_SetPILevel(u8g, U8G_PI_CS, 1); /* CS = 1 (high active) */
iforce2d 0:972874f31c98 167 }
iforce2d 0:972874f31c98 168 break;
iforce2d 0:972874f31c98 169
iforce2d 0:972874f31c98 170
iforce2d 0:972874f31c98 171 case U8G_COM_MSG_WRITE_BYTE:
iforce2d 0:972874f31c98 172 u8g_com_atmega_st7920_write_byte_hw_spi(u8g, u8g->pin_list[U8G_PI_A0_STATE], arg_val);
iforce2d 0:972874f31c98 173 //u8g->pin_list[U8G_PI_A0_STATE] = 2;
iforce2d 0:972874f31c98 174 break;
iforce2d 0:972874f31c98 175
iforce2d 0:972874f31c98 176 case U8G_COM_MSG_WRITE_SEQ:
iforce2d 0:972874f31c98 177 {
iforce2d 0:972874f31c98 178 register uint8_t *ptr = arg_ptr;
iforce2d 0:972874f31c98 179 while( arg_val > 0 )
iforce2d 0:972874f31c98 180 {
iforce2d 0:972874f31c98 181 u8g_com_atmega_st7920_write_byte_hw_spi(u8g, u8g->pin_list[U8G_PI_A0_STATE], *ptr++);
iforce2d 0:972874f31c98 182 //u8g->pin_list[U8G_PI_A0_STATE] = 2;
iforce2d 0:972874f31c98 183 arg_val--;
iforce2d 0:972874f31c98 184 }
iforce2d 0:972874f31c98 185 }
iforce2d 0:972874f31c98 186 break;
iforce2d 0:972874f31c98 187
iforce2d 0:972874f31c98 188 case U8G_COM_MSG_WRITE_SEQ_P:
iforce2d 0:972874f31c98 189 {
iforce2d 0:972874f31c98 190 register uint8_t *ptr = arg_ptr;
iforce2d 0:972874f31c98 191 while( arg_val > 0 )
iforce2d 0:972874f31c98 192 {
iforce2d 0:972874f31c98 193 u8g_com_atmega_st7920_write_byte_hw_spi(u8g, u8g->pin_list[U8G_PI_A0_STATE], u8g_pgm_read(ptr));
iforce2d 0:972874f31c98 194 //u8g->pin_list[U8G_PI_A0_STATE] = 2;
iforce2d 0:972874f31c98 195 ptr++;
iforce2d 0:972874f31c98 196 arg_val--;
iforce2d 0:972874f31c98 197 }
iforce2d 0:972874f31c98 198 }
iforce2d 0:972874f31c98 199 break;
iforce2d 0:972874f31c98 200 }
iforce2d 0:972874f31c98 201 return 1;
iforce2d 0:972874f31c98 202 }
iforce2d 0:972874f31c98 203
iforce2d 0:972874f31c98 204 #else
iforce2d 0:972874f31c98 205
iforce2d 0:972874f31c98 206
iforce2d 0:972874f31c98 207 uint8_t u8g_com_atmega_st7920_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
iforce2d 0:972874f31c98 208 {
iforce2d 0:972874f31c98 209 return 1;
iforce2d 0:972874f31c98 210 }
iforce2d 0:972874f31c98 211
iforce2d 0:972874f31c98 212
iforce2d 0:972874f31c98 213 #endif
iforce2d 0:972874f31c98 214
iforce2d 0:972874f31c98 215