iforce2d Chris / Mbed 2 deprecated ubxDistanceMeter

Displays distance to start location on OLED screen.

Dependencies:   mbed

u8g_com_atmega_hw_spi.c@0:972874f31c98, 2018-03-07 (annotated)

Committer:
iforce2d
Date:
Wed Mar 07 12:49:14 2018 +0000
Revision:
0:972874f31c98
First commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
iforce2d 0:972874f31c98 1 /*
iforce2d 0:972874f31c98 2
iforce2d 0:972874f31c98 3 u8g_com_atmega_hw_spi.c
iforce2d 0:972874f31c98 4
iforce2d 0:972874f31c98 5 Universal 8bit Graphics Library
iforce2d 0:972874f31c98 6
iforce2d 0:972874f31c98 7 Copyright (c) 2012, olikraus@gmail.com
iforce2d 0:972874f31c98 8 All rights reserved.
iforce2d 0:972874f31c98 9
iforce2d 0:972874f31c98 10 Redistribution and use in source and binary forms, with or without modification,
iforce2d 0:972874f31c98 11 are permitted provided that the following conditions are met:
iforce2d 0:972874f31c98 12
iforce2d 0:972874f31c98 13 * Redistributions of source code must retain the above copyright notice, this list
iforce2d 0:972874f31c98 14 of conditions and the following disclaimer.
iforce2d 0:972874f31c98 15
iforce2d 0:972874f31c98 16 * Redistributions in binary form must reproduce the above copyright notice, this
iforce2d 0:972874f31c98 17 list of conditions and the following disclaimer in the documentation and/or other
iforce2d 0:972874f31c98 18 materials provided with the distribution.
iforce2d 0:972874f31c98 19
iforce2d 0:972874f31c98 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
iforce2d 0:972874f31c98 21 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
iforce2d 0:972874f31c98 22 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
iforce2d 0:972874f31c98 23 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
iforce2d 0:972874f31c98 24 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
iforce2d 0:972874f31c98 25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
iforce2d 0:972874f31c98 26 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
iforce2d 0:972874f31c98 27 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
iforce2d 0:972874f31c98 28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
iforce2d 0:972874f31c98 29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
iforce2d 0:972874f31c98 30 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
iforce2d 0:972874f31c98 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
iforce2d 0:972874f31c98 32 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
iforce2d 0:972874f31c98 33
iforce2d 0:972874f31c98 34
iforce2d 0:972874f31c98 35 Assumes, that
iforce2d 0:972874f31c98 36 MOSI is at PORTB, Pin 3
iforce2d 0:972874f31c98 37 and
iforce2d 0:972874f31c98 38 SCK is at PORTB, Pin 5
iforce2d 0:972874f31c98 39
iforce2d 0:972874f31c98 40 Update for ATOMIC operation done (01 Jun 2013)
iforce2d 0:972874f31c98 41 U8G_ATOMIC_OR(ptr, val)
iforce2d 0:972874f31c98 42 U8G_ATOMIC_AND(ptr, val)
iforce2d 0:972874f31c98 43 U8G_ATOMIC_START()
iforce2d 0:972874f31c98 44 U8G_ATOMIC_END()
iforce2d 0:972874f31c98 45
iforce2d 0:972874f31c98 46
iforce2d 0:972874f31c98 47
iforce2d 0:972874f31c98 48 */
iforce2d 0:972874f31c98 49
iforce2d 0:972874f31c98 50 #include "u8g.h"
iforce2d 0:972874f31c98 51
iforce2d 0:972874f31c98 52
iforce2d 0:972874f31c98 53 #if defined(__AVR__)
iforce2d 0:972874f31c98 54 #define U8G_ATMEGA_HW_SPI
iforce2d 0:972874f31c98 55
iforce2d 0:972874f31c98 56 /* remove the definition for attiny */
iforce2d 0:972874f31c98 57 #if __AVR_ARCH__ == 2
iforce2d 0:972874f31c98 58 #undef U8G_ATMEGA_HW_SPI
iforce2d 0:972874f31c98 59 #endif
iforce2d 0:972874f31c98 60 #if __AVR_ARCH__ == 25
iforce2d 0:972874f31c98 61 #undef U8G_ATMEGA_HW_SPI
iforce2d 0:972874f31c98 62 #endif
iforce2d 0:972874f31c98 63 #endif
iforce2d 0:972874f31c98 64
iforce2d 0:972874f31c98 65
iforce2d 0:972874f31c98 66 #if defined(U8G_ATMEGA_HW_SPI)
iforce2d 0:972874f31c98 67
iforce2d 0:972874f31c98 68 #include <avr/interrupt.h>
iforce2d 0:972874f31c98 69 #include <avr/io.h>
iforce2d 0:972874f31c98 70
iforce2d 0:972874f31c98 71
iforce2d 0:972874f31c98 72 static uint8_t u8g_atmega_spi_out(uint8_t data)
iforce2d 0:972874f31c98 73 {
iforce2d 0:972874f31c98 74 /* unsigned char x = 100; */
iforce2d 0:972874f31c98 75 /* send data */
iforce2d 0:972874f31c98 76 SPDR = data;
iforce2d 0:972874f31c98 77 /* wait for transmission */
iforce2d 0:972874f31c98 78 while (!(SPSR & (1<<SPIF)))
iforce2d 0:972874f31c98 79 ;
iforce2d 0:972874f31c98 80 /* clear the SPIF flag by reading SPDR */
iforce2d 0:972874f31c98 81 return SPDR;
iforce2d 0:972874f31c98 82 }
iforce2d 0:972874f31c98 83
iforce2d 0:972874f31c98 84
iforce2d 0:972874f31c98 85 uint8_t u8g_com_atmega_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
iforce2d 0:972874f31c98 86 {
iforce2d 0:972874f31c98 87 switch(msg)
iforce2d 0:972874f31c98 88 {
iforce2d 0:972874f31c98 89 case U8G_COM_MSG_STOP:
iforce2d 0:972874f31c98 90 break;
iforce2d 0:972874f31c98 91
iforce2d 0:972874f31c98 92 case U8G_COM_MSG_INIT:
iforce2d 0:972874f31c98 93
iforce2d 0:972874f31c98 94 u8g_SetPIOutput(u8g, U8G_PI_CS);
iforce2d 0:972874f31c98 95 u8g_SetPIOutput(u8g, U8G_PI_A0);
iforce2d 0:972874f31c98 96
iforce2d 0:972874f31c98 97 U8G_ATOMIC_START();
iforce2d 0:972874f31c98 98
iforce2d 0:972874f31c98 99 DDRB |= _BV(3); /* D0, MOSI */
iforce2d 0:972874f31c98 100 DDRB |= _BV(5); /* SCK */
iforce2d 0:972874f31c98 101 DDRB |= _BV(2); /* slave select */
iforce2d 0:972874f31c98 102
iforce2d 0:972874f31c98 103 PORTB &= ~_BV(3); /* D0, MOSI = 0 */
iforce2d 0:972874f31c98 104 PORTB &= ~_BV(5); /* SCK = 0 */
iforce2d 0:972874f31c98 105
iforce2d 0:972874f31c98 106 U8G_ATOMIC_END();
iforce2d 0:972874f31c98 107
iforce2d 0:972874f31c98 108 u8g_SetPILevel(u8g, U8G_PI_CS, 1);
iforce2d 0:972874f31c98 109
iforce2d 0:972874f31c98 110 /*
iforce2d 0:972874f31c98 111 SPR1 SPR0
iforce2d 0:972874f31c98 112 0 0 fclk/4 x
iforce2d 0:972874f31c98 113 0 1 fclk/16
iforce2d 0:972874f31c98 114 1 0 fclk/64
iforce2d 0:972874f31c98 115 1 1 fclk/128
iforce2d 0:972874f31c98 116 */
iforce2d 0:972874f31c98 117 SPCR = 0;
iforce2d 0:972874f31c98 118 SPCR = (1<<SPE) | (1<<MSTR)|(0<<SPR1)|(0<<SPR0)|(0<<CPOL)|(0<<CPHA);
iforce2d 0:972874f31c98 119 #ifdef U8G_HW_SPI_2X
iforce2d 0:972874f31c98 120 SPSR = (1 << SPI2X); /* double speed, issue 89 */
iforce2d 0:972874f31c98 121 #endif
iforce2d 0:972874f31c98 122
iforce2d 0:972874f31c98 123 break;
iforce2d 0:972874f31c98 124
iforce2d 0:972874f31c98 125 case U8G_COM_MSG_ADDRESS: /* define cmd (arg_val = 0) or data mode (arg_val = 1) */
iforce2d 0:972874f31c98 126 u8g_SetPILevel(u8g, U8G_PI_A0, arg_val);
iforce2d 0:972874f31c98 127 break;
iforce2d 0:972874f31c98 128
iforce2d 0:972874f31c98 129 case U8G_COM_MSG_CHIP_SELECT:
iforce2d 0:972874f31c98 130
iforce2d 0:972874f31c98 131 if ( arg_val == 0 )
iforce2d 0:972874f31c98 132 {
iforce2d 0:972874f31c98 133 /* disable */
iforce2d 0:972874f31c98 134 u8g_SetPILevel(u8g, U8G_PI_CS, 1);
iforce2d 0:972874f31c98 135 }
iforce2d 0:972874f31c98 136 else
iforce2d 0:972874f31c98 137 {
iforce2d 0:972874f31c98 138 PORTB &= ~_BV(5); /* SCK = 0 */
iforce2d 0:972874f31c98 139 /* enable */
iforce2d 0:972874f31c98 140 u8g_SetPILevel(u8g, U8G_PI_CS, 0); /* CS = 0 (low active) */
iforce2d 0:972874f31c98 141 }
iforce2d 0:972874f31c98 142
iforce2d 0:972874f31c98 143 break;
iforce2d 0:972874f31c98 144
iforce2d 0:972874f31c98 145 case U8G_COM_MSG_RESET:
iforce2d 0:972874f31c98 146 u8g_SetPILevel(u8g, U8G_PI_RESET, arg_val);
iforce2d 0:972874f31c98 147 break;
iforce2d 0:972874f31c98 148
iforce2d 0:972874f31c98 149 case U8G_COM_MSG_WRITE_BYTE:
iforce2d 0:972874f31c98 150 u8g_atmega_spi_out(arg_val);
iforce2d 0:972874f31c98 151 break;
iforce2d 0:972874f31c98 152
iforce2d 0:972874f31c98 153 case U8G_COM_MSG_WRITE_SEQ:
iforce2d 0:972874f31c98 154 {
iforce2d 0:972874f31c98 155 register uint8_t *ptr = arg_ptr;
iforce2d 0:972874f31c98 156 while( arg_val > 0 )
iforce2d 0:972874f31c98 157 {
iforce2d 0:972874f31c98 158 u8g_atmega_spi_out(*ptr++);
iforce2d 0:972874f31c98 159 arg_val--;
iforce2d 0:972874f31c98 160 }
iforce2d 0:972874f31c98 161 }
iforce2d 0:972874f31c98 162 break;
iforce2d 0:972874f31c98 163 case U8G_COM_MSG_WRITE_SEQ_P:
iforce2d 0:972874f31c98 164 {
iforce2d 0:972874f31c98 165 register uint8_t *ptr = arg_ptr;
iforce2d 0:972874f31c98 166 while( arg_val > 0 )
iforce2d 0:972874f31c98 167 {
iforce2d 0:972874f31c98 168 u8g_atmega_spi_out(u8g_pgm_read(ptr));
iforce2d 0:972874f31c98 169 ptr++;
iforce2d 0:972874f31c98 170 arg_val--;
iforce2d 0:972874f31c98 171 }
iforce2d 0:972874f31c98 172 }
iforce2d 0:972874f31c98 173 break;
iforce2d 0:972874f31c98 174 }
iforce2d 0:972874f31c98 175 return 1;
iforce2d 0:972874f31c98 176 }
iforce2d 0:972874f31c98 177
iforce2d 0:972874f31c98 178 #else
iforce2d 0:972874f31c98 179
iforce2d 0:972874f31c98 180 uint8_t u8g_com_atmega_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
iforce2d 0:972874f31c98 181 {
iforce2d 0:972874f31c98 182 return 1;
iforce2d 0:972874f31c98 183 }
iforce2d 0:972874f31c98 184
iforce2d 0:972874f31c98 185 #endif
iforce2d 0:972874f31c98 186
iforce2d 0:972874f31c98 187
iforce2d 0:972874f31c98 188