Kiyoteru Hayama / mbedRobotracer_Edu

mbed robotracer for education.

Robotracer (line follower robot ) using stepper motor.

/media/uploads/hayama/cimg8463.jpg

/media/uploads/hayama/mbedrobotracer-manual-english.pdf

/media/uploads/hayama/mbedrobotracer-manual-japanese.pdf

/media/uploads/hayama/eagle-design-robotracer.zip

movie -> https://www.youtube.com/watch?v=INwun8gSds4

(for competition->) https://www.youtube.com/watch?v=l_gP2pUt4w0

mbed/LPC1768/LPC17xx.h@0:da22b0b4395a, 2013-06-19 (annotated)

Committer:
hayama
Date:
Wed Jun 19 10:00:41 2013 +0000
Revision:
0:da22b0b4395a
mbed robotracer for education ver 1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
hayama 0:da22b0b4395a 1 /**************************************************************************//**
hayama 0:da22b0b4395a 2 * @file LPC17xx.h
hayama 0:da22b0b4395a 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
hayama 0:da22b0b4395a 4 * NXP LPC17xx Device Series
hayama 0:da22b0b4395a 5 * @version: V1.09
hayama 0:da22b0b4395a 6 * @date: 17. March 2010
hayama 0:da22b0b4395a 7
hayama 0:da22b0b4395a 8 *
hayama 0:da22b0b4395a 9 * @note
hayama 0:da22b0b4395a 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
hayama 0:da22b0b4395a 11 *
hayama 0:da22b0b4395a 12 * @par
hayama 0:da22b0b4395a 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
hayama 0:da22b0b4395a 14 * processor based microcontrollers. This file can be freely distributed
hayama 0:da22b0b4395a 15 * within development tools that are supporting such ARM based processors.
hayama 0:da22b0b4395a 16 *
hayama 0:da22b0b4395a 17 * @par
hayama 0:da22b0b4395a 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
hayama 0:da22b0b4395a 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
hayama 0:da22b0b4395a 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
hayama 0:da22b0b4395a 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
hayama 0:da22b0b4395a 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
hayama 0:da22b0b4395a 23 *
hayama 0:da22b0b4395a 24 ******************************************************************************/
hayama 0:da22b0b4395a 25
hayama 0:da22b0b4395a 26
hayama 0:da22b0b4395a 27 #ifndef __LPC17xx_H__
hayama 0:da22b0b4395a 28 #define __LPC17xx_H__
hayama 0:da22b0b4395a 29
hayama 0:da22b0b4395a 30 /*
hayama 0:da22b0b4395a 31 * ==========================================================================
hayama 0:da22b0b4395a 32 * ---------- Interrupt Number Definition -----------------------------------
hayama 0:da22b0b4395a 33 * ==========================================================================
hayama 0:da22b0b4395a 34 */
hayama 0:da22b0b4395a 35
hayama 0:da22b0b4395a 36 typedef enum IRQn
hayama 0:da22b0b4395a 37 {
hayama 0:da22b0b4395a 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
hayama 0:da22b0b4395a 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
hayama 0:da22b0b4395a 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
hayama 0:da22b0b4395a 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
hayama 0:da22b0b4395a 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
hayama 0:da22b0b4395a 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
hayama 0:da22b0b4395a 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
hayama 0:da22b0b4395a 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
hayama 0:da22b0b4395a 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
hayama 0:da22b0b4395a 47
hayama 0:da22b0b4395a 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
hayama 0:da22b0b4395a 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
hayama 0:da22b0b4395a 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
hayama 0:da22b0b4395a 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
hayama 0:da22b0b4395a 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
hayama 0:da22b0b4395a 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
hayama 0:da22b0b4395a 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
hayama 0:da22b0b4395a 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
hayama 0:da22b0b4395a 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
hayama 0:da22b0b4395a 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
hayama 0:da22b0b4395a 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
hayama 0:da22b0b4395a 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
hayama 0:da22b0b4395a 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
hayama 0:da22b0b4395a 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
hayama 0:da22b0b4395a 62 SPI_IRQn = 13, /*!< SPI Interrupt */
hayama 0:da22b0b4395a 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
hayama 0:da22b0b4395a 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
hayama 0:da22b0b4395a 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
hayama 0:da22b0b4395a 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
hayama 0:da22b0b4395a 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
hayama 0:da22b0b4395a 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
hayama 0:da22b0b4395a 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
hayama 0:da22b0b4395a 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
hayama 0:da22b0b4395a 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
hayama 0:da22b0b4395a 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
hayama 0:da22b0b4395a 73 USB_IRQn = 24, /*!< USB Interrupt */
hayama 0:da22b0b4395a 74 CAN_IRQn = 25, /*!< CAN Interrupt */
hayama 0:da22b0b4395a 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
hayama 0:da22b0b4395a 76 I2S_IRQn = 27, /*!< I2S Interrupt */
hayama 0:da22b0b4395a 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
hayama 0:da22b0b4395a 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
hayama 0:da22b0b4395a 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
hayama 0:da22b0b4395a 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
hayama 0:da22b0b4395a 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
hayama 0:da22b0b4395a 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
hayama 0:da22b0b4395a 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
hayama 0:da22b0b4395a 84 } IRQn_Type;
hayama 0:da22b0b4395a 85
hayama 0:da22b0b4395a 86
hayama 0:da22b0b4395a 87 /*
hayama 0:da22b0b4395a 88 * ==========================================================================
hayama 0:da22b0b4395a 89 * ----------- Processor and Core Peripheral Section ------------------------
hayama 0:da22b0b4395a 90 * ==========================================================================
hayama 0:da22b0b4395a 91 */
hayama 0:da22b0b4395a 92
hayama 0:da22b0b4395a 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
hayama 0:da22b0b4395a 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
hayama 0:da22b0b4395a 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
hayama 0:da22b0b4395a 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
hayama 0:da22b0b4395a 97
hayama 0:da22b0b4395a 98
hayama 0:da22b0b4395a 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
hayama 0:da22b0b4395a 100 #include "system_LPC17xx.h" /* System Header */
hayama 0:da22b0b4395a 101
hayama 0:da22b0b4395a 102
hayama 0:da22b0b4395a 103 /******************************************************************************/
hayama 0:da22b0b4395a 104 /* Device Specific Peripheral registers structures */
hayama 0:da22b0b4395a 105 /******************************************************************************/
hayama 0:da22b0b4395a 106
hayama 0:da22b0b4395a 107 #if defined ( __CC_ARM )
hayama 0:da22b0b4395a 108 #pragma anon_unions
hayama 0:da22b0b4395a 109 #endif
hayama 0:da22b0b4395a 110
hayama 0:da22b0b4395a 111 /*------------- System Control (SC) ------------------------------------------*/
hayama 0:da22b0b4395a 112 typedef struct
hayama 0:da22b0b4395a 113 {
hayama 0:da22b0b4395a 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
hayama 0:da22b0b4395a 115 uint32_t RESERVED0[31];
hayama 0:da22b0b4395a 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
hayama 0:da22b0b4395a 117 __IO uint32_t PLL0CFG;
hayama 0:da22b0b4395a 118 __I uint32_t PLL0STAT;
hayama 0:da22b0b4395a 119 __O uint32_t PLL0FEED;
hayama 0:da22b0b4395a 120 uint32_t RESERVED1[4];
hayama 0:da22b0b4395a 121 __IO uint32_t PLL1CON;
hayama 0:da22b0b4395a 122 __IO uint32_t PLL1CFG;
hayama 0:da22b0b4395a 123 __I uint32_t PLL1STAT;
hayama 0:da22b0b4395a 124 __O uint32_t PLL1FEED;
hayama 0:da22b0b4395a 125 uint32_t RESERVED2[4];
hayama 0:da22b0b4395a 126 __IO uint32_t PCON;
hayama 0:da22b0b4395a 127 __IO uint32_t PCONP;
hayama 0:da22b0b4395a 128 uint32_t RESERVED3[15];
hayama 0:da22b0b4395a 129 __IO uint32_t CCLKCFG;
hayama 0:da22b0b4395a 130 __IO uint32_t USBCLKCFG;
hayama 0:da22b0b4395a 131 __IO uint32_t CLKSRCSEL;
hayama 0:da22b0b4395a 132 __IO uint32_t CANSLEEPCLR;
hayama 0:da22b0b4395a 133 __IO uint32_t CANWAKEFLAGS;
hayama 0:da22b0b4395a 134 uint32_t RESERVED4[10];
hayama 0:da22b0b4395a 135 __IO uint32_t EXTINT; /* External Interrupts */
hayama 0:da22b0b4395a 136 uint32_t RESERVED5;
hayama 0:da22b0b4395a 137 __IO uint32_t EXTMODE;
hayama 0:da22b0b4395a 138 __IO uint32_t EXTPOLAR;
hayama 0:da22b0b4395a 139 uint32_t RESERVED6[12];
hayama 0:da22b0b4395a 140 __IO uint32_t RSID; /* Reset */
hayama 0:da22b0b4395a 141 uint32_t RESERVED7[7];
hayama 0:da22b0b4395a 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
hayama 0:da22b0b4395a 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
hayama 0:da22b0b4395a 144 __IO uint32_t PCLKSEL0;
hayama 0:da22b0b4395a 145 __IO uint32_t PCLKSEL1;
hayama 0:da22b0b4395a 146 uint32_t RESERVED8[4];
hayama 0:da22b0b4395a 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
hayama 0:da22b0b4395a 148 __IO uint32_t DMAREQSEL;
hayama 0:da22b0b4395a 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
hayama 0:da22b0b4395a 150 } LPC_SC_TypeDef;
hayama 0:da22b0b4395a 151
hayama 0:da22b0b4395a 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
hayama 0:da22b0b4395a 153 typedef struct
hayama 0:da22b0b4395a 154 {
hayama 0:da22b0b4395a 155 __IO uint32_t PINSEL0;
hayama 0:da22b0b4395a 156 __IO uint32_t PINSEL1;
hayama 0:da22b0b4395a 157 __IO uint32_t PINSEL2;
hayama 0:da22b0b4395a 158 __IO uint32_t PINSEL3;
hayama 0:da22b0b4395a 159 __IO uint32_t PINSEL4;
hayama 0:da22b0b4395a 160 __IO uint32_t PINSEL5;
hayama 0:da22b0b4395a 161 __IO uint32_t PINSEL6;
hayama 0:da22b0b4395a 162 __IO uint32_t PINSEL7;
hayama 0:da22b0b4395a 163 __IO uint32_t PINSEL8;
hayama 0:da22b0b4395a 164 __IO uint32_t PINSEL9;
hayama 0:da22b0b4395a 165 __IO uint32_t PINSEL10;
hayama 0:da22b0b4395a 166 uint32_t RESERVED0[5];
hayama 0:da22b0b4395a 167 __IO uint32_t PINMODE0;
hayama 0:da22b0b4395a 168 __IO uint32_t PINMODE1;
hayama 0:da22b0b4395a 169 __IO uint32_t PINMODE2;
hayama 0:da22b0b4395a 170 __IO uint32_t PINMODE3;
hayama 0:da22b0b4395a 171 __IO uint32_t PINMODE4;
hayama 0:da22b0b4395a 172 __IO uint32_t PINMODE5;
hayama 0:da22b0b4395a 173 __IO uint32_t PINMODE6;
hayama 0:da22b0b4395a 174 __IO uint32_t PINMODE7;
hayama 0:da22b0b4395a 175 __IO uint32_t PINMODE8;
hayama 0:da22b0b4395a 176 __IO uint32_t PINMODE9;
hayama 0:da22b0b4395a 177 __IO uint32_t PINMODE_OD0;
hayama 0:da22b0b4395a 178 __IO uint32_t PINMODE_OD1;
hayama 0:da22b0b4395a 179 __IO uint32_t PINMODE_OD2;
hayama 0:da22b0b4395a 180 __IO uint32_t PINMODE_OD3;
hayama 0:da22b0b4395a 181 __IO uint32_t PINMODE_OD4;
hayama 0:da22b0b4395a 182 __IO uint32_t I2CPADCFG;
hayama 0:da22b0b4395a 183 } LPC_PINCON_TypeDef;
hayama 0:da22b0b4395a 184
hayama 0:da22b0b4395a 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
hayama 0:da22b0b4395a 186 typedef struct
hayama 0:da22b0b4395a 187 {
hayama 0:da22b0b4395a 188 union {
hayama 0:da22b0b4395a 189 __IO uint32_t FIODIR;
hayama 0:da22b0b4395a 190 struct {
hayama 0:da22b0b4395a 191 __IO uint16_t FIODIRL;
hayama 0:da22b0b4395a 192 __IO uint16_t FIODIRH;
hayama 0:da22b0b4395a 193 };
hayama 0:da22b0b4395a 194 struct {
hayama 0:da22b0b4395a 195 __IO uint8_t FIODIR0;
hayama 0:da22b0b4395a 196 __IO uint8_t FIODIR1;
hayama 0:da22b0b4395a 197 __IO uint8_t FIODIR2;
hayama 0:da22b0b4395a 198 __IO uint8_t FIODIR3;
hayama 0:da22b0b4395a 199 };
hayama 0:da22b0b4395a 200 };
hayama 0:da22b0b4395a 201 uint32_t RESERVED0[3];
hayama 0:da22b0b4395a 202 union {
hayama 0:da22b0b4395a 203 __IO uint32_t FIOMASK;
hayama 0:da22b0b4395a 204 struct {
hayama 0:da22b0b4395a 205 __IO uint16_t FIOMASKL;
hayama 0:da22b0b4395a 206 __IO uint16_t FIOMASKH;
hayama 0:da22b0b4395a 207 };
hayama 0:da22b0b4395a 208 struct {
hayama 0:da22b0b4395a 209 __IO uint8_t FIOMASK0;
hayama 0:da22b0b4395a 210 __IO uint8_t FIOMASK1;
hayama 0:da22b0b4395a 211 __IO uint8_t FIOMASK2;
hayama 0:da22b0b4395a 212 __IO uint8_t FIOMASK3;
hayama 0:da22b0b4395a 213 };
hayama 0:da22b0b4395a 214 };
hayama 0:da22b0b4395a 215 union {
hayama 0:da22b0b4395a 216 __IO uint32_t FIOPIN;
hayama 0:da22b0b4395a 217 struct {
hayama 0:da22b0b4395a 218 __IO uint16_t FIOPINL;
hayama 0:da22b0b4395a 219 __IO uint16_t FIOPINH;
hayama 0:da22b0b4395a 220 };
hayama 0:da22b0b4395a 221 struct {
hayama 0:da22b0b4395a 222 __IO uint8_t FIOPIN0;
hayama 0:da22b0b4395a 223 __IO uint8_t FIOPIN1;
hayama 0:da22b0b4395a 224 __IO uint8_t FIOPIN2;
hayama 0:da22b0b4395a 225 __IO uint8_t FIOPIN3;
hayama 0:da22b0b4395a 226 };
hayama 0:da22b0b4395a 227 };
hayama 0:da22b0b4395a 228 union {
hayama 0:da22b0b4395a 229 __IO uint32_t FIOSET;
hayama 0:da22b0b4395a 230 struct {
hayama 0:da22b0b4395a 231 __IO uint16_t FIOSETL;
hayama 0:da22b0b4395a 232 __IO uint16_t FIOSETH;
hayama 0:da22b0b4395a 233 };
hayama 0:da22b0b4395a 234 struct {
hayama 0:da22b0b4395a 235 __IO uint8_t FIOSET0;
hayama 0:da22b0b4395a 236 __IO uint8_t FIOSET1;
hayama 0:da22b0b4395a 237 __IO uint8_t FIOSET2;
hayama 0:da22b0b4395a 238 __IO uint8_t FIOSET3;
hayama 0:da22b0b4395a 239 };
hayama 0:da22b0b4395a 240 };
hayama 0:da22b0b4395a 241 union {
hayama 0:da22b0b4395a 242 __O uint32_t FIOCLR;
hayama 0:da22b0b4395a 243 struct {
hayama 0:da22b0b4395a 244 __O uint16_t FIOCLRL;
hayama 0:da22b0b4395a 245 __O uint16_t FIOCLRH;
hayama 0:da22b0b4395a 246 };
hayama 0:da22b0b4395a 247 struct {
hayama 0:da22b0b4395a 248 __O uint8_t FIOCLR0;
hayama 0:da22b0b4395a 249 __O uint8_t FIOCLR1;
hayama 0:da22b0b4395a 250 __O uint8_t FIOCLR2;
hayama 0:da22b0b4395a 251 __O uint8_t FIOCLR3;
hayama 0:da22b0b4395a 252 };
hayama 0:da22b0b4395a 253 };
hayama 0:da22b0b4395a 254 } LPC_GPIO_TypeDef;
hayama 0:da22b0b4395a 255
hayama 0:da22b0b4395a 256 typedef struct
hayama 0:da22b0b4395a 257 {
hayama 0:da22b0b4395a 258 __I uint32_t IntStatus;
hayama 0:da22b0b4395a 259 __I uint32_t IO0IntStatR;
hayama 0:da22b0b4395a 260 __I uint32_t IO0IntStatF;
hayama 0:da22b0b4395a 261 __O uint32_t IO0IntClr;
hayama 0:da22b0b4395a 262 __IO uint32_t IO0IntEnR;
hayama 0:da22b0b4395a 263 __IO uint32_t IO0IntEnF;
hayama 0:da22b0b4395a 264 uint32_t RESERVED0[3];
hayama 0:da22b0b4395a 265 __I uint32_t IO2IntStatR;
hayama 0:da22b0b4395a 266 __I uint32_t IO2IntStatF;
hayama 0:da22b0b4395a 267 __O uint32_t IO2IntClr;
hayama 0:da22b0b4395a 268 __IO uint32_t IO2IntEnR;
hayama 0:da22b0b4395a 269 __IO uint32_t IO2IntEnF;
hayama 0:da22b0b4395a 270 } LPC_GPIOINT_TypeDef;
hayama 0:da22b0b4395a 271
hayama 0:da22b0b4395a 272 /*------------- Timer (TIM) --------------------------------------------------*/
hayama 0:da22b0b4395a 273 typedef struct
hayama 0:da22b0b4395a 274 {
hayama 0:da22b0b4395a 275 __IO uint32_t IR;
hayama 0:da22b0b4395a 276 __IO uint32_t TCR;
hayama 0:da22b0b4395a 277 __IO uint32_t TC;
hayama 0:da22b0b4395a 278 __IO uint32_t PR;
hayama 0:da22b0b4395a 279 __IO uint32_t PC;
hayama 0:da22b0b4395a 280 __IO uint32_t MCR;
hayama 0:da22b0b4395a 281 __IO uint32_t MR0;
hayama 0:da22b0b4395a 282 __IO uint32_t MR1;
hayama 0:da22b0b4395a 283 __IO uint32_t MR2;
hayama 0:da22b0b4395a 284 __IO uint32_t MR3;
hayama 0:da22b0b4395a 285 __IO uint32_t CCR;
hayama 0:da22b0b4395a 286 __I uint32_t CR0;
hayama 0:da22b0b4395a 287 __I uint32_t CR1;
hayama 0:da22b0b4395a 288 uint32_t RESERVED0[2];
hayama 0:da22b0b4395a 289 __IO uint32_t EMR;
hayama 0:da22b0b4395a 290 uint32_t RESERVED1[12];
hayama 0:da22b0b4395a 291 __IO uint32_t CTCR;
hayama 0:da22b0b4395a 292 } LPC_TIM_TypeDef;
hayama 0:da22b0b4395a 293
hayama 0:da22b0b4395a 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
hayama 0:da22b0b4395a 295 typedef struct
hayama 0:da22b0b4395a 296 {
hayama 0:da22b0b4395a 297 __IO uint32_t IR;
hayama 0:da22b0b4395a 298 __IO uint32_t TCR;
hayama 0:da22b0b4395a 299 __IO uint32_t TC;
hayama 0:da22b0b4395a 300 __IO uint32_t PR;
hayama 0:da22b0b4395a 301 __IO uint32_t PC;
hayama 0:da22b0b4395a 302 __IO uint32_t MCR;
hayama 0:da22b0b4395a 303 __IO uint32_t MR0;
hayama 0:da22b0b4395a 304 __IO uint32_t MR1;
hayama 0:da22b0b4395a 305 __IO uint32_t MR2;
hayama 0:da22b0b4395a 306 __IO uint32_t MR3;
hayama 0:da22b0b4395a 307 __IO uint32_t CCR;
hayama 0:da22b0b4395a 308 __I uint32_t CR0;
hayama 0:da22b0b4395a 309 __I uint32_t CR1;
hayama 0:da22b0b4395a 310 __I uint32_t CR2;
hayama 0:da22b0b4395a 311 __I uint32_t CR3;
hayama 0:da22b0b4395a 312 uint32_t RESERVED0;
hayama 0:da22b0b4395a 313 __IO uint32_t MR4;
hayama 0:da22b0b4395a 314 __IO uint32_t MR5;
hayama 0:da22b0b4395a 315 __IO uint32_t MR6;
hayama 0:da22b0b4395a 316 __IO uint32_t PCR;
hayama 0:da22b0b4395a 317 __IO uint32_t LER;
hayama 0:da22b0b4395a 318 uint32_t RESERVED1[7];
hayama 0:da22b0b4395a 319 __IO uint32_t CTCR;
hayama 0:da22b0b4395a 320 } LPC_PWM_TypeDef;
hayama 0:da22b0b4395a 321
hayama 0:da22b0b4395a 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
hayama 0:da22b0b4395a 323 typedef struct
hayama 0:da22b0b4395a 324 {
hayama 0:da22b0b4395a 325 union {
hayama 0:da22b0b4395a 326 __I uint8_t RBR;
hayama 0:da22b0b4395a 327 __O uint8_t THR;
hayama 0:da22b0b4395a 328 __IO uint8_t DLL;
hayama 0:da22b0b4395a 329 uint32_t RESERVED0;
hayama 0:da22b0b4395a 330 };
hayama 0:da22b0b4395a 331 union {
hayama 0:da22b0b4395a 332 __IO uint8_t DLM;
hayama 0:da22b0b4395a 333 __IO uint32_t IER;
hayama 0:da22b0b4395a 334 };
hayama 0:da22b0b4395a 335 union {
hayama 0:da22b0b4395a 336 __I uint32_t IIR;
hayama 0:da22b0b4395a 337 __O uint8_t FCR;
hayama 0:da22b0b4395a 338 };
hayama 0:da22b0b4395a 339 __IO uint8_t LCR;
hayama 0:da22b0b4395a 340 uint8_t RESERVED1[7];
hayama 0:da22b0b4395a 341 __I uint8_t LSR;
hayama 0:da22b0b4395a 342 uint8_t RESERVED2[7];
hayama 0:da22b0b4395a 343 __IO uint8_t SCR;
hayama 0:da22b0b4395a 344 uint8_t RESERVED3[3];
hayama 0:da22b0b4395a 345 __IO uint32_t ACR;
hayama 0:da22b0b4395a 346 __IO uint8_t ICR;
hayama 0:da22b0b4395a 347 uint8_t RESERVED4[3];
hayama 0:da22b0b4395a 348 __IO uint8_t FDR;
hayama 0:da22b0b4395a 349 uint8_t RESERVED5[7];
hayama 0:da22b0b4395a 350 __IO uint8_t TER;
hayama 0:da22b0b4395a 351 uint8_t RESERVED6[39];
hayama 0:da22b0b4395a 352 __IO uint32_t FIFOLVL;
hayama 0:da22b0b4395a 353 } LPC_UART_TypeDef;
hayama 0:da22b0b4395a 354
hayama 0:da22b0b4395a 355 typedef struct
hayama 0:da22b0b4395a 356 {
hayama 0:da22b0b4395a 357 union {
hayama 0:da22b0b4395a 358 __I uint8_t RBR;
hayama 0:da22b0b4395a 359 __O uint8_t THR;
hayama 0:da22b0b4395a 360 __IO uint8_t DLL;
hayama 0:da22b0b4395a 361 uint32_t RESERVED0;
hayama 0:da22b0b4395a 362 };
hayama 0:da22b0b4395a 363 union {
hayama 0:da22b0b4395a 364 __IO uint8_t DLM;
hayama 0:da22b0b4395a 365 __IO uint32_t IER;
hayama 0:da22b0b4395a 366 };
hayama 0:da22b0b4395a 367 union {
hayama 0:da22b0b4395a 368 __I uint32_t IIR;
hayama 0:da22b0b4395a 369 __O uint8_t FCR;
hayama 0:da22b0b4395a 370 };
hayama 0:da22b0b4395a 371 __IO uint8_t LCR;
hayama 0:da22b0b4395a 372 uint8_t RESERVED1[7];
hayama 0:da22b0b4395a 373 __I uint8_t LSR;
hayama 0:da22b0b4395a 374 uint8_t RESERVED2[7];
hayama 0:da22b0b4395a 375 __IO uint8_t SCR;
hayama 0:da22b0b4395a 376 uint8_t RESERVED3[3];
hayama 0:da22b0b4395a 377 __IO uint32_t ACR;
hayama 0:da22b0b4395a 378 __IO uint8_t ICR;
hayama 0:da22b0b4395a 379 uint8_t RESERVED4[3];
hayama 0:da22b0b4395a 380 __IO uint8_t FDR;
hayama 0:da22b0b4395a 381 uint8_t RESERVED5[7];
hayama 0:da22b0b4395a 382 __IO uint8_t TER;
hayama 0:da22b0b4395a 383 uint8_t RESERVED6[39];
hayama 0:da22b0b4395a 384 __IO uint32_t FIFOLVL;
hayama 0:da22b0b4395a 385 } LPC_UART0_TypeDef;
hayama 0:da22b0b4395a 386
hayama 0:da22b0b4395a 387 typedef struct
hayama 0:da22b0b4395a 388 {
hayama 0:da22b0b4395a 389 union {
hayama 0:da22b0b4395a 390 __I uint8_t RBR;
hayama 0:da22b0b4395a 391 __O uint8_t THR;
hayama 0:da22b0b4395a 392 __IO uint8_t DLL;
hayama 0:da22b0b4395a 393 uint32_t RESERVED0;
hayama 0:da22b0b4395a 394 };
hayama 0:da22b0b4395a 395 union {
hayama 0:da22b0b4395a 396 __IO uint8_t DLM;
hayama 0:da22b0b4395a 397 __IO uint32_t IER;
hayama 0:da22b0b4395a 398 };
hayama 0:da22b0b4395a 399 union {
hayama 0:da22b0b4395a 400 __I uint32_t IIR;
hayama 0:da22b0b4395a 401 __O uint8_t FCR;
hayama 0:da22b0b4395a 402 };
hayama 0:da22b0b4395a 403 __IO uint8_t LCR;
hayama 0:da22b0b4395a 404 uint8_t RESERVED1[3];
hayama 0:da22b0b4395a 405 __IO uint8_t MCR;
hayama 0:da22b0b4395a 406 uint8_t RESERVED2[3];
hayama 0:da22b0b4395a 407 __I uint8_t LSR;
hayama 0:da22b0b4395a 408 uint8_t RESERVED3[3];
hayama 0:da22b0b4395a 409 __I uint8_t MSR;
hayama 0:da22b0b4395a 410 uint8_t RESERVED4[3];
hayama 0:da22b0b4395a 411 __IO uint8_t SCR;
hayama 0:da22b0b4395a 412 uint8_t RESERVED5[3];
hayama 0:da22b0b4395a 413 __IO uint32_t ACR;
hayama 0:da22b0b4395a 414 uint32_t RESERVED6;
hayama 0:da22b0b4395a 415 __IO uint32_t FDR;
hayama 0:da22b0b4395a 416 uint32_t RESERVED7;
hayama 0:da22b0b4395a 417 __IO uint8_t TER;
hayama 0:da22b0b4395a 418 uint8_t RESERVED8[27];
hayama 0:da22b0b4395a 419 __IO uint8_t RS485CTRL;
hayama 0:da22b0b4395a 420 uint8_t RESERVED9[3];
hayama 0:da22b0b4395a 421 __IO uint8_t ADRMATCH;
hayama 0:da22b0b4395a 422 uint8_t RESERVED10[3];
hayama 0:da22b0b4395a 423 __IO uint8_t RS485DLY;
hayama 0:da22b0b4395a 424 uint8_t RESERVED11[3];
hayama 0:da22b0b4395a 425 __IO uint32_t FIFOLVL;
hayama 0:da22b0b4395a 426 } LPC_UART1_TypeDef;
hayama 0:da22b0b4395a 427
hayama 0:da22b0b4395a 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
hayama 0:da22b0b4395a 429 typedef struct
hayama 0:da22b0b4395a 430 {
hayama 0:da22b0b4395a 431 __IO uint32_t SPCR;
hayama 0:da22b0b4395a 432 __I uint32_t SPSR;
hayama 0:da22b0b4395a 433 __IO uint32_t SPDR;
hayama 0:da22b0b4395a 434 __IO uint32_t SPCCR;
hayama 0:da22b0b4395a 435 uint32_t RESERVED0[3];
hayama 0:da22b0b4395a 436 __IO uint32_t SPINT;
hayama 0:da22b0b4395a 437 } LPC_SPI_TypeDef;
hayama 0:da22b0b4395a 438
hayama 0:da22b0b4395a 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
hayama 0:da22b0b4395a 440 typedef struct
hayama 0:da22b0b4395a 441 {
hayama 0:da22b0b4395a 442 __IO uint32_t CR0;
hayama 0:da22b0b4395a 443 __IO uint32_t CR1;
hayama 0:da22b0b4395a 444 __IO uint32_t DR;
hayama 0:da22b0b4395a 445 __I uint32_t SR;
hayama 0:da22b0b4395a 446 __IO uint32_t CPSR;
hayama 0:da22b0b4395a 447 __IO uint32_t IMSC;
hayama 0:da22b0b4395a 448 __IO uint32_t RIS;
hayama 0:da22b0b4395a 449 __IO uint32_t MIS;
hayama 0:da22b0b4395a 450 __IO uint32_t ICR;
hayama 0:da22b0b4395a 451 __IO uint32_t DMACR;
hayama 0:da22b0b4395a 452 } LPC_SSP_TypeDef;
hayama 0:da22b0b4395a 453
hayama 0:da22b0b4395a 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
hayama 0:da22b0b4395a 455 typedef struct
hayama 0:da22b0b4395a 456 {
hayama 0:da22b0b4395a 457 __IO uint32_t I2CONSET;
hayama 0:da22b0b4395a 458 __I uint32_t I2STAT;
hayama 0:da22b0b4395a 459 __IO uint32_t I2DAT;
hayama 0:da22b0b4395a 460 __IO uint32_t I2ADR0;
hayama 0:da22b0b4395a 461 __IO uint32_t I2SCLH;
hayama 0:da22b0b4395a 462 __IO uint32_t I2SCLL;
hayama 0:da22b0b4395a 463 __O uint32_t I2CONCLR;
hayama 0:da22b0b4395a 464 __IO uint32_t MMCTRL;
hayama 0:da22b0b4395a 465 __IO uint32_t I2ADR1;
hayama 0:da22b0b4395a 466 __IO uint32_t I2ADR2;
hayama 0:da22b0b4395a 467 __IO uint32_t I2ADR3;
hayama 0:da22b0b4395a 468 __I uint32_t I2DATA_BUFFER;
hayama 0:da22b0b4395a 469 __IO uint32_t I2MASK0;
hayama 0:da22b0b4395a 470 __IO uint32_t I2MASK1;
hayama 0:da22b0b4395a 471 __IO uint32_t I2MASK2;
hayama 0:da22b0b4395a 472 __IO uint32_t I2MASK3;
hayama 0:da22b0b4395a 473 } LPC_I2C_TypeDef;
hayama 0:da22b0b4395a 474
hayama 0:da22b0b4395a 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
hayama 0:da22b0b4395a 476 typedef struct
hayama 0:da22b0b4395a 477 {
hayama 0:da22b0b4395a 478 __IO uint32_t I2SDAO;
hayama 0:da22b0b4395a 479 __IO uint32_t I2SDAI;
hayama 0:da22b0b4395a 480 __O uint32_t I2STXFIFO;
hayama 0:da22b0b4395a 481 __I uint32_t I2SRXFIFO;
hayama 0:da22b0b4395a 482 __I uint32_t I2SSTATE;
hayama 0:da22b0b4395a 483 __IO uint32_t I2SDMA1;
hayama 0:da22b0b4395a 484 __IO uint32_t I2SDMA2;
hayama 0:da22b0b4395a 485 __IO uint32_t I2SIRQ;
hayama 0:da22b0b4395a 486 __IO uint32_t I2STXRATE;
hayama 0:da22b0b4395a 487 __IO uint32_t I2SRXRATE;
hayama 0:da22b0b4395a 488 __IO uint32_t I2STXBITRATE;
hayama 0:da22b0b4395a 489 __IO uint32_t I2SRXBITRATE;
hayama 0:da22b0b4395a 490 __IO uint32_t I2STXMODE;
hayama 0:da22b0b4395a 491 __IO uint32_t I2SRXMODE;
hayama 0:da22b0b4395a 492 } LPC_I2S_TypeDef;
hayama 0:da22b0b4395a 493
hayama 0:da22b0b4395a 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
hayama 0:da22b0b4395a 495 typedef struct
hayama 0:da22b0b4395a 496 {
hayama 0:da22b0b4395a 497 __IO uint32_t RICOMPVAL;
hayama 0:da22b0b4395a 498 __IO uint32_t RIMASK;
hayama 0:da22b0b4395a 499 __IO uint8_t RICTRL;
hayama 0:da22b0b4395a 500 uint8_t RESERVED0[3];
hayama 0:da22b0b4395a 501 __IO uint32_t RICOUNTER;
hayama 0:da22b0b4395a 502 } LPC_RIT_TypeDef;
hayama 0:da22b0b4395a 503
hayama 0:da22b0b4395a 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
hayama 0:da22b0b4395a 505 typedef struct
hayama 0:da22b0b4395a 506 {
hayama 0:da22b0b4395a 507 __IO uint8_t ILR;
hayama 0:da22b0b4395a 508 uint8_t RESERVED0[7];
hayama 0:da22b0b4395a 509 __IO uint8_t CCR;
hayama 0:da22b0b4395a 510 uint8_t RESERVED1[3];
hayama 0:da22b0b4395a 511 __IO uint8_t CIIR;
hayama 0:da22b0b4395a 512 uint8_t RESERVED2[3];
hayama 0:da22b0b4395a 513 __IO uint8_t AMR;
hayama 0:da22b0b4395a 514 uint8_t RESERVED3[3];
hayama 0:da22b0b4395a 515 __I uint32_t CTIME0;
hayama 0:da22b0b4395a 516 __I uint32_t CTIME1;
hayama 0:da22b0b4395a 517 __I uint32_t CTIME2;
hayama 0:da22b0b4395a 518 __IO uint8_t SEC;
hayama 0:da22b0b4395a 519 uint8_t RESERVED4[3];
hayama 0:da22b0b4395a 520 __IO uint8_t MIN;
hayama 0:da22b0b4395a 521 uint8_t RESERVED5[3];
hayama 0:da22b0b4395a 522 __IO uint8_t HOUR;
hayama 0:da22b0b4395a 523 uint8_t RESERVED6[3];
hayama 0:da22b0b4395a 524 __IO uint8_t DOM;
hayama 0:da22b0b4395a 525 uint8_t RESERVED7[3];
hayama 0:da22b0b4395a 526 __IO uint8_t DOW;
hayama 0:da22b0b4395a 527 uint8_t RESERVED8[3];
hayama 0:da22b0b4395a 528 __IO uint16_t DOY;
hayama 0:da22b0b4395a 529 uint16_t RESERVED9;
hayama 0:da22b0b4395a 530 __IO uint8_t MONTH;
hayama 0:da22b0b4395a 531 uint8_t RESERVED10[3];
hayama 0:da22b0b4395a 532 __IO uint16_t YEAR;
hayama 0:da22b0b4395a 533 uint16_t RESERVED11;
hayama 0:da22b0b4395a 534 __IO uint32_t CALIBRATION;
hayama 0:da22b0b4395a 535 __IO uint32_t GPREG0;
hayama 0:da22b0b4395a 536 __IO uint32_t GPREG1;
hayama 0:da22b0b4395a 537 __IO uint32_t GPREG2;
hayama 0:da22b0b4395a 538 __IO uint32_t GPREG3;
hayama 0:da22b0b4395a 539 __IO uint32_t GPREG4;
hayama 0:da22b0b4395a 540 __IO uint8_t RTC_AUXEN;
hayama 0:da22b0b4395a 541 uint8_t RESERVED12[3];
hayama 0:da22b0b4395a 542 __IO uint8_t RTC_AUX;
hayama 0:da22b0b4395a 543 uint8_t RESERVED13[3];
hayama 0:da22b0b4395a 544 __IO uint8_t ALSEC;
hayama 0:da22b0b4395a 545 uint8_t RESERVED14[3];
hayama 0:da22b0b4395a 546 __IO uint8_t ALMIN;
hayama 0:da22b0b4395a 547 uint8_t RESERVED15[3];
hayama 0:da22b0b4395a 548 __IO uint8_t ALHOUR;
hayama 0:da22b0b4395a 549 uint8_t RESERVED16[3];
hayama 0:da22b0b4395a 550 __IO uint8_t ALDOM;
hayama 0:da22b0b4395a 551 uint8_t RESERVED17[3];
hayama 0:da22b0b4395a 552 __IO uint8_t ALDOW;
hayama 0:da22b0b4395a 553 uint8_t RESERVED18[3];
hayama 0:da22b0b4395a 554 __IO uint16_t ALDOY;
hayama 0:da22b0b4395a 555 uint16_t RESERVED19;
hayama 0:da22b0b4395a 556 __IO uint8_t ALMON;
hayama 0:da22b0b4395a 557 uint8_t RESERVED20[3];
hayama 0:da22b0b4395a 558 __IO uint16_t ALYEAR;
hayama 0:da22b0b4395a 559 uint16_t RESERVED21;
hayama 0:da22b0b4395a 560 } LPC_RTC_TypeDef;
hayama 0:da22b0b4395a 561
hayama 0:da22b0b4395a 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
hayama 0:da22b0b4395a 563 typedef struct
hayama 0:da22b0b4395a 564 {
hayama 0:da22b0b4395a 565 __IO uint8_t WDMOD;
hayama 0:da22b0b4395a 566 uint8_t RESERVED0[3];
hayama 0:da22b0b4395a 567 __IO uint32_t WDTC;
hayama 0:da22b0b4395a 568 __O uint8_t WDFEED;
hayama 0:da22b0b4395a 569 uint8_t RESERVED1[3];
hayama 0:da22b0b4395a 570 __I uint32_t WDTV;
hayama 0:da22b0b4395a 571 __IO uint32_t WDCLKSEL;
hayama 0:da22b0b4395a 572 } LPC_WDT_TypeDef;
hayama 0:da22b0b4395a 573
hayama 0:da22b0b4395a 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
hayama 0:da22b0b4395a 575 typedef struct
hayama 0:da22b0b4395a 576 {
hayama 0:da22b0b4395a 577 __IO uint32_t ADCR;
hayama 0:da22b0b4395a 578 __IO uint32_t ADGDR;
hayama 0:da22b0b4395a 579 uint32_t RESERVED0;
hayama 0:da22b0b4395a 580 __IO uint32_t ADINTEN;
hayama 0:da22b0b4395a 581 __I uint32_t ADDR0;
hayama 0:da22b0b4395a 582 __I uint32_t ADDR1;
hayama 0:da22b0b4395a 583 __I uint32_t ADDR2;
hayama 0:da22b0b4395a 584 __I uint32_t ADDR3;
hayama 0:da22b0b4395a 585 __I uint32_t ADDR4;
hayama 0:da22b0b4395a 586 __I uint32_t ADDR5;
hayama 0:da22b0b4395a 587 __I uint32_t ADDR6;
hayama 0:da22b0b4395a 588 __I uint32_t ADDR7;
hayama 0:da22b0b4395a 589 __I uint32_t ADSTAT;
hayama 0:da22b0b4395a 590 __IO uint32_t ADTRM;
hayama 0:da22b0b4395a 591 } LPC_ADC_TypeDef;
hayama 0:da22b0b4395a 592
hayama 0:da22b0b4395a 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
hayama 0:da22b0b4395a 594 typedef struct
hayama 0:da22b0b4395a 595 {
hayama 0:da22b0b4395a 596 __IO uint32_t DACR;
hayama 0:da22b0b4395a 597 __IO uint32_t DACCTRL;
hayama 0:da22b0b4395a 598 __IO uint16_t DACCNTVAL;
hayama 0:da22b0b4395a 599 } LPC_DAC_TypeDef;
hayama 0:da22b0b4395a 600
hayama 0:da22b0b4395a 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
hayama 0:da22b0b4395a 602 typedef struct
hayama 0:da22b0b4395a 603 {
hayama 0:da22b0b4395a 604 __I uint32_t MCCON;
hayama 0:da22b0b4395a 605 __O uint32_t MCCON_SET;
hayama 0:da22b0b4395a 606 __O uint32_t MCCON_CLR;
hayama 0:da22b0b4395a 607 __I uint32_t MCCAPCON;
hayama 0:da22b0b4395a 608 __O uint32_t MCCAPCON_SET;
hayama 0:da22b0b4395a 609 __O uint32_t MCCAPCON_CLR;
hayama 0:da22b0b4395a 610 __IO uint32_t MCTIM0;
hayama 0:da22b0b4395a 611 __IO uint32_t MCTIM1;
hayama 0:da22b0b4395a 612 __IO uint32_t MCTIM2;
hayama 0:da22b0b4395a 613 __IO uint32_t MCPER0;
hayama 0:da22b0b4395a 614 __IO uint32_t MCPER1;
hayama 0:da22b0b4395a 615 __IO uint32_t MCPER2;
hayama 0:da22b0b4395a 616 __IO uint32_t MCPW0;
hayama 0:da22b0b4395a 617 __IO uint32_t MCPW1;
hayama 0:da22b0b4395a 618 __IO uint32_t MCPW2;
hayama 0:da22b0b4395a 619 __IO uint32_t MCDEADTIME;
hayama 0:da22b0b4395a 620 __IO uint32_t MCCCP;
hayama 0:da22b0b4395a 621 __IO uint32_t MCCR0;
hayama 0:da22b0b4395a 622 __IO uint32_t MCCR1;
hayama 0:da22b0b4395a 623 __IO uint32_t MCCR2;
hayama 0:da22b0b4395a 624 __I uint32_t MCINTEN;
hayama 0:da22b0b4395a 625 __O uint32_t MCINTEN_SET;
hayama 0:da22b0b4395a 626 __O uint32_t MCINTEN_CLR;
hayama 0:da22b0b4395a 627 __I uint32_t MCCNTCON;
hayama 0:da22b0b4395a 628 __O uint32_t MCCNTCON_SET;
hayama 0:da22b0b4395a 629 __O uint32_t MCCNTCON_CLR;
hayama 0:da22b0b4395a 630 __I uint32_t MCINTFLAG;
hayama 0:da22b0b4395a 631 __O uint32_t MCINTFLAG_SET;
hayama 0:da22b0b4395a 632 __O uint32_t MCINTFLAG_CLR;
hayama 0:da22b0b4395a 633 __O uint32_t MCCAP_CLR;
hayama 0:da22b0b4395a 634 } LPC_MCPWM_TypeDef;
hayama 0:da22b0b4395a 635
hayama 0:da22b0b4395a 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
hayama 0:da22b0b4395a 637 typedef struct
hayama 0:da22b0b4395a 638 {
hayama 0:da22b0b4395a 639 __O uint32_t QEICON;
hayama 0:da22b0b4395a 640 __I uint32_t QEISTAT;
hayama 0:da22b0b4395a 641 __IO uint32_t QEICONF;
hayama 0:da22b0b4395a 642 __I uint32_t QEIPOS;
hayama 0:da22b0b4395a 643 __IO uint32_t QEIMAXPOS;
hayama 0:da22b0b4395a 644 __IO uint32_t CMPOS0;
hayama 0:da22b0b4395a 645 __IO uint32_t CMPOS1;
hayama 0:da22b0b4395a 646 __IO uint32_t CMPOS2;
hayama 0:da22b0b4395a 647 __I uint32_t INXCNT;
hayama 0:da22b0b4395a 648 __IO uint32_t INXCMP;
hayama 0:da22b0b4395a 649 __IO uint32_t QEILOAD;
hayama 0:da22b0b4395a 650 __I uint32_t QEITIME;
hayama 0:da22b0b4395a 651 __I uint32_t QEIVEL;
hayama 0:da22b0b4395a 652 __I uint32_t QEICAP;
hayama 0:da22b0b4395a 653 __IO uint32_t VELCOMP;
hayama 0:da22b0b4395a 654 __IO uint32_t FILTER;
hayama 0:da22b0b4395a 655 uint32_t RESERVED0[998];
hayama 0:da22b0b4395a 656 __O uint32_t QEIIEC;
hayama 0:da22b0b4395a 657 __O uint32_t QEIIES;
hayama 0:da22b0b4395a 658 __I uint32_t QEIINTSTAT;
hayama 0:da22b0b4395a 659 __I uint32_t QEIIE;
hayama 0:da22b0b4395a 660 __O uint32_t QEICLR;
hayama 0:da22b0b4395a 661 __O uint32_t QEISET;
hayama 0:da22b0b4395a 662 } LPC_QEI_TypeDef;
hayama 0:da22b0b4395a 663
hayama 0:da22b0b4395a 664 /*------------- Controller Area Network (CAN) --------------------------------*/
hayama 0:da22b0b4395a 665 typedef struct
hayama 0:da22b0b4395a 666 {
hayama 0:da22b0b4395a 667 __IO uint32_t mask[512]; /* ID Masks */
hayama 0:da22b0b4395a 668 } LPC_CANAF_RAM_TypeDef;
hayama 0:da22b0b4395a 669
hayama 0:da22b0b4395a 670 typedef struct /* Acceptance Filter Registers */
hayama 0:da22b0b4395a 671 {
hayama 0:da22b0b4395a 672 __IO uint32_t AFMR;
hayama 0:da22b0b4395a 673 __IO uint32_t SFF_sa;
hayama 0:da22b0b4395a 674 __IO uint32_t SFF_GRP_sa;
hayama 0:da22b0b4395a 675 __IO uint32_t EFF_sa;
hayama 0:da22b0b4395a 676 __IO uint32_t EFF_GRP_sa;
hayama 0:da22b0b4395a 677 __IO uint32_t ENDofTable;
hayama 0:da22b0b4395a 678 __I uint32_t LUTerrAd;
hayama 0:da22b0b4395a 679 __I uint32_t LUTerr;
hayama 0:da22b0b4395a 680 __IO uint32_t FCANIE;
hayama 0:da22b0b4395a 681 __IO uint32_t FCANIC0;
hayama 0:da22b0b4395a 682 __IO uint32_t FCANIC1;
hayama 0:da22b0b4395a 683 } LPC_CANAF_TypeDef;
hayama 0:da22b0b4395a 684
hayama 0:da22b0b4395a 685 typedef struct /* Central Registers */
hayama 0:da22b0b4395a 686 {
hayama 0:da22b0b4395a 687 __I uint32_t CANTxSR;
hayama 0:da22b0b4395a 688 __I uint32_t CANRxSR;
hayama 0:da22b0b4395a 689 __I uint32_t CANMSR;
hayama 0:da22b0b4395a 690 } LPC_CANCR_TypeDef;
hayama 0:da22b0b4395a 691
hayama 0:da22b0b4395a 692 typedef struct /* Controller Registers */
hayama 0:da22b0b4395a 693 {
hayama 0:da22b0b4395a 694 __IO uint32_t MOD;
hayama 0:da22b0b4395a 695 __O uint32_t CMR;
hayama 0:da22b0b4395a 696 __IO uint32_t GSR;
hayama 0:da22b0b4395a 697 __I uint32_t ICR;
hayama 0:da22b0b4395a 698 __IO uint32_t IER;
hayama 0:da22b0b4395a 699 __IO uint32_t BTR;
hayama 0:da22b0b4395a 700 __IO uint32_t EWL;
hayama 0:da22b0b4395a 701 __I uint32_t SR;
hayama 0:da22b0b4395a 702 __IO uint32_t RFS;
hayama 0:da22b0b4395a 703 __IO uint32_t RID;
hayama 0:da22b0b4395a 704 __IO uint32_t RDA;
hayama 0:da22b0b4395a 705 __IO uint32_t RDB;
hayama 0:da22b0b4395a 706 __IO uint32_t TFI1;
hayama 0:da22b0b4395a 707 __IO uint32_t TID1;
hayama 0:da22b0b4395a 708 __IO uint32_t TDA1;
hayama 0:da22b0b4395a 709 __IO uint32_t TDB1;
hayama 0:da22b0b4395a 710 __IO uint32_t TFI2;
hayama 0:da22b0b4395a 711 __IO uint32_t TID2;
hayama 0:da22b0b4395a 712 __IO uint32_t TDA2;
hayama 0:da22b0b4395a 713 __IO uint32_t TDB2;
hayama 0:da22b0b4395a 714 __IO uint32_t TFI3;
hayama 0:da22b0b4395a 715 __IO uint32_t TID3;
hayama 0:da22b0b4395a 716 __IO uint32_t TDA3;
hayama 0:da22b0b4395a 717 __IO uint32_t TDB3;
hayama 0:da22b0b4395a 718 } LPC_CAN_TypeDef;
hayama 0:da22b0b4395a 719
hayama 0:da22b0b4395a 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
hayama 0:da22b0b4395a 721 typedef struct /* Common Registers */
hayama 0:da22b0b4395a 722 {
hayama 0:da22b0b4395a 723 __I uint32_t DMACIntStat;
hayama 0:da22b0b4395a 724 __I uint32_t DMACIntTCStat;
hayama 0:da22b0b4395a 725 __O uint32_t DMACIntTCClear;
hayama 0:da22b0b4395a 726 __I uint32_t DMACIntErrStat;
hayama 0:da22b0b4395a 727 __O uint32_t DMACIntErrClr;
hayama 0:da22b0b4395a 728 __I uint32_t DMACRawIntTCStat;
hayama 0:da22b0b4395a 729 __I uint32_t DMACRawIntErrStat;
hayama 0:da22b0b4395a 730 __I uint32_t DMACEnbldChns;
hayama 0:da22b0b4395a 731 __IO uint32_t DMACSoftBReq;
hayama 0:da22b0b4395a 732 __IO uint32_t DMACSoftSReq;
hayama 0:da22b0b4395a 733 __IO uint32_t DMACSoftLBReq;
hayama 0:da22b0b4395a 734 __IO uint32_t DMACSoftLSReq;
hayama 0:da22b0b4395a 735 __IO uint32_t DMACConfig;
hayama 0:da22b0b4395a 736 __IO uint32_t DMACSync;
hayama 0:da22b0b4395a 737 } LPC_GPDMA_TypeDef;
hayama 0:da22b0b4395a 738
hayama 0:da22b0b4395a 739 typedef struct /* Channel Registers */
hayama 0:da22b0b4395a 740 {
hayama 0:da22b0b4395a 741 __IO uint32_t DMACCSrcAddr;
hayama 0:da22b0b4395a 742 __IO uint32_t DMACCDestAddr;
hayama 0:da22b0b4395a 743 __IO uint32_t DMACCLLI;
hayama 0:da22b0b4395a 744 __IO uint32_t DMACCControl;
hayama 0:da22b0b4395a 745 __IO uint32_t DMACCConfig;
hayama 0:da22b0b4395a 746 } LPC_GPDMACH_TypeDef;
hayama 0:da22b0b4395a 747
hayama 0:da22b0b4395a 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
hayama 0:da22b0b4395a 749 typedef struct
hayama 0:da22b0b4395a 750 {
hayama 0:da22b0b4395a 751 __I uint32_t HcRevision; /* USB Host Registers */
hayama 0:da22b0b4395a 752 __IO uint32_t HcControl;
hayama 0:da22b0b4395a 753 __IO uint32_t HcCommandStatus;
hayama 0:da22b0b4395a 754 __IO uint32_t HcInterruptStatus;
hayama 0:da22b0b4395a 755 __IO uint32_t HcInterruptEnable;
hayama 0:da22b0b4395a 756 __IO uint32_t HcInterruptDisable;
hayama 0:da22b0b4395a 757 __IO uint32_t HcHCCA;
hayama 0:da22b0b4395a 758 __I uint32_t HcPeriodCurrentED;
hayama 0:da22b0b4395a 759 __IO uint32_t HcControlHeadED;
hayama 0:da22b0b4395a 760 __IO uint32_t HcControlCurrentED;
hayama 0:da22b0b4395a 761 __IO uint32_t HcBulkHeadED;
hayama 0:da22b0b4395a 762 __IO uint32_t HcBulkCurrentED;
hayama 0:da22b0b4395a 763 __I uint32_t HcDoneHead;
hayama 0:da22b0b4395a 764 __IO uint32_t HcFmInterval;
hayama 0:da22b0b4395a 765 __I uint32_t HcFmRemaining;
hayama 0:da22b0b4395a 766 __I uint32_t HcFmNumber;
hayama 0:da22b0b4395a 767 __IO uint32_t HcPeriodicStart;
hayama 0:da22b0b4395a 768 __IO uint32_t HcLSTreshold;
hayama 0:da22b0b4395a 769 __IO uint32_t HcRhDescriptorA;
hayama 0:da22b0b4395a 770 __IO uint32_t HcRhDescriptorB;
hayama 0:da22b0b4395a 771 __IO uint32_t HcRhStatus;
hayama 0:da22b0b4395a 772 __IO uint32_t HcRhPortStatus1;
hayama 0:da22b0b4395a 773 __IO uint32_t HcRhPortStatus2;
hayama 0:da22b0b4395a 774 uint32_t RESERVED0[40];
hayama 0:da22b0b4395a 775 __I uint32_t Module_ID;
hayama 0:da22b0b4395a 776
hayama 0:da22b0b4395a 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
hayama 0:da22b0b4395a 778 __IO uint32_t OTGIntEn;
hayama 0:da22b0b4395a 779 __O uint32_t OTGIntSet;
hayama 0:da22b0b4395a 780 __O uint32_t OTGIntClr;
hayama 0:da22b0b4395a 781 __IO uint32_t OTGStCtrl;
hayama 0:da22b0b4395a 782 __IO uint32_t OTGTmr;
hayama 0:da22b0b4395a 783 uint32_t RESERVED1[58];
hayama 0:da22b0b4395a 784
hayama 0:da22b0b4395a 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
hayama 0:da22b0b4395a 786 __IO uint32_t USBDevIntEn;
hayama 0:da22b0b4395a 787 __O uint32_t USBDevIntClr;
hayama 0:da22b0b4395a 788 __O uint32_t USBDevIntSet;
hayama 0:da22b0b4395a 789
hayama 0:da22b0b4395a 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
hayama 0:da22b0b4395a 791 __I uint32_t USBCmdData;
hayama 0:da22b0b4395a 792
hayama 0:da22b0b4395a 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
hayama 0:da22b0b4395a 794 __O uint32_t USBTxData;
hayama 0:da22b0b4395a 795 __I uint32_t USBRxPLen;
hayama 0:da22b0b4395a 796 __O uint32_t USBTxPLen;
hayama 0:da22b0b4395a 797 __IO uint32_t USBCtrl;
hayama 0:da22b0b4395a 798 __O uint32_t USBDevIntPri;
hayama 0:da22b0b4395a 799
hayama 0:da22b0b4395a 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
hayama 0:da22b0b4395a 801 __IO uint32_t USBEpIntEn;
hayama 0:da22b0b4395a 802 __O uint32_t USBEpIntClr;
hayama 0:da22b0b4395a 803 __O uint32_t USBEpIntSet;
hayama 0:da22b0b4395a 804 __O uint32_t USBEpIntPri;
hayama 0:da22b0b4395a 805
hayama 0:da22b0b4395a 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
hayama 0:da22b0b4395a 807 __O uint32_t USBEpInd;
hayama 0:da22b0b4395a 808 __IO uint32_t USBMaxPSize;
hayama 0:da22b0b4395a 809
hayama 0:da22b0b4395a 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
hayama 0:da22b0b4395a 811 __O uint32_t USBDMARClr;
hayama 0:da22b0b4395a 812 __O uint32_t USBDMARSet;
hayama 0:da22b0b4395a 813 uint32_t RESERVED2[9];
hayama 0:da22b0b4395a 814 __IO uint32_t USBUDCAH;
hayama 0:da22b0b4395a 815 __I uint32_t USBEpDMASt;
hayama 0:da22b0b4395a 816 __O uint32_t USBEpDMAEn;
hayama 0:da22b0b4395a 817 __O uint32_t USBEpDMADis;
hayama 0:da22b0b4395a 818 __I uint32_t USBDMAIntSt;
hayama 0:da22b0b4395a 819 __IO uint32_t USBDMAIntEn;
hayama 0:da22b0b4395a 820 uint32_t RESERVED3[2];
hayama 0:da22b0b4395a 821 __I uint32_t USBEoTIntSt;
hayama 0:da22b0b4395a 822 __O uint32_t USBEoTIntClr;
hayama 0:da22b0b4395a 823 __O uint32_t USBEoTIntSet;
hayama 0:da22b0b4395a 824 __I uint32_t USBNDDRIntSt;
hayama 0:da22b0b4395a 825 __O uint32_t USBNDDRIntClr;
hayama 0:da22b0b4395a 826 __O uint32_t USBNDDRIntSet;
hayama 0:da22b0b4395a 827 __I uint32_t USBSysErrIntSt;
hayama 0:da22b0b4395a 828 __O uint32_t USBSysErrIntClr;
hayama 0:da22b0b4395a 829 __O uint32_t USBSysErrIntSet;
hayama 0:da22b0b4395a 830 uint32_t RESERVED4[15];
hayama 0:da22b0b4395a 831
hayama 0:da22b0b4395a 832 union {
hayama 0:da22b0b4395a 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
hayama 0:da22b0b4395a 834 __O uint32_t I2C_TX;
hayama 0:da22b0b4395a 835 };
hayama 0:da22b0b4395a 836 __I uint32_t I2C_STS;
hayama 0:da22b0b4395a 837 __IO uint32_t I2C_CTL;
hayama 0:da22b0b4395a 838 __IO uint32_t I2C_CLKHI;
hayama 0:da22b0b4395a 839 __O uint32_t I2C_CLKLO;
hayama 0:da22b0b4395a 840 uint32_t RESERVED5[824];
hayama 0:da22b0b4395a 841
hayama 0:da22b0b4395a 842 union {
hayama 0:da22b0b4395a 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
hayama 0:da22b0b4395a 844 __IO uint32_t OTGClkCtrl;
hayama 0:da22b0b4395a 845 };
hayama 0:da22b0b4395a 846 union {
hayama 0:da22b0b4395a 847 __I uint32_t USBClkSt;
hayama 0:da22b0b4395a 848 __I uint32_t OTGClkSt;
hayama 0:da22b0b4395a 849 };
hayama 0:da22b0b4395a 850 } LPC_USB_TypeDef;
hayama 0:da22b0b4395a 851
hayama 0:da22b0b4395a 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
hayama 0:da22b0b4395a 853 typedef struct
hayama 0:da22b0b4395a 854 {
hayama 0:da22b0b4395a 855 __IO uint32_t MAC1; /* MAC Registers */
hayama 0:da22b0b4395a 856 __IO uint32_t MAC2;
hayama 0:da22b0b4395a 857 __IO uint32_t IPGT;
hayama 0:da22b0b4395a 858 __IO uint32_t IPGR;
hayama 0:da22b0b4395a 859 __IO uint32_t CLRT;
hayama 0:da22b0b4395a 860 __IO uint32_t MAXF;
hayama 0:da22b0b4395a 861 __IO uint32_t SUPP;
hayama 0:da22b0b4395a 862 __IO uint32_t TEST;
hayama 0:da22b0b4395a 863 __IO uint32_t MCFG;
hayama 0:da22b0b4395a 864 __IO uint32_t MCMD;
hayama 0:da22b0b4395a 865 __IO uint32_t MADR;
hayama 0:da22b0b4395a 866 __O uint32_t MWTD;
hayama 0:da22b0b4395a 867 __I uint32_t MRDD;
hayama 0:da22b0b4395a 868 __I uint32_t MIND;
hayama 0:da22b0b4395a 869 uint32_t RESERVED0[2];
hayama 0:da22b0b4395a 870 __IO uint32_t SA0;
hayama 0:da22b0b4395a 871 __IO uint32_t SA1;
hayama 0:da22b0b4395a 872 __IO uint32_t SA2;
hayama 0:da22b0b4395a 873 uint32_t RESERVED1[45];
hayama 0:da22b0b4395a 874 __IO uint32_t Command; /* Control Registers */
hayama 0:da22b0b4395a 875 __I uint32_t Status;
hayama 0:da22b0b4395a 876 __IO uint32_t RxDescriptor;
hayama 0:da22b0b4395a 877 __IO uint32_t RxStatus;
hayama 0:da22b0b4395a 878 __IO uint32_t RxDescriptorNumber;
hayama 0:da22b0b4395a 879 __I uint32_t RxProduceIndex;
hayama 0:da22b0b4395a 880 __IO uint32_t RxConsumeIndex;
hayama 0:da22b0b4395a 881 __IO uint32_t TxDescriptor;
hayama 0:da22b0b4395a 882 __IO uint32_t TxStatus;
hayama 0:da22b0b4395a 883 __IO uint32_t TxDescriptorNumber;
hayama 0:da22b0b4395a 884 __IO uint32_t TxProduceIndex;
hayama 0:da22b0b4395a 885 __I uint32_t TxConsumeIndex;
hayama 0:da22b0b4395a 886 uint32_t RESERVED2[10];
hayama 0:da22b0b4395a 887 __I uint32_t TSV0;
hayama 0:da22b0b4395a 888 __I uint32_t TSV1;
hayama 0:da22b0b4395a 889 __I uint32_t RSV;
hayama 0:da22b0b4395a 890 uint32_t RESERVED3[3];
hayama 0:da22b0b4395a 891 __IO uint32_t FlowControlCounter;
hayama 0:da22b0b4395a 892 __I uint32_t FlowControlStatus;
hayama 0:da22b0b4395a 893 uint32_t RESERVED4[34];
hayama 0:da22b0b4395a 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
hayama 0:da22b0b4395a 895 __IO uint32_t RxFilterWoLStatus;
hayama 0:da22b0b4395a 896 __IO uint32_t RxFilterWoLClear;
hayama 0:da22b0b4395a 897 uint32_t RESERVED5;
hayama 0:da22b0b4395a 898 __IO uint32_t HashFilterL;
hayama 0:da22b0b4395a 899 __IO uint32_t HashFilterH;
hayama 0:da22b0b4395a 900 uint32_t RESERVED6[882];
hayama 0:da22b0b4395a 901 __I uint32_t IntStatus; /* Module Control Registers */
hayama 0:da22b0b4395a 902 __IO uint32_t IntEnable;
hayama 0:da22b0b4395a 903 __O uint32_t IntClear;
hayama 0:da22b0b4395a 904 __O uint32_t IntSet;
hayama 0:da22b0b4395a 905 uint32_t RESERVED7;
hayama 0:da22b0b4395a 906 __IO uint32_t PowerDown;
hayama 0:da22b0b4395a 907 uint32_t RESERVED8;
hayama 0:da22b0b4395a 908 __IO uint32_t Module_ID;
hayama 0:da22b0b4395a 909 } LPC_EMAC_TypeDef;
hayama 0:da22b0b4395a 910
hayama 0:da22b0b4395a 911 #if defined ( __CC_ARM )
hayama 0:da22b0b4395a 912 #pragma no_anon_unions
hayama 0:da22b0b4395a 913 #endif
hayama 0:da22b0b4395a 914
hayama 0:da22b0b4395a 915
hayama 0:da22b0b4395a 916 /******************************************************************************/
hayama 0:da22b0b4395a 917 /* Peripheral memory map */
hayama 0:da22b0b4395a 918 /******************************************************************************/
hayama 0:da22b0b4395a 919 /* Base addresses */
hayama 0:da22b0b4395a 920 #define LPC_FLASH_BASE (0x00000000UL)
hayama 0:da22b0b4395a 921 #define LPC_RAM_BASE (0x10000000UL)
hayama 0:da22b0b4395a 922 #define LPC_GPIO_BASE (0x2009C000UL)
hayama 0:da22b0b4395a 923 #define LPC_APB0_BASE (0x40000000UL)
hayama 0:da22b0b4395a 924 #define LPC_APB1_BASE (0x40080000UL)
hayama 0:da22b0b4395a 925 #define LPC_AHB_BASE (0x50000000UL)
hayama 0:da22b0b4395a 926 #define LPC_CM3_BASE (0xE0000000UL)
hayama 0:da22b0b4395a 927
hayama 0:da22b0b4395a 928 /* APB0 peripherals */
hayama 0:da22b0b4395a 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
hayama 0:da22b0b4395a 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
hayama 0:da22b0b4395a 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
hayama 0:da22b0b4395a 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
hayama 0:da22b0b4395a 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
hayama 0:da22b0b4395a 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
hayama 0:da22b0b4395a 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
hayama 0:da22b0b4395a 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
hayama 0:da22b0b4395a 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
hayama 0:da22b0b4395a 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
hayama 0:da22b0b4395a 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
hayama 0:da22b0b4395a 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
hayama 0:da22b0b4395a 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
hayama 0:da22b0b4395a 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
hayama 0:da22b0b4395a 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
hayama 0:da22b0b4395a 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
hayama 0:da22b0b4395a 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
hayama 0:da22b0b4395a 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
hayama 0:da22b0b4395a 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
hayama 0:da22b0b4395a 948
hayama 0:da22b0b4395a 949 /* APB1 peripherals */
hayama 0:da22b0b4395a 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
hayama 0:da22b0b4395a 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
hayama 0:da22b0b4395a 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
hayama 0:da22b0b4395a 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
hayama 0:da22b0b4395a 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
hayama 0:da22b0b4395a 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
hayama 0:da22b0b4395a 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
hayama 0:da22b0b4395a 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
hayama 0:da22b0b4395a 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
hayama 0:da22b0b4395a 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
hayama 0:da22b0b4395a 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
hayama 0:da22b0b4395a 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
hayama 0:da22b0b4395a 962
hayama 0:da22b0b4395a 963 /* AHB peripherals */
hayama 0:da22b0b4395a 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
hayama 0:da22b0b4395a 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
hayama 0:da22b0b4395a 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
hayama 0:da22b0b4395a 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
hayama 0:da22b0b4395a 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
hayama 0:da22b0b4395a 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
hayama 0:da22b0b4395a 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
hayama 0:da22b0b4395a 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
hayama 0:da22b0b4395a 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
hayama 0:da22b0b4395a 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
hayama 0:da22b0b4395a 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
hayama 0:da22b0b4395a 975
hayama 0:da22b0b4395a 976 /* GPIOs */
hayama 0:da22b0b4395a 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
hayama 0:da22b0b4395a 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
hayama 0:da22b0b4395a 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
hayama 0:da22b0b4395a 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
hayama 0:da22b0b4395a 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
hayama 0:da22b0b4395a 982
hayama 0:da22b0b4395a 983
hayama 0:da22b0b4395a 984 /******************************************************************************/
hayama 0:da22b0b4395a 985 /* Peripheral declaration */
hayama 0:da22b0b4395a 986 /******************************************************************************/
hayama 0:da22b0b4395a 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
hayama 0:da22b0b4395a 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
hayama 0:da22b0b4395a 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
hayama 0:da22b0b4395a 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
hayama 0:da22b0b4395a 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
hayama 0:da22b0b4395a 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
hayama 0:da22b0b4395a 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
hayama 0:da22b0b4395a 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
hayama 0:da22b0b4395a 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
hayama 0:da22b0b4395a 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
hayama 0:da22b0b4395a 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
hayama 0:da22b0b4395a 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
hayama 0:da22b0b4395a 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
hayama 0:da22b0b4395a 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
hayama 0:da22b0b4395a 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
hayama 0:da22b0b4395a 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
hayama 0:da22b0b4395a 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
hayama 0:da22b0b4395a 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
hayama 0:da22b0b4395a 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
hayama 0:da22b0b4395a 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
hayama 0:da22b0b4395a 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
hayama 0:da22b0b4395a 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
hayama 0:da22b0b4395a 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
hayama 0:da22b0b4395a 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
hayama 0:da22b0b4395a 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
hayama 0:da22b0b4395a 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
hayama 0:da22b0b4395a 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
hayama 0:da22b0b4395a 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
hayama 0:da22b0b4395a 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
hayama 0:da22b0b4395a 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
hayama 0:da22b0b4395a 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
hayama 0:da22b0b4395a 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
hayama 0:da22b0b4395a 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
hayama 0:da22b0b4395a 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
hayama 0:da22b0b4395a 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
hayama 0:da22b0b4395a 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
hayama 0:da22b0b4395a 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
hayama 0:da22b0b4395a 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
hayama 0:da22b0b4395a 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
hayama 0:da22b0b4395a 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
hayama 0:da22b0b4395a 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
hayama 0:da22b0b4395a 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
hayama 0:da22b0b4395a 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
hayama 0:da22b0b4395a 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
hayama 0:da22b0b4395a 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
hayama 0:da22b0b4395a 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
hayama 0:da22b0b4395a 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
hayama 0:da22b0b4395a 1034
hayama 0:da22b0b4395a 1035 #endif // __LPC17xx_H__