green rosh / Mbed 2 deprecated BAE_vr3honeycomb1_christmas

integrated code with threads to be removed

Dependencies:   mbed-rtos mbed

Fork of BAE_vr3honeycomb1 by sakthi priya amirtharaj

beacon.cpp@3:89a09736acd3, 2015-01-28 (annotated)

Committer:
greenroshks
Date:
Wed Jan 28 17:35:45 2015 +0000
Revision:
3:89a09736acd3
Parent:
0:ebdf4f859dca 
iist version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
greenroshks 3:89a09736acd3 1 #include "beacon.h"
greenroshks 3:89a09736acd3 2 #include "HK.h"
greenroshks 3:89a09736acd3 3 Serial chavan(USBTX, USBRX); // tx, rx
greenroshks 3:89a09736acd3 4 SPI spi(PTA16,PTA17,PTA15); // mosi, miso, sclk
greenroshks 3:89a09736acd3 5 DigitalOut cs(PTC11); //slave select or chip select
greenroshks 3:89a09736acd3 6
greenroshks 3:89a09736acd3 7 extern ShortBeacy Shortbeacon;
greenroshks 3:89a09736acd3 8
greenroshks 3:89a09736acd3 9 void writereg(uint8_t reg,uint8_t val)
greenroshks 3:89a09736acd3 10 {
greenroshks 3:89a09736acd3 11 cs = 0;__disable_irq();spi.write(reg | 0x80);spi.write(val);__enable_irq();cs = 1;
greenroshks 3:89a09736acd3 12 }
greenroshks 3:89a09736acd3 13 uint8_t readreg(uint8_t reg)
greenroshks 3:89a09736acd3 14 {
greenroshks 3:89a09736acd3 15 int val;cs = 0;__disable_irq();spi.write(reg & ~0x80);val = spi.write(0);__enable_irq();cs = 1;return val;
greenroshks 3:89a09736acd3 16 }
greenroshks 3:89a09736acd3 17 void clearTxBuf()
greenroshks 3:89a09736acd3 18 {
greenroshks 3:89a09736acd3 19 writereg(RF22_REG_08_OPERATING_MODE2,0x01);
greenroshks 3:89a09736acd3 20 writereg(RF22_REG_08_OPERATING_MODE2,0x00);
greenroshks 3:89a09736acd3 21 }
greenroshks 3:89a09736acd3 22 void clearRxBuf()
greenroshks 3:89a09736acd3 23 {
greenroshks 3:89a09736acd3 24 writereg(RF22_REG_08_OPERATING_MODE2,0x02);
greenroshks 3:89a09736acd3 25 writereg(RF22_REG_08_OPERATING_MODE2,0x00);
greenroshks 3:89a09736acd3 26 }
greenroshks 3:89a09736acd3 27 int setFrequency(float centre,float afcPullInRange)
greenroshks 3:89a09736acd3 28 {
greenroshks 3:89a09736acd3 29 //freq setting begins
greenroshks 3:89a09736acd3 30 uint8_t fbsel = 0x40;
greenroshks 3:89a09736acd3 31 uint8_t afclimiter;
greenroshks 3:89a09736acd3 32 if (centre >= 480.0) {
greenroshks 3:89a09736acd3 33 centre /= 2;
greenroshks 3:89a09736acd3 34 fbsel |= 0x20;
greenroshks 3:89a09736acd3 35 afclimiter = afcPullInRange * 1000000.0 / 1250.0;
greenroshks 3:89a09736acd3 36 } else {
greenroshks 3:89a09736acd3 37 if (afcPullInRange < 0.0 || afcPullInRange > 0.159375)
greenroshks 3:89a09736acd3 38 return false;
greenroshks 3:89a09736acd3 39 afclimiter = afcPullInRange * 1000000.0 / 625.0;
greenroshks 3:89a09736acd3 40 }
greenroshks 3:89a09736acd3 41 centre /= 10.0;
greenroshks 3:89a09736acd3 42 float integerPart = floor(centre);
greenroshks 3:89a09736acd3 43 float fractionalPart = centre - integerPart;
greenroshks 3:89a09736acd3 44
greenroshks 3:89a09736acd3 45 uint8_t fb = (uint8_t)integerPart - 24; // Range 0 to 23
greenroshks 3:89a09736acd3 46 fbsel |= fb;
greenroshks 3:89a09736acd3 47 uint16_t fc = fractionalPart * 64000;
greenroshks 3:89a09736acd3 48 writereg(RF22_REG_73_FREQUENCY_OFFSET1, 0); // REVISIT
greenroshks 3:89a09736acd3 49 writereg(RF22_REG_74_FREQUENCY_OFFSET2, 0);
greenroshks 3:89a09736acd3 50 writereg(RF22_REG_75_FREQUENCY_BAND_SELECT, fbsel);
greenroshks 3:89a09736acd3 51 writereg(RF22_REG_76_NOMINAL_CARRIER_FREQUENCY1, fc >> 8);
greenroshks 3:89a09736acd3 52 writereg(RF22_REG_77_NOMINAL_CARRIER_FREQUENCY0, fc & 0xff);
greenroshks 3:89a09736acd3 53 writereg(RF22_REG_2A_AFC_LIMITER, afclimiter);
greenroshks 3:89a09736acd3 54 return 0;
greenroshks 3:89a09736acd3 55 }
greenroshks 3:89a09736acd3 56
greenroshks 3:89a09736acd3 57 void init()
greenroshks 3:89a09736acd3 58 {
greenroshks 3:89a09736acd3 59 //reset()
greenroshks 3:89a09736acd3 60 writereg(RF22_REG_07_OPERATING_MODE1,0x80); //sw_reset
greenroshks 3:89a09736acd3 61 wait(1); //takes time to reset
greenroshks 3:89a09736acd3 62
greenroshks 3:89a09736acd3 63 clearTxBuf();
greenroshks 3:89a09736acd3 64 clearRxBuf();
greenroshks 3:89a09736acd3 65 //txfifoalmostempty
greenroshks 3:89a09736acd3 66 writereg(RF22_REG_7D_TX_FIFO_CONTROL2,5);
greenroshks 3:89a09736acd3 67 //rxfifoalmostfull
greenroshks 3:89a09736acd3 68 writereg(RF22_REG_7E_RX_FIFO_CONTROL,20);
greenroshks 3:89a09736acd3 69 //Packet-engine registers
greenroshks 3:89a09736acd3 70 writereg(RF22_REG_30_DATA_ACCESS_CONTROL,0x8E); //RF22_REG_30_DATA_ACCESS_CONTROL, RF22_ENPACRX | RF22_ENPACTX | RF22_ENCRC | RF22_CRC_CRC_16_IBM
greenroshks 3:89a09736acd3 71 //&0x77 = diasable packet rx-tx handling
greenroshks 3:89a09736acd3 72 writereg(RF22_REG_32_HEADER_CONTROL1,0x88); //RF22_REG_32_HEADER_CONTROL1, RF22_BCEN_HEADER3 | RF22_HDCH_HEADER3
greenroshks 3:89a09736acd3 73 writereg(RF22_REG_33_HEADER_CONTROL2,0x42); //RF22_REG_33_HEADER_CONTROL2, RF22_HDLEN_4 | RF22_SYNCLEN_2
greenroshks 3:89a09736acd3 74 writereg(RF22_REG_34_PREAMBLE_LENGTH,8); //RF22_REG_34_PREAMBLE_LENGTH, nibbles); preamble length = 8;
greenroshks 3:89a09736acd3 75 writereg(RF22_REG_36_SYNC_WORD3,0x2D); //syncword3=2D
greenroshks 3:89a09736acd3 76 writereg(RF22_REG_37_SYNC_WORD2,0xD4); //syncword2=D4
greenroshks 3:89a09736acd3 77 writereg(RF22_REG_3F_CHECK_HEADER3,0); //RF22_REG_3F_CHECK_HEADER3, RF22_DEFAULT_NODE_ADDRESS
greenroshks 3:89a09736acd3 78 writereg(RF22_REG_3A_TRANSMIT_HEADER3,0xab); //header_to
greenroshks 3:89a09736acd3 79 writereg(RF22_REG_3B_TRANSMIT_HEADER2,0xbc); //header_from
greenroshks 3:89a09736acd3 80 writereg(RF22_REG_3C_TRANSMIT_HEADER1,0xcd); //header_ids
greenroshks 3:89a09736acd3 81 writereg(RF22_REG_3D_TRANSMIT_HEADER0,0xde); //header_flags
greenroshks 3:89a09736acd3 82 writereg(RF22_REG_3F_CHECK_HEADER3,0xab);
greenroshks 3:89a09736acd3 83 writereg(RF22_REG_40_CHECK_HEADER2,0xbc);
greenroshks 3:89a09736acd3 84 writereg(RF22_REG_41_CHECK_HEADER1,0xcd);
greenroshks 3:89a09736acd3 85 writereg(RF22_REG_42_CHECK_HEADER0,0xde);
greenroshks 3:89a09736acd3 86
greenroshks 3:89a09736acd3 87 //RSSI threshold for clear channel indicator
greenroshks 3:89a09736acd3 88 writereg(RF22_REG_27_RSSI_THRESHOLD,0xA5); //55 for -80dBm, 2D for -100dBm, 7D for -60dBm, A5 for -40dBm, CD for -20 dBm
greenroshks 3:89a09736acd3 89
greenroshks 3:89a09736acd3 90 writereg(RF22_REG_0B_GPIO_CONFIGURATION0,0x15); // TX state ??
greenroshks 3:89a09736acd3 91 writereg(RF22_REG_0C_GPIO_CONFIGURATION1,0x12); // RX state ??
greenroshks 3:89a09736acd3 92
greenroshks 3:89a09736acd3 93 //interrupts
greenroshks 3:89a09736acd3 94 // spiWrite(RF22_REG_05_INTERRUPT_ENABLE1, RF22_ENTXFFAEM |RF22_ENRXFFAFULL | RF22_ENPKSENT |RF22_ENPKVALID| RF22_ENCRCERROR);
greenroshks 3:89a09736acd3 95 // spiWrite(RF22_REG_06_INTERRUPT_ENABLE2, RF22_ENPREAVAL);
greenroshks 3:89a09736acd3 96
greenroshks 3:89a09736acd3 97 setFrequency(435.0, 0.05);
greenroshks 3:89a09736acd3 98
greenroshks 3:89a09736acd3 99 //return !(statusRead() & RF22_FREQERR);
greenroshks 3:89a09736acd3 100 if((readreg(RF22_REG_02_DEVICE_STATUS)& 0x08)!= 0x00)
greenroshks 3:89a09736acd3 101 chavan.printf("frequency not set properly\n");
greenroshks 3:89a09736acd3 102 //frequency set
greenroshks 3:89a09736acd3 103
greenroshks 3:89a09736acd3 104 //setModemConfig(FSK_Rb2_4Fd36); FSK_Rb2_4Fd36, ///< FSK, No Manchester, Rb = 2.4kbs, Fd = 36kHz
greenroshks 3:89a09736acd3 105 //setmodemregisters
greenroshks 3:89a09736acd3 106 //0x1b, 0x03, 0x41, 0x60, 0x27, 0x52, 0x00, 0x07, 0x40, 0x0a, 0x1e, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x22, 0x3a = FSK_RB2_4FD36
greenroshks 3:89a09736acd3 107 //0xc8, 0x03, 0x39, 0x20, 0x68, 0xdc, 0x00, 0x6b, 0x2a, 0x08, 0x2a, 0x80, 0x60, 0x13, 0xa9, 0x2c, 0x21, 0x08 = OOK,2.4, 335
greenroshks 3:89a09736acd3 108 writereg(RF22_REG_1C_IF_FILTER_BANDWIDTH,0x2B);
greenroshks 3:89a09736acd3 109 writereg(RF22_REG_1F_CLOCK_RECOVERY_GEARSHIFT_OVERRIDE,0x03);
greenroshks 3:89a09736acd3 110 writereg(RF22_REG_20_CLOCK_RECOVERY_OVERSAMPLING_RATE,0x41);
greenroshks 3:89a09736acd3 111 writereg(RF22_REG_21_CLOCK_RECOVERY_OFFSET2,0x60);
greenroshks 3:89a09736acd3 112 writereg(RF22_REG_22_CLOCK_RECOVERY_OFFSET1,0x27); //updated 20 to 25 reg values from excel sheet for 1.2 Khz freq. deviation,fsk
greenroshks 3:89a09736acd3 113 writereg(RF22_REG_23_CLOCK_RECOVERY_OFFSET0,0x52);
greenroshks 3:89a09736acd3 114 writereg(RF22_REG_24_CLOCK_RECOVERY_TIMING_LOOP_GAIN1,0x00);
greenroshks 3:89a09736acd3 115 writereg(RF22_REG_25_CLOCK_RECOVERY_TIMING_LOOP_GAIN0,0x51);
greenroshks 3:89a09736acd3 116 /*writereg(RF22_REG_2C_OOK_COUNTER_VALUE_1,0x2a);
greenroshks 3:89a09736acd3 117 writereg(RF22_REG_2D_OOK_COUNTER_VALUE_2,0x08);*/ //not required for fsk (OOK counter value)
greenroshks 3:89a09736acd3 118 writereg(RF22_REG_2E_SLICER_PEAK_HOLD,0x1e); //??
greenroshks 3:89a09736acd3 119 writereg(RF22_REG_58,0x80);
greenroshks 3:89a09736acd3 120 writereg(RF22_REG_69_AGC_OVERRIDE1,0x60);
greenroshks 3:89a09736acd3 121 writereg(RF22_REG_6E_TX_DATA_RATE1,0x09);
greenroshks 3:89a09736acd3 122 writereg(RF22_REG_6F_TX_DATA_RATE0,0xd5);
greenroshks 3:89a09736acd3 123 writereg(RF22_REG_70_MODULATION_CONTROL1,0x2c);
greenroshks 3:89a09736acd3 124 writereg(RF22_REG_71_MODULATION_CONTROL2,0x22);//ook = 0x21 //fsk = 0x22
greenroshks 3:89a09736acd3 125 writereg(RF22_REG_72_FREQUENCY_DEVIATION,0x02);
greenroshks 3:89a09736acd3 126 //set tx power
greenroshks 3:89a09736acd3 127 writereg(RF22_REG_6D_TX_POWER,0x07); //20dbm
greenroshks 3:89a09736acd3 128 writereg(RF22_REG_3E_PACKET_LENGTH,TX_DATA); //packet length
greenroshks 3:89a09736acd3 129 }
greenroshks 3:89a09736acd3 130 void FUNC_BEA()
greenroshks 3:89a09736acd3 131 {
greenroshks 3:89a09736acd3 132 printf("\nBeacon function entered\n");
greenroshks 3:89a09736acd3 133 wait(1); // wait for POR to complete //change the timing later
greenroshks 3:89a09736acd3 134 cs=1; // chip must be deselected
greenroshks 3:89a09736acd3 135 wait(1); //change the time later
greenroshks 3:89a09736acd3 136 spi.format(8,0);
greenroshks 3:89a09736acd3 137 spi.frequency(10000000); //10MHz SCLK
greenroshks 3:89a09736acd3 138 if (readreg(RF22_REG_00_DEVICE_TYPE) == 0x08) chavan.printf("spi connection valid\n");
greenroshks 3:89a09736acd3 139 else chavan.printf("error in spi connection\n");
greenroshks 3:89a09736acd3 140
greenroshks 3:89a09736acd3 141 init();
greenroshks 3:89a09736acd3 142
greenroshks 3:89a09736acd3 143 //********
greenroshks 3:89a09736acd3 144 //button.rise(&interrupt_func); //interrupt enabled ( rising edge of pin 9)
greenroshks 3:89a09736acd3 145 wait(0.02); // pl. update this value or even avoid it!!!
greenroshks 3:89a09736acd3 146 //extract values from short_beacon[]
greenroshks 3:89a09736acd3 147 uint8_t byte_counter = 0;
greenroshks 3:89a09736acd3 148 /*struct Short_beacon{
greenroshks 3:89a09736acd3 149 uint8_t Voltage[1];
greenroshks 3:89a09736acd3 150 uint8_t AngularSpeed[2];
greenroshks 3:89a09736acd3 151 uint8_t SubsystemStatus[1];
greenroshks 3:89a09736acd3 152 uint8_t Temp[3];
greenroshks 3:89a09736acd3 153 uint8_t ErrorFlag[1];
greenroshks 3:89a09736acd3 154 }Shortbeacon = { {0x88}, {0x99, 0xAA} , {0xAA},{0xAA,0xDD,0xEE}, {0x00} };
greenroshks 3:89a09736acd3 155 */
greenroshks 3:89a09736acd3 156 //filling hk data
greenroshks 3:89a09736acd3 157 uint8_t short_beacon[] = { 0xAB, 0x8A, 0xE2, 0xBB, 0xB8, 0xA2, 0x8E,Shortbeacon.Voltage[0],Shortbeacon.AngularSpeed[0], Shortbeacon.AngularSpeed[1],Shortbeacon.SubsystemStatus[0],Shortbeacon.Temp[0],Shortbeacon.Temp[1],Shortbeacon.Temp[2],Shortbeacon.ErrorFlag[0]};
greenroshks 3:89a09736acd3 158
greenroshks 3:89a09736acd3 159 for(int i = 0; i < 15 ; i++)
greenroshks 3:89a09736acd3 160 {
greenroshks 3:89a09736acd3 161 chavan.printf("0x%X\n",(short_beacon[i]));
greenroshks 3:89a09736acd3 162 }
greenroshks 3:89a09736acd3 163 //tx settings begin
greenroshks 3:89a09736acd3 164 //setModeIdle();
greenroshks 3:89a09736acd3 165 writereg(RF22_REG_07_OPERATING_MODE1,0x01); //ready mode
greenroshks 3:89a09736acd3 166 //fillTxBuf(data, len);
greenroshks 3:89a09736acd3 167 clearTxBuf();
greenroshks 3:89a09736acd3 168
greenroshks 3:89a09736acd3 169 //Set to Tx mode
greenroshks 3:89a09736acd3 170 writereg(RF22_REG_07_OPERATING_MODE1,0x09);
greenroshks 3:89a09736acd3 171
greenroshks 3:89a09736acd3 172 while(byte_counter!=15){
greenroshks 3:89a09736acd3 173 //Check for fifoThresh
greenroshks 3:89a09736acd3 174 while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x20) != 0x20);
greenroshks 3:89a09736acd3 175 //writing again
greenroshks 3:89a09736acd3 176 cs = 0;
greenroshks 3:89a09736acd3 177 spi.write(0xFF);
greenroshks 3:89a09736acd3 178 for(int i=7; i>=0 ;i--)
greenroshks 3:89a09736acd3 179 {
greenroshks 3:89a09736acd3 180 //chavan.printf("%d\n",byte_counter);
greenroshks 3:89a09736acd3 181 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!=0)
greenroshks 3:89a09736acd3 182 {
greenroshks 3:89a09736acd3 183 spi.write(0xFF);
greenroshks 3:89a09736acd3 184 spi.write(0xFF);
greenroshks 3:89a09736acd3 185 }
greenroshks 3:89a09736acd3 186 else
greenroshks 3:89a09736acd3 187 {
greenroshks 3:89a09736acd3 188 spi.write(0x00);
greenroshks 3:89a09736acd3 189 spi.write(0x00);
greenroshks 3:89a09736acd3 190
greenroshks 3:89a09736acd3 191 }
greenroshks 3:89a09736acd3 192 }
greenroshks 3:89a09736acd3 193 cs = 1;
greenroshks 3:89a09736acd3 194 byte_counter++;
greenroshks 3:89a09736acd3 195
greenroshks 3:89a09736acd3 196 }
greenroshks 3:89a09736acd3 197 //rf22.waitPacketSent();
greenroshks 3:89a09736acd3 198 while((readreg(RF22_REG_03_INTERRUPT_STATUS1) & 0x04) != 0x04);//chavan.printf(" chck pkt sent!\n");
greenroshks 3:89a09736acd3 199 printf("\nBeacon function exiting\n");
greenroshks 3:89a09736acd3 200
greenroshks 3:89a09736acd3 201 }