Gian Paolo Donnarumma / LPS22HH

LPS22HH single file class Library for I2C

LPS22HH

#include "LPS22HH.h"

LPS22HH     BAROMETER(I2C_SDA,I2C_SCL);

void main()
{
   BAROMETER.begin();
    BAROMETER.Enable();

   while(1)
  {
     printf("%f hPa \r\n,BAROMETER.GetPressure());
  }
}

LPS22HH.cpp@0:b74c7741e608, 2021-04-14 (annotated)

Committer:
gpmbed
Date:
Wed Apr 14 16:15:25 2021 +0000
Revision:
0:b74c7741e608
Single file LPS22HH class

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gpmbed 0:b74c7741e608 1 #include "LPS22HH.h"
gpmbed 0:b74c7741e608 2
gpmbed 0:b74c7741e608 3 int32_t lps22hh_write_reg(lps22hh_ctx_t* ctx, uint8_t reg, uint8_t* data, uint16_t len);
gpmbed 0:b74c7741e608 4 int32_t lps22hh_read_reg(lps22hh_ctx_t* ctx, uint8_t reg, uint8_t* data, uint16_t len);
gpmbed 0:b74c7741e608 5
gpmbed 0:b74c7741e608 6 int32_t lps22hh_data_rate_set(lps22hh_ctx_t *ctx, lps22hh_odr_t val);
gpmbed 0:b74c7741e608 7 int32_t lps22hh_data_rate_get(lps22hh_ctx_t *ctx, lps22hh_odr_t *val);
gpmbed 0:b74c7741e608 8
gpmbed 0:b74c7741e608 9 int32_t lps22hh_lp_bandwidth_set(lps22hh_ctx_t *ctx, lps22hh_lpfp_cfg_t val);
gpmbed 0:b74c7741e608 10 int32_t lps22hh_lp_bandwidth_get(lps22hh_ctx_t *ctx, lps22hh_lpfp_cfg_t *val);
gpmbed 0:b74c7741e608 11
gpmbed 0:b74c7741e608 12 int32_t lps22hh_block_data_update_set(lps22hh_ctx_t *ctx, uint8_t val);
gpmbed 0:b74c7741e608 13 int32_t lps22hh_auto_increment_set(lps22hh_ctx_t *ctx, uint8_t val);
gpmbed 0:b74c7741e608 14
gpmbed 0:b74c7741e608 15 int32_t lps22hh_pressure_raw_get(lps22hh_ctx_t *ctx, uint8_t *buff);
gpmbed 0:b74c7741e608 16 int32_t lps22hh_temperature_raw_get(lps22hh_ctx_t *ctx, uint8_t *buff);
gpmbed 0:b74c7741e608 17
gpmbed 0:b74c7741e608 18 int32_t lps22hh_press_flag_data_ready_get(lps22hh_ctx_t *ctx, uint8_t *val);
gpmbed 0:b74c7741e608 19 int32_t lps22hh_temp_flag_data_ready_get(lps22hh_ctx_t *ctx, uint8_t *val);
gpmbed 0:b74c7741e608 20
gpmbed 0:b74c7741e608 21 int32_t lps22hh_fifo_pressure_raw_get(lps22hh_ctx_t *ctx, uint8_t *buff);
gpmbed 0:b74c7741e608 22 int32_t lps22hh_fifo_temperature_raw_get(lps22hh_ctx_t *ctx, uint8_t *buff);
gpmbed 0:b74c7741e608 23 int32_t lps22hh_fifo_wtm_flag_get(lps22hh_ctx_t *ctx, uint8_t *val);
gpmbed 0:b74c7741e608 24 int32_t lps22hh_fifo_ovr_flag_get(lps22hh_ctx_t *ctx, uint8_t *val);
gpmbed 0:b74c7741e608 25 int32_t lps22hh_fifo_full_flag_get(lps22hh_ctx_t *ctx, uint8_t *val);
gpmbed 0:b74c7741e608 26 int32_t lps22hh_fifo_src_get(lps22hh_ctx_t *ctx, lps22hh_fifo_status2_t *val);
gpmbed 0:b74c7741e608 27 int32_t lps22hh_fifo_data_level_get(lps22hh_ctx_t *ctx, uint8_t *buff);
gpmbed 0:b74c7741e608 28 int32_t lps22hh_fifo_threshold_on_int_set(lps22hh_ctx_t *ctx, uint8_t val);
gpmbed 0:b74c7741e608 29 int32_t lps22hh_fifo_full_on_int_set(lps22hh_ctx_t *ctx, uint8_t val);
gpmbed 0:b74c7741e608 30 int32_t lps22hh_fifo_ovr_on_int_set(lps22hh_ctx_t *ctx, uint8_t val);
gpmbed 0:b74c7741e608 31 int32_t lps22hh_fifo_stop_on_wtm_set(lps22hh_ctx_t *ctx, uint8_t val);
gpmbed 0:b74c7741e608 32 int32_t lps22hh_fifo_mode_get(lps22hh_ctx_t *ctx, lps22hh_f_mode_t *val);
gpmbed 0:b74c7741e608 33 int32_t lps22hh_fifo_mode_set(lps22hh_ctx_t *ctx, lps22hh_f_mode_t val);
gpmbed 0:b74c7741e608 34 int32_t lps22hh_fifo_watermark_set(lps22hh_ctx_t *ctx, uint8_t val);
gpmbed 0:b74c7741e608 35
gpmbed 0:b74c7741e608 36 /* Class Implementation ------------------------------------------------------*/
gpmbed 0:b74c7741e608 37
gpmbed 0:b74c7741e608 38 /** Constructor
gpmbed 0:b74c7741e608 39 * @param i2c object of an helper class which handles the I2C peripheral
gpmbed 0:b74c7741e608 40 * @param address the address of the component's instance
gpmbed 0:b74c7741e608 41 */
gpmbed 0:b74c7741e608 42 LPS22HH::LPS22HH(PinName sda, PinName scl) : _i2c(sda, scl)
gpmbed 0:b74c7741e608 43 {
gpmbed 0:b74c7741e608 44 address=LPS22HH_I2C_ADD_H;
gpmbed 0:b74c7741e608 45 reg_ctx.write_reg = LPS22HH_io_write;
gpmbed 0:b74c7741e608 46 reg_ctx.read_reg = LPS22HH_io_read;
gpmbed 0:b74c7741e608 47 reg_ctx.handle = (void *)this;
gpmbed 0:b74c7741e608 48 enabled = 0;
gpmbed 0:b74c7741e608 49 }
gpmbed 0:b74c7741e608 50
gpmbed 0:b74c7741e608 51 /** Constructor
gpmbed 0:b74c7741e608 52 * @param spi object of an helper class which handles the SPI peripheral
gpmbed 0:b74c7741e608 53 * @param cs_pin the chip select pin
gpmbed 0:b74c7741e608 54 * @param spi_speed the SPI speed
gpmbed 0:b74c7741e608 55
gpmbed 0:b74c7741e608 56 LPS22HH::LPS22HH(SPIClass *spi, int cs_pin, uint32_t spi_speed) : dev_spi(spi), cs_pin(cs_pin), spi_speed(spi_speed)
gpmbed 0:b74c7741e608 57 {
gpmbed 0:b74c7741e608 58 reg_ctx.write_reg = LPS22HH_io_write;
gpmbed 0:b74c7741e608 59 reg_ctx.read_reg = LPS22HH_io_read;
gpmbed 0:b74c7741e608 60 reg_ctx.handle = (void *)this;
gpmbed 0:b74c7741e608 61 dev_i2c = NULL;
gpmbed 0:b74c7741e608 62 address = 0;
gpmbed 0:b74c7741e608 63 enabled = 0;
gpmbed 0:b74c7741e608 64 }
gpmbed 0:b74c7741e608 65 */
gpmbed 0:b74c7741e608 66
gpmbed 0:b74c7741e608 67 /**
gpmbed 0:b74c7741e608 68 * @brief Configure the sensor in order to be used
gpmbed 0:b74c7741e608 69 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 70 */
gpmbed 0:b74c7741e608 71 LPS22HHStatusTypeDef LPS22HH::begin()
gpmbed 0:b74c7741e608 72 {
gpmbed 0:b74c7741e608 73
gpmbed 0:b74c7741e608 74 /* Power down the device, set Low Noise Enable (bit 5), clear One Shot (bit 4) */
gpmbed 0:b74c7741e608 75 if (lps22hh_data_rate_set(&reg_ctx, (lps22hh_odr_t)(LPS22HH_POWER_DOWN | 0x10)) != LPS22HH_OK)
gpmbed 0:b74c7741e608 76 {
gpmbed 0:b74c7741e608 77 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 78 }
gpmbed 0:b74c7741e608 79
gpmbed 0:b74c7741e608 80 /* Disable low-pass filter on LPS22HH pressure data */
gpmbed 0:b74c7741e608 81 if (lps22hh_lp_bandwidth_set(&reg_ctx, LPS22HH_LPF_ODR_DIV_2) != LPS22HH_OK)
gpmbed 0:b74c7741e608 82 {
gpmbed 0:b74c7741e608 83 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 84 }
gpmbed 0:b74c7741e608 85
gpmbed 0:b74c7741e608 86 /* Set block data update mode */
gpmbed 0:b74c7741e608 87 if (lps22hh_block_data_update_set(&reg_ctx, PROPERTY_ENABLE) != LPS22HH_OK)
gpmbed 0:b74c7741e608 88 {
gpmbed 0:b74c7741e608 89 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 90 }
gpmbed 0:b74c7741e608 91
gpmbed 0:b74c7741e608 92 /* Set autoincrement for multi-byte read/write */
gpmbed 0:b74c7741e608 93 if (lps22hh_auto_increment_set(&reg_ctx, PROPERTY_ENABLE) != LPS22HH_OK)
gpmbed 0:b74c7741e608 94 {
gpmbed 0:b74c7741e608 95 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 96 }
gpmbed 0:b74c7741e608 97
gpmbed 0:b74c7741e608 98 last_odr = LPS22HH_25_Hz;
gpmbed 0:b74c7741e608 99 enabled = 0;
gpmbed 0:b74c7741e608 100
gpmbed 0:b74c7741e608 101 return LPS22HH_OK;
gpmbed 0:b74c7741e608 102 }
gpmbed 0:b74c7741e608 103
gpmbed 0:b74c7741e608 104 /**
gpmbed 0:b74c7741e608 105 * @brief Disable the sensor and relative resources
gpmbed 0:b74c7741e608 106 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 107 */
gpmbed 0:b74c7741e608 108 LPS22HHStatusTypeDef LPS22HH::end()
gpmbed 0:b74c7741e608 109 {
gpmbed 0:b74c7741e608 110 /* Disable pressure and temperature sensor */
gpmbed 0:b74c7741e608 111 if (Disable() != LPS22HH_OK)
gpmbed 0:b74c7741e608 112 {
gpmbed 0:b74c7741e608 113 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 114 }
gpmbed 0:b74c7741e608 115
gpmbed 0:b74c7741e608 116
gpmbed 0:b74c7741e608 117 return LPS22HH_OK;
gpmbed 0:b74c7741e608 118 }
gpmbed 0:b74c7741e608 119
gpmbed 0:b74c7741e608 120 /**
gpmbed 0:b74c7741e608 121 * @brief Get WHO_AM_I value
gpmbed 0:b74c7741e608 122 * @param Id the WHO_AM_I value
gpmbed 0:b74c7741e608 123 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 124 */
gpmbed 0:b74c7741e608 125 LPS22HHStatusTypeDef LPS22HH::ReadID(uint8_t *Id)
gpmbed 0:b74c7741e608 126 {
gpmbed 0:b74c7741e608 127
gpmbed 0:b74c7741e608 128 //lps22hh_device_id_get(lps22hh_ctx_t *ctx, uint8_t *buff)
gpmbed 0:b74c7741e608 129 int32_t ret;
gpmbed 0:b74c7741e608 130 ret = lps22hh_read_reg(&reg_ctx, LPS22HH_WHO_AM_I, Id, 1);
gpmbed 0:b74c7741e608 131
gpmbed 0:b74c7741e608 132
gpmbed 0:b74c7741e608 133 if (ret != LPS22HH_OK)
gpmbed 0:b74c7741e608 134 {
gpmbed 0:b74c7741e608 135 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 136 }
gpmbed 0:b74c7741e608 137
gpmbed 0:b74c7741e608 138 return LPS22HH_OK;
gpmbed 0:b74c7741e608 139 }
gpmbed 0:b74c7741e608 140
gpmbed 0:b74c7741e608 141 /**
gpmbed 0:b74c7741e608 142 * @brief Enable the LPS22HH pressure sensor
gpmbed 0:b74c7741e608 143 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 144 */
gpmbed 0:b74c7741e608 145 LPS22HHStatusTypeDef LPS22HH::Enable()
gpmbed 0:b74c7741e608 146 {
gpmbed 0:b74c7741e608 147 /* Check if the component is already enabled */
gpmbed 0:b74c7741e608 148 if (enabled == 1U)
gpmbed 0:b74c7741e608 149 {
gpmbed 0:b74c7741e608 150 return LPS22HH_OK;
gpmbed 0:b74c7741e608 151 }
gpmbed 0:b74c7741e608 152
gpmbed 0:b74c7741e608 153 /* Output data rate selection. */
gpmbed 0:b74c7741e608 154 if (lps22hh_data_rate_set(&reg_ctx, last_odr) != LPS22HH_OK)
gpmbed 0:b74c7741e608 155 {
gpmbed 0:b74c7741e608 156 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 157 }
gpmbed 0:b74c7741e608 158
gpmbed 0:b74c7741e608 159 enabled = 1;
gpmbed 0:b74c7741e608 160
gpmbed 0:b74c7741e608 161 return LPS22HH_OK;
gpmbed 0:b74c7741e608 162 }
gpmbed 0:b74c7741e608 163
gpmbed 0:b74c7741e608 164 /**
gpmbed 0:b74c7741e608 165 * @brief Disable the LPS22HH pressure sensor
gpmbed 0:b74c7741e608 166 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 167 */
gpmbed 0:b74c7741e608 168 LPS22HHStatusTypeDef LPS22HH::Disable()
gpmbed 0:b74c7741e608 169 {
gpmbed 0:b74c7741e608 170 /* Check if the component is already disabled */
gpmbed 0:b74c7741e608 171 if (enabled == 0U)
gpmbed 0:b74c7741e608 172 {
gpmbed 0:b74c7741e608 173 return LPS22HH_OK;
gpmbed 0:b74c7741e608 174 }
gpmbed 0:b74c7741e608 175
gpmbed 0:b74c7741e608 176 lps22hh_ctrl_reg1_t ctrl_reg1;
gpmbed 0:b74c7741e608 177 lps22hh_ctrl_reg2_t ctrl_reg2;
gpmbed 0:b74c7741e608 178 int32_t ret;
gpmbed 0:b74c7741e608 179
gpmbed 0:b74c7741e608 180 //lps22hh_data_rate_get(&reg_ctx, &last_odr)
gpmbed 0:b74c7741e608 181
gpmbed 0:b74c7741e608 182 ret = lps22hh_read_reg(&reg_ctx, LPS22HH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
gpmbed 0:b74c7741e608 183 if (ret == 0) {
gpmbed 0:b74c7741e608 184 ret = lps22hh_read_reg(&reg_ctx, LPS22HH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
gpmbed 0:b74c7741e608 185 }
gpmbed 0:b74c7741e608 186 if (ret == 0) {
gpmbed 0:b74c7741e608 187 ret = lps22hh_read_reg(&reg_ctx, LPS22HH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
gpmbed 0:b74c7741e608 188 switch (((ctrl_reg2.low_noise_en << 4) + (ctrl_reg2.one_shot << 3) +
gpmbed 0:b74c7741e608 189 ctrl_reg1.odr )) {
gpmbed 0:b74c7741e608 190 case LPS22HH_POWER_DOWN:
gpmbed 0:b74c7741e608 191 last_odr = LPS22HH_POWER_DOWN;
gpmbed 0:b74c7741e608 192 break;
gpmbed 0:b74c7741e608 193 case LPS22HH_ONE_SHOOT:
gpmbed 0:b74c7741e608 194 last_odr = LPS22HH_ONE_SHOOT;
gpmbed 0:b74c7741e608 195 break;
gpmbed 0:b74c7741e608 196 case LPS22HH_1_Hz:
gpmbed 0:b74c7741e608 197 last_odr = LPS22HH_1_Hz;
gpmbed 0:b74c7741e608 198 break;
gpmbed 0:b74c7741e608 199 case LPS22HH_10_Hz:
gpmbed 0:b74c7741e608 200 last_odr = LPS22HH_10_Hz;
gpmbed 0:b74c7741e608 201 break;
gpmbed 0:b74c7741e608 202 case LPS22HH_25_Hz:
gpmbed 0:b74c7741e608 203 last_odr = LPS22HH_25_Hz;
gpmbed 0:b74c7741e608 204 break;
gpmbed 0:b74c7741e608 205 case LPS22HH_50_Hz:
gpmbed 0:b74c7741e608 206 last_odr = LPS22HH_50_Hz;
gpmbed 0:b74c7741e608 207 break;
gpmbed 0:b74c7741e608 208 case LPS22HH_75_Hz:
gpmbed 0:b74c7741e608 209 last_odr = LPS22HH_75_Hz;
gpmbed 0:b74c7741e608 210 break;
gpmbed 0:b74c7741e608 211 case LPS22HH_1_Hz_LOW_NOISE:
gpmbed 0:b74c7741e608 212 last_odr = LPS22HH_1_Hz_LOW_NOISE;
gpmbed 0:b74c7741e608 213 break;
gpmbed 0:b74c7741e608 214 case LPS22HH_10_Hz_LOW_NOISE:
gpmbed 0:b74c7741e608 215 last_odr = LPS22HH_10_Hz_LOW_NOISE;
gpmbed 0:b74c7741e608 216 break;
gpmbed 0:b74c7741e608 217 case LPS22HH_25_Hz_LOW_NOISE:
gpmbed 0:b74c7741e608 218 last_odr = LPS22HH_25_Hz_LOW_NOISE;
gpmbed 0:b74c7741e608 219 break;
gpmbed 0:b74c7741e608 220 case LPS22HH_50_Hz_LOW_NOISE:
gpmbed 0:b74c7741e608 221 last_odr = LPS22HH_50_Hz_LOW_NOISE;
gpmbed 0:b74c7741e608 222 break;
gpmbed 0:b74c7741e608 223 case LPS22HH_75_Hz_LOW_NOISE:
gpmbed 0:b74c7741e608 224 last_odr = LPS22HH_75_Hz_LOW_NOISE;
gpmbed 0:b74c7741e608 225 break;
gpmbed 0:b74c7741e608 226 case LPS22HH_100_Hz:
gpmbed 0:b74c7741e608 227 last_odr = LPS22HH_100_Hz;
gpmbed 0:b74c7741e608 228 break;
gpmbed 0:b74c7741e608 229 case LPS22HH_200_Hz:
gpmbed 0:b74c7741e608 230 last_odr = LPS22HH_200_Hz;
gpmbed 0:b74c7741e608 231 break;
gpmbed 0:b74c7741e608 232 default:
gpmbed 0:b74c7741e608 233 last_odr = LPS22HH_POWER_DOWN;
gpmbed 0:b74c7741e608 234 break;
gpmbed 0:b74c7741e608 235 }
gpmbed 0:b74c7741e608 236 }
gpmbed 0:b74c7741e608 237
gpmbed 0:b74c7741e608 238
gpmbed 0:b74c7741e608 239 /* Get current output data rate. */
gpmbed 0:b74c7741e608 240 if (ret != LPS22HH_OK)
gpmbed 0:b74c7741e608 241 {
gpmbed 0:b74c7741e608 242 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 243 }
gpmbed 0:b74c7741e608 244 /* Output data rate selection - power down. */
gpmbed 0:b74c7741e608 245 if (lps22hh_data_rate_set(&reg_ctx, LPS22HH_POWER_DOWN) != LPS22HH_OK)
gpmbed 0:b74c7741e608 246 {
gpmbed 0:b74c7741e608 247 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 248 }
gpmbed 0:b74c7741e608 249
gpmbed 0:b74c7741e608 250
gpmbed 0:b74c7741e608 251 enabled = 0;
gpmbed 0:b74c7741e608 252
gpmbed 0:b74c7741e608 253 return LPS22HH_OK;
gpmbed 0:b74c7741e608 254 }
gpmbed 0:b74c7741e608 255
gpmbed 0:b74c7741e608 256
gpmbed 0:b74c7741e608 257 /**
gpmbed 0:b74c7741e608 258 * @brief Get output data rate
gpmbed 0:b74c7741e608 259 * @param Odr the output data rate value
gpmbed 0:b74c7741e608 260 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 261 */
gpmbed 0:b74c7741e608 262 LPS22HHStatusTypeDef LPS22HH::GetOutputDataRate(float *Odr)
gpmbed 0:b74c7741e608 263 {
gpmbed 0:b74c7741e608 264 LPS22HHStatusTypeDef result = LPS22HH_OK;
gpmbed 0:b74c7741e608 265 lps22hh_odr_t odr_low_level;
gpmbed 0:b74c7741e608 266
gpmbed 0:b74c7741e608 267 lps22hh_ctrl_reg1_t ctrl_reg1;
gpmbed 0:b74c7741e608 268 lps22hh_ctrl_reg2_t ctrl_reg2;
gpmbed 0:b74c7741e608 269 int32_t ret;
gpmbed 0:b74c7741e608 270
gpmbed 0:b74c7741e608 271 ret = lps22hh_read_reg(&reg_ctx, LPS22HH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
gpmbed 0:b74c7741e608 272 if (ret == 0) {
gpmbed 0:b74c7741e608 273 ret = lps22hh_read_reg(&reg_ctx, LPS22HH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
gpmbed 0:b74c7741e608 274 }
gpmbed 0:b74c7741e608 275 if (ret == 0) {
gpmbed 0:b74c7741e608 276 ret = lps22hh_read_reg(&reg_ctx, LPS22HH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
gpmbed 0:b74c7741e608 277 switch (((ctrl_reg2.low_noise_en << 4) + (ctrl_reg2.one_shot << 3) +
gpmbed 0:b74c7741e608 278 ctrl_reg1.odr )) {
gpmbed 0:b74c7741e608 279 case LPS22HH_POWER_DOWN:
gpmbed 0:b74c7741e608 280 odr_low_level = LPS22HH_POWER_DOWN;
gpmbed 0:b74c7741e608 281 break;
gpmbed 0:b74c7741e608 282 case LPS22HH_ONE_SHOOT:
gpmbed 0:b74c7741e608 283 odr_low_level = LPS22HH_ONE_SHOOT;
gpmbed 0:b74c7741e608 284 break;
gpmbed 0:b74c7741e608 285 case LPS22HH_1_Hz:
gpmbed 0:b74c7741e608 286 odr_low_level = LPS22HH_1_Hz;
gpmbed 0:b74c7741e608 287 break;
gpmbed 0:b74c7741e608 288 case LPS22HH_10_Hz:
gpmbed 0:b74c7741e608 289 odr_low_level = LPS22HH_10_Hz;
gpmbed 0:b74c7741e608 290 break;
gpmbed 0:b74c7741e608 291 case LPS22HH_25_Hz:
gpmbed 0:b74c7741e608 292 odr_low_level = LPS22HH_25_Hz;
gpmbed 0:b74c7741e608 293 break;
gpmbed 0:b74c7741e608 294 case LPS22HH_50_Hz:
gpmbed 0:b74c7741e608 295 odr_low_level = LPS22HH_50_Hz;
gpmbed 0:b74c7741e608 296 break;
gpmbed 0:b74c7741e608 297 case LPS22HH_75_Hz:
gpmbed 0:b74c7741e608 298 odr_low_level = LPS22HH_75_Hz;
gpmbed 0:b74c7741e608 299 break;
gpmbed 0:b74c7741e608 300 case LPS22HH_1_Hz_LOW_NOISE:
gpmbed 0:b74c7741e608 301 odr_low_level = LPS22HH_1_Hz_LOW_NOISE;
gpmbed 0:b74c7741e608 302 break;
gpmbed 0:b74c7741e608 303 case LPS22HH_10_Hz_LOW_NOISE:
gpmbed 0:b74c7741e608 304 odr_low_level = LPS22HH_10_Hz_LOW_NOISE;
gpmbed 0:b74c7741e608 305 break;
gpmbed 0:b74c7741e608 306 case LPS22HH_25_Hz_LOW_NOISE:
gpmbed 0:b74c7741e608 307 odr_low_level = LPS22HH_25_Hz_LOW_NOISE;
gpmbed 0:b74c7741e608 308 break;
gpmbed 0:b74c7741e608 309 case LPS22HH_50_Hz_LOW_NOISE:
gpmbed 0:b74c7741e608 310 odr_low_level = LPS22HH_50_Hz_LOW_NOISE;
gpmbed 0:b74c7741e608 311 break;
gpmbed 0:b74c7741e608 312 case LPS22HH_75_Hz_LOW_NOISE:
gpmbed 0:b74c7741e608 313 odr_low_level = LPS22HH_75_Hz_LOW_NOISE;
gpmbed 0:b74c7741e608 314 break;
gpmbed 0:b74c7741e608 315 case LPS22HH_100_Hz:
gpmbed 0:b74c7741e608 316 odr_low_level = LPS22HH_100_Hz;
gpmbed 0:b74c7741e608 317 break;
gpmbed 0:b74c7741e608 318 case LPS22HH_200_Hz:
gpmbed 0:b74c7741e608 319 odr_low_level = LPS22HH_200_Hz;
gpmbed 0:b74c7741e608 320 break;
gpmbed 0:b74c7741e608 321 default:
gpmbed 0:b74c7741e608 322 odr_low_level = LPS22HH_POWER_DOWN;
gpmbed 0:b74c7741e608 323 break;
gpmbed 0:b74c7741e608 324 }
gpmbed 0:b74c7741e608 325 }
gpmbed 0:b74c7741e608 326
gpmbed 0:b74c7741e608 327 if (ret != LPS22HH_OK)
gpmbed 0:b74c7741e608 328 {
gpmbed 0:b74c7741e608 329 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 330 }
gpmbed 0:b74c7741e608 331
gpmbed 0:b74c7741e608 332 switch (odr_low_level)
gpmbed 0:b74c7741e608 333 {
gpmbed 0:b74c7741e608 334 case LPS22HH_POWER_DOWN:
gpmbed 0:b74c7741e608 335 *Odr = 0.0f;
gpmbed 0:b74c7741e608 336 break;
gpmbed 0:b74c7741e608 337
gpmbed 0:b74c7741e608 338 case LPS22HH_1_Hz:
gpmbed 0:b74c7741e608 339 *Odr = 1.0f;
gpmbed 0:b74c7741e608 340 break;
gpmbed 0:b74c7741e608 341
gpmbed 0:b74c7741e608 342 case LPS22HH_10_Hz:
gpmbed 0:b74c7741e608 343 *Odr = 10.0f;
gpmbed 0:b74c7741e608 344 break;
gpmbed 0:b74c7741e608 345
gpmbed 0:b74c7741e608 346 case LPS22HH_25_Hz:
gpmbed 0:b74c7741e608 347 *Odr = 25.0f;
gpmbed 0:b74c7741e608 348 break;
gpmbed 0:b74c7741e608 349
gpmbed 0:b74c7741e608 350 case LPS22HH_50_Hz:
gpmbed 0:b74c7741e608 351 *Odr = 50.0f;
gpmbed 0:b74c7741e608 352 break;
gpmbed 0:b74c7741e608 353
gpmbed 0:b74c7741e608 354 case LPS22HH_75_Hz:
gpmbed 0:b74c7741e608 355 *Odr = 75.0f;
gpmbed 0:b74c7741e608 356 break;
gpmbed 0:b74c7741e608 357
gpmbed 0:b74c7741e608 358 case LPS22HH_100_Hz:
gpmbed 0:b74c7741e608 359 *Odr = 100.0f;
gpmbed 0:b74c7741e608 360 break;
gpmbed 0:b74c7741e608 361
gpmbed 0:b74c7741e608 362 case LPS22HH_200_Hz:
gpmbed 0:b74c7741e608 363 *Odr = 200.0f;
gpmbed 0:b74c7741e608 364 break;
gpmbed 0:b74c7741e608 365
gpmbed 0:b74c7741e608 366 default:
gpmbed 0:b74c7741e608 367 result = LPS22HH_ERROR;
gpmbed 0:b74c7741e608 368 break;
gpmbed 0:b74c7741e608 369 }
gpmbed 0:b74c7741e608 370
gpmbed 0:b74c7741e608 371 return result;
gpmbed 0:b74c7741e608 372 }
gpmbed 0:b74c7741e608 373
gpmbed 0:b74c7741e608 374 /**
gpmbed 0:b74c7741e608 375 * @brief Set the LPS22HH pressure sensor output data rate
gpmbed 0:b74c7741e608 376 * @param Odr the output data rate value to be set
gpmbed 0:b74c7741e608 377 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 378 */
gpmbed 0:b74c7741e608 379 LPS22HHStatusTypeDef LPS22HH::SetOutputDataRate(float Odr)
gpmbed 0:b74c7741e608 380 {
gpmbed 0:b74c7741e608 381 /* Check if the component is enabled */
gpmbed 0:b74c7741e608 382 if (enabled == 1U)
gpmbed 0:b74c7741e608 383 {
gpmbed 0:b74c7741e608 384 return SetOutputDataRate_When_Enabled(Odr);
gpmbed 0:b74c7741e608 385 }
gpmbed 0:b74c7741e608 386 else
gpmbed 0:b74c7741e608 387 {
gpmbed 0:b74c7741e608 388 return SetOutputDataRate_When_Disabled(Odr);
gpmbed 0:b74c7741e608 389 }
gpmbed 0:b74c7741e608 390 }
gpmbed 0:b74c7741e608 391
gpmbed 0:b74c7741e608 392
gpmbed 0:b74c7741e608 393 /**
gpmbed 0:b74c7741e608 394 * @brief Set output data rate
gpmbed 0:b74c7741e608 395 * @param Odr the output data rate value to be set
gpmbed 0:b74c7741e608 396 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 397 */
gpmbed 0:b74c7741e608 398 LPS22HHStatusTypeDef LPS22HH::SetOutputDataRate_When_Enabled(float Odr)
gpmbed 0:b74c7741e608 399 {
gpmbed 0:b74c7741e608 400 lps22hh_odr_t new_odr;
gpmbed 0:b74c7741e608 401
gpmbed 0:b74c7741e608 402 new_odr = (Odr <= 1.0f) ? LPS22HH_1_Hz
gpmbed 0:b74c7741e608 403 : (Odr <= 10.0f) ? LPS22HH_10_Hz
gpmbed 0:b74c7741e608 404 : (Odr <= 25.0f) ? LPS22HH_25_Hz
gpmbed 0:b74c7741e608 405 : (Odr <= 50.0f) ? LPS22HH_50_Hz
gpmbed 0:b74c7741e608 406 : (Odr <= 75.0f) ? LPS22HH_75_Hz
gpmbed 0:b74c7741e608 407 : (Odr <= 100.0f) ? LPS22HH_100_Hz
gpmbed 0:b74c7741e608 408 : LPS22HH_200_Hz;
gpmbed 0:b74c7741e608 409
gpmbed 0:b74c7741e608 410 if (lps22hh_data_rate_set(&reg_ctx, new_odr) != LPS22HH_OK)
gpmbed 0:b74c7741e608 411 {
gpmbed 0:b74c7741e608 412 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 413 }
gpmbed 0:b74c7741e608 414
gpmbed 0:b74c7741e608 415 if (lps22hh_data_rate_get(&reg_ctx, &last_odr) != LPS22HH_OK)
gpmbed 0:b74c7741e608 416 {
gpmbed 0:b74c7741e608 417 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 418 }
gpmbed 0:b74c7741e608 419
gpmbed 0:b74c7741e608 420 return LPS22HH_OK;
gpmbed 0:b74c7741e608 421 }
gpmbed 0:b74c7741e608 422
gpmbed 0:b74c7741e608 423 /**
gpmbed 0:b74c7741e608 424 * @brief Set output data rate when disabled
gpmbed 0:b74c7741e608 425 * @param Odr the output data rate value to be set
gpmbed 0:b74c7741e608 426 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 427 */
gpmbed 0:b74c7741e608 428 LPS22HHStatusTypeDef LPS22HH::SetOutputDataRate_When_Disabled(float Odr)
gpmbed 0:b74c7741e608 429 {
gpmbed 0:b74c7741e608 430 last_odr = (Odr <= 1.0f) ? LPS22HH_1_Hz
gpmbed 0:b74c7741e608 431 : (Odr <= 10.0f) ? LPS22HH_10_Hz
gpmbed 0:b74c7741e608 432 : (Odr <= 25.0f) ? LPS22HH_25_Hz
gpmbed 0:b74c7741e608 433 : (Odr <= 50.0f) ? LPS22HH_50_Hz
gpmbed 0:b74c7741e608 434 : (Odr <= 75.0f) ? LPS22HH_75_Hz
gpmbed 0:b74c7741e608 435 : (Odr <= 100.0f) ? LPS22HH_100_Hz
gpmbed 0:b74c7741e608 436 : LPS22HH_200_Hz;
gpmbed 0:b74c7741e608 437
gpmbed 0:b74c7741e608 438 return LPS22HH_OK;
gpmbed 0:b74c7741e608 439 }
gpmbed 0:b74c7741e608 440
gpmbed 0:b74c7741e608 441 /**
gpmbed 0:b74c7741e608 442 * @brief Get the LPS22HH pressure value
gpmbed 0:b74c7741e608 443 * @param Value pointer where the pressure value is written
gpmbed 0:b74c7741e608 444 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 445 */
gpmbed 0:b74c7741e608 446 ////LPS22HHStatusTypeDef LPS22HH::GetPressure(float *Value)
gpmbed 0:b74c7741e608 447 float LPS22HH::GetPressure()
gpmbed 0:b74c7741e608 448 {
gpmbed 0:b74c7741e608 449 axis1bit32_t data_raw_pressure;
gpmbed 0:b74c7741e608 450
gpmbed 0:b74c7741e608 451 (void)memset(data_raw_pressure.u8bit, 0x00, sizeof(int32_t));
gpmbed 0:b74c7741e608 452 if (lps22hh_pressure_raw_get(&reg_ctx, data_raw_pressure.u8bit) != LPS22HH_OK)
gpmbed 0:b74c7741e608 453 {
gpmbed 0:b74c7741e608 454 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 455 }
gpmbed 0:b74c7741e608 456
gpmbed 0:b74c7741e608 457 ////*Value = LPS22HH_FROM_LSB_TO_hPa((float)(data_raw_pressure.i32bit));
gpmbed 0:b74c7741e608 458 return LPS22HH_FROM_LSB_TO_hPa((float)(data_raw_pressure.i32bit));
gpmbed 0:b74c7741e608 459
gpmbed 0:b74c7741e608 460 ////return LPS22HH_OK;
gpmbed 0:b74c7741e608 461 }
gpmbed 0:b74c7741e608 462
gpmbed 0:b74c7741e608 463 /**
gpmbed 0:b74c7741e608 464 * @brief Get the LPS22HH pressure data ready bit value
gpmbed 0:b74c7741e608 465 * @param Status the status of data ready bit
gpmbed 0:b74c7741e608 466 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 467 */
gpmbed 0:b74c7741e608 468 LPS22HHStatusTypeDef LPS22HH::Get_PRESS_DRDY_Status(uint8_t *Status)
gpmbed 0:b74c7741e608 469 {
gpmbed 0:b74c7741e608 470 if (lps22hh_press_flag_data_ready_get(&reg_ctx, Status) != LPS22HH_OK)
gpmbed 0:b74c7741e608 471 {
gpmbed 0:b74c7741e608 472 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 473 }
gpmbed 0:b74c7741e608 474
gpmbed 0:b74c7741e608 475 return LPS22HH_OK;
gpmbed 0:b74c7741e608 476 }
gpmbed 0:b74c7741e608 477
gpmbed 0:b74c7741e608 478 /**
gpmbed 0:b74c7741e608 479 * @brief Get the LPS22HH temperature value
gpmbed 0:b74c7741e608 480 * @param Value pointer where the temperature value is written
gpmbed 0:b74c7741e608 481 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 482 */
gpmbed 0:b74c7741e608 483 LPS22HHStatusTypeDef LPS22HH::GetTemperature(float *Value)
gpmbed 0:b74c7741e608 484 {
gpmbed 0:b74c7741e608 485 axis1bit16_t data_raw_temperature;
gpmbed 0:b74c7741e608 486
gpmbed 0:b74c7741e608 487 (void)memset(data_raw_temperature.u8bit, 0x00, sizeof(int16_t));
gpmbed 0:b74c7741e608 488 if (lps22hh_temperature_raw_get(&reg_ctx, data_raw_temperature.u8bit) != LPS22HH_OK)
gpmbed 0:b74c7741e608 489 {
gpmbed 0:b74c7741e608 490 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 491 }
gpmbed 0:b74c7741e608 492
gpmbed 0:b74c7741e608 493 *Value = LPS22HH_FROM_LSB_TO_degC((float)(data_raw_temperature.i16bit));
gpmbed 0:b74c7741e608 494
gpmbed 0:b74c7741e608 495 return LPS22HH_OK;
gpmbed 0:b74c7741e608 496 }
gpmbed 0:b74c7741e608 497
gpmbed 0:b74c7741e608 498 /**
gpmbed 0:b74c7741e608 499 * @brief Get the LPS22HH temperature data ready bit value
gpmbed 0:b74c7741e608 500 * @param Status the status of data ready bit
gpmbed 0:b74c7741e608 501 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 502 */
gpmbed 0:b74c7741e608 503 LPS22HHStatusTypeDef LPS22HH::Get_TEMP_DRDY_Status(uint8_t *Status)
gpmbed 0:b74c7741e608 504 {
gpmbed 0:b74c7741e608 505 if (lps22hh_temp_flag_data_ready_get(&reg_ctx, Status) != LPS22HH_OK)
gpmbed 0:b74c7741e608 506 {
gpmbed 0:b74c7741e608 507 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 508 }
gpmbed 0:b74c7741e608 509
gpmbed 0:b74c7741e608 510 return LPS22HH_OK;
gpmbed 0:b74c7741e608 511 }
gpmbed 0:b74c7741e608 512
gpmbed 0:b74c7741e608 513 /**
gpmbed 0:b74c7741e608 514 * @brief Get the LPS22HH register value
gpmbed 0:b74c7741e608 515 * @param Reg address to be written
gpmbed 0:b74c7741e608 516 * @param Data value to be written
gpmbed 0:b74c7741e608 517 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 518 */
gpmbed 0:b74c7741e608 519 LPS22HHStatusTypeDef LPS22HH::Read_Reg(uint8_t Reg, uint8_t *Data)
gpmbed 0:b74c7741e608 520 {
gpmbed 0:b74c7741e608 521 if (lps22hh_read_reg(&reg_ctx, Reg, Data, 1) != LPS22HH_OK)
gpmbed 0:b74c7741e608 522 {
gpmbed 0:b74c7741e608 523 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 524 }
gpmbed 0:b74c7741e608 525
gpmbed 0:b74c7741e608 526 return LPS22HH_OK;
gpmbed 0:b74c7741e608 527 }
gpmbed 0:b74c7741e608 528
gpmbed 0:b74c7741e608 529 /**
gpmbed 0:b74c7741e608 530 * @brief Set the LPS22HH register value
gpmbed 0:b74c7741e608 531 * @param pObj the device pObj
gpmbed 0:b74c7741e608 532 * @param Reg address to be written
gpmbed 0:b74c7741e608 533 * @param Data value to be written
gpmbed 0:b74c7741e608 534 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 535 */
gpmbed 0:b74c7741e608 536 LPS22HHStatusTypeDef LPS22HH::Write_Reg(uint8_t Reg, uint8_t Data)
gpmbed 0:b74c7741e608 537 {
gpmbed 0:b74c7741e608 538 if (lps22hh_write_reg(&reg_ctx, Reg, &Data, 1) != LPS22HH_OK)
gpmbed 0:b74c7741e608 539 {
gpmbed 0:b74c7741e608 540 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 541 }
gpmbed 0:b74c7741e608 542
gpmbed 0:b74c7741e608 543 return LPS22HH_OK;
gpmbed 0:b74c7741e608 544 }
gpmbed 0:b74c7741e608 545
gpmbed 0:b74c7741e608 546 /**
gpmbed 0:b74c7741e608 547 * @brief Get the LPS22HH FIFO data level
gpmbed 0:b74c7741e608 548 * @param Status the status of data ready bit
gpmbed 0:b74c7741e608 549 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 550 */
gpmbed 0:b74c7741e608 551 LPS22HHStatusTypeDef LPS22HH::Get_FIFO_Data(float *Press, float *Temp)
gpmbed 0:b74c7741e608 552 {
gpmbed 0:b74c7741e608 553 axis1bit32_t data_raw_pressure;
gpmbed 0:b74c7741e608 554 axis1bit16_t data_raw_temperature;
gpmbed 0:b74c7741e608 555
gpmbed 0:b74c7741e608 556 (void)memset(data_raw_pressure.u8bit, 0x00, sizeof(int32_t));
gpmbed 0:b74c7741e608 557 if (lps22hh_fifo_pressure_raw_get(&reg_ctx, data_raw_pressure.u8bit) != LPS22HH_OK)
gpmbed 0:b74c7741e608 558 {
gpmbed 0:b74c7741e608 559 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 560 }
gpmbed 0:b74c7741e608 561
gpmbed 0:b74c7741e608 562 *Press = LPS22HH_FROM_LSB_TO_hPa((float)(data_raw_pressure.i32bit));
gpmbed 0:b74c7741e608 563
gpmbed 0:b74c7741e608 564 (void)memset(data_raw_temperature.u8bit, 0x00, sizeof(int16_t));
gpmbed 0:b74c7741e608 565 if (lps22hh_fifo_temperature_raw_get(&reg_ctx, data_raw_temperature.u8bit) != LPS22HH_OK)
gpmbed 0:b74c7741e608 566 {
gpmbed 0:b74c7741e608 567 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 568 }
gpmbed 0:b74c7741e608 569
gpmbed 0:b74c7741e608 570 *Temp = LPS22HH_FROM_LSB_TO_degC((float)(data_raw_temperature.i16bit));
gpmbed 0:b74c7741e608 571
gpmbed 0:b74c7741e608 572 return LPS22HH_OK;
gpmbed 0:b74c7741e608 573 }
gpmbed 0:b74c7741e608 574
gpmbed 0:b74c7741e608 575 /**
gpmbed 0:b74c7741e608 576 * @brief Get the LPS22HH FIFO threshold
gpmbed 0:b74c7741e608 577 * @param Status the status of data ready bit
gpmbed 0:b74c7741e608 578 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 579 */
gpmbed 0:b74c7741e608 580 LPS22HHStatusTypeDef LPS22HH::Get_FIFO_FTh_Status(uint8_t *Status)
gpmbed 0:b74c7741e608 581 {
gpmbed 0:b74c7741e608 582 if (lps22hh_fifo_wtm_flag_get(&reg_ctx, Status) != LPS22HH_OK)
gpmbed 0:b74c7741e608 583 {
gpmbed 0:b74c7741e608 584 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 585 }
gpmbed 0:b74c7741e608 586
gpmbed 0:b74c7741e608 587 return LPS22HH_OK;
gpmbed 0:b74c7741e608 588 }
gpmbed 0:b74c7741e608 589
gpmbed 0:b74c7741e608 590 /**
gpmbed 0:b74c7741e608 591 * @brief Get the LPS22HH FIFO full status
gpmbed 0:b74c7741e608 592 * @param Status the status of data ready bit
gpmbed 0:b74c7741e608 593 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 594 */
gpmbed 0:b74c7741e608 595 LPS22HHStatusTypeDef LPS22HH::Get_FIFO_Full_Status(uint8_t *Status)
gpmbed 0:b74c7741e608 596 {
gpmbed 0:b74c7741e608 597 if (lps22hh_fifo_full_flag_get(&reg_ctx, Status) != LPS22HH_OK)
gpmbed 0:b74c7741e608 598 {
gpmbed 0:b74c7741e608 599 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 600 }
gpmbed 0:b74c7741e608 601
gpmbed 0:b74c7741e608 602 return LPS22HH_OK;
gpmbed 0:b74c7741e608 603 }
gpmbed 0:b74c7741e608 604
gpmbed 0:b74c7741e608 605 /**
gpmbed 0:b74c7741e608 606 * @brief Get the LPS22HH FIFO OVR status
gpmbed 0:b74c7741e608 607 * @param Status the status of data ready bit
gpmbed 0:b74c7741e608 608 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 609 */
gpmbed 0:b74c7741e608 610 LPS22HHStatusTypeDef LPS22HH::Get_FIFO_Ovr_Status(uint8_t *Status)
gpmbed 0:b74c7741e608 611 {
gpmbed 0:b74c7741e608 612 if (lps22hh_fifo_ovr_flag_get(&reg_ctx, Status) != LPS22HH_OK)
gpmbed 0:b74c7741e608 613 {
gpmbed 0:b74c7741e608 614 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 615 }
gpmbed 0:b74c7741e608 616
gpmbed 0:b74c7741e608 617 return LPS22HH_OK;
gpmbed 0:b74c7741e608 618 }
gpmbed 0:b74c7741e608 619
gpmbed 0:b74c7741e608 620 /**
gpmbed 0:b74c7741e608 621 * @brief Get the LPS22HH FIFO data level
gpmbed 0:b74c7741e608 622 * @param Status the status of data ready bit
gpmbed 0:b74c7741e608 623 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 624 */
gpmbed 0:b74c7741e608 625 LPS22HHStatusTypeDef LPS22HH::Get_FIFO_Level(uint8_t *Status)
gpmbed 0:b74c7741e608 626 {
gpmbed 0:b74c7741e608 627 if (lps22hh_fifo_data_level_get(&reg_ctx, Status) != LPS22HH_OK)
gpmbed 0:b74c7741e608 628 {
gpmbed 0:b74c7741e608 629 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 630 }
gpmbed 0:b74c7741e608 631
gpmbed 0:b74c7741e608 632 return LPS22HH_OK;
gpmbed 0:b74c7741e608 633 }
gpmbed 0:b74c7741e608 634
gpmbed 0:b74c7741e608 635 /**
gpmbed 0:b74c7741e608 636 * @brief Reset the FIFO interrupt
gpmbed 0:b74c7741e608 637 * @param interrupt The FIFO interrupt to be reset; values: 0 = FTH; 1 = FULL; 2 = OVR
gpmbed 0:b74c7741e608 638 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 639 */
gpmbed 0:b74c7741e608 640 LPS22HHStatusTypeDef LPS22HH::Reset_FIFO_Interrupt(uint8_t interrupt)
gpmbed 0:b74c7741e608 641 {
gpmbed 0:b74c7741e608 642 switch (interrupt)
gpmbed 0:b74c7741e608 643 {
gpmbed 0:b74c7741e608 644 case 0:
gpmbed 0:b74c7741e608 645 if (lps22hh_fifo_threshold_on_int_set(&reg_ctx, PROPERTY_DISABLE) != LPS22HH_OK)
gpmbed 0:b74c7741e608 646 {
gpmbed 0:b74c7741e608 647 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 648 }
gpmbed 0:b74c7741e608 649 break;
gpmbed 0:b74c7741e608 650 case 1:
gpmbed 0:b74c7741e608 651 if (lps22hh_fifo_full_on_int_set(&reg_ctx, PROPERTY_DISABLE) != LPS22HH_OK)
gpmbed 0:b74c7741e608 652 {
gpmbed 0:b74c7741e608 653 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 654 }
gpmbed 0:b74c7741e608 655 break;
gpmbed 0:b74c7741e608 656 case 2:
gpmbed 0:b74c7741e608 657 if (lps22hh_fifo_ovr_on_int_set(&reg_ctx, PROPERTY_DISABLE) != LPS22HH_OK)
gpmbed 0:b74c7741e608 658 {
gpmbed 0:b74c7741e608 659 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 660 }
gpmbed 0:b74c7741e608 661 break;
gpmbed 0:b74c7741e608 662 default:
gpmbed 0:b74c7741e608 663 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 664 }
gpmbed 0:b74c7741e608 665
gpmbed 0:b74c7741e608 666 return LPS22HH_OK;
gpmbed 0:b74c7741e608 667 }
gpmbed 0:b74c7741e608 668
gpmbed 0:b74c7741e608 669 /**
gpmbed 0:b74c7741e608 670 * @brief Set the FIFO interrupt
gpmbed 0:b74c7741e608 671 * @param interrupt The FIFO interrupt to be reset; values: 0 = FTH; 1 = FULL; 2 = OVR
gpmbed 0:b74c7741e608 672 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 673 */
gpmbed 0:b74c7741e608 674 LPS22HHStatusTypeDef LPS22HH::Set_FIFO_Interrupt(uint8_t interrupt)
gpmbed 0:b74c7741e608 675 {
gpmbed 0:b74c7741e608 676 switch (interrupt)
gpmbed 0:b74c7741e608 677 {
gpmbed 0:b74c7741e608 678 case 0:
gpmbed 0:b74c7741e608 679 if (lps22hh_fifo_threshold_on_int_set(&reg_ctx, PROPERTY_ENABLE) != LPS22HH_OK)
gpmbed 0:b74c7741e608 680 {
gpmbed 0:b74c7741e608 681 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 682 }
gpmbed 0:b74c7741e608 683 break;
gpmbed 0:b74c7741e608 684 case 1:
gpmbed 0:b74c7741e608 685 if (lps22hh_fifo_full_on_int_set(&reg_ctx, PROPERTY_ENABLE) != LPS22HH_OK)
gpmbed 0:b74c7741e608 686 {
gpmbed 0:b74c7741e608 687 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 688 }
gpmbed 0:b74c7741e608 689 break;
gpmbed 0:b74c7741e608 690 case 2:
gpmbed 0:b74c7741e608 691 if (lps22hh_fifo_ovr_on_int_set(&reg_ctx, PROPERTY_ENABLE) != LPS22HH_OK)
gpmbed 0:b74c7741e608 692 {
gpmbed 0:b74c7741e608 693 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 694 }
gpmbed 0:b74c7741e608 695 break;
gpmbed 0:b74c7741e608 696 default:
gpmbed 0:b74c7741e608 697 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 698 }
gpmbed 0:b74c7741e608 699
gpmbed 0:b74c7741e608 700 return LPS22HH_OK;
gpmbed 0:b74c7741e608 701 }
gpmbed 0:b74c7741e608 702
gpmbed 0:b74c7741e608 703 /**
gpmbed 0:b74c7741e608 704 * @brief Set the FIFO mode
gpmbed 0:b74c7741e608 705 * @param Mode the FIFO mode to be set
gpmbed 0:b74c7741e608 706 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 707 */
gpmbed 0:b74c7741e608 708 LPS22HHStatusTypeDef LPS22HH::Set_FIFO_Mode(uint8_t Mode)
gpmbed 0:b74c7741e608 709 {
gpmbed 0:b74c7741e608 710 /* Verify that the passed parameter contains one of the valid values */
gpmbed 0:b74c7741e608 711 switch ((lps22hh_f_mode_t)Mode)
gpmbed 0:b74c7741e608 712 {
gpmbed 0:b74c7741e608 713 case LPS22HH_BYPASS_MODE:
gpmbed 0:b74c7741e608 714 case LPS22HH_FIFO_MODE:
gpmbed 0:b74c7741e608 715 case LPS22HH_STREAM_MODE:
gpmbed 0:b74c7741e608 716 case LPS22HH_STREAM_TO_FIFO_MODE:
gpmbed 0:b74c7741e608 717 case LPS22HH_BYPASS_TO_STREAM_MODE:
gpmbed 0:b74c7741e608 718 case LPS22HH_BYPASS_TO_FIFO_MODE:
gpmbed 0:b74c7741e608 719 break;
gpmbed 0:b74c7741e608 720 default:
gpmbed 0:b74c7741e608 721 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 722 }
gpmbed 0:b74c7741e608 723
gpmbed 0:b74c7741e608 724 if (lps22hh_fifo_mode_set(&reg_ctx, (lps22hh_f_mode_t)Mode) != LPS22HH_OK)
gpmbed 0:b74c7741e608 725 {
gpmbed 0:b74c7741e608 726 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 727 }
gpmbed 0:b74c7741e608 728
gpmbed 0:b74c7741e608 729 return LPS22HH_OK;
gpmbed 0:b74c7741e608 730 }
gpmbed 0:b74c7741e608 731
gpmbed 0:b74c7741e608 732 /**
gpmbed 0:b74c7741e608 733 * @brief Set the LPS22HH FIFO data level
gpmbed 0:b74c7741e608 734 * @param Status the status of data ready bit
gpmbed 0:b74c7741e608 735 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 736 */
gpmbed 0:b74c7741e608 737 LPS22HHStatusTypeDef LPS22HH::Set_FIFO_Watermark_Level(uint8_t Watermark)
gpmbed 0:b74c7741e608 738 {
gpmbed 0:b74c7741e608 739 if (lps22hh_fifo_watermark_set(&reg_ctx, Watermark) != LPS22HH_OK)
gpmbed 0:b74c7741e608 740 {
gpmbed 0:b74c7741e608 741 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 742 }
gpmbed 0:b74c7741e608 743
gpmbed 0:b74c7741e608 744 return LPS22HH_OK;
gpmbed 0:b74c7741e608 745 }
gpmbed 0:b74c7741e608 746
gpmbed 0:b74c7741e608 747 /**
gpmbed 0:b74c7741e608 748 * @brief Set the LPS22HH stop on watermark function
gpmbed 0:b74c7741e608 749 * @param Stop the state of stop on watermark function
gpmbed 0:b74c7741e608 750 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 751 */
gpmbed 0:b74c7741e608 752 LPS22HHStatusTypeDef LPS22HH::Stop_FIFO_On_Watermark(uint8_t Stop)
gpmbed 0:b74c7741e608 753 {
gpmbed 0:b74c7741e608 754 if (lps22hh_fifo_stop_on_wtm_set(&reg_ctx, Stop) != LPS22HH_OK)
gpmbed 0:b74c7741e608 755 {
gpmbed 0:b74c7741e608 756 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 757 }
gpmbed 0:b74c7741e608 758
gpmbed 0:b74c7741e608 759 return LPS22HH_OK;
gpmbed 0:b74c7741e608 760 }
gpmbed 0:b74c7741e608 761
gpmbed 0:b74c7741e608 762 /**
gpmbed 0:b74c7741e608 763 * @brief Set the LPS22HH One Shot Mode
gpmbed 0:b74c7741e608 764 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 765 */
gpmbed 0:b74c7741e608 766 LPS22HHStatusTypeDef LPS22HH::Set_One_Shot()
gpmbed 0:b74c7741e608 767 {
gpmbed 0:b74c7741e608 768 /* Start One Shot Measurement */
gpmbed 0:b74c7741e608 769 if(lps22hh_data_rate_set(&reg_ctx, LPS22HH_ONE_SHOOT) != LPS22HH_OK)
gpmbed 0:b74c7741e608 770 {
gpmbed 0:b74c7741e608 771 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 772 }
gpmbed 0:b74c7741e608 773
gpmbed 0:b74c7741e608 774 return LPS22HH_OK;
gpmbed 0:b74c7741e608 775 }
gpmbed 0:b74c7741e608 776
gpmbed 0:b74c7741e608 777 /**
gpmbed 0:b74c7741e608 778 * @brief Get the LPS22HH One Shot Status
gpmbed 0:b74c7741e608 779 * @param Status pointer to the one shot status (1 means measurements available, 0 means measurements not available yet)
gpmbed 0:b74c7741e608 780 * @retval 0 in case of success, an error code otherwise
gpmbed 0:b74c7741e608 781 */
gpmbed 0:b74c7741e608 782 LPS22HHStatusTypeDef LPS22HH::Get_One_Shot_Status(uint8_t *Status)
gpmbed 0:b74c7741e608 783 {
gpmbed 0:b74c7741e608 784 uint8_t p_da;
gpmbed 0:b74c7741e608 785 uint8_t t_da;
gpmbed 0:b74c7741e608 786
gpmbed 0:b74c7741e608 787 /* Get DataReady for pressure */
gpmbed 0:b74c7741e608 788 if(lps22hh_press_flag_data_ready_get(&reg_ctx, &p_da) != LPS22HH_OK)
gpmbed 0:b74c7741e608 789 {
gpmbed 0:b74c7741e608 790 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 791 }
gpmbed 0:b74c7741e608 792
gpmbed 0:b74c7741e608 793 /* Get DataReady for temperature */
gpmbed 0:b74c7741e608 794 if(lps22hh_temp_flag_data_ready_get(&reg_ctx, &t_da) != LPS22HH_OK)
gpmbed 0:b74c7741e608 795 {
gpmbed 0:b74c7741e608 796 return LPS22HH_ERROR;
gpmbed 0:b74c7741e608 797 }
gpmbed 0:b74c7741e608 798
gpmbed 0:b74c7741e608 799 if(p_da && t_da)
gpmbed 0:b74c7741e608 800 {
gpmbed 0:b74c7741e608 801 *Status = 1;
gpmbed 0:b74c7741e608 802 }
gpmbed 0:b74c7741e608 803 else
gpmbed 0:b74c7741e608 804 {
gpmbed 0:b74c7741e608 805 *Status = 0;
gpmbed 0:b74c7741e608 806 }
gpmbed 0:b74c7741e608 807
gpmbed 0:b74c7741e608 808 return LPS22HH_OK;
gpmbed 0:b74c7741e608 809 }
gpmbed 0:b74c7741e608 810
gpmbed 0:b74c7741e608 811 int32_t LPS22HH_io_write(void *handle, uint8_t WriteAddr, uint8_t *pBuffer, uint16_t nBytesToWrite)
gpmbed 0:b74c7741e608 812 {
gpmbed 0:b74c7741e608 813 return ((LPS22HH *)handle)->IO_Write(pBuffer, WriteAddr, nBytesToWrite);
gpmbed 0:b74c7741e608 814 }
gpmbed 0:b74c7741e608 815
gpmbed 0:b74c7741e608 816 int32_t LPS22HH_io_read(void *handle, uint8_t ReadAddr, uint8_t *pBuffer, uint16_t nBytesToRead)
gpmbed 0:b74c7741e608 817 {
gpmbed 0:b74c7741e608 818 return ((LPS22HH *)handle)->IO_Read(pBuffer, ReadAddr, nBytesToRead);
gpmbed 0:b74c7741e608 819 }
gpmbed 0:b74c7741e608 820
gpmbed 0:b74c7741e608 821 // *********************************** *****************************************
gpmbed 0:b74c7741e608 822
gpmbed 0:b74c7741e608 823
gpmbed 0:b74c7741e608 824
gpmbed 0:b74c7741e608 825 /**
gpmbed 0:b74c7741e608 826 * @brief Read generic device register
gpmbed 0:b74c7741e608 827 *
gpmbed 0:b74c7741e608 828 * @param ctx read / write interface definitions(ptr)
gpmbed 0:b74c7741e608 829 * @param reg register to read
gpmbed 0:b74c7741e608 830 * @param data pointer to buffer that store the data read(ptr)
gpmbed 0:b74c7741e608 831 * @param len number of consecutive register to read
gpmbed 0:b74c7741e608 832 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 833 *
gpmbed 0:b74c7741e608 834 */
gpmbed 0:b74c7741e608 835 int32_t lps22hh_read_reg(lps22hh_ctx_t* ctx, uint8_t reg, uint8_t* data, uint16_t len)
gpmbed 0:b74c7741e608 836 {
gpmbed 0:b74c7741e608 837 int32_t ret;
gpmbed 0:b74c7741e608 838 ret = ctx->read_reg(ctx->handle, reg, data, len);
gpmbed 0:b74c7741e608 839 return ret;
gpmbed 0:b74c7741e608 840 }
gpmbed 0:b74c7741e608 841
gpmbed 0:b74c7741e608 842 /**
gpmbed 0:b74c7741e608 843 * @brief Write generic device register
gpmbed 0:b74c7741e608 844 *
gpmbed 0:b74c7741e608 845 * @param ctx read / write interface definitions(ptr)
gpmbed 0:b74c7741e608 846 * @param reg register to write
gpmbed 0:b74c7741e608 847 * @param data pointer to data to write in register reg(ptr)
gpmbed 0:b74c7741e608 848 * @param len number of consecutive register to write
gpmbed 0:b74c7741e608 849 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 850 *
gpmbed 0:b74c7741e608 851 */
gpmbed 0:b74c7741e608 852 int32_t lps22hh_write_reg(lps22hh_ctx_t* ctx, uint8_t reg, uint8_t* data, uint16_t len)
gpmbed 0:b74c7741e608 853 {
gpmbed 0:b74c7741e608 854 int32_t ret;
gpmbed 0:b74c7741e608 855 ret = ctx->write_reg(ctx->handle, reg, data, len);
gpmbed 0:b74c7741e608 856 return ret;
gpmbed 0:b74c7741e608 857 }
gpmbed 0:b74c7741e608 858
gpmbed 0:b74c7741e608 859 // ************ *************** ************** ************ ************
gpmbed 0:b74c7741e608 860 // ************ *************** ************** ************ ************
gpmbed 0:b74c7741e608 861 // ************ *************** ************** ************ ************
gpmbed 0:b74c7741e608 862
gpmbed 0:b74c7741e608 863 int32_t lps22hh_data_rate_set(lps22hh_ctx_t *ctx, lps22hh_odr_t val)
gpmbed 0:b74c7741e608 864 {
gpmbed 0:b74c7741e608 865 lps22hh_ctrl_reg1_t ctrl_reg1;
gpmbed 0:b74c7741e608 866 lps22hh_ctrl_reg2_t ctrl_reg2;
gpmbed 0:b74c7741e608 867 int32_t ret;
gpmbed 0:b74c7741e608 868
gpmbed 0:b74c7741e608 869 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
gpmbed 0:b74c7741e608 870 if (ret == 0) {
gpmbed 0:b74c7741e608 871 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
gpmbed 0:b74c7741e608 872 }
gpmbed 0:b74c7741e608 873 if (ret == 0) {
gpmbed 0:b74c7741e608 874 ctrl_reg1.odr = (uint8_t)val & 0x07U;
gpmbed 0:b74c7741e608 875 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
gpmbed 0:b74c7741e608 876 }
gpmbed 0:b74c7741e608 877 if (ret == 0) {
gpmbed 0:b74c7741e608 878 ctrl_reg2.low_noise_en = ((uint8_t)val & 0x10U) >> 4;
gpmbed 0:b74c7741e608 879 ctrl_reg2.one_shot = ((uint8_t)val & 0x08U) >> 3;
gpmbed 0:b74c7741e608 880 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
gpmbed 0:b74c7741e608 881 }
gpmbed 0:b74c7741e608 882 return ret;
gpmbed 0:b74c7741e608 883 }
gpmbed 0:b74c7741e608 884
gpmbed 0:b74c7741e608 885 /**
gpmbed 0:b74c7741e608 886 * @brief Low-pass bandwidth selection.[set]
gpmbed 0:b74c7741e608 887 *
gpmbed 0:b74c7741e608 888 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 889 * @param val change the values of lpfp_cfg in reg CTRL_REG1
gpmbed 0:b74c7741e608 890 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 891 *
gpmbed 0:b74c7741e608 892 */
gpmbed 0:b74c7741e608 893 int32_t lps22hh_lp_bandwidth_set(lps22hh_ctx_t *ctx, lps22hh_lpfp_cfg_t val)
gpmbed 0:b74c7741e608 894 {
gpmbed 0:b74c7741e608 895 lps22hh_ctrl_reg1_t reg;
gpmbed 0:b74c7741e608 896 int32_t ret;
gpmbed 0:b74c7741e608 897
gpmbed 0:b74c7741e608 898 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 899 if (ret == 0) {
gpmbed 0:b74c7741e608 900 reg.lpfp_cfg = (uint8_t)val;
gpmbed 0:b74c7741e608 901 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 902 }
gpmbed 0:b74c7741e608 903 return ret;
gpmbed 0:b74c7741e608 904 }
gpmbed 0:b74c7741e608 905
gpmbed 0:b74c7741e608 906 /**
gpmbed 0:b74c7741e608 907 * @brief Low-pass bandwidth selection.[get]
gpmbed 0:b74c7741e608 908 *
gpmbed 0:b74c7741e608 909 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 910 * @param val Get the values of lpfp_cfg in reg CTRL_REG1
gpmbed 0:b74c7741e608 911 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 912 *
gpmbed 0:b74c7741e608 913 */
gpmbed 0:b74c7741e608 914 int32_t lps22hh_lp_bandwidth_get(lps22hh_ctx_t *ctx, lps22hh_lpfp_cfg_t *val)
gpmbed 0:b74c7741e608 915 {
gpmbed 0:b74c7741e608 916 lps22hh_ctrl_reg1_t reg;
gpmbed 0:b74c7741e608 917 int32_t ret;
gpmbed 0:b74c7741e608 918
gpmbed 0:b74c7741e608 919 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 920 switch (reg.lpfp_cfg) {
gpmbed 0:b74c7741e608 921 case LPS22HH_LPF_ODR_DIV_2:
gpmbed 0:b74c7741e608 922 *val = LPS22HH_LPF_ODR_DIV_2;
gpmbed 0:b74c7741e608 923 break;
gpmbed 0:b74c7741e608 924 case LPS22HH_LPF_ODR_DIV_9:
gpmbed 0:b74c7741e608 925 *val = LPS22HH_LPF_ODR_DIV_9;
gpmbed 0:b74c7741e608 926 break;
gpmbed 0:b74c7741e608 927 case LPS22HH_LPF_ODR_DIV_20:
gpmbed 0:b74c7741e608 928 *val = LPS22HH_LPF_ODR_DIV_20;
gpmbed 0:b74c7741e608 929 break;
gpmbed 0:b74c7741e608 930 default:
gpmbed 0:b74c7741e608 931 *val = LPS22HH_LPF_ODR_DIV_2;
gpmbed 0:b74c7741e608 932 break;
gpmbed 0:b74c7741e608 933 }
gpmbed 0:b74c7741e608 934
gpmbed 0:b74c7741e608 935 return ret;
gpmbed 0:b74c7741e608 936 }
gpmbed 0:b74c7741e608 937
gpmbed 0:b74c7741e608 938 /**
gpmbed 0:b74c7741e608 939 * @brief Block Data Update.[set]
gpmbed 0:b74c7741e608 940 *
gpmbed 0:b74c7741e608 941 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 942 * @param val change the values of bdu in reg CTRL_REG1
gpmbed 0:b74c7741e608 943 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 944 *
gpmbed 0:b74c7741e608 945 */
gpmbed 0:b74c7741e608 946 int32_t lps22hh_block_data_update_set(lps22hh_ctx_t *ctx, uint8_t val)
gpmbed 0:b74c7741e608 947 {
gpmbed 0:b74c7741e608 948 lps22hh_ctrl_reg1_t reg;
gpmbed 0:b74c7741e608 949 int32_t ret;
gpmbed 0:b74c7741e608 950
gpmbed 0:b74c7741e608 951 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 952 if (ret == 0) {
gpmbed 0:b74c7741e608 953 reg.bdu = val;
gpmbed 0:b74c7741e608 954 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 955 }
gpmbed 0:b74c7741e608 956 return ret;
gpmbed 0:b74c7741e608 957 }
gpmbed 0:b74c7741e608 958
gpmbed 0:b74c7741e608 959 /**
gpmbed 0:b74c7741e608 960 * @brief Register address automatically
gpmbed 0:b74c7741e608 961 * incremented during a multiple byte access
gpmbed 0:b74c7741e608 962 * with a serial interface.[set]
gpmbed 0:b74c7741e608 963 *
gpmbed 0:b74c7741e608 964 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 965 * @param val change the values of if_add_inc in reg CTRL_REG2
gpmbed 0:b74c7741e608 966 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 967 *
gpmbed 0:b74c7741e608 968 */
gpmbed 0:b74c7741e608 969 int32_t lps22hh_auto_increment_set(lps22hh_ctx_t *ctx, uint8_t val)
gpmbed 0:b74c7741e608 970 {
gpmbed 0:b74c7741e608 971 lps22hh_ctrl_reg2_t reg;
gpmbed 0:b74c7741e608 972 int32_t ret;
gpmbed 0:b74c7741e608 973
gpmbed 0:b74c7741e608 974 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 975 if (ret == 0) {
gpmbed 0:b74c7741e608 976 reg.if_add_inc = val;
gpmbed 0:b74c7741e608 977 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 978 }
gpmbed 0:b74c7741e608 979 return ret;
gpmbed 0:b74c7741e608 980 }
gpmbed 0:b74c7741e608 981
gpmbed 0:b74c7741e608 982 /**
gpmbed 0:b74c7741e608 983 * @brief Output data rate selection.[get]
gpmbed 0:b74c7741e608 984 *
gpmbed 0:b74c7741e608 985 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 986 * @param val Get the values of odr in reg CTRL_REG1
gpmbed 0:b74c7741e608 987 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 988 *
gpmbed 0:b74c7741e608 989 */
gpmbed 0:b74c7741e608 990 int32_t lps22hh_data_rate_get(lps22hh_ctx_t *ctx, lps22hh_odr_t *val)
gpmbed 0:b74c7741e608 991 {
gpmbed 0:b74c7741e608 992 lps22hh_ctrl_reg1_t ctrl_reg1;
gpmbed 0:b74c7741e608 993 lps22hh_ctrl_reg2_t ctrl_reg2;
gpmbed 0:b74c7741e608 994 int32_t ret;
gpmbed 0:b74c7741e608 995
gpmbed 0:b74c7741e608 996 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG1, (uint8_t*)&ctrl_reg1, 1);
gpmbed 0:b74c7741e608 997 if (ret == 0) {
gpmbed 0:b74c7741e608 998 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
gpmbed 0:b74c7741e608 999 }
gpmbed 0:b74c7741e608 1000 if (ret == 0) {
gpmbed 0:b74c7741e608 1001 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG2, (uint8_t*)&ctrl_reg2, 1);
gpmbed 0:b74c7741e608 1002 switch (((ctrl_reg2.low_noise_en << 4) + (ctrl_reg2.one_shot << 3) +
gpmbed 0:b74c7741e608 1003 ctrl_reg1.odr )) {
gpmbed 0:b74c7741e608 1004 case LPS22HH_POWER_DOWN:
gpmbed 0:b74c7741e608 1005 *val = LPS22HH_POWER_DOWN;
gpmbed 0:b74c7741e608 1006 break;
gpmbed 0:b74c7741e608 1007 case LPS22HH_ONE_SHOOT:
gpmbed 0:b74c7741e608 1008 *val = LPS22HH_ONE_SHOOT;
gpmbed 0:b74c7741e608 1009 break;
gpmbed 0:b74c7741e608 1010 case LPS22HH_1_Hz:
gpmbed 0:b74c7741e608 1011 *val = LPS22HH_1_Hz;
gpmbed 0:b74c7741e608 1012 break;
gpmbed 0:b74c7741e608 1013 case LPS22HH_10_Hz:
gpmbed 0:b74c7741e608 1014 *val = LPS22HH_10_Hz;
gpmbed 0:b74c7741e608 1015 break;
gpmbed 0:b74c7741e608 1016 case LPS22HH_25_Hz:
gpmbed 0:b74c7741e608 1017 *val = LPS22HH_25_Hz;
gpmbed 0:b74c7741e608 1018 break;
gpmbed 0:b74c7741e608 1019 case LPS22HH_50_Hz:
gpmbed 0:b74c7741e608 1020 *val = LPS22HH_50_Hz;
gpmbed 0:b74c7741e608 1021 break;
gpmbed 0:b74c7741e608 1022 case LPS22HH_75_Hz:
gpmbed 0:b74c7741e608 1023 *val = LPS22HH_75_Hz;
gpmbed 0:b74c7741e608 1024 break;
gpmbed 0:b74c7741e608 1025 case LPS22HH_1_Hz_LOW_NOISE:
gpmbed 0:b74c7741e608 1026 *val = LPS22HH_1_Hz_LOW_NOISE;
gpmbed 0:b74c7741e608 1027 break;
gpmbed 0:b74c7741e608 1028 case LPS22HH_10_Hz_LOW_NOISE:
gpmbed 0:b74c7741e608 1029 *val = LPS22HH_10_Hz_LOW_NOISE;
gpmbed 0:b74c7741e608 1030 break;
gpmbed 0:b74c7741e608 1031 case LPS22HH_25_Hz_LOW_NOISE:
gpmbed 0:b74c7741e608 1032 *val = LPS22HH_25_Hz_LOW_NOISE;
gpmbed 0:b74c7741e608 1033 break;
gpmbed 0:b74c7741e608 1034 case LPS22HH_50_Hz_LOW_NOISE:
gpmbed 0:b74c7741e608 1035 *val = LPS22HH_50_Hz_LOW_NOISE;
gpmbed 0:b74c7741e608 1036 break;
gpmbed 0:b74c7741e608 1037 case LPS22HH_75_Hz_LOW_NOISE:
gpmbed 0:b74c7741e608 1038 *val = LPS22HH_75_Hz_LOW_NOISE;
gpmbed 0:b74c7741e608 1039 break;
gpmbed 0:b74c7741e608 1040 case LPS22HH_100_Hz:
gpmbed 0:b74c7741e608 1041 *val = LPS22HH_100_Hz;
gpmbed 0:b74c7741e608 1042 break;
gpmbed 0:b74c7741e608 1043 case LPS22HH_200_Hz:
gpmbed 0:b74c7741e608 1044 *val = LPS22HH_200_Hz;
gpmbed 0:b74c7741e608 1045 break;
gpmbed 0:b74c7741e608 1046 default:
gpmbed 0:b74c7741e608 1047 *val = LPS22HH_POWER_DOWN;
gpmbed 0:b74c7741e608 1048 break;
gpmbed 0:b74c7741e608 1049 }
gpmbed 0:b74c7741e608 1050 }
gpmbed 0:b74c7741e608 1051 return ret;
gpmbed 0:b74c7741e608 1052 }
gpmbed 0:b74c7741e608 1053
gpmbed 0:b74c7741e608 1054 /**
gpmbed 0:b74c7741e608 1055 * @brief Pressure output value.[get]
gpmbed 0:b74c7741e608 1056 *
gpmbed 0:b74c7741e608 1057 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 1058 * @param buff buffer that stores data read
gpmbed 0:b74c7741e608 1059 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 1060 *
gpmbed 0:b74c7741e608 1061 */
gpmbed 0:b74c7741e608 1062 int32_t lps22hh_pressure_raw_get(lps22hh_ctx_t *ctx, uint8_t *buff)
gpmbed 0:b74c7741e608 1063 {
gpmbed 0:b74c7741e608 1064 int32_t ret;
gpmbed 0:b74c7741e608 1065 ret = lps22hh_read_reg(ctx, LPS22HH_PRESSURE_OUT_XL, buff, 3);
gpmbed 0:b74c7741e608 1066 return ret;
gpmbed 0:b74c7741e608 1067 }
gpmbed 0:b74c7741e608 1068
gpmbed 0:b74c7741e608 1069 /**
gpmbed 0:b74c7741e608 1070 * @brief Temperature output value.[get]
gpmbed 0:b74c7741e608 1071 *
gpmbed 0:b74c7741e608 1072 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 1073 * @param buff buffer that stores data read
gpmbed 0:b74c7741e608 1074 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 1075 *
gpmbed 0:b74c7741e608 1076 */
gpmbed 0:b74c7741e608 1077 int32_t lps22hh_temperature_raw_get(lps22hh_ctx_t *ctx, uint8_t *buff)
gpmbed 0:b74c7741e608 1078 {
gpmbed 0:b74c7741e608 1079 int32_t ret;
gpmbed 0:b74c7741e608 1080 ret = lps22hh_read_reg(ctx, LPS22HH_TEMP_OUT_L, buff, 2);
gpmbed 0:b74c7741e608 1081 return ret;
gpmbed 0:b74c7741e608 1082 }
gpmbed 0:b74c7741e608 1083
gpmbed 0:b74c7741e608 1084 /**
gpmbed 0:b74c7741e608 1085 * @brief Pressure new data available.[get]
gpmbed 0:b74c7741e608 1086 *
gpmbed 0:b74c7741e608 1087 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 1088 * @param val change the values of p_da in reg STATUS
gpmbed 0:b74c7741e608 1089 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 1090 *
gpmbed 0:b74c7741e608 1091 */
gpmbed 0:b74c7741e608 1092 int32_t lps22hh_press_flag_data_ready_get(lps22hh_ctx_t *ctx, uint8_t *val)
gpmbed 0:b74c7741e608 1093 {
gpmbed 0:b74c7741e608 1094 lps22hh_status_t reg;
gpmbed 0:b74c7741e608 1095 int32_t ret;
gpmbed 0:b74c7741e608 1096
gpmbed 0:b74c7741e608 1097 ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 1098 *val = reg.p_da;
gpmbed 0:b74c7741e608 1099
gpmbed 0:b74c7741e608 1100 return ret;
gpmbed 0:b74c7741e608 1101 }
gpmbed 0:b74c7741e608 1102
gpmbed 0:b74c7741e608 1103 /**
gpmbed 0:b74c7741e608 1104 * @brief Temperature data available.[get]
gpmbed 0:b74c7741e608 1105 *
gpmbed 0:b74c7741e608 1106 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 1107 * @param val change the values of t_da in reg STATUS
gpmbed 0:b74c7741e608 1108 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 1109 *
gpmbed 0:b74c7741e608 1110 */
gpmbed 0:b74c7741e608 1111 int32_t lps22hh_temp_flag_data_ready_get(lps22hh_ctx_t *ctx, uint8_t *val)
gpmbed 0:b74c7741e608 1112 {
gpmbed 0:b74c7741e608 1113 lps22hh_status_t reg;
gpmbed 0:b74c7741e608 1114 int32_t ret;
gpmbed 0:b74c7741e608 1115
gpmbed 0:b74c7741e608 1116 ret = lps22hh_read_reg(ctx, LPS22HH_STATUS, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 1117 *val = reg.t_da;
gpmbed 0:b74c7741e608 1118
gpmbed 0:b74c7741e608 1119 return ret;
gpmbed 0:b74c7741e608 1120 }
gpmbed 0:b74c7741e608 1121
gpmbed 0:b74c7741e608 1122 /**
gpmbed 0:b74c7741e608 1123 * @brief Pressure output from FIFO value.[get]
gpmbed 0:b74c7741e608 1124 *
gpmbed 0:b74c7741e608 1125 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 1126 * @param buff buffer that stores data read
gpmbed 0:b74c7741e608 1127 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 1128 *
gpmbed 0:b74c7741e608 1129 */
gpmbed 0:b74c7741e608 1130 int32_t lps22hh_fifo_pressure_raw_get(lps22hh_ctx_t *ctx, uint8_t *buff)
gpmbed 0:b74c7741e608 1131 {
gpmbed 0:b74c7741e608 1132 int32_t ret;
gpmbed 0:b74c7741e608 1133 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_DATA_OUT_PRESS_XL, buff, 3);
gpmbed 0:b74c7741e608 1134 return ret;
gpmbed 0:b74c7741e608 1135 }
gpmbed 0:b74c7741e608 1136
gpmbed 0:b74c7741e608 1137 /**
gpmbed 0:b74c7741e608 1138 * @brief Temperature output from FIFO value.[get]
gpmbed 0:b74c7741e608 1139 *
gpmbed 0:b74c7741e608 1140 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 1141 * @param buff buffer that stores data read
gpmbed 0:b74c7741e608 1142 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 1143 *
gpmbed 0:b74c7741e608 1144 */
gpmbed 0:b74c7741e608 1145 int32_t lps22hh_fifo_temperature_raw_get(lps22hh_ctx_t *ctx, uint8_t *buff)
gpmbed 0:b74c7741e608 1146 {
gpmbed 0:b74c7741e608 1147 int32_t ret;
gpmbed 0:b74c7741e608 1148 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_DATA_OUT_TEMP_L, buff, 2);
gpmbed 0:b74c7741e608 1149 return ret;
gpmbed 0:b74c7741e608 1150 }
gpmbed 0:b74c7741e608 1151
gpmbed 0:b74c7741e608 1152 /**
gpmbed 0:b74c7741e608 1153 * @brief FIFO watermark status.[get]
gpmbed 0:b74c7741e608 1154 *
gpmbed 0:b74c7741e608 1155 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 1156 * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
gpmbed 0:b74c7741e608 1157 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 1158 *
gpmbed 0:b74c7741e608 1159 */
gpmbed 0:b74c7741e608 1160 int32_t lps22hh_fifo_wtm_flag_get(lps22hh_ctx_t *ctx, uint8_t *val)
gpmbed 0:b74c7741e608 1161 {
gpmbed 0:b74c7741e608 1162 lps22hh_fifo_status2_t reg;
gpmbed 0:b74c7741e608 1163 int32_t ret;
gpmbed 0:b74c7741e608 1164
gpmbed 0:b74c7741e608 1165 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 1166 *val = reg.fifo_wtm_ia;
gpmbed 0:b74c7741e608 1167
gpmbed 0:b74c7741e608 1168 return ret;
gpmbed 0:b74c7741e608 1169 }
gpmbed 0:b74c7741e608 1170
gpmbed 0:b74c7741e608 1171 /**
gpmbed 0:b74c7741e608 1172 * @brief Read all the FIFO status flag of the device.[get]
gpmbed 0:b74c7741e608 1173 *
gpmbed 0:b74c7741e608 1174 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 1175 * @param val registers FIFO_STATUS2
gpmbed 0:b74c7741e608 1176 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 1177 *
gpmbed 0:b74c7741e608 1178 */
gpmbed 0:b74c7741e608 1179 int32_t lps22hh_fifo_src_get(lps22hh_ctx_t *ctx, lps22hh_fifo_status2_t *val)
gpmbed 0:b74c7741e608 1180 {
gpmbed 0:b74c7741e608 1181 int32_t ret;
gpmbed 0:b74c7741e608 1182 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t*) val, 1);
gpmbed 0:b74c7741e608 1183 return ret;
gpmbed 0:b74c7741e608 1184 }
gpmbed 0:b74c7741e608 1185
gpmbed 0:b74c7741e608 1186 /**
gpmbed 0:b74c7741e608 1187 * @brief Smart FIFO full status.[get]
gpmbed 0:b74c7741e608 1188 *
gpmbed 0:b74c7741e608 1189 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 1190 * @param val change the values of fifo_full_ia in reg FIFO_STATUS2
gpmbed 0:b74c7741e608 1191 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 1192 *
gpmbed 0:b74c7741e608 1193 */
gpmbed 0:b74c7741e608 1194 int32_t lps22hh_fifo_full_flag_get(lps22hh_ctx_t *ctx, uint8_t *val)
gpmbed 0:b74c7741e608 1195 {
gpmbed 0:b74c7741e608 1196 lps22hh_fifo_status2_t reg;
gpmbed 0:b74c7741e608 1197 int32_t ret;
gpmbed 0:b74c7741e608 1198
gpmbed 0:b74c7741e608 1199 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 1200 *val = reg.fifo_full_ia;
gpmbed 0:b74c7741e608 1201
gpmbed 0:b74c7741e608 1202 return ret;
gpmbed 0:b74c7741e608 1203 }
gpmbed 0:b74c7741e608 1204
gpmbed 0:b74c7741e608 1205 /**
gpmbed 0:b74c7741e608 1206 * @brief FIFO overrun status.[get]
gpmbed 0:b74c7741e608 1207 *
gpmbed 0:b74c7741e608 1208 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 1209 * @param val change the values of fifo_ovr_ia in reg FIFO_STATUS2
gpmbed 0:b74c7741e608 1210 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 1211 *
gpmbed 0:b74c7741e608 1212 */
gpmbed 0:b74c7741e608 1213 int32_t lps22hh_fifo_ovr_flag_get(lps22hh_ctx_t *ctx, uint8_t *val)
gpmbed 0:b74c7741e608 1214 {
gpmbed 0:b74c7741e608 1215 lps22hh_fifo_status2_t reg;
gpmbed 0:b74c7741e608 1216 int32_t ret;
gpmbed 0:b74c7741e608 1217
gpmbed 0:b74c7741e608 1218 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS2, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 1219 *val = reg.fifo_ovr_ia;
gpmbed 0:b74c7741e608 1220
gpmbed 0:b74c7741e608 1221 return ret;
gpmbed 0:b74c7741e608 1222 }
gpmbed 0:b74c7741e608 1223
gpmbed 0:b74c7741e608 1224 /**
gpmbed 0:b74c7741e608 1225 * @brief FIFO stored data level.[get]
gpmbed 0:b74c7741e608 1226 *
gpmbed 0:b74c7741e608 1227 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 1228 * @param buff buffer that stores data read
gpmbed 0:b74c7741e608 1229 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 1230 *
gpmbed 0:b74c7741e608 1231 */
gpmbed 0:b74c7741e608 1232 int32_t lps22hh_fifo_data_level_get(lps22hh_ctx_t *ctx, uint8_t *buff)
gpmbed 0:b74c7741e608 1233 {
gpmbed 0:b74c7741e608 1234 int32_t ret;
gpmbed 0:b74c7741e608 1235 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_STATUS1, buff, 1);
gpmbed 0:b74c7741e608 1236 return ret;
gpmbed 0:b74c7741e608 1237 }
gpmbed 0:b74c7741e608 1238
gpmbed 0:b74c7741e608 1239 /**
gpmbed 0:b74c7741e608 1240 * @brief FIFO watermark status on INT_DRDY pin.[set]
gpmbed 0:b74c7741e608 1241 *
gpmbed 0:b74c7741e608 1242 * @param lps22hh_ctx_t *ctx: read / write interface definitions
gpmbed 0:b74c7741e608 1243 * @param uint8_t val: change the values of f_fth in reg CTRL_REG3
gpmbed 0:b74c7741e608 1244 *
gpmbed 0:b74c7741e608 1245 */
gpmbed 0:b74c7741e608 1246 int32_t lps22hh_fifo_threshold_on_int_set(lps22hh_ctx_t *ctx, uint8_t val)
gpmbed 0:b74c7741e608 1247 {
gpmbed 0:b74c7741e608 1248 lps22hh_reg_t reg;
gpmbed 0:b74c7741e608 1249 int32_t ret;
gpmbed 0:b74c7741e608 1250
gpmbed 0:b74c7741e608 1251 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, &(reg.byte), 1);
gpmbed 0:b74c7741e608 1252 reg.ctrl_reg3.int_f_wtm = val;
gpmbed 0:b74c7741e608 1253 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, &(reg.byte), 1);
gpmbed 0:b74c7741e608 1254
gpmbed 0:b74c7741e608 1255 return ret;
gpmbed 0:b74c7741e608 1256 }
gpmbed 0:b74c7741e608 1257
gpmbed 0:b74c7741e608 1258 /**
gpmbed 0:b74c7741e608 1259 * @brief FIFO full flag on INT_DRDY pin.[set]
gpmbed 0:b74c7741e608 1260 *
gpmbed 0:b74c7741e608 1261 * @param lps22hh_ctx_t *ctx: read / write interface definitions
gpmbed 0:b74c7741e608 1262 * @param uint8_t val: change the values of f_fss5 in reg CTRL_REG3
gpmbed 0:b74c7741e608 1263 *
gpmbed 0:b74c7741e608 1264 */
gpmbed 0:b74c7741e608 1265 int32_t lps22hh_fifo_full_on_int_set(lps22hh_ctx_t *ctx, uint8_t val)
gpmbed 0:b74c7741e608 1266 {
gpmbed 0:b74c7741e608 1267 lps22hh_reg_t reg;
gpmbed 0:b74c7741e608 1268 int32_t ret;
gpmbed 0:b74c7741e608 1269
gpmbed 0:b74c7741e608 1270 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, &(reg.byte), 1);
gpmbed 0:b74c7741e608 1271 reg.ctrl_reg3.int_f_full = val;
gpmbed 0:b74c7741e608 1272 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, &(reg.byte), 1);
gpmbed 0:b74c7741e608 1273
gpmbed 0:b74c7741e608 1274 return ret;
gpmbed 0:b74c7741e608 1275 }
gpmbed 0:b74c7741e608 1276
gpmbed 0:b74c7741e608 1277 /**
gpmbed 0:b74c7741e608 1278 * @brief FIFO overrun interrupt on INT_DRDY pin.[set]
gpmbed 0:b74c7741e608 1279 *
gpmbed 0:b74c7741e608 1280 * @param lps22hh_ctx_t *ctx: read / write interface definitions
gpmbed 0:b74c7741e608 1281 * @param uint8_t val: change the values of f_ovr in reg CTRL_REG3
gpmbed 0:b74c7741e608 1282 *
gpmbed 0:b74c7741e608 1283 */
gpmbed 0:b74c7741e608 1284 int32_t lps22hh_fifo_ovr_on_int_set(lps22hh_ctx_t *ctx, uint8_t val)
gpmbed 0:b74c7741e608 1285 {
gpmbed 0:b74c7741e608 1286 lps22hh_reg_t reg;
gpmbed 0:b74c7741e608 1287 int32_t ret;
gpmbed 0:b74c7741e608 1288
gpmbed 0:b74c7741e608 1289 ret = lps22hh_read_reg(ctx, LPS22HH_CTRL_REG3, &(reg.byte), 1);
gpmbed 0:b74c7741e608 1290 reg.ctrl_reg3.int_f_ovr = val;
gpmbed 0:b74c7741e608 1291 ret = lps22hh_write_reg(ctx, LPS22HH_CTRL_REG3, &(reg.byte), 1);
gpmbed 0:b74c7741e608 1292
gpmbed 0:b74c7741e608 1293 return ret;
gpmbed 0:b74c7741e608 1294 }
gpmbed 0:b74c7741e608 1295
gpmbed 0:b74c7741e608 1296 /**
gpmbed 0:b74c7741e608 1297 * @brief Fifo Mode selection.[set]
gpmbed 0:b74c7741e608 1298 *
gpmbed 0:b74c7741e608 1299 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 1300 * @param val change the values of f_mode in reg FIFO_CTRL
gpmbed 0:b74c7741e608 1301 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 1302 *
gpmbed 0:b74c7741e608 1303 */
gpmbed 0:b74c7741e608 1304
gpmbed 0:b74c7741e608 1305 int32_t lps22hh_fifo_mode_set(lps22hh_ctx_t *ctx, lps22hh_f_mode_t val)
gpmbed 0:b74c7741e608 1306 {
gpmbed 0:b74c7741e608 1307 lps22hh_fifo_ctrl_t reg;
gpmbed 0:b74c7741e608 1308 int32_t ret;
gpmbed 0:b74c7741e608 1309
gpmbed 0:b74c7741e608 1310 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 1311 if (ret == 0) {
gpmbed 0:b74c7741e608 1312 reg.f_mode = (uint8_t)val;
gpmbed 0:b74c7741e608 1313 ret = lps22hh_write_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 1314 }
gpmbed 0:b74c7741e608 1315 return ret;
gpmbed 0:b74c7741e608 1316 }
gpmbed 0:b74c7741e608 1317
gpmbed 0:b74c7741e608 1318 /**
gpmbed 0:b74c7741e608 1319 * @brief Fifo Mode selection.[get]
gpmbed 0:b74c7741e608 1320 *
gpmbed 0:b74c7741e608 1321 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 1322 * @param val Get the values of f_mode in reg FIFO_CTRL
gpmbed 0:b74c7741e608 1323 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 1324 *
gpmbed 0:b74c7741e608 1325 */
gpmbed 0:b74c7741e608 1326
gpmbed 0:b74c7741e608 1327 int32_t lps22hh_fifo_mode_get(lps22hh_ctx_t *ctx, lps22hh_f_mode_t *val)
gpmbed 0:b74c7741e608 1328 {
gpmbed 0:b74c7741e608 1329 lps22hh_fifo_ctrl_t reg;
gpmbed 0:b74c7741e608 1330 int32_t ret;
gpmbed 0:b74c7741e608 1331
gpmbed 0:b74c7741e608 1332 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 1333
gpmbed 0:b74c7741e608 1334 switch (reg.f_mode) {
gpmbed 0:b74c7741e608 1335 case LPS22HH_BYPASS_MODE:
gpmbed 0:b74c7741e608 1336 *val = LPS22HH_BYPASS_MODE;
gpmbed 0:b74c7741e608 1337 break;
gpmbed 0:b74c7741e608 1338 case LPS22HH_FIFO_MODE:
gpmbed 0:b74c7741e608 1339 *val = LPS22HH_FIFO_MODE;
gpmbed 0:b74c7741e608 1340 break;
gpmbed 0:b74c7741e608 1341 case LPS22HH_STREAM_MODE:
gpmbed 0:b74c7741e608 1342 *val = LPS22HH_STREAM_MODE;
gpmbed 0:b74c7741e608 1343 break;
gpmbed 0:b74c7741e608 1344 case LPS22HH_DYNAMIC_STREAM_MODE:
gpmbed 0:b74c7741e608 1345 *val = LPS22HH_DYNAMIC_STREAM_MODE;
gpmbed 0:b74c7741e608 1346 break;
gpmbed 0:b74c7741e608 1347 case LPS22HH_BYPASS_TO_FIFO_MODE:
gpmbed 0:b74c7741e608 1348 *val = LPS22HH_BYPASS_TO_FIFO_MODE;
gpmbed 0:b74c7741e608 1349 break;
gpmbed 0:b74c7741e608 1350 case LPS22HH_BYPASS_TO_STREAM_MODE:
gpmbed 0:b74c7741e608 1351 *val = LPS22HH_BYPASS_TO_STREAM_MODE;
gpmbed 0:b74c7741e608 1352 break;
gpmbed 0:b74c7741e608 1353 case LPS22HH_STREAM_TO_FIFO_MODE:
gpmbed 0:b74c7741e608 1354 *val = LPS22HH_STREAM_TO_FIFO_MODE;
gpmbed 0:b74c7741e608 1355 break;
gpmbed 0:b74c7741e608 1356 default:
gpmbed 0:b74c7741e608 1357 *val = LPS22HH_BYPASS_MODE;
gpmbed 0:b74c7741e608 1358 break;
gpmbed 0:b74c7741e608 1359 }
gpmbed 0:b74c7741e608 1360
gpmbed 0:b74c7741e608 1361 return ret;
gpmbed 0:b74c7741e608 1362 }
gpmbed 0:b74c7741e608 1363
gpmbed 0:b74c7741e608 1364 /**
gpmbed 0:b74c7741e608 1365 * @brief Sensing chain FIFO stop values memorization at
gpmbed 0:b74c7741e608 1366 * threshold level.[set]
gpmbed 0:b74c7741e608 1367 *
gpmbed 0:b74c7741e608 1368 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 1369 * @param val change the values of stop_on_wtm in reg FIFO_CTRL
gpmbed 0:b74c7741e608 1370 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 1371 *
gpmbed 0:b74c7741e608 1372 */
gpmbed 0:b74c7741e608 1373 int32_t lps22hh_fifo_stop_on_wtm_set(lps22hh_ctx_t *ctx, uint8_t val)
gpmbed 0:b74c7741e608 1374 {
gpmbed 0:b74c7741e608 1375 lps22hh_fifo_ctrl_t reg;
gpmbed 0:b74c7741e608 1376 int32_t ret;
gpmbed 0:b74c7741e608 1377
gpmbed 0:b74c7741e608 1378 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 1379 if (ret == 0) {
gpmbed 0:b74c7741e608 1380 reg.stop_on_wtm = val;
gpmbed 0:b74c7741e608 1381 ret = lps22hh_write_reg(ctx, LPS22HH_FIFO_CTRL, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 1382 }
gpmbed 0:b74c7741e608 1383 return ret;
gpmbed 0:b74c7741e608 1384 }
gpmbed 0:b74c7741e608 1385
gpmbed 0:b74c7741e608 1386 /**
gpmbed 0:b74c7741e608 1387 * @brief FIFO watermark level selection.[set]
gpmbed 0:b74c7741e608 1388 *
gpmbed 0:b74c7741e608 1389 * @param ctx read / write interface definitions
gpmbed 0:b74c7741e608 1390 * @param val change the values of wtm in reg FIFO_WTM
gpmbed 0:b74c7741e608 1391 * @retval interface status (MANDATORY: return 0 -> no Error)
gpmbed 0:b74c7741e608 1392 *
gpmbed 0:b74c7741e608 1393 */
gpmbed 0:b74c7741e608 1394 int32_t lps22hh_fifo_watermark_set(lps22hh_ctx_t *ctx, uint8_t val)
gpmbed 0:b74c7741e608 1395 {
gpmbed 0:b74c7741e608 1396 lps22hh_fifo_wtm_t reg;
gpmbed 0:b74c7741e608 1397 int32_t ret;
gpmbed 0:b74c7741e608 1398
gpmbed 0:b74c7741e608 1399 ret = lps22hh_read_reg(ctx, LPS22HH_FIFO_WTM, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 1400 if (ret == 0) {
gpmbed 0:b74c7741e608 1401 reg.wtm = val;
gpmbed 0:b74c7741e608 1402 ret = lps22hh_write_reg(ctx, LPS22HH_FIFO_WTM, (uint8_t*) &reg, 1);
gpmbed 0:b74c7741e608 1403 }
gpmbed 0:b74c7741e608 1404 return ret;
gpmbed 0:b74c7741e608 1405 }