Mike Moore / Mbed 2 deprecated USB_device_project

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Dependencies:   C12832_lcd USBDevice mbed-rtos mbed mmSPI

mmRTL/shadow_load_control.txt@12:d10f526ca443, 2013-09-01 (annotated)

Committer:
gatedClock
Date:
Sun Sep 01 22:02:19 2013 +0000
Revision:
12:d10f526ca443
Parent:
7:d1aca9ccbab8 
cpu add comments.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 3:659ffc90b59e 1 /*----------------------------------copyright---------------------------------*/
gatedClock 7:d1aca9ccbab8 2 // licensed for personal and academic use.
gatedClock 7:d1aca9ccbab8 3 // commercial use must be approved by the account-holder of
gatedClock 7:d1aca9ccbab8 4 // gated.clock@gmail.com
gatedClock 3:659ffc90b59e 5 /*-----------------------------------module-----------------------------------*/
gatedClock 7:d1aca9ccbab8 6 module shadow_load_control
gatedClock 3:659ffc90b59e 7 (
gatedClock 7:d1aca9ccbab8 8 iCPUclk,
gatedClock 7:d1aca9ccbab8 9 iSPIclk,
gatedClock 7:d1aca9ccbab8 10 iRstn, // direct clear.
gatedClock 7:d1aca9ccbab8 11 oLoadEnable // shadow registers load enable.
gatedClock 3:659ffc90b59e 12 );
gatedClock 3:659ffc90b59e 13 /*--------------------------------description-----------------------------------
gatedClock 7:d1aca9ccbab8 14 when the CPU clock goes low, the CPU state is stable, and its time
gatedClock 7:d1aca9ccbab8 15 for the SPI shadow registers to do a parallel load of the CPU state,
gatedClock 7:d1aca9ccbab8 16 so its time to turn on the load-enable signal.
gatedClock 3:659ffc90b59e 17
gatedClock 7:d1aca9ccbab8 18 when the first SPI clock goes high, the parallel load completes and
gatedClock 7:d1aca9ccbab8 19 its time to turn off the load-enable signal.
gatedClock 3:659ffc90b59e 20 -------------------------------------notes--------------------------------------
gatedClock 3:659ffc90b59e 21 ------------------------------------defines-----------------------------------*/
gatedClock 3:659ffc90b59e 22 /*-----------------------------------ports------------------------------------*/
gatedClock 7:d1aca9ccbab8 23 input iCPUclk;
gatedClock 7:d1aca9ccbab8 24 input iSPIclk;
gatedClock 7:d1aca9ccbab8 25 input iRstn; // direct clear.
gatedClock 7:d1aca9ccbab8 26 output oLoadEnable; // shadow registers load enable.
gatedClock 3:659ffc90b59e 27 /*-----------------------------------wires------------------------------------*/
gatedClock 7:d1aca9ccbab8 28 wire iCPUclk;
gatedClock 7:d1aca9ccbab8 29 wire iSPIclk;
gatedClock 7:d1aca9ccbab8 30 wire iRstn; // direct clear.
gatedClock 7:d1aca9ccbab8 31 wire oLoadEnable; // shadow registers load enable.
gatedClock 3:659ffc90b59e 32
gatedClock 7:d1aca9ccbab8 33 wire wOrClock; // OR the clocks.
gatedClock 3:659ffc90b59e 34 /*---------------------------------registers----------------------------------*/
gatedClock 7:d1aca9ccbab8 35 reg rRegister;
gatedClock 3:659ffc90b59e 36 /*---------------------------------variables----------------------------------*/
gatedClock 3:659ffc90b59e 37 /*---------------------------------parameters---------------------------------*/
gatedClock 3:659ffc90b59e 38 /*-----------------------------------clocks-----------------------------------*/
gatedClock 3:659ffc90b59e 39 /*---------------------------------instances----------------------------------*/
gatedClock 3:659ffc90b59e 40 /*-----------------------------------logic------------------------------------*/
gatedClock 7:d1aca9ccbab8 41 always @ (negedge wOrClock or negedge iRstn)
gatedClock 7:d1aca9ccbab8 42 begin
gatedClock 7:d1aca9ccbab8 43 if (!iRstn ) rRegister <= 1'b0;
gatedClock 7:d1aca9ccbab8 44 else if (!wOrClock) rRegister <= !iSPIclk;
gatedClock 7:d1aca9ccbab8 45 end
gatedClock 3:659ffc90b59e 46
gatedClock 7:d1aca9ccbab8 47 assign wOrClock = iCPUclk | iSPIclk;
gatedClock 7:d1aca9ccbab8 48 assign oLoadEnable = rRegister;
gatedClock 3:659ffc90b59e 49 /*-------------------------------*/endmodule/*--------------------------------*/
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