File content as of revision 12:d10f526ca443:

/*----------------------------------copyright---------------------------------*/
//      licensed for personal and academic use.
//      commercial use must be approved by the account-holder of
//      gated.clock@gmail.com
/*-----------------------------------module-----------------------------------*/
        module shadow_load_control
        (
          iCPUclk,
          iSPIclk,
          iRstn,                                // direct clear.
          oLoadEnable                           // shadow registers load enable.
        );
/*--------------------------------description-----------------------------------
        when the CPU clock goes low, the CPU state is stable, and its time
        for the SPI shadow registers to do a parallel load of the CPU state,
        so its time to turn on the load-enable signal.

        when the first SPI clock goes high, the parallel load completes and
        its time to turn off the load-enable signal.
-------------------------------------notes--------------------------------------
------------------------------------defines-----------------------------------*/
/*-----------------------------------ports------------------------------------*/
        input           iCPUclk;
        input           iSPIclk;
        input           iRstn;                  // direct clear.
        output          oLoadEnable;            // shadow registers load enable.
/*-----------------------------------wires------------------------------------*/
        wire            iCPUclk;
        wire            iSPIclk;
        wire            iRstn;                  // direct clear.
        wire            oLoadEnable;            // shadow registers load enable.

        wire            wOrClock;               // OR the clocks.
/*---------------------------------registers----------------------------------*/
        reg            rRegister;
/*---------------------------------variables----------------------------------*/
/*---------------------------------parameters---------------------------------*/
/*-----------------------------------clocks-----------------------------------*/
/*---------------------------------instances----------------------------------*/
/*-----------------------------------logic------------------------------------*/
        always @ (negedge wOrClock or negedge iRstn)
        begin
               if (!iRstn   ) rRegister <= 1'b0;
          else if (!wOrClock) rRegister <= !iSPIclk;
        end

        assign wOrClock    =  iCPUclk | iSPIclk;
        assign oLoadEnable =  rRegister;
/*-------------------------------*/endmodule/*--------------------------------*/