Mike Moore / Mbed 2 deprecated USB_device_project

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Dependencies:   C12832_lcd USBDevice mbed-rtos mbed mmSPI

mmRTL/shadow_load_control.txt@3:659ffc90b59e, 2013-09-01 (annotated)

Committer:
gatedClock
Date:
Sun Sep 01 02:53:39 2013 +0000
Revision:
3:659ffc90b59e
Child:
7:d1aca9ccbab8
add the project RTL files.  the tab-formatting needs to be redone.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 3:659ffc90b59e 1 /*----------------------------------copyright---------------------------------*/
gatedClock 3:659ffc90b59e 2 // licensed for personal and academic use.
gatedClock 3:659ffc90b59e 3 // commercial use must be approved by the account-holder of
gatedClock 3:659ffc90b59e 4 // gated.clock@gmail.com
gatedClock 3:659ffc90b59e 5 /*-----------------------------------module-----------------------------------*/
gatedClock 3:659ffc90b59e 6 module shadow_load_control
gatedClock 3:659ffc90b59e 7 (
gatedClock 3:659ffc90b59e 8 iCPUclk,
gatedClock 3:659ffc90b59e 9 iSPIclk,
gatedClock 3:659ffc90b59e 10 iRstn, // direct clear.
gatedClock 3:659ffc90b59e 11 oLoadEnable // shadow registers load enable.
gatedClock 3:659ffc90b59e 12 );
gatedClock 3:659ffc90b59e 13 /*--------------------------------description-----------------------------------
gatedClock 3:659ffc90b59e 14 when the CPU clock goes low, the CPU state is stable, and its time
gatedClock 3:659ffc90b59e 15 for the SPI shadow registers to do a parallel load of the CPU state,
gatedClock 3:659ffc90b59e 16 so its time to turn on the load-enable signal.
gatedClock 3:659ffc90b59e 17
gatedClock 3:659ffc90b59e 18 when the first SPI clock goes high, the parallel load completes and
gatedClock 3:659ffc90b59e 19 its time to turn off the load-enable signal.
gatedClock 3:659ffc90b59e 20 -------------------------------------notes--------------------------------------
gatedClock 3:659ffc90b59e 21 ------------------------------------defines-----------------------------------*/
gatedClock 3:659ffc90b59e 22 /*-----------------------------------ports------------------------------------*/
gatedClock 3:659ffc90b59e 23 input iCPUclk;
gatedClock 3:659ffc90b59e 24 input iSPIclk;
gatedClock 3:659ffc90b59e 25 input iRstn; // direct clear.
gatedClock 3:659ffc90b59e 26 output oLoadEnable; // shadow registers load enable.
gatedClock 3:659ffc90b59e 27 /*-----------------------------------wires------------------------------------*/
gatedClock 3:659ffc90b59e 28 wire iCPUclk;
gatedClock 3:659ffc90b59e 29 wire iSPIclk;
gatedClock 3:659ffc90b59e 30 wire iRstn; // direct clear.
gatedClock 3:659ffc90b59e 31 wire oLoadEnable; // shadow registers load enable.
gatedClock 3:659ffc90b59e 32
gatedClock 3:659ffc90b59e 33 wire wOrClock; // OR the clocks.
gatedClock 3:659ffc90b59e 34 /*---------------------------------registers----------------------------------*/
gatedClock 3:659ffc90b59e 35 reg rRegister;
gatedClock 3:659ffc90b59e 36 /*---------------------------------variables----------------------------------*/
gatedClock 3:659ffc90b59e 37 /*---------------------------------parameters---------------------------------*/
gatedClock 3:659ffc90b59e 38 /*-----------------------------------clocks-----------------------------------*/
gatedClock 3:659ffc90b59e 39 /*---------------------------------instances----------------------------------*/
gatedClock 3:659ffc90b59e 40 /*-----------------------------------logic------------------------------------*/
gatedClock 3:659ffc90b59e 41 always @ (negedge wOrClock or negedge iRstn)
gatedClock 3:659ffc90b59e 42 begin
gatedClock 3:659ffc90b59e 43 if (!iRstn ) rRegister <= 1'b0;
gatedClock 3:659ffc90b59e 44 else if (!wOrClock) rRegister <= !iSPIclk;
gatedClock 3:659ffc90b59e 45 end
gatedClock 3:659ffc90b59e 46
gatedClock 3:659ffc90b59e 47 assign wOrClock = iCPUclk | iSPIclk;
gatedClock 3:659ffc90b59e 48 assign oLoadEnable = rRegister;
gatedClock 3:659ffc90b59e 49 /*-------------------------------*/endmodule/*--------------------------------*/
gatedClock 3:659ffc90b59e 50
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