Diff: mmRTL/shadow_load_control.txt

Revision:

3:659ffc90b59e

Child:

7:d1aca9ccbab8

diff -r 08655e2bb776 -r 659ffc90b59e mmRTL/shadow_load_control.txt
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/shadow_load_control.txt	Sun Sep 01 02:53:39 2013 +0000
@@ -0,0 +1,65 @@
+/*----------------------------------copyright---------------------------------*/
+//  licensed for personal and academic use.
+//  commercial use must be approved by the account-holder of
+//  gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+    module shadow_load_control
+        (
+      iCPUclk,
+      iSPIclk,
+      iRstn,                // direct clear.
+      oLoadEnable               // shadow registers load enable.
+        );
+/*--------------------------------description-----------------------------------
+    when the CPU clock goes low, the CPU state is stable, and its time
+    for the SPI shadow registers to do a parallel load of the CPU state,
+    so its time to turn on the load-enable signal.
+
+    when the first SPI clock goes high, the parallel load completes and
+    its time to turn off the load-enable signal.
+-------------------------------------notes--------------------------------------
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+    input           iCPUclk;
+    input           iSPIclk;
+    input           iRstn;          // direct clear.
+    output          oLoadEnable;        // shadow registers load enable.
+/*-----------------------------------wires------------------------------------*/
+    wire            iCPUclk;
+    wire            iSPIclk;
+    wire            iRstn;          // direct clear.
+    wire            oLoadEnable;        // shadow registers load enable.
+
+    wire            wOrClock;       // OR the clocks.
+/*---------------------------------registers----------------------------------*/
+    reg            rRegister;
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+    always @ (negedge wOrClock or negedge iRstn)
+    begin
+           if (!iRstn   ) rRegister <= 1'b0;
+      else if (!wOrClock) rRegister <= !iSPIclk;
+    end
+
+    assign wOrClock    =  iCPUclk | iSPIclk;
+    assign oLoadEnable =  rRegister;
+/*-------------------------------*/endmodule/*--------------------------------*/
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