Mike Moore / Mbed 2 deprecated USB_device_project

USB Device Programming class project. This project allows a Python/Tk program running on a PC host to monitor/control a test-CPU programmed into an altera development board.

Dependencies:   C12832_lcd USBDevice mbed-rtos mbed mmSPI

mmRTL/cpu.txt@7:d1aca9ccbab8, 2013-09-01 (annotated)

Committer:
gatedClock
Date:
Sun Sep 01 03:48:07 2013 +0000
Revision:
7:d1aca9ccbab8
Parent:
3:659ffc90b59e
Child:
12:d10f526ca443
improve tab formatting of code under mmRTL.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 3:659ffc90b59e 1 /*----------------------------------copyright---//----------------------------*/
gatedClock 7:d1aca9ccbab8 2 // licensed for personal and academic use.
gatedClock 7:d1aca9ccbab8 3 // commercial use must be approved by the account-holder of
gatedClock 7:d1aca9ccbab8 4 // gated.clock@gmail.com
gatedClock 3:659ffc90b59e 5 /*-----------------------------------module-----//----------------------------*/
gatedClock 7:d1aca9ccbab8 6 module cpu
gatedClock 3:659ffc90b59e 7 (
gatedClock 7:d1aca9ccbab8 8 iMOSI,
gatedClock 3:659ffc90b59e 9 oMISO,
gatedClock 7:d1aca9ccbab8 10 iSPIclk,
gatedClock 7:d1aca9ccbab8 11 iCPUclk,
gatedClock 7:d1aca9ccbab8 12 iKEY,
gatedClock 7:d1aca9ccbab8 13 iSW,
gatedClock 7:d1aca9ccbab8 14 oLEDR,
gatedClock 7:d1aca9ccbab8 15 oLEDG,
gatedClock 7:d1aca9ccbab8 16 oDummyLoad
gatedClock 3:659ffc90b59e 17 );
gatedClock 3:659ffc90b59e 18 /*--------------------------------description---//------------------------------
gatedClock 7:d1aca9ccbab8 19 the demonstration cpu datapath.
gatedClock 3:659ffc90b59e 20
gatedClock 7:d1aca9ccbab8 21 the CPU consists of
gatedClock 7:d1aca9ccbab8 22 R0 - 8-bit register and accumulator.
gatedClock 7:d1aca9ccbab8 23 R1 - 8-bit register and main-memory address register.
gatedClock 7:d1aca9ccbab8 24 R2 - 8-bit register and main-memory high data byte.
gatedClock 7:d1aca9ccbab8 25 R3 - 8-bit register and main-memory low data byte.
gatedClock 7:d1aca9ccbab8 26 PC - 8-bit program counter.
gatedClock 7:d1aca9ccbab8 27 IR - 16-bit instruction register.
gatedClock 7:d1aca9ccbab8 28 ID - combinatorial instruction decoder.
gatedClock 7:d1aca9ccbab8 29 MM - 16-bit-wide x 256-address Main Memory.
gatedClock 3:659ffc90b59e 30
gatedClock 7:d1aca9ccbab8 31 the instruction words is sixteen bits long, and is comprised of
gatedClock 7:d1aca9ccbab8 32 <15:13> = source resource.
gatedClock 7:d1aca9ccbab8 33 <12:10> = destination resource.
gatedClock 7:d1aca9ccbab8 34 < 9> = write-enable.
gatedClock 7:d1aca9ccbab8 35 < 8> = program-counter-enable.
gatedClock 7:d1aca9ccbab8 36 < 7: 0> = immediate data.
gatedClock 3:659ffc90b59e 37
gatedClock 7:d1aca9ccbab8 38 the registers (U00 through U05) have a iSel input which define the source.
gatedClock 7:d1aca9ccbab8 39 the instruction decoder (U06) enables the loading of the destinations.
gatedClock 3:659ffc90b59e 40
gatedClock 7:d1aca9ccbab8 41 the SPI shadow registers (U19-U25) monitor the CPU state, and can
gatedClock 7:d1aca9ccbab8 42 control the CPU state by asserting U19's bits 1 and 2.
gatedClock 3:659ffc90b59e 43
gatedClock 7:d1aca9ccbab8 44 U08 provides a shadow register load-enable pulse which
gatedClock 7:d1aca9ccbab8 45 begins at the falling edge of a CPU clock and ends at
gatedClock 7:d1aca9ccbab8 46 the falling edge of the next SPI clock, allowing the shadow
gatedClock 3:659ffc90b59e 47 registers the ability to capture the state of the CPU.
gatedClock 3:659ffc90b59e 48
gatedClock 7:d1aca9ccbab8 49 U30 routes internal nets out to the green LED bank according
gatedClock 7:d1aca9ccbab8 50 to the setting of switches SW<3:0>.
gatedClock 3:659ffc90b59e 51
gatedClock 3:659ffc90b59e 52 -------------------------------------notes------//------------------------------
gatedClock 3:659ffc90b59e 53
gatedClock 7:d1aca9ccbab8 54 fpga board pin assignments.
gatedClock 3:659ffc90b59e 55
gatedClock 3:659ffc90b59e 56
gatedClock 7:d1aca9ccbab8 57 project:
gatedClock 7:d1aca9ccbab8 58 MOSI P17
gatedClock 7:d1aca9ccbab8 59 MISO D15
gatedClock 7:d1aca9ccbab8 60 SPIclk E20
gatedClock 7:d1aca9ccbab8 61 CPUclk E14
gatedClock 3:659ffc90b59e 62
gatedClock 3:659ffc90b59e 63
gatedClock 7:d1aca9ccbab8 64 key3 T21
gatedClock 7:d1aca9ccbab8 65 key2 T22
gatedClock 7:d1aca9ccbab8 66 key1 R21
gatedClock 7:d1aca9ccbab8 67 key0 R22 iRstn
gatedClock 3:659ffc90b59e 68
gatedClock 7:d1aca9ccbab8 69 sw9 L2
gatedClock 7:d1aca9ccbab8 70 sw8 M1
gatedClock 7:d1aca9ccbab8 71 sw7 M2
gatedClock 7:d1aca9ccbab8 72 sw6 U11
gatedClock 7:d1aca9ccbab8 73 sw5 U12
gatedClock 7:d1aca9ccbab8 74 sw4 W12
gatedClock 7:d1aca9ccbab8 75 sw3 V12
gatedClock 7:d1aca9ccbab8 76 sw2 M22
gatedClock 7:d1aca9ccbab8 77 sw1 L21
gatedClock 7:d1aca9ccbab8 78 sw0 L22
gatedClock 3:659ffc90b59e 79
gatedClock 7:d1aca9ccbab8 80 ledr9 R17
gatedClock 7:d1aca9ccbab8 81 ledr8 R18
gatedClock 7:d1aca9ccbab8 82 ledr7 U18
gatedClock 7:d1aca9ccbab8 83 ledr6 Y18
gatedClock 7:d1aca9ccbab8 84 ledr5 V19
gatedClock 7:d1aca9ccbab8 85 ledr4 T18
gatedClock 7:d1aca9ccbab8 86 ledr3 Y19
gatedClock 7:d1aca9ccbab8 87 ledr2 U19
gatedClock 7:d1aca9ccbab8 88 ledr1 R19
gatedClock 7:d1aca9ccbab8 89 ledr0 R20
gatedClock 3:659ffc90b59e 90
gatedClock 7:d1aca9ccbab8 91 ledg7 Y21
gatedClock 7:d1aca9ccbab8 92 ledg6 Y22
gatedClock 7:d1aca9ccbab8 93 ledg5 W21
gatedClock 7:d1aca9ccbab8 94 ledg4 W22
gatedClock 7:d1aca9ccbab8 95 ledg3 V21
gatedClock 7:d1aca9ccbab8 96 ledg2 V22
gatedClock 7:d1aca9ccbab8 97 ledg1 U21
gatedClock 7:d1aca9ccbab8 98 ledg0 U22
gatedClock 3:659ffc90b59e 99 ------------------------------------defines-----//----------------------------*/
gatedClock 3:659ffc90b59e 100 /*-----------------------------------ports------//----------------------------*/
gatedClock 7:d1aca9ccbab8 101 input iMOSI; // SPI input.
gatedClock 7:d1aca9ccbab8 102 output oMISO; // SPI output.
gatedClock 7:d1aca9ccbab8 103 input iSPIclk; // SPI clock.
gatedClock 7:d1aca9ccbab8 104 input iCPUclk; // CPU clock.
gatedClock 7:d1aca9ccbab8 105 input [ 3:0] iKEY; // keypress.
gatedClock 7:d1aca9ccbab8 106 input [ 9:0] iSW; // slide-switches.
gatedClock 7:d1aca9ccbab8 107 output [ 9:0] oLEDR; // red LED bank.
gatedClock 7:d1aca9ccbab8 108 output [ 7:0] oLEDG; // green LED bank.
gatedClock 7:d1aca9ccbab8 109 output oDummyLoad; // anti-optimization.
gatedClock 3:659ffc90b59e 110 /*-----------------------------------wires------//----------------------------*/
gatedClock 7:d1aca9ccbab8 111 wire iMOSI; // SPI input.
gatedClock 7:d1aca9ccbab8 112 wire oMISO; // SPI output.
gatedClock 7:d1aca9ccbab8 113 wire iSPIclk; // SPI clock.
gatedClock 7:d1aca9ccbab8 114 wire iCPUclk; // CPU clock.
gatedClock 7:d1aca9ccbab8 115 wire [ 3:0] iKEY; // keypress.
gatedClock 7:d1aca9ccbab8 116 wire [ 9:0] iSW; // slide-switches.
gatedClock 7:d1aca9ccbab8 117 wire [ 9:0] oLEDR; // red LED bank.
gatedClock 7:d1aca9ccbab8 118 wire [ 7:0] oLEDG; // green LED bank.
gatedClock 3:659ffc90b59e 119
gatedClock 7:d1aca9ccbab8 120 wire wCEPC; // program counter count-enable.
gatedClock 7:d1aca9ccbab8 121 wire [15:0] wIR; // instruction register.
gatedClock 7:d1aca9ccbab8 122 wire wLEIR; // instruction register load-enable.
gatedClock 7:d1aca9ccbab8 123 wire wLEPC; // program counter load-enable.
gatedClock 7:d1aca9ccbab8 124 wire wLER0; // R0 load-enable.
gatedClock 7:d1aca9ccbab8 125 wire wLER1; // R1 load-enable.
gatedClock 7:d1aca9ccbab8 126 wire wLER2; // R2 load-enable.
gatedClock 7:d1aca9ccbab8 127 wire wLER3; // R3 load-enable.
gatedClock 7:d1aca9ccbab8 128 wire [15:0] wMMD; // main-memory data-out.
gatedClock 7:d1aca9ccbab8 129 wire [15:0] wMMI; // main-memory instruction-out.
gatedClock 7:d1aca9ccbab8 130 wire [ 7:0] wPC; // program-counter.
gatedClock 7:d1aca9ccbab8 131 wire [ 7:0] wR0; // R0.
gatedClock 7:d1aca9ccbab8 132 wire [ 7:0] wR1; // R1.
gatedClock 7:d1aca9ccbab8 133 wire [ 7:0] wR2; // R2.
gatedClock 7:d1aca9ccbab8 134 wire [ 7:0] wR3; // R3.
gatedClock 7:d1aca9ccbab8 135 wire wRstn; // system reset.
gatedClock 7:d1aca9ccbab8 136 wire [ 2:0] wSel; // common data-in selector.
gatedClock 7:d1aca9ccbab8 137 wire [ 7:0] wShadow0; // R0 shadow register.
gatedClock 7:d1aca9ccbab8 138 wire [ 7:0] wShadow1; // R1 shadow register.
gatedClock 7:d1aca9ccbab8 139 wire [ 7:0] wShadow2; // R2 shadow register.
gatedClock 7:d1aca9ccbab8 140 wire [ 7:0] wShadow3; // R3 shadow register.
gatedClock 7:d1aca9ccbab8 141 wire [15:0] wShadowIR; // instruction register shadow.
gatedClock 7:d1aca9ccbab8 142 wire [ 7:0] wShadowPC; // program counter shadow.
gatedClock 7:d1aca9ccbab8 143 wire wSIR; // instruction register shadow shift-up.
gatedClock 7:d1aca9ccbab8 144 wire wSPC; // program counter shadow shift-up.
gatedClock 7:d1aca9ccbab8 145 wire wSR0; // R0 shadow shift-up.
gatedClock 7:d1aca9ccbab8 146 wire wSR1; // R1 shadow shift-up.
gatedClock 7:d1aca9ccbab8 147 wire wSR2; // R2 shadow shift-up.
gatedClock 7:d1aca9ccbab8 148 wire wSR3; // R3 shadow shift-up.
gatedClock 7:d1aca9ccbab8 149 wire wWE; // write-enable pulse.
gatedClock 7:d1aca9ccbab8 150 wire [ 7:0] wImmediate; // immediate data.
gatedClock 7:d1aca9ccbab8 151 wire [ 7:0] wSpiControl; // from spi control register.
gatedClock 7:d1aca9ccbab8 152 wire wSquelch; // from spi control register.
gatedClock 7:d1aca9ccbab8 153 wire wBypassIR; // from spi control register.
gatedClock 7:d1aca9ccbab8 154 wire wLoadShadows; // shadow registers parallel load.
gatedClock 3:659ffc90b59e 155
gatedClock 7:d1aca9ccbab8 156 // not currently used.
gatedClock 7:d1aca9ccbab8 157 wire [ 7:0] wGreenLEDBus7; // green LED bus.
gatedClock 7:d1aca9ccbab8 158 wire [ 7:0] wGreenLEDBus6; // green LED bus.
gatedClock 7:d1aca9ccbab8 159 wire [ 7:0] wGreenLEDBus5; // green LED bus.
gatedClock 7:d1aca9ccbab8 160 wire [ 7:0] wGreenLEDBus4; // green LED bus.
gatedClock 7:d1aca9ccbab8 161 wire [ 7:0] wGreenLEDBus3; // green LED bus.
gatedClock 7:d1aca9ccbab8 162 wire [ 7:0] wGreenLEDBus2; // green LED bus.
gatedClock 7:d1aca9ccbab8 163 wire [ 7:0] wGreenLEDBus1; // green LED bus.
gatedClock 7:d1aca9ccbab8 164 wire [ 7:0] wGreenLEDBus0; // green LED bus.
gatedClock 7:d1aca9ccbab8 165 wire oDummyLoad; // anti-optimization.
gatedClock 7:d1aca9ccbab8 166 wire [ 3:0] wTrigger; // trigger control.
gatedClock 3:659ffc90b59e 167 /*---------------------------------registers----//----------------------------*/
gatedClock 3:659ffc90b59e 168 /*---------------------------------variables----//----------------------------*/
gatedClock 3:659ffc90b59e 169 /*---------------------------------parameters---//----------------------------*/
gatedClock 3:659ffc90b59e 170 /*-----------------------------------clocks-----//----------------------------*/
gatedClock 3:659ffc90b59e 171 /*---------------------------------instances----//----------------------------*/
gatedClock 3:659ffc90b59e 172
gatedClock 3:659ffc90b59e 173 //--- begin regular CPU section.
gatedClock 3:659ffc90b59e 174
gatedClock 3:659ffc90b59e 175
gatedClock 7:d1aca9ccbab8 176 reg_08 U00_R0 // CPU R0.
gatedClock 3:659ffc90b59e 177 (
gatedClock 3:659ffc90b59e 178 .oParallel (wR0),
gatedClock 3:659ffc90b59e 179 .iParallel7 (wShadow0),
gatedClock 7:d1aca9ccbab8 180 .iParallel6 (wR1 + wR2), // adder.
gatedClock 3:659ffc90b59e 181 .iParallel5 (wImmediate),
gatedClock 3:659ffc90b59e 182 .iParallel4 (wR0),
gatedClock 3:659ffc90b59e 183 .iParallel3 (wR3),
gatedClock 3:659ffc90b59e 184 .iParallel2 (wR2),
gatedClock 3:659ffc90b59e 185 .iParallel1 (wR1),
gatedClock 7:d1aca9ccbab8 186 .iParallel0 (wR0), // needed for zero vector no-op.
gatedClock 7:d1aca9ccbab8 187 .iSel (wSel),
gatedClock 7:d1aca9ccbab8 188 .oSerial (),
gatedClock 7:d1aca9ccbab8 189 .iSerial (1'b0),
gatedClock 7:d1aca9ccbab8 190 .iLoadEnable (wLER0),
gatedClock 7:d1aca9ccbab8 191 .iShiftEnable(1'b0),
gatedClock 7:d1aca9ccbab8 192 .iResetN (wRstn),
gatedClock 7:d1aca9ccbab8 193 .iClk (iCPUclk)
gatedClock 3:659ffc90b59e 194 );
gatedClock 3:659ffc90b59e 195
gatedClock 3:659ffc90b59e 196
gatedClock 3:659ffc90b59e 197
gatedClock 7:d1aca9ccbab8 198 reg_08 U01_R1 // CPU R1.
gatedClock 3:659ffc90b59e 199 (
gatedClock 3:659ffc90b59e 200 .oParallel (wR1),
gatedClock 3:659ffc90b59e 201 .iParallel7 (wShadow1),
gatedClock 3:659ffc90b59e 202 .iParallel6 (wMMD[7:0]),
gatedClock 3:659ffc90b59e 203 .iParallel5 (wImmediate),
gatedClock 3:659ffc90b59e 204 .iParallel4 (wR1),
gatedClock 3:659ffc90b59e 205 .iParallel3 (wR3),
gatedClock 3:659ffc90b59e 206 .iParallel2 (wR2),
gatedClock 3:659ffc90b59e 207 .iParallel1 (wR1),
gatedClock 3:659ffc90b59e 208 .iParallel0 (wR0),
gatedClock 7:d1aca9ccbab8 209 .iSel (wSel),
gatedClock 7:d1aca9ccbab8 210 .oSerial (),
gatedClock 7:d1aca9ccbab8 211 .iSerial (1'b0),
gatedClock 7:d1aca9ccbab8 212 .iLoadEnable (wLER1),
gatedClock 7:d1aca9ccbab8 213 .iShiftEnable(1'b0),
gatedClock 7:d1aca9ccbab8 214 .iResetN (wRstn),
gatedClock 7:d1aca9ccbab8 215 .iClk (iCPUclk)
gatedClock 3:659ffc90b59e 216 );
gatedClock 3:659ffc90b59e 217
gatedClock 3:659ffc90b59e 218
gatedClock 3:659ffc90b59e 219
gatedClock 7:d1aca9ccbab8 220 reg_08 U02_R2 // CPU R2.
gatedClock 3:659ffc90b59e 221 (
gatedClock 3:659ffc90b59e 222 .oParallel (wR2),
gatedClock 3:659ffc90b59e 223 .iParallel7 (wShadow2),
gatedClock 3:659ffc90b59e 224 .iParallel6 (wMMD[15:8]),
gatedClock 3:659ffc90b59e 225 .iParallel5 (wImmediate),
gatedClock 3:659ffc90b59e 226 .iParallel4 (wR2),
gatedClock 3:659ffc90b59e 227 .iParallel3 (wR3),
gatedClock 3:659ffc90b59e 228 .iParallel2 (wR2),
gatedClock 3:659ffc90b59e 229 .iParallel1 (wR1),
gatedClock 3:659ffc90b59e 230 .iParallel0 (wR0),
gatedClock 7:d1aca9ccbab8 231 .iSel (wSel),
gatedClock 7:d1aca9ccbab8 232 .oSerial (),
gatedClock 7:d1aca9ccbab8 233 .iSerial (1'b0),
gatedClock 7:d1aca9ccbab8 234 .iLoadEnable (wLER2),
gatedClock 7:d1aca9ccbab8 235 .iShiftEnable(1'b0),
gatedClock 7:d1aca9ccbab8 236 .iResetN (wRstn),
gatedClock 7:d1aca9ccbab8 237 .iClk (iCPUclk)
gatedClock 3:659ffc90b59e 238 );
gatedClock 3:659ffc90b59e 239
gatedClock 3:659ffc90b59e 240
gatedClock 7:d1aca9ccbab8 241 reg_08 U03_R3 // CPU R3.
gatedClock 3:659ffc90b59e 242 (
gatedClock 3:659ffc90b59e 243 .oParallel (wR3),
gatedClock 3:659ffc90b59e 244 .iParallel7 (wShadow3),
gatedClock 3:659ffc90b59e 245 .iParallel6 (wMMD[7:0]),
gatedClock 3:659ffc90b59e 246 .iParallel5 (wImmediate),
gatedClock 3:659ffc90b59e 247 .iParallel4 (wR3),
gatedClock 3:659ffc90b59e 248 .iParallel3 (wR3),
gatedClock 3:659ffc90b59e 249 .iParallel2 (wR2),
gatedClock 3:659ffc90b59e 250 .iParallel1 (wR1),
gatedClock 3:659ffc90b59e 251 .iParallel0 (wR0),
gatedClock 7:d1aca9ccbab8 252 .iSel (wSel),
gatedClock 7:d1aca9ccbab8 253 .oSerial (),
gatedClock 7:d1aca9ccbab8 254 .iSerial (1'b0),
gatedClock 7:d1aca9ccbab8 255 .iLoadEnable (wLER3),
gatedClock 7:d1aca9ccbab8 256 .iShiftEnable(1'b0),
gatedClock 7:d1aca9ccbab8 257 .iResetN (wRstn),
gatedClock 7:d1aca9ccbab8 258 .iClk (iCPUclk)
gatedClock 3:659ffc90b59e 259 );
gatedClock 3:659ffc90b59e 260
gatedClock 3:659ffc90b59e 261
gatedClock 3:659ffc90b59e 262
gatedClock 7:d1aca9ccbab8 263 counter_08 U04_PC // CPU program counter.
gatedClock 3:659ffc90b59e 264 (
gatedClock 3:659ffc90b59e 265 .oCount (wPC),
gatedClock 3:659ffc90b59e 266 .iParallel7 (wShadowPC),
gatedClock 3:659ffc90b59e 267 .iParallel6 (wMMD[7:0]),
gatedClock 3:659ffc90b59e 268 .iParallel5 (wImmediate),
gatedClock 3:659ffc90b59e 269 .iParallel4 (wPC),
gatedClock 3:659ffc90b59e 270 .iParallel3 (wR3),
gatedClock 3:659ffc90b59e 271 .iParallel2 (wR2),
gatedClock 3:659ffc90b59e 272 .iParallel1 (wR1),
gatedClock 3:659ffc90b59e 273 .iParallel0 (wR0),
gatedClock 7:d1aca9ccbab8 274 .iSel (wSel),
gatedClock 7:d1aca9ccbab8 275 .oSerial (),
gatedClock 7:d1aca9ccbab8 276 .iSerial (1'b0),
gatedClock 7:d1aca9ccbab8 277 .iLoadEnable (wLEPC),
gatedClock 7:d1aca9ccbab8 278 .iShiftEnable(1'b0),
gatedClock 7:d1aca9ccbab8 279 .iCountEnable(wCEPC),
gatedClock 7:d1aca9ccbab8 280 .iResetN (wRstn),
gatedClock 7:d1aca9ccbab8 281 .iClk (iCPUclk)
gatedClock 3:659ffc90b59e 282 );
gatedClock 3:659ffc90b59e 283
gatedClock 3:659ffc90b59e 284
gatedClock 7:d1aca9ccbab8 285 reg_16 U05_IR // CPU instruction register.
gatedClock 3:659ffc90b59e 286 (
gatedClock 7:d1aca9ccbab8 287 .oParallel (wIR), // IR state.
gatedClock 7:d1aca9ccbab8 288 .iParallel1 (wShadowIR), // IR shadow state.
gatedClock 7:d1aca9ccbab8 289 .iParallel0 (wMMI), // MM output.
gatedClock 7:d1aca9ccbab8 290 .iSel (wSpiControl[2]), // special control.
gatedClock 7:d1aca9ccbab8 291 .oSerial (),
gatedClock 7:d1aca9ccbab8 292 .iSerial (1'b0),
gatedClock 7:d1aca9ccbab8 293 .iLoadEnable (wLEIR),
gatedClock 7:d1aca9ccbab8 294 .iShiftEnable(1'b0),
gatedClock 7:d1aca9ccbab8 295 .iResetN (wRstn),
gatedClock 7:d1aca9ccbab8 296 .iClk (iCPUclk)
gatedClock 3:659ffc90b59e 297 );
gatedClock 3:659ffc90b59e 298
gatedClock 3:659ffc90b59e 299
gatedClock 7:d1aca9ccbab8 300 instruction_decoder U06_ID // instruction decoder.
gatedClock 3:659ffc90b59e 301 (
gatedClock 7:d1aca9ccbab8 302 .iSquelch (wSquelch), // squelch when writing to IR.
gatedClock 7:d1aca9ccbab8 303 .iIR (wIR), // instruction register.
gatedClock 7:d1aca9ccbab8 304 .iBypass (wShadowIR), // IR bypass from SPI.
gatedClock 7:d1aca9ccbab8 305 .iBypassIR (wBypassIR), // bypass the IR.
gatedClock 7:d1aca9ccbab8 306 .oSel (wSel), // common data-in selector.
gatedClock 7:d1aca9ccbab8 307 .oLER0 (wLER0), // R0 load-enable.
gatedClock 7:d1aca9ccbab8 308 .oLER1 (wLER1), // R1 load-enable.
gatedClock 7:d1aca9ccbab8 309 .oLER2 (wLER2), // R2 load-enable.
gatedClock 7:d1aca9ccbab8 310 .oLER3 (wLER3), // R3 load-enable.
gatedClock 7:d1aca9ccbab8 311 .oLEPC (wLEPC), // PC load-enable.
gatedClock 7:d1aca9ccbab8 312 .oWE (wWE), // write-enable pulse.
gatedClock 7:d1aca9ccbab8 313 .oCEPC (wCEPC), // PC count-enable.
gatedClock 7:d1aca9ccbab8 314 .oImmediate(wImmediate) // immediate data.
gatedClock 3:659ffc90b59e 315 );
gatedClock 3:659ffc90b59e 316
gatedClock 3:659ffc90b59e 317
gatedClock 3:659ffc90b59e 318
gatedClock 7:d1aca9ccbab8 319 // main memory:
gatedClock 7:d1aca9ccbab8 320 // the program counter reads from read-port-0.
gatedClock 7:d1aca9ccbab8 321 // the R2:R1 port reads from read-port-1.
gatedClock 7:d1aca9ccbab8 322 // the R2:R1 port writes to the write port.
gatedClock 7:d1aca9ccbab8 323 // the R2:R1 port reads/writes using address from R3.
gatedClock 3:659ffc90b59e 324
gatedClock 3:659ffc90b59e 325
gatedClock 7:d1aca9ccbab8 326 main_memory U07_MM // main-memory.
gatedClock 3:659ffc90b59e 327 (
gatedClock 7:d1aca9ccbab8 328 .iReadAddress1(wR3), // from R3.
gatedClock 7:d1aca9ccbab8 329 .iReadAddress0(wPC), // from PC
gatedClock 7:d1aca9ccbab8 330 .iWriteAddress(wR3), // from R3
gatedClock 7:d1aca9ccbab8 331 .oReadData1 (wMMD), // to <R2:R1>
gatedClock 7:d1aca9ccbab8 332 .oReadData0 (wMMI), // to IR.
gatedClock 7:d1aca9ccbab8 333 .iWriteData ({wR2,wR1}), // from <R2:R1>.
gatedClock 7:d1aca9ccbab8 334 .iWE (wWE), // from the instruction decoder.
gatedClock 7:d1aca9ccbab8 335 .iCPUclk (iCPUclk)
gatedClock 3:659ffc90b59e 336 );
gatedClock 3:659ffc90b59e 337
gatedClock 3:659ffc90b59e 338
gatedClock 7:d1aca9ccbab8 339 // load shadow-registers upon rising
gatedClock 7:d1aca9ccbab8 340 // edge of first SPI clock following
gatedClock 7:d1aca9ccbab8 341 // the falling edge of a CPU clock.
gatedClock 7:d1aca9ccbab8 342 shadow_load_control U08_shadow_load // shadow-register load control.
gatedClock 3:659ffc90b59e 343 (
gatedClock 7:d1aca9ccbab8 344 .iCPUclk(iCPUclk),
gatedClock 7:d1aca9ccbab8 345 .iSPIclk(iSPIclk),
gatedClock 7:d1aca9ccbab8 346 .iRstn(wRstn),
gatedClock 7:d1aca9ccbab8 347 .oLoadEnable(wLoadShadows)
gatedClock 3:659ffc90b59e 348 );
gatedClock 3:659ffc90b59e 349
gatedClock 3:659ffc90b59e 350
gatedClock 3:659ffc90b59e 351 //--- begin SPI shadow-scan section.
gatedClock 3:659ffc90b59e 352
gatedClock 3:659ffc90b59e 353
gatedClock 7:d1aca9ccbab8 354 // the SPI scan registers are generally
gatedClock 7:d1aca9ccbab8 355 // given the term 'shadow registers'.
gatedClock 3:659ffc90b59e 356
gatedClock 3:659ffc90b59e 357
gatedClock 7:d1aca9ccbab8 358 scan_08 U19_spi_control // top of SPI scan chain, used for control.
gatedClock 3:659ffc90b59e 359 (
gatedClock 7:d1aca9ccbab8 360 .oParallel (wSpiControl), // green LED select 7.
gatedClock 7:d1aca9ccbab8 361 .iParallel (wSpiControl), // self-refresh.
gatedClock 7:d1aca9ccbab8 362 .oSerial (oMISO),
gatedClock 7:d1aca9ccbab8 363 .iSerial (wSR0),
gatedClock 7:d1aca9ccbab8 364 .iLoadEnable (wLoadShadows),
gatedClock 7:d1aca9ccbab8 365 .iShiftEnable(1'b1),
gatedClock 7:d1aca9ccbab8 366 .iResetN (wRstn),
gatedClock 7:d1aca9ccbab8 367 .iClk (iSPIclk)
gatedClock 3:659ffc90b59e 368 );
gatedClock 3:659ffc90b59e 369
gatedClock 3:659ffc90b59e 370
gatedClock 3:659ffc90b59e 371
gatedClock 7:d1aca9ccbab8 372 scan_08 U20_shadowR0 // R0 shadow register.
gatedClock 3:659ffc90b59e 373 (
gatedClock 7:d1aca9ccbab8 374 .oParallel (wShadow0), // green LED select 6.
gatedClock 3:659ffc90b59e 375 .iParallel (wR0),
gatedClock 7:d1aca9ccbab8 376 .oSerial (wSR0),
gatedClock 7:d1aca9ccbab8 377 .iSerial (wSR1),
gatedClock 7:d1aca9ccbab8 378 .iLoadEnable (wLoadShadows),
gatedClock 7:d1aca9ccbab8 379 .iShiftEnable(1'b1),
gatedClock 7:d1aca9ccbab8 380 .iResetN (wRstn),
gatedClock 7:d1aca9ccbab8 381 .iClk (iSPIclk)
gatedClock 3:659ffc90b59e 382 );
gatedClock 3:659ffc90b59e 383
gatedClock 7:d1aca9ccbab8 384 scan_08 U21_shadowR1 // R1 shadow register.
gatedClock 3:659ffc90b59e 385 (
gatedClock 7:d1aca9ccbab8 386 .oParallel (wShadow1), // green LED select 5.
gatedClock 3:659ffc90b59e 387 .iParallel (wR1),
gatedClock 7:d1aca9ccbab8 388 .oSerial (wSR1),
gatedClock 7:d1aca9ccbab8 389 .iSerial (wSR2),
gatedClock 7:d1aca9ccbab8 390 .iLoadEnable (wLoadShadows),
gatedClock 7:d1aca9ccbab8 391 .iShiftEnable(1'b1),
gatedClock 7:d1aca9ccbab8 392 .iResetN (wRstn),
gatedClock 7:d1aca9ccbab8 393 .iClk (iSPIclk)
gatedClock 3:659ffc90b59e 394 );
gatedClock 3:659ffc90b59e 395
gatedClock 7:d1aca9ccbab8 396 scan_08 U22_shadowR2 // R2 shadow register.
gatedClock 3:659ffc90b59e 397 (
gatedClock 7:d1aca9ccbab8 398 .oParallel (wShadow2), // green LED select 4.
gatedClock 3:659ffc90b59e 399 .iParallel (wR2),
gatedClock 7:d1aca9ccbab8 400 .oSerial (wSR2),
gatedClock 7:d1aca9ccbab8 401 .iSerial (wSR3),
gatedClock 7:d1aca9ccbab8 402 .iLoadEnable (wLoadShadows),
gatedClock 7:d1aca9ccbab8 403 .iShiftEnable(1'b1),
gatedClock 7:d1aca9ccbab8 404 .iResetN (wRstn),
gatedClock 7:d1aca9ccbab8 405 .iClk (iSPIclk)
gatedClock 3:659ffc90b59e 406 );
gatedClock 3:659ffc90b59e 407
gatedClock 7:d1aca9ccbab8 408 scan_08 U23_shadowR3 // R3 shadow register.
gatedClock 3:659ffc90b59e 409 (
gatedClock 7:d1aca9ccbab8 410 .oParallel (wShadow3), // green LED select 3.
gatedClock 3:659ffc90b59e 411 .iParallel (wR3),
gatedClock 7:d1aca9ccbab8 412 .oSerial (wSR3),
gatedClock 7:d1aca9ccbab8 413 .iSerial (wSPC),
gatedClock 7:d1aca9ccbab8 414 .iLoadEnable (wLoadShadows),
gatedClock 7:d1aca9ccbab8 415 .iShiftEnable(1'b1),
gatedClock 7:d1aca9ccbab8 416 .iResetN (wRstn),
gatedClock 7:d1aca9ccbab8 417 .iClk (iSPIclk)
gatedClock 3:659ffc90b59e 418 );
gatedClock 3:659ffc90b59e 419
gatedClock 7:d1aca9ccbab8 420 scan_08 U24_shadowPC // program-counter shadow register.
gatedClock 3:659ffc90b59e 421 (
gatedClock 7:d1aca9ccbab8 422 .oParallel (wShadowPC), // green LED select 2.
gatedClock 3:659ffc90b59e 423 .iParallel (wPC),
gatedClock 7:d1aca9ccbab8 424 .oSerial (wSPC),
gatedClock 7:d1aca9ccbab8 425 .iSerial (wSIR),
gatedClock 7:d1aca9ccbab8 426 .iLoadEnable (wLoadShadows),
gatedClock 7:d1aca9ccbab8 427 .iShiftEnable(1'b1),
gatedClock 7:d1aca9ccbab8 428 .iResetN (wRstn),
gatedClock 7:d1aca9ccbab8 429 .iClk (iSPIclk)
gatedClock 3:659ffc90b59e 430 );
gatedClock 3:659ffc90b59e 431
gatedClock 7:d1aca9ccbab8 432 scan_16 U25_shadowIR // instruction-register shadow register.
gatedClock 3:659ffc90b59e 433 (
gatedClock 7:d1aca9ccbab8 434 .oParallel (wShadowIR), // green LED select 1,0.
gatedClock 3:659ffc90b59e 435 .iParallel (wIR),
gatedClock 7:d1aca9ccbab8 436 .oSerial (wSIR),
gatedClock 7:d1aca9ccbab8 437 .iSerial (iMOSI),
gatedClock 7:d1aca9ccbab8 438 .iLoadEnable (wLoadShadows),
gatedClock 7:d1aca9ccbab8 439 .iShiftEnable(1'b1),
gatedClock 7:d1aca9ccbab8 440 .iResetN (wRstn),
gatedClock 7:d1aca9ccbab8 441 .iClk (iSPIclk)
gatedClock 3:659ffc90b59e 442 );
gatedClock 3:659ffc90b59e 443
gatedClock 3:659ffc90b59e 444
gatedClock 3:659ffc90b59e 445
gatedClock 3:659ffc90b59e 446 //--- begin green LED signal-monitoring section.
gatedClock 3:659ffc90b59e 447
gatedClock 3:659ffc90b59e 448
gatedClock 3:659ffc90b59e 449
gatedClock 7:d1aca9ccbab8 450 mux8x16 U30_green_led_mux // green LED diagnostic mux.
gatedClock 3:659ffc90b59e 451 (
gatedClock 7:d1aca9ccbab8 452 .iDin15({wLER0,wLER1,wLER2,wLER3,wLEPC,wLEIR,wWE,wCEPC}),
gatedClock 7:d1aca9ccbab8 453 .iDin14(wIR[15:8]), // IR-H.
gatedClock 7:d1aca9ccbab8 454 .iDin13(wIR[7:0]), // IR-L.
gatedClock 7:d1aca9ccbab8 455 .iDin12(wPC), // PC.
gatedClock 7:d1aca9ccbab8 456 .iDin11(wR3), // R3.
gatedClock 7:d1aca9ccbab8 457 .iDin10(wR2), // R2.
gatedClock 7:d1aca9ccbab8 458 .iDin9 (wR1), // R1.
gatedClock 7:d1aca9ccbab8 459 .iDin8 (wR0), // R0.
gatedClock 7:d1aca9ccbab8 460 .iDin7 (wSpiControl), // SPI control.
gatedClock 7:d1aca9ccbab8 461 .iDin6 (wShadowIR[15:8]), // IR-H shadow.
gatedClock 7:d1aca9ccbab8 462 .iDin5 (wShadowIR[7:0]), // IR-L shadow.
gatedClock 7:d1aca9ccbab8 463 .iDin4 (wShadowPC), // PC shadow.
gatedClock 7:d1aca9ccbab8 464 .iDin3 (wShadow3), // R3 shadow.
gatedClock 7:d1aca9ccbab8 465 .iDin2 (wShadow2), // R2 shadow.
gatedClock 7:d1aca9ccbab8 466 .iDin1 (wShadow1), // R1 shadow.
gatedClock 7:d1aca9ccbab8 467 .iDin0 (wShadow0), // R0 shadow.
gatedClock 7:d1aca9ccbab8 468 .iSel (iSW[3:0]), // mux-select.
gatedClock 7:d1aca9ccbab8 469 .oDout (oLEDG) // to green LED bank.
gatedClock 3:659ffc90b59e 470 );
gatedClock 3:659ffc90b59e 471 /*-----------------------------------logic------//----------------------------*/
gatedClock 7:d1aca9ccbab8 472 assign wRstn = iKEY[0]; // pushbutton system reset.
gatedClock 7:d1aca9ccbab8 473 assign wSquelch = wSpiControl[2]; // for python squelching ins. decode.
gatedClock 7:d1aca9ccbab8 474 assign wBypassIR = wSpiControl[1]; // for python controlling CPU.
gatedClock 7:d1aca9ccbab8 475 assign wTrigger = wSpiControl[7:4]; // for signaltap triggering, not used.
gatedClock 3:659ffc90b59e 476
gatedClock 7:d1aca9ccbab8 477 // load instruction register
gatedClock 7:d1aca9ccbab8 478 // if neither or both shadow
gatedClock 7:d1aca9ccbab8 479 // control signals asserted.
gatedClock 7:d1aca9ccbab8 480 assign wLEIR = !(wSquelch ^ wBypassIR);
gatedClock 3:659ffc90b59e 481
gatedClock 3:659ffc90b59e 482
gatedClock 7:d1aca9ccbab8 483 assign oLEDR[9] = 1'b0; // red LED hookup.
gatedClock 7:d1aca9ccbab8 484 assign oLEDR[8] = 1'b0;
gatedClock 7:d1aca9ccbab8 485 assign oLEDR[7] = wSel[2];
gatedClock 7:d1aca9ccbab8 486 assign oLEDR[6] = wSel[1];
gatedClock 7:d1aca9ccbab8 487 assign oLEDR[5] = wSel[0];
gatedClock 7:d1aca9ccbab8 488 assign oLEDR[4] = wRstn;
gatedClock 7:d1aca9ccbab8 489 assign oLEDR[3] = iCPUclk;
gatedClock 7:d1aca9ccbab8 490 assign oLEDR[2] = oMISO;
gatedClock 7:d1aca9ccbab8 491 assign oLEDR[1] = iMOSI;
gatedClock 7:d1aca9ccbab8 492 assign oLEDR[0] = iSPIclk;
gatedClock 3:659ffc90b59e 493
gatedClock 3:659ffc90b59e 494
gatedClock 7:d1aca9ccbab8 495 // signals not to be optimized
gatedClock 7:d1aca9ccbab8 496 // out, place here.
gatedClock 7:d1aca9ccbab8 497 assign oDummyLoad = (|wShadowIR) | wSIR | (|wSpiControl) | (|wTrigger);
gatedClock 3:659ffc90b59e 498 /*-------------------------------*/endmodule/*--------------------------------*/
gatedClock 3:659ffc90b59e 499
gatedClock 3:659ffc90b59e 500
gatedClock 3:659ffc90b59e 501
gatedClock 3:659ffc90b59e 502
gatedClock 3:659ffc90b59e 503
gatedClock 3:659ffc90b59e 504
gatedClock 3:659ffc90b59e 505
gatedClock 3:659ffc90b59e 506
gatedClock 3:659ffc90b59e 507
gatedClock 3:659ffc90b59e 508
gatedClock 3:659ffc90b59e 509
gatedClock 3:659ffc90b59e 510
gatedClock 3:659ffc90b59e 511
gatedClock 3:659ffc90b59e 512
gatedClock 3:659ffc90b59e 513
gatedClock 3:659ffc90b59e 514
gatedClock 7:d1aca9ccbab8 515
gatedClock 7:d1aca9ccbab8 516
gatedClock 7:d1aca9ccbab8 517
gatedClock 7:d1aca9ccbab8 518
gatedClock 7:d1aca9ccbab8 519
gatedClock 7:d1aca9ccbab8 520
gatedClock 7:d1aca9ccbab8 521
gatedClock 7:d1aca9ccbab8 522
gatedClock 7:d1aca9ccbab8 523
gatedClock 7:d1aca9ccbab8 524
gatedClock 7:d1aca9ccbab8 525
gatedClock 7:d1aca9ccbab8 526
gatedClock 7:d1aca9ccbab8 527
gatedClock 7:d1aca9ccbab8 528
gatedClock 7:d1aca9ccbab8 529
gatedClock 7:d1aca9ccbab8 530
gatedClock 7:d1aca9ccbab8 531