Mike Moore / Mbed 2 deprecated USB_device_project

USB Device Programming class project. This project allows a Python/Tk program running on a PC host to monitor/control a test-CPU programmed into an altera development board.

Dependencies:   C12832_lcd USBDevice mbed-rtos mbed mmSPI

mmRTL/cpu.txt@3:659ffc90b59e, 2013-09-01 (annotated)

Committer:
gatedClock
Date:
Sun Sep 01 02:53:39 2013 +0000
Revision:
3:659ffc90b59e
Child:
7:d1aca9ccbab8
add the project RTL files.  the tab-formatting needs to be redone.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 3:659ffc90b59e 1 /*----------------------------------copyright---//----------------------------*/
gatedClock 3:659ffc90b59e 2 // licensed for personal and academic use.
gatedClock 3:659ffc90b59e 3 // commercial use must be approved by the account-holder of
gatedClock 3:659ffc90b59e 4 // gated.clock@gmail.com
gatedClock 3:659ffc90b59e 5 /*-----------------------------------module-----//----------------------------*/
gatedClock 3:659ffc90b59e 6 module cpu
gatedClock 3:659ffc90b59e 7 (
gatedClock 3:659ffc90b59e 8 iMOSI,
gatedClock 3:659ffc90b59e 9 oMISO,
gatedClock 3:659ffc90b59e 10 iSPIclk,
gatedClock 3:659ffc90b59e 11 iCPUclk,
gatedClock 3:659ffc90b59e 12 iKEY,
gatedClock 3:659ffc90b59e 13 iSW,
gatedClock 3:659ffc90b59e 14 oLEDR,
gatedClock 3:659ffc90b59e 15 oLEDG,
gatedClock 3:659ffc90b59e 16 oDummyLoad
gatedClock 3:659ffc90b59e 17 );
gatedClock 3:659ffc90b59e 18 /*--------------------------------description---//------------------------------
gatedClock 3:659ffc90b59e 19 the demonstration cpu datapath.
gatedClock 3:659ffc90b59e 20
gatedClock 3:659ffc90b59e 21 the CPU consists of
gatedClock 3:659ffc90b59e 22 R0 - 8-bit register and accumulator.
gatedClock 3:659ffc90b59e 23 R1 - 8-bit register and main-memory address register.
gatedClock 3:659ffc90b59e 24 R2 - 8-bit register and main-memory high data byte.
gatedClock 3:659ffc90b59e 25 R3 - 8-bit register and main-memory low data byte.
gatedClock 3:659ffc90b59e 26 PC - 8-bit program counter.
gatedClock 3:659ffc90b59e 27 IR - 16-bit instruction register.
gatedClock 3:659ffc90b59e 28 ID - combinatorial instruction decoder.
gatedClock 3:659ffc90b59e 29 MM - 16-bit-wide x 256-address Main Memory.
gatedClock 3:659ffc90b59e 30
gatedClock 3:659ffc90b59e 31 the instruction words is sixteen bits long, and is comprised of
gatedClock 3:659ffc90b59e 32 <15:13> = source resource.
gatedClock 3:659ffc90b59e 33 <12:10> = destination resource.
gatedClock 3:659ffc90b59e 34 < 9> = write-enable.
gatedClock 3:659ffc90b59e 35 < 8> = program-counter-enable.
gatedClock 3:659ffc90b59e 36 < 7: 0> = immediate data.
gatedClock 3:659ffc90b59e 37
gatedClock 3:659ffc90b59e 38 the registers (U00 through U05) have a iSel input which define the source.
gatedClock 3:659ffc90b59e 39 the instruction decoder (U06) enables the loading of the destinations.
gatedClock 3:659ffc90b59e 40
gatedClock 3:659ffc90b59e 41 the SPI shadow registers (U19-U25) monitor the CPU state, and can
gatedClock 3:659ffc90b59e 42 control the CPU state by asserting U19's bits 1 and 2.
gatedClock 3:659ffc90b59e 43
gatedClock 3:659ffc90b59e 44 U08 provides a shadow register load-enable pulse which
gatedClock 3:659ffc90b59e 45 begins at the falling edge of a CPU clock and ends at
gatedClock 3:659ffc90b59e 46 the falling edge of the next SPI clock, allowing the shadow
gatedClock 3:659ffc90b59e 47 registers the ability to capture the state of the CPU.
gatedClock 3:659ffc90b59e 48
gatedClock 3:659ffc90b59e 49 U30 routes internal nets out to the green LED bank according
gatedClock 3:659ffc90b59e 50 to the setting of switches SW<3:0>.
gatedClock 3:659ffc90b59e 51
gatedClock 3:659ffc90b59e 52 -------------------------------------notes------//------------------------------
gatedClock 3:659ffc90b59e 53
gatedClock 3:659ffc90b59e 54 fpga board pin assignments.
gatedClock 3:659ffc90b59e 55
gatedClock 3:659ffc90b59e 56
gatedClock 3:659ffc90b59e 57 project:
gatedClock 3:659ffc90b59e 58 MOSI P17
gatedClock 3:659ffc90b59e 59 MISO D15
gatedClock 3:659ffc90b59e 60 SPIclk E20
gatedClock 3:659ffc90b59e 61 CPUclk E14
gatedClock 3:659ffc90b59e 62
gatedClock 3:659ffc90b59e 63
gatedClock 3:659ffc90b59e 64 key3 T21
gatedClock 3:659ffc90b59e 65 key2 T22
gatedClock 3:659ffc90b59e 66 key1 R21
gatedClock 3:659ffc90b59e 67 key0 R22 iRstn
gatedClock 3:659ffc90b59e 68
gatedClock 3:659ffc90b59e 69 sw9 L2
gatedClock 3:659ffc90b59e 70 sw8 M1
gatedClock 3:659ffc90b59e 71 sw7 M2
gatedClock 3:659ffc90b59e 72 sw6 U11
gatedClock 3:659ffc90b59e 73 sw5 U12
gatedClock 3:659ffc90b59e 74 sw4 W12
gatedClock 3:659ffc90b59e 75 sw3 V12
gatedClock 3:659ffc90b59e 76 sw2 M22
gatedClock 3:659ffc90b59e 77 sw1 L21
gatedClock 3:659ffc90b59e 78 sw0 L22
gatedClock 3:659ffc90b59e 79
gatedClock 3:659ffc90b59e 80 ledr9 R17
gatedClock 3:659ffc90b59e 81 ledr8 R18
gatedClock 3:659ffc90b59e 82 ledr7 U18
gatedClock 3:659ffc90b59e 83 ledr6 Y18
gatedClock 3:659ffc90b59e 84 ledr5 V19
gatedClock 3:659ffc90b59e 85 ledr4 T18
gatedClock 3:659ffc90b59e 86 ledr3 Y19
gatedClock 3:659ffc90b59e 87 ledr2 U19
gatedClock 3:659ffc90b59e 88 ledr1 R19
gatedClock 3:659ffc90b59e 89 ledr0 R20
gatedClock 3:659ffc90b59e 90
gatedClock 3:659ffc90b59e 91 ledg7 Y21
gatedClock 3:659ffc90b59e 92 ledg6 Y22
gatedClock 3:659ffc90b59e 93 ledg5 W21
gatedClock 3:659ffc90b59e 94 ledg4 W22
gatedClock 3:659ffc90b59e 95 ledg3 V21
gatedClock 3:659ffc90b59e 96 ledg2 V22
gatedClock 3:659ffc90b59e 97 ledg1 U21
gatedClock 3:659ffc90b59e 98 ledg0 U22
gatedClock 3:659ffc90b59e 99 ------------------------------------defines-----//----------------------------*/
gatedClock 3:659ffc90b59e 100 /*-----------------------------------ports------//----------------------------*/
gatedClock 3:659ffc90b59e 101 input iMOSI; // SPI input.
gatedClock 3:659ffc90b59e 102 output oMISO; // SPI output.
gatedClock 3:659ffc90b59e 103 input iSPIclk; // SPI clock.
gatedClock 3:659ffc90b59e 104 input iCPUclk; // CPU clock.
gatedClock 3:659ffc90b59e 105 input [ 3:0] iKEY; // keypress.
gatedClock 3:659ffc90b59e 106 input [ 9:0] iSW; // slide-switches.
gatedClock 3:659ffc90b59e 107 output [ 9:0] oLEDR; // red LED bank.
gatedClock 3:659ffc90b59e 108 output [ 7:0] oLEDG; // green LED bank.
gatedClock 3:659ffc90b59e 109 output oDummyLoad; // anti-optimization.
gatedClock 3:659ffc90b59e 110 /*-----------------------------------wires------//----------------------------*/
gatedClock 3:659ffc90b59e 111 wire iMOSI; // SPI input.
gatedClock 3:659ffc90b59e 112 wire oMISO; // SPI output.
gatedClock 3:659ffc90b59e 113 wire iSPIclk; // SPI clock.
gatedClock 3:659ffc90b59e 114 wire iCPUclk; // CPU clock.
gatedClock 3:659ffc90b59e 115 wire [ 3:0] iKEY; // keypress.
gatedClock 3:659ffc90b59e 116 wire [ 9:0] iSW; // slide-switches.
gatedClock 3:659ffc90b59e 117 wire [ 9:0] oLEDR; // red LED bank.
gatedClock 3:659ffc90b59e 118 wire [ 7:0] oLEDG; // green LED bank.
gatedClock 3:659ffc90b59e 119
gatedClock 3:659ffc90b59e 120 wire wCEPC; // program counter count-enable.
gatedClock 3:659ffc90b59e 121 wire [15:0] wIR; // instruction register.
gatedClock 3:659ffc90b59e 122 wire wLEIR; // instruction register load-enable.
gatedClock 3:659ffc90b59e 123 wire wLEPC; // program counter load-enable.
gatedClock 3:659ffc90b59e 124 wire wLER0; // R0 load-enable.
gatedClock 3:659ffc90b59e 125 wire wLER1; // R1 load-enable.
gatedClock 3:659ffc90b59e 126 wire wLER2; // R2 load-enable.
gatedClock 3:659ffc90b59e 127 wire wLER3; // R3 load-enable.
gatedClock 3:659ffc90b59e 128 wire [15:0] wMMD; // main-memory data-out.
gatedClock 3:659ffc90b59e 129 wire [15:0] wMMI; // main-memory instruction-out.
gatedClock 3:659ffc90b59e 130 wire [ 7:0] wPC; // program-counter.
gatedClock 3:659ffc90b59e 131 wire [ 7:0] wR0; // R0.
gatedClock 3:659ffc90b59e 132 wire [ 7:0] wR1; // R1.
gatedClock 3:659ffc90b59e 133 wire [ 7:0] wR2; // R2.
gatedClock 3:659ffc90b59e 134 wire [ 7:0] wR3; // R3.
gatedClock 3:659ffc90b59e 135 wire wRstn; // system reset.
gatedClock 3:659ffc90b59e 136 wire [ 2:0] wSel; // common data-in selector.
gatedClock 3:659ffc90b59e 137 wire [ 7:0] wShadow0; // R0 shadow register.
gatedClock 3:659ffc90b59e 138 wire [ 7:0] wShadow1; // R1 shadow register.
gatedClock 3:659ffc90b59e 139 wire [ 7:0] wShadow2; // R2 shadow register.
gatedClock 3:659ffc90b59e 140 wire [ 7:0] wShadow3; // R3 shadow register.
gatedClock 3:659ffc90b59e 141 wire [15:0] wShadowIR; // instruction register shadow.
gatedClock 3:659ffc90b59e 142 wire [ 7:0] wShadowPC; // program counter shadow.
gatedClock 3:659ffc90b59e 143 wire wSIR; // instruction register shadow shift-up.
gatedClock 3:659ffc90b59e 144 wire wSPC; // program counter shadow shift-up.
gatedClock 3:659ffc90b59e 145 wire wSR0; // R0 shadow shift-up.
gatedClock 3:659ffc90b59e 146 wire wSR1; // R1 shadow shift-up.
gatedClock 3:659ffc90b59e 147 wire wSR2; // R2 shadow shift-up.
gatedClock 3:659ffc90b59e 148 wire wSR3; // R3 shadow shift-up.
gatedClock 3:659ffc90b59e 149 wire wWE; // write-enable pulse.
gatedClock 3:659ffc90b59e 150 wire [ 7:0] wImmediate; // immediate data.
gatedClock 3:659ffc90b59e 151 wire [ 7:0] wSpiControl; // from spi control register.
gatedClock 3:659ffc90b59e 152 wire wSquelch; // from spi control register.
gatedClock 3:659ffc90b59e 153 wire wBypassIR; // from spi control register.
gatedClock 3:659ffc90b59e 154 wire wLoadShadows; // shadow registers parallel load.
gatedClock 3:659ffc90b59e 155
gatedClock 3:659ffc90b59e 156 // not currently used.
gatedClock 3:659ffc90b59e 157 wire [ 7:0] wGreenLEDBus7; // green LED bus.
gatedClock 3:659ffc90b59e 158 wire [ 7:0] wGreenLEDBus6; // green LED bus.
gatedClock 3:659ffc90b59e 159 wire [ 7:0] wGreenLEDBus5; // green LED bus.
gatedClock 3:659ffc90b59e 160 wire [ 7:0] wGreenLEDBus4; // green LED bus.
gatedClock 3:659ffc90b59e 161 wire [ 7:0] wGreenLEDBus3; // green LED bus.
gatedClock 3:659ffc90b59e 162 wire [ 7:0] wGreenLEDBus2; // green LED bus.
gatedClock 3:659ffc90b59e 163 wire [ 7:0] wGreenLEDBus1; // green LED bus.
gatedClock 3:659ffc90b59e 164 wire [ 7:0] wGreenLEDBus0; // green LED bus.
gatedClock 3:659ffc90b59e 165 wire oDummyLoad; // anti-optimization.
gatedClock 3:659ffc90b59e 166 wire [ 3:0] wTrigger; // trigger control.
gatedClock 3:659ffc90b59e 167 /*---------------------------------registers----//----------------------------*/
gatedClock 3:659ffc90b59e 168 /*---------------------------------variables----//----------------------------*/
gatedClock 3:659ffc90b59e 169 /*---------------------------------parameters---//----------------------------*/
gatedClock 3:659ffc90b59e 170 /*-----------------------------------clocks-----//----------------------------*/
gatedClock 3:659ffc90b59e 171 /*---------------------------------instances----//----------------------------*/
gatedClock 3:659ffc90b59e 172
gatedClock 3:659ffc90b59e 173 //--- begin regular CPU section.
gatedClock 3:659ffc90b59e 174
gatedClock 3:659ffc90b59e 175
gatedClock 3:659ffc90b59e 176 reg_08 U00_R0 // CPU R0.
gatedClock 3:659ffc90b59e 177 (
gatedClock 3:659ffc90b59e 178 .oParallel (wR0),
gatedClock 3:659ffc90b59e 179 .iParallel7 (wShadow0),
gatedClock 3:659ffc90b59e 180 .iParallel6 (wR1 + wR2), // adder.
gatedClock 3:659ffc90b59e 181 .iParallel5 (wImmediate),
gatedClock 3:659ffc90b59e 182 .iParallel4 (wR0),
gatedClock 3:659ffc90b59e 183 .iParallel3 (wR3),
gatedClock 3:659ffc90b59e 184 .iParallel2 (wR2),
gatedClock 3:659ffc90b59e 185 .iParallel1 (wR1),
gatedClock 3:659ffc90b59e 186 .iParallel0 (wR0), // needed for zero vector no-op.
gatedClock 3:659ffc90b59e 187 .iSel (wSel),
gatedClock 3:659ffc90b59e 188 .oSerial (),
gatedClock 3:659ffc90b59e 189 .iSerial (1'b0),
gatedClock 3:659ffc90b59e 190 .iLoadEnable (wLER0),
gatedClock 3:659ffc90b59e 191 .iShiftEnable(1'b0),
gatedClock 3:659ffc90b59e 192 .iResetN (wRstn),
gatedClock 3:659ffc90b59e 193 .iClk (iCPUclk)
gatedClock 3:659ffc90b59e 194 );
gatedClock 3:659ffc90b59e 195
gatedClock 3:659ffc90b59e 196
gatedClock 3:659ffc90b59e 197
gatedClock 3:659ffc90b59e 198 reg_08 U01_R1 // CPU R1.
gatedClock 3:659ffc90b59e 199 (
gatedClock 3:659ffc90b59e 200 .oParallel (wR1),
gatedClock 3:659ffc90b59e 201 .iParallel7 (wShadow1),
gatedClock 3:659ffc90b59e 202 .iParallel6 (wMMD[7:0]),
gatedClock 3:659ffc90b59e 203 .iParallel5 (wImmediate),
gatedClock 3:659ffc90b59e 204 .iParallel4 (wR1),
gatedClock 3:659ffc90b59e 205 .iParallel3 (wR3),
gatedClock 3:659ffc90b59e 206 .iParallel2 (wR2),
gatedClock 3:659ffc90b59e 207 .iParallel1 (wR1),
gatedClock 3:659ffc90b59e 208 .iParallel0 (wR0),
gatedClock 3:659ffc90b59e 209 .iSel (wSel),
gatedClock 3:659ffc90b59e 210 .oSerial (),
gatedClock 3:659ffc90b59e 211 .iSerial (1'b0),
gatedClock 3:659ffc90b59e 212 .iLoadEnable (wLER1),
gatedClock 3:659ffc90b59e 213 .iShiftEnable(1'b0),
gatedClock 3:659ffc90b59e 214 .iResetN (wRstn),
gatedClock 3:659ffc90b59e 215 .iClk (iCPUclk)
gatedClock 3:659ffc90b59e 216 );
gatedClock 3:659ffc90b59e 217
gatedClock 3:659ffc90b59e 218
gatedClock 3:659ffc90b59e 219
gatedClock 3:659ffc90b59e 220 reg_08 U02_R2 // CPU R2.
gatedClock 3:659ffc90b59e 221 (
gatedClock 3:659ffc90b59e 222 .oParallel (wR2),
gatedClock 3:659ffc90b59e 223 .iParallel7 (wShadow2),
gatedClock 3:659ffc90b59e 224 .iParallel6 (wMMD[15:8]),
gatedClock 3:659ffc90b59e 225 .iParallel5 (wImmediate),
gatedClock 3:659ffc90b59e 226 .iParallel4 (wR2),
gatedClock 3:659ffc90b59e 227 .iParallel3 (wR3),
gatedClock 3:659ffc90b59e 228 .iParallel2 (wR2),
gatedClock 3:659ffc90b59e 229 .iParallel1 (wR1),
gatedClock 3:659ffc90b59e 230 .iParallel0 (wR0),
gatedClock 3:659ffc90b59e 231 .iSel (wSel),
gatedClock 3:659ffc90b59e 232 .oSerial (),
gatedClock 3:659ffc90b59e 233 .iSerial (1'b0),
gatedClock 3:659ffc90b59e 234 .iLoadEnable (wLER2),
gatedClock 3:659ffc90b59e 235 .iShiftEnable(1'b0),
gatedClock 3:659ffc90b59e 236 .iResetN (wRstn),
gatedClock 3:659ffc90b59e 237 .iClk (iCPUclk)
gatedClock 3:659ffc90b59e 238 );
gatedClock 3:659ffc90b59e 239
gatedClock 3:659ffc90b59e 240
gatedClock 3:659ffc90b59e 241 reg_08 U03_R3 // CPU R3.
gatedClock 3:659ffc90b59e 242 (
gatedClock 3:659ffc90b59e 243 .oParallel (wR3),
gatedClock 3:659ffc90b59e 244 .iParallel7 (wShadow3),
gatedClock 3:659ffc90b59e 245 .iParallel6 (wMMD[7:0]),
gatedClock 3:659ffc90b59e 246 .iParallel5 (wImmediate),
gatedClock 3:659ffc90b59e 247 .iParallel4 (wR3),
gatedClock 3:659ffc90b59e 248 .iParallel3 (wR3),
gatedClock 3:659ffc90b59e 249 .iParallel2 (wR2),
gatedClock 3:659ffc90b59e 250 .iParallel1 (wR1),
gatedClock 3:659ffc90b59e 251 .iParallel0 (wR0),
gatedClock 3:659ffc90b59e 252 .iSel (wSel),
gatedClock 3:659ffc90b59e 253 .oSerial (),
gatedClock 3:659ffc90b59e 254 .iSerial (1'b0),
gatedClock 3:659ffc90b59e 255 .iLoadEnable (wLER3),
gatedClock 3:659ffc90b59e 256 .iShiftEnable(1'b0),
gatedClock 3:659ffc90b59e 257 .iResetN (wRstn),
gatedClock 3:659ffc90b59e 258 .iClk (iCPUclk)
gatedClock 3:659ffc90b59e 259 );
gatedClock 3:659ffc90b59e 260
gatedClock 3:659ffc90b59e 261
gatedClock 3:659ffc90b59e 262
gatedClock 3:659ffc90b59e 263 counter_08 U04_PC // CPU program counter.
gatedClock 3:659ffc90b59e 264 (
gatedClock 3:659ffc90b59e 265 .oCount (wPC),
gatedClock 3:659ffc90b59e 266 .iParallel7 (wShadowPC),
gatedClock 3:659ffc90b59e 267 .iParallel6 (wMMD[7:0]),
gatedClock 3:659ffc90b59e 268 .iParallel5 (wImmediate),
gatedClock 3:659ffc90b59e 269 .iParallel4 (wPC),
gatedClock 3:659ffc90b59e 270 .iParallel3 (wR3),
gatedClock 3:659ffc90b59e 271 .iParallel2 (wR2),
gatedClock 3:659ffc90b59e 272 .iParallel1 (wR1),
gatedClock 3:659ffc90b59e 273 .iParallel0 (wR0),
gatedClock 3:659ffc90b59e 274 .iSel (wSel),
gatedClock 3:659ffc90b59e 275 .oSerial (),
gatedClock 3:659ffc90b59e 276 .iSerial (1'b0),
gatedClock 3:659ffc90b59e 277 .iLoadEnable (wLEPC),
gatedClock 3:659ffc90b59e 278 .iShiftEnable(1'b0),
gatedClock 3:659ffc90b59e 279 .iCountEnable(wCEPC),
gatedClock 3:659ffc90b59e 280 .iResetN (wRstn),
gatedClock 3:659ffc90b59e 281 .iClk (iCPUclk)
gatedClock 3:659ffc90b59e 282 );
gatedClock 3:659ffc90b59e 283
gatedClock 3:659ffc90b59e 284
gatedClock 3:659ffc90b59e 285 reg_16 U05_IR // CPU instruction register.
gatedClock 3:659ffc90b59e 286 (
gatedClock 3:659ffc90b59e 287 .oParallel (wIR), // IR state.
gatedClock 3:659ffc90b59e 288 .iParallel1 (wShadowIR), // IR shadow state.
gatedClock 3:659ffc90b59e 289 .iParallel0 (wMMI), // MM output.
gatedClock 3:659ffc90b59e 290 .iSel (wSpiControl[2]), // special control.
gatedClock 3:659ffc90b59e 291 .oSerial (),
gatedClock 3:659ffc90b59e 292 .iSerial (1'b0),
gatedClock 3:659ffc90b59e 293 .iLoadEnable (wLEIR),
gatedClock 3:659ffc90b59e 294 .iShiftEnable(1'b0),
gatedClock 3:659ffc90b59e 295 .iResetN (wRstn),
gatedClock 3:659ffc90b59e 296 .iClk (iCPUclk)
gatedClock 3:659ffc90b59e 297 );
gatedClock 3:659ffc90b59e 298
gatedClock 3:659ffc90b59e 299
gatedClock 3:659ffc90b59e 300 instruction_decoder U06_ID // instruction decoder.
gatedClock 3:659ffc90b59e 301 (
gatedClock 3:659ffc90b59e 302 .iSquelch (wSquelch), // squelch when writing to IR.
gatedClock 3:659ffc90b59e 303 .iIR (wIR), // instruction register.
gatedClock 3:659ffc90b59e 304 .iBypass (wShadowIR), // IR bypass from SPI.
gatedClock 3:659ffc90b59e 305 .iBypassIR (wBypassIR), // bypass the IR.
gatedClock 3:659ffc90b59e 306 .oSel (wSel), // common data-in selector.
gatedClock 3:659ffc90b59e 307 .oLER0 (wLER0), // R0 load-enable.
gatedClock 3:659ffc90b59e 308 .oLER1 (wLER1), // R1 load-enable.
gatedClock 3:659ffc90b59e 309 .oLER2 (wLER2), // R2 load-enable.
gatedClock 3:659ffc90b59e 310 .oLER3 (wLER3), // R3 load-enable.
gatedClock 3:659ffc90b59e 311 .oLEPC (wLEPC), // PC load-enable.
gatedClock 3:659ffc90b59e 312 .oWE (wWE), // write-enable pulse.
gatedClock 3:659ffc90b59e 313 .oCEPC (wCEPC), // PC count-enable.
gatedClock 3:659ffc90b59e 314 .oImmediate(wImmediate) // immediate data.
gatedClock 3:659ffc90b59e 315 );
gatedClock 3:659ffc90b59e 316
gatedClock 3:659ffc90b59e 317
gatedClock 3:659ffc90b59e 318
gatedClock 3:659ffc90b59e 319 // main memory:
gatedClock 3:659ffc90b59e 320 // the program counter reads from read-port-0.
gatedClock 3:659ffc90b59e 321 // the R2:R1 port reads from read-port-1.
gatedClock 3:659ffc90b59e 322 // the R2:R1 port writes to the write port.
gatedClock 3:659ffc90b59e 323 // the R2:R1 port reads/writes using address from R3.
gatedClock 3:659ffc90b59e 324
gatedClock 3:659ffc90b59e 325
gatedClock 3:659ffc90b59e 326 main_memory U07_MM // main-memory.
gatedClock 3:659ffc90b59e 327 (
gatedClock 3:659ffc90b59e 328 .iReadAddress1(wR3), // from R3.
gatedClock 3:659ffc90b59e 329 .iReadAddress0(wPC), // from PC
gatedClock 3:659ffc90b59e 330 .iWriteAddress(wR3), // from R3
gatedClock 3:659ffc90b59e 331 .oReadData1 (wMMD), // to <R2:R1>
gatedClock 3:659ffc90b59e 332 .oReadData0 (wMMI), // to IR.
gatedClock 3:659ffc90b59e 333 .iWriteData ({wR2,wR1}), // from <R2:R1>.
gatedClock 3:659ffc90b59e 334 .iWE (wWE), // from the instruction decoder.
gatedClock 3:659ffc90b59e 335 .iCPUclk (iCPUclk)
gatedClock 3:659ffc90b59e 336 );
gatedClock 3:659ffc90b59e 337
gatedClock 3:659ffc90b59e 338
gatedClock 3:659ffc90b59e 339 // load shadow-registers upon rising
gatedClock 3:659ffc90b59e 340 // edge of first SPI clock following
gatedClock 3:659ffc90b59e 341 // the falling edge of a CPU clock.
gatedClock 3:659ffc90b59e 342 shadow_load_control U08_shadow_load // shadow-register load control.
gatedClock 3:659ffc90b59e 343 (
gatedClock 3:659ffc90b59e 344 .iCPUclk(iCPUclk),
gatedClock 3:659ffc90b59e 345 .iSPIclk(iSPIclk),
gatedClock 3:659ffc90b59e 346 .iRstn(wRstn),
gatedClock 3:659ffc90b59e 347 .oLoadEnable(wLoadShadows)
gatedClock 3:659ffc90b59e 348 );
gatedClock 3:659ffc90b59e 349
gatedClock 3:659ffc90b59e 350
gatedClock 3:659ffc90b59e 351 //--- begin SPI shadow-scan section.
gatedClock 3:659ffc90b59e 352
gatedClock 3:659ffc90b59e 353
gatedClock 3:659ffc90b59e 354 // the SPI scan registers are generally
gatedClock 3:659ffc90b59e 355 // given the term 'shadow registers'.
gatedClock 3:659ffc90b59e 356
gatedClock 3:659ffc90b59e 357
gatedClock 3:659ffc90b59e 358 scan_08 U19_spi_control // top of SPI scan chain, used for control.
gatedClock 3:659ffc90b59e 359 (
gatedClock 3:659ffc90b59e 360 .oParallel (wSpiControl), // green LED select 7.
gatedClock 3:659ffc90b59e 361 .iParallel (wSpiControl), // self-refresh.
gatedClock 3:659ffc90b59e 362 .oSerial (oMISO),
gatedClock 3:659ffc90b59e 363 .iSerial (wSR0),
gatedClock 3:659ffc90b59e 364 .iLoadEnable (wLoadShadows),
gatedClock 3:659ffc90b59e 365 .iShiftEnable(1'b1),
gatedClock 3:659ffc90b59e 366 .iResetN (wRstn),
gatedClock 3:659ffc90b59e 367 .iClk (iSPIclk)
gatedClock 3:659ffc90b59e 368 );
gatedClock 3:659ffc90b59e 369
gatedClock 3:659ffc90b59e 370
gatedClock 3:659ffc90b59e 371
gatedClock 3:659ffc90b59e 372 scan_08 U20_shadowR0 // R0 shadow register.
gatedClock 3:659ffc90b59e 373 (
gatedClock 3:659ffc90b59e 374 .oParallel (wShadow0), // green LED select 6.
gatedClock 3:659ffc90b59e 375 .iParallel (wR0),
gatedClock 3:659ffc90b59e 376 .oSerial (wSR0),
gatedClock 3:659ffc90b59e 377 .iSerial (wSR1),
gatedClock 3:659ffc90b59e 378 .iLoadEnable (wLoadShadows),
gatedClock 3:659ffc90b59e 379 .iShiftEnable(1'b1),
gatedClock 3:659ffc90b59e 380 .iResetN (wRstn),
gatedClock 3:659ffc90b59e 381 .iClk (iSPIclk)
gatedClock 3:659ffc90b59e 382 );
gatedClock 3:659ffc90b59e 383
gatedClock 3:659ffc90b59e 384 scan_08 U21_shadowR1 // R1 shadow register.
gatedClock 3:659ffc90b59e 385 (
gatedClock 3:659ffc90b59e 386 .oParallel (wShadow1), // green LED select 5.
gatedClock 3:659ffc90b59e 387 .iParallel (wR1),
gatedClock 3:659ffc90b59e 388 .oSerial (wSR1),
gatedClock 3:659ffc90b59e 389 .iSerial (wSR2),
gatedClock 3:659ffc90b59e 390 .iLoadEnable (wLoadShadows),
gatedClock 3:659ffc90b59e 391 .iShiftEnable(1'b1),
gatedClock 3:659ffc90b59e 392 .iResetN (wRstn),
gatedClock 3:659ffc90b59e 393 .iClk (iSPIclk)
gatedClock 3:659ffc90b59e 394 );
gatedClock 3:659ffc90b59e 395
gatedClock 3:659ffc90b59e 396 scan_08 U22_shadowR2 // R2 shadow register.
gatedClock 3:659ffc90b59e 397 (
gatedClock 3:659ffc90b59e 398 .oParallel (wShadow2), // green LED select 4.
gatedClock 3:659ffc90b59e 399 .iParallel (wR2),
gatedClock 3:659ffc90b59e 400 .oSerial (wSR2),
gatedClock 3:659ffc90b59e 401 .iSerial (wSR3),
gatedClock 3:659ffc90b59e 402 .iLoadEnable (wLoadShadows),
gatedClock 3:659ffc90b59e 403 .iShiftEnable(1'b1),
gatedClock 3:659ffc90b59e 404 .iResetN (wRstn),
gatedClock 3:659ffc90b59e 405 .iClk (iSPIclk)
gatedClock 3:659ffc90b59e 406 );
gatedClock 3:659ffc90b59e 407
gatedClock 3:659ffc90b59e 408 scan_08 U23_shadowR3 // R3 shadow register.
gatedClock 3:659ffc90b59e 409 (
gatedClock 3:659ffc90b59e 410 .oParallel (wShadow3), // green LED select 3.
gatedClock 3:659ffc90b59e 411 .iParallel (wR3),
gatedClock 3:659ffc90b59e 412 .oSerial (wSR3),
gatedClock 3:659ffc90b59e 413 .iSerial (wSPC),
gatedClock 3:659ffc90b59e 414 .iLoadEnable (wLoadShadows),
gatedClock 3:659ffc90b59e 415 .iShiftEnable(1'b1),
gatedClock 3:659ffc90b59e 416 .iResetN (wRstn),
gatedClock 3:659ffc90b59e 417 .iClk (iSPIclk)
gatedClock 3:659ffc90b59e 418 );
gatedClock 3:659ffc90b59e 419
gatedClock 3:659ffc90b59e 420 scan_08 U24_shadowPC // program-counter shadow register.
gatedClock 3:659ffc90b59e 421 (
gatedClock 3:659ffc90b59e 422 .oParallel (wShadowPC), // green LED select 2.
gatedClock 3:659ffc90b59e 423 .iParallel (wPC),
gatedClock 3:659ffc90b59e 424 .oSerial (wSPC),
gatedClock 3:659ffc90b59e 425 .iSerial (wSIR),
gatedClock 3:659ffc90b59e 426 .iLoadEnable (wLoadShadows),
gatedClock 3:659ffc90b59e 427 .iShiftEnable(1'b1),
gatedClock 3:659ffc90b59e 428 .iResetN (wRstn),
gatedClock 3:659ffc90b59e 429 .iClk (iSPIclk)
gatedClock 3:659ffc90b59e 430 );
gatedClock 3:659ffc90b59e 431
gatedClock 3:659ffc90b59e 432 scan_16 U25_shadowIR // instruction-register shadow register.
gatedClock 3:659ffc90b59e 433 (
gatedClock 3:659ffc90b59e 434 .oParallel (wShadowIR), // green LED select 1,0.
gatedClock 3:659ffc90b59e 435 .iParallel (wIR),
gatedClock 3:659ffc90b59e 436 .oSerial (wSIR),
gatedClock 3:659ffc90b59e 437 .iSerial (iMOSI),
gatedClock 3:659ffc90b59e 438 .iLoadEnable (wLoadShadows),
gatedClock 3:659ffc90b59e 439 .iShiftEnable(1'b1),
gatedClock 3:659ffc90b59e 440 .iResetN (wRstn),
gatedClock 3:659ffc90b59e 441 .iClk (iSPIclk)
gatedClock 3:659ffc90b59e 442 );
gatedClock 3:659ffc90b59e 443
gatedClock 3:659ffc90b59e 444
gatedClock 3:659ffc90b59e 445
gatedClock 3:659ffc90b59e 446 //--- begin green LED signal-monitoring section.
gatedClock 3:659ffc90b59e 447
gatedClock 3:659ffc90b59e 448
gatedClock 3:659ffc90b59e 449
gatedClock 3:659ffc90b59e 450 mux8x16 U30_green_led_mux // green LED diagnostic mux.
gatedClock 3:659ffc90b59e 451 (
gatedClock 3:659ffc90b59e 452 .iDin15({wLER0,wLER1,wLER2,wLER3,wLEPC,wLEIR,wWE,wCEPC}),
gatedClock 3:659ffc90b59e 453 .iDin14(wIR[15:8]), // IR-H.
gatedClock 3:659ffc90b59e 454 .iDin13(wIR[7:0]), // IR-L.
gatedClock 3:659ffc90b59e 455 .iDin12(wPC), // PC.
gatedClock 3:659ffc90b59e 456 .iDin11(wR3), // R3.
gatedClock 3:659ffc90b59e 457 .iDin10(wR2), // R2.
gatedClock 3:659ffc90b59e 458 .iDin9 (wR1), // R1.
gatedClock 3:659ffc90b59e 459 .iDin8 (wR0), // R0.
gatedClock 3:659ffc90b59e 460 .iDin7 (wSpiControl), // SPI control.
gatedClock 3:659ffc90b59e 461 .iDin6 (wShadowIR[15:8]), // IR-H shadow.
gatedClock 3:659ffc90b59e 462 .iDin5 (wShadowIR[7:0]), // IR-L shadow.
gatedClock 3:659ffc90b59e 463 .iDin4 (wShadowPC), // PC shadow.
gatedClock 3:659ffc90b59e 464 .iDin3 (wShadow3), // R3 shadow.
gatedClock 3:659ffc90b59e 465 .iDin2 (wShadow2), // R2 shadow.
gatedClock 3:659ffc90b59e 466 .iDin1 (wShadow1), // R1 shadow.
gatedClock 3:659ffc90b59e 467 .iDin0 (wShadow0), // R0 shadow.
gatedClock 3:659ffc90b59e 468 .iSel (iSW[3:0]), // mux-select.
gatedClock 3:659ffc90b59e 469 .oDout (oLEDG) // to green LED bank.
gatedClock 3:659ffc90b59e 470 );
gatedClock 3:659ffc90b59e 471 /*-----------------------------------logic------//----------------------------*/
gatedClock 3:659ffc90b59e 472 assign wRstn = iKEY[0]; // pushbutton system reset.
gatedClock 3:659ffc90b59e 473 assign wSquelch = wSpiControl[2]; // for python squelching ins. decode.
gatedClock 3:659ffc90b59e 474 assign wBypassIR = wSpiControl[1]; // for python controlling CPU.
gatedClock 3:659ffc90b59e 475 assign wTrigger = wSpiControl[7:4]; // for signaltap triggering, not used.
gatedClock 3:659ffc90b59e 476
gatedClock 3:659ffc90b59e 477 // load instruction register
gatedClock 3:659ffc90b59e 478 // if neither or both shadow
gatedClock 3:659ffc90b59e 479 // control signals asserted.
gatedClock 3:659ffc90b59e 480 assign wLEIR = !(wSquelch ^ wBypassIR);
gatedClock 3:659ffc90b59e 481
gatedClock 3:659ffc90b59e 482
gatedClock 3:659ffc90b59e 483 assign oLEDR[9] = 1'b0; // red LED hookup.
gatedClock 3:659ffc90b59e 484 assign oLEDR[8] = 1'b0;
gatedClock 3:659ffc90b59e 485 assign oLEDR[7] = wSel[2];
gatedClock 3:659ffc90b59e 486 assign oLEDR[6] = wSel[1];
gatedClock 3:659ffc90b59e 487 assign oLEDR[5] = wSel[0];
gatedClock 3:659ffc90b59e 488 assign oLEDR[4] = wRstn;
gatedClock 3:659ffc90b59e 489 assign oLEDR[3] = iCPUclk;
gatedClock 3:659ffc90b59e 490 assign oLEDR[2] = oMISO;
gatedClock 3:659ffc90b59e 491 assign oLEDR[1] = iMOSI;
gatedClock 3:659ffc90b59e 492 assign oLEDR[0] = iSPIclk;
gatedClock 3:659ffc90b59e 493
gatedClock 3:659ffc90b59e 494
gatedClock 3:659ffc90b59e 495 // signals not to be optimized
gatedClock 3:659ffc90b59e 496 // out, place here.
gatedClock 3:659ffc90b59e 497 assign oDummyLoad = (|wShadowIR) | wSIR | (|wSpiControl) | (|wTrigger);
gatedClock 3:659ffc90b59e 498 /*-------------------------------*/endmodule/*--------------------------------*/
gatedClock 3:659ffc90b59e 499
gatedClock 3:659ffc90b59e 500
gatedClock 3:659ffc90b59e 501
gatedClock 3:659ffc90b59e 502
gatedClock 3:659ffc90b59e 503
gatedClock 3:659ffc90b59e 504
gatedClock 3:659ffc90b59e 505
gatedClock 3:659ffc90b59e 506
gatedClock 3:659ffc90b59e 507
gatedClock 3:659ffc90b59e 508
gatedClock 3:659ffc90b59e 509
gatedClock 3:659ffc90b59e 510
gatedClock 3:659ffc90b59e 511
gatedClock 3:659ffc90b59e 512
gatedClock 3:659ffc90b59e 513
gatedClock 3:659ffc90b59e 514