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Dependencies:   C12832_lcd USBDevice mbed-rtos mbed mmSPI-2 watchdog

Fork of USB_device_project by Mike Moore

mmRTL/instruction_decoder.txt@7:d1aca9ccbab8, 2013-09-01 (annotated)

Committer:
gatedClock
Date:
Sun Sep 01 03:48:07 2013 +0000
Revision:
7:d1aca9ccbab8
Parent:
3:659ffc90b59e 
improve tab formatting of code under mmRTL.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 3:659ffc90b59e 1 /*----------------------------------copyright---------------------------------*/
gatedClock 7:d1aca9ccbab8 2 // licensed for personal and academic use.
gatedClock 7:d1aca9ccbab8 3 // commercial use must be approved by the account-holder of
gatedClock 7:d1aca9ccbab8 4 // gated.clock@gmail.com
gatedClock 3:659ffc90b59e 5 /*-----------------------------------module-----------------------------------*/
gatedClock 7:d1aca9ccbab8 6 module instruction_decoder
gatedClock 3:659ffc90b59e 7 (
gatedClock 7:d1aca9ccbab8 8 iSquelch, // disrupt output enables.
gatedClock 7:d1aca9ccbab8 9 iIR, // instruction register.
gatedClock 7:d1aca9ccbab8 10 iBypass, // instruction from SPI.
gatedClock 7:d1aca9ccbab8 11 iBypassIR, // override the IR.
gatedClock 7:d1aca9ccbab8 12 oSel, // common data-in selector.
gatedClock 7:d1aca9ccbab8 13 oLER0, // R0 load-enable.
gatedClock 7:d1aca9ccbab8 14 oLER1, // R1 load-enable.
gatedClock 7:d1aca9ccbab8 15 oLER2, // R2 load-enable.
gatedClock 7:d1aca9ccbab8 16 oLER3, // R3 load-enable.
gatedClock 7:d1aca9ccbab8 17 oLEPC, // PC load-enable.
gatedClock 7:d1aca9ccbab8 18 oWE, // write-enable pulse.
gatedClock 7:d1aca9ccbab8 19 oCEPC, // PC count-enable.
gatedClock 7:d1aca9ccbab8 20 oImmediate // immediate data.
gatedClock 3:659ffc90b59e 21 );
gatedClock 3:659ffc90b59e 22 /*--------------------------------description-----------------------------------
gatedClock 7:d1aca9ccbab8 23 the instruction decoder.
gatedClock 3:659ffc90b59e 24 -------------------------------------notes--------------------------------------
gatedClock 7:d1aca9ccbab8 25 this instruction decoder operates in three different 'modes'.
gatedClock 7:d1aca9ccbab8 26 1. nominal mode: the instruction word is decoded as per the CPU spec.
gatedClock 7:d1aca9ccbab8 27 2. regular test mode: the instruction register is ignored, and instead
gatedClock 3:659ffc90b59e 28 this decoder makes use of iBypass, which is the instruction pattern
gatedClock 3:659ffc90b59e 29 provided by the instruction word shadow register (which is part of
gatedClock 3:659ffc90b59e 30 the spi scan chain). this allows the python code to take over the
gatedClock 3:659ffc90b59e 31 operation of the CPU.
gatedClock 7:d1aca9ccbab8 32 3. IR-write test mode: a special-case mode which occurs when python
gatedClock 3:659ffc90b59e 33 writes to the instruction register. in this case, the outputs of
gatedClock 7:d1aca9ccbab8 34 this decoder which are used to provide load-enables to CPU
gatedClock 7:d1aca9ccbab8 35 resources, must be squelched. this is because we don't want the
gatedClock 3:659ffc90b59e 36 python-written instruction register content to be decoded and
gatedClock 7:d1aca9ccbab8 37 the decoded signals sent into the CPU. why? because most likely
gatedClock 3:659ffc90b59e 38 the python-write to the IR is only to check that it can be done,
gatedClock 3:659ffc90b59e 39 and if the result of such a write were allowed to propagate, then
gatedClock 3:659ffc90b59e 40 the other registers may be arbitrarily updated, confusing the
gatedClock 3:659ffc90b59e 41 user at the python end.
gatedClock 3:659ffc90b59e 42 ------------------------------------defines-----------------------------------*/
gatedClock 3:659ffc90b59e 43 /*-----------------------------------ports------------------------------------*/
gatedClock 7:d1aca9ccbab8 44 input iSquelch; // disrupt output enables.
gatedClock 7:d1aca9ccbab8 45 input [15:0] iIR; // instruction register.
gatedClock 7:d1aca9ccbab8 46 input [15:0] iBypass; // instruction from SPI.
gatedClock 7:d1aca9ccbab8 47 input iBypassIR; // override the IR.
gatedClock 7:d1aca9ccbab8 48 output [ 2:0] oSel; // common data-in selector.
gatedClock 7:d1aca9ccbab8 49 output oLER0; // R0 load-enable.
gatedClock 7:d1aca9ccbab8 50 output oLER1; // R1 load-enable.
gatedClock 7:d1aca9ccbab8 51 output oLER2; // R2 load-enable.
gatedClock 7:d1aca9ccbab8 52 output oLER3; // R3 load-enable.
gatedClock 7:d1aca9ccbab8 53 output oLEPC; // PC load-enable.
gatedClock 7:d1aca9ccbab8 54 output oWE; // write-enable pulse.
gatedClock 7:d1aca9ccbab8 55 output oCEPC; // PC count-enable.
gatedClock 7:d1aca9ccbab8 56 output [ 7:0] oImmediate; // immediate data.
gatedClock 3:659ffc90b59e 57 /*-----------------------------------wires------------------------------------*/
gatedClock 7:d1aca9ccbab8 58 wire iSquelch; // disrupt output enables.
gatedClock 7:d1aca9ccbab8 59 wire [15:0] iIR; // instruction register.
gatedClock 7:d1aca9ccbab8 60 wire [15:0] iBypass; // instruction from SPI.
gatedClock 7:d1aca9ccbab8 61 wire iBypassIR; // override the IR.
gatedClock 7:d1aca9ccbab8 62 wire [ 2:0] oSel; // common data-in selector.
gatedClock 7:d1aca9ccbab8 63 wire oLER0; // R0 load-enable.
gatedClock 7:d1aca9ccbab8 64 wire oLER1; // R1 load-enable.
gatedClock 7:d1aca9ccbab8 65 wire oLER2; // R2 load-enable.
gatedClock 7:d1aca9ccbab8 66 wire oLER3; // R3 load-enable.
gatedClock 7:d1aca9ccbab8 67 wire oLEPC; // PC load-enable.
gatedClock 7:d1aca9ccbab8 68 wire oWE; // write-enable pulse.
gatedClock 7:d1aca9ccbab8 69 wire oCEPC; // PC count-enable.
gatedClock 7:d1aca9ccbab8 70 wire [ 7:0] oImmediate; // immediate data.
gatedClock 3:659ffc90b59e 71 /*---------------------------------registers----------------------------------*/
gatedClock 7:d1aca9ccbab8 72 reg [15:0] rIR; // instruction.
gatedClock 7:d1aca9ccbab8 73 reg rLER0; // R0 load-enable.
gatedClock 7:d1aca9ccbab8 74 reg rLER1; // R1 load-enable.
gatedClock 7:d1aca9ccbab8 75 reg rLER2; // R2 load-enable.
gatedClock 7:d1aca9ccbab8 76 reg rLER3; // R3 load-enable.
gatedClock 7:d1aca9ccbab8 77 reg rLEPC; // PC load-enable.
gatedClock 3:659ffc90b59e 78 /*---------------------------------variables----------------------------------*/
gatedClock 3:659ffc90b59e 79 /*---------------------------------parameters---------------------------------*/
gatedClock 3:659ffc90b59e 80 /*-----------------------------------clocks-----------------------------------*/
gatedClock 3:659ffc90b59e 81 /*---------------------------------instances----------------------------------*/
gatedClock 3:659ffc90b59e 82 /*-----------------------------------logic------------------------------------*/
gatedClock 3:659ffc90b59e 83
gatedClock 3:659ffc90b59e 84
gatedClock 7:d1aca9ccbab8 85 always @ (rIR)
gatedClock 7:d1aca9ccbab8 86 case (rIR[12:10]) // decode the load-enables.
gatedClock 3:659ffc90b59e 87
gatedClock 7:d1aca9ccbab8 88 7 : begin // no register.
gatedClock 7:d1aca9ccbab8 89 rLER0 = 1'b0;
gatedClock 7:d1aca9ccbab8 90 rLER1 = 1'b0;
gatedClock 7:d1aca9ccbab8 91 rLER2 = 1'b0;
gatedClock 7:d1aca9ccbab8 92 rLER3 = 1'b0;
gatedClock 7:d1aca9ccbab8 93 rLEPC = 1'b0;
gatedClock 3:659ffc90b59e 94 end
gatedClock 3:659ffc90b59e 95
gatedClock 7:d1aca9ccbab8 96 6 : begin // no register.
gatedClock 7:d1aca9ccbab8 97 rLER0 = 1'b0;
gatedClock 7:d1aca9ccbab8 98 rLER1 = 1'b0;
gatedClock 7:d1aca9ccbab8 99 rLER2 = 1'b0;
gatedClock 7:d1aca9ccbab8 100 rLER3 = 1'b0;
gatedClock 7:d1aca9ccbab8 101 rLEPC = 1'b0;
gatedClock 3:659ffc90b59e 102 end
gatedClock 3:659ffc90b59e 103
gatedClock 7:d1aca9ccbab8 104 5 : begin // no register.
gatedClock 7:d1aca9ccbab8 105 rLER0 = 1'b0;
gatedClock 7:d1aca9ccbab8 106 rLER1 = 1'b0;
gatedClock 7:d1aca9ccbab8 107 rLER2 = 1'b0;
gatedClock 7:d1aca9ccbab8 108 rLER3 = 1'b0;
gatedClock 7:d1aca9ccbab8 109 rLEPC = 1'b0;
gatedClock 3:659ffc90b59e 110 end
gatedClock 3:659ffc90b59e 111
gatedClock 7:d1aca9ccbab8 112 4 : begin // PC
gatedClock 7:d1aca9ccbab8 113 rLER0 = 1'b0;
gatedClock 7:d1aca9ccbab8 114 rLER1 = 1'b0;
gatedClock 7:d1aca9ccbab8 115 rLER2 = 1'b0;
gatedClock 7:d1aca9ccbab8 116 rLER3 = 1'b0;
gatedClock 7:d1aca9ccbab8 117 rLEPC = 1'b1;
gatedClock 3:659ffc90b59e 118 end
gatedClock 3:659ffc90b59e 119
gatedClock 7:d1aca9ccbab8 120 3 : begin // R3
gatedClock 7:d1aca9ccbab8 121 rLER0 = 1'b0;
gatedClock 7:d1aca9ccbab8 122 rLER1 = 1'b0;
gatedClock 7:d1aca9ccbab8 123 rLER2 = 1'b0;
gatedClock 7:d1aca9ccbab8 124 rLER3 = 1'b1;
gatedClock 7:d1aca9ccbab8 125 rLEPC = 1'b0;
gatedClock 3:659ffc90b59e 126 end
gatedClock 3:659ffc90b59e 127
gatedClock 7:d1aca9ccbab8 128 2 : begin // R2
gatedClock 7:d1aca9ccbab8 129 rLER0 = 1'b0;
gatedClock 7:d1aca9ccbab8 130 rLER1 = 1'b0;
gatedClock 7:d1aca9ccbab8 131 rLER2 = 1'b1;
gatedClock 7:d1aca9ccbab8 132 rLER3 = 1'b0;
gatedClock 7:d1aca9ccbab8 133 rLEPC = 1'b0;
gatedClock 3:659ffc90b59e 134 end
gatedClock 3:659ffc90b59e 135
gatedClock 7:d1aca9ccbab8 136 1 : begin // R1
gatedClock 7:d1aca9ccbab8 137 rLER0 = 1'b0;
gatedClock 7:d1aca9ccbab8 138 rLER1 = 1'b1;
gatedClock 7:d1aca9ccbab8 139 rLER2 = 1'b0;
gatedClock 7:d1aca9ccbab8 140 rLER3 = 1'b0;
gatedClock 7:d1aca9ccbab8 141 rLEPC = 1'b0;
gatedClock 3:659ffc90b59e 142 end
gatedClock 3:659ffc90b59e 143
gatedClock 7:d1aca9ccbab8 144 0 : begin // R0
gatedClock 7:d1aca9ccbab8 145 rLER0 = 1'b1;
gatedClock 7:d1aca9ccbab8 146 rLER1 = 1'b0;
gatedClock 7:d1aca9ccbab8 147 rLER2 = 1'b0;
gatedClock 7:d1aca9ccbab8 148 rLER3 = 1'b0;
gatedClock 7:d1aca9ccbab8 149 rLEPC = 1'b0;
gatedClock 3:659ffc90b59e 150 end
gatedClock 3:659ffc90b59e 151
gatedClock 7:d1aca9ccbab8 152
gatedClock 7:d1aca9ccbab8 153 endcase
gatedClock 3:659ffc90b59e 154
gatedClock 7:d1aca9ccbab8 155 assign oSel = rIR[15:13]; // pass-through.
gatedClock 7:d1aca9ccbab8 156 assign oLER0 = rLER0 & !iSquelch; // decode iIR[12:10].
gatedClock 7:d1aca9ccbab8 157 assign oLER1 = rLER1 & !iSquelch; // decode iIR[12:10].
gatedClock 7:d1aca9ccbab8 158 assign oLER2 = rLER2 & !iSquelch; // decode iIR[12:10].
gatedClock 7:d1aca9ccbab8 159 assign oLER3 = rLER3 & !iSquelch; // decode iIR[12:10].
gatedClock 7:d1aca9ccbab8 160 assign oLEPC = rLEPC & !iSquelch; // decode iIR[12:10].
gatedClock 7:d1aca9ccbab8 161 assign oWE = rIR[9] & !iSquelch; // pass-through.
gatedClock 7:d1aca9ccbab8 162 assign oCEPC = rIR[8] & !iSquelch; // pass-through.
gatedClock 7:d1aca9ccbab8 163 assign oImmediate = rIR[7:0]; // pass-through.
gatedClock 3:659ffc90b59e 164
gatedClock 3:659ffc90b59e 165
gatedClock 7:d1aca9ccbab8 166 always @ (iIR or iBypass or iBypassIR)
gatedClock 7:d1aca9ccbab8 167 if (iBypassIR) rIR = iBypass;
gatedClock 7:d1aca9ccbab8 168 else rIR = iIR;
gatedClock 3:659ffc90b59e 169 /*-------------------------------*/endmodule/*--------------------------------*/
gatedClock 3:659ffc90b59e 170
gatedClock 3:659ffc90b59e 171
gatedClock 3:659ffc90b59e 172
gatedClock 3:659ffc90b59e 173
gatedClock 3:659ffc90b59e 174
gatedClock 3:659ffc90b59e 175
gatedClock 3:659ffc90b59e 176
gatedClock 3:659ffc90b59e 177
gatedClock 3:659ffc90b59e 178
gatedClock 3:659ffc90b59e 179
gatedClock 3:659ffc90b59e 180
gatedClock 3:659ffc90b59e 181
gatedClock 3:659ffc90b59e 182
gatedClock 3:659ffc90b59e 183
gatedClock 3:659ffc90b59e 184
gatedClock 3:659ffc90b59e 185
gatedClock 7:d1aca9ccbab8 186
gatedClock 7:d1aca9ccbab8 187
gatedClock 7:d1aca9ccbab8 188
gatedClock 7:d1aca9ccbab8 189
gatedClock 7:d1aca9ccbab8 190
gatedClock 7:d1aca9ccbab8 191
gatedClock 7:d1aca9ccbab8 192
gatedClock 7:d1aca9ccbab8 193
gatedClock 7:d1aca9ccbab8 194
gatedClock 7:d1aca9ccbab8 195
gatedClock 7:d1aca9ccbab8 196
gatedClock 7:d1aca9ccbab8 197
gatedClock 7:d1aca9ccbab8 198
gatedClock 7:d1aca9ccbab8 199
gatedClock 7:d1aca9ccbab8 200
gatedClock 7:d1aca9ccbab8 201
gatedClock 7:d1aca9ccbab8 202