Mike Moore / Mbed 2 deprecated Embedded_RTOS_Project

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Dependencies:   C12832_lcd USBDevice mbed-rtos mbed mmSPI-2 watchdog

Fork of USB_device_project by Mike Moore

mmRTL/instruction_decoder.txt@3:659ffc90b59e, 2013-09-01 (annotated)

Committer:
gatedClock
Date:
Sun Sep 01 02:53:39 2013 +0000
Revision:
3:659ffc90b59e
Child:
7:d1aca9ccbab8
add the project RTL files.  the tab-formatting needs to be redone.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gatedClock 3:659ffc90b59e 1 /*----------------------------------copyright---------------------------------*/
gatedClock 3:659ffc90b59e 2 // licensed for personal and academic use.
gatedClock 3:659ffc90b59e 3 // commercial use must be approved by the account-holder of
gatedClock 3:659ffc90b59e 4 // gated.clock@gmail.com
gatedClock 3:659ffc90b59e 5 /*-----------------------------------module-----------------------------------*/
gatedClock 3:659ffc90b59e 6 module instruction_decoder
gatedClock 3:659ffc90b59e 7 (
gatedClock 3:659ffc90b59e 8 iSquelch, // disrupt output enables.
gatedClock 3:659ffc90b59e 9 iIR, // instruction register.
gatedClock 3:659ffc90b59e 10 iBypass, // instruction from SPI.
gatedClock 3:659ffc90b59e 11 iBypassIR, // override the IR.
gatedClock 3:659ffc90b59e 12 oSel, // common data-in selector.
gatedClock 3:659ffc90b59e 13 oLER0, // R0 load-enable.
gatedClock 3:659ffc90b59e 14 oLER1, // R1 load-enable.
gatedClock 3:659ffc90b59e 15 oLER2, // R2 load-enable.
gatedClock 3:659ffc90b59e 16 oLER3, // R3 load-enable.
gatedClock 3:659ffc90b59e 17 oLEPC, // PC load-enable.
gatedClock 3:659ffc90b59e 18 oWE, // write-enable pulse.
gatedClock 3:659ffc90b59e 19 oCEPC, // PC count-enable.
gatedClock 3:659ffc90b59e 20 oImmediate // immediate data.
gatedClock 3:659ffc90b59e 21 );
gatedClock 3:659ffc90b59e 22 /*--------------------------------description-----------------------------------
gatedClock 3:659ffc90b59e 23 the instruction decoder.
gatedClock 3:659ffc90b59e 24 -------------------------------------notes--------------------------------------
gatedClock 3:659ffc90b59e 25 this instruction decoder operates in three different 'modes'.
gatedClock 3:659ffc90b59e 26 1. nominal mode: the instruction word is decoded as per the CPU spec.
gatedClock 3:659ffc90b59e 27 2. regular test mode: the instruction register is ignored, and instead
gatedClock 3:659ffc90b59e 28 this decoder makes use of iBypass, which is the instruction pattern
gatedClock 3:659ffc90b59e 29 provided by the instruction word shadow register (which is part of
gatedClock 3:659ffc90b59e 30 the spi scan chain). this allows the python code to take over the
gatedClock 3:659ffc90b59e 31 operation of the CPU.
gatedClock 3:659ffc90b59e 32 3. IR-write test mode: a special-case mode which occurs when python
gatedClock 3:659ffc90b59e 33 writes to the instruction register. in this case, the outputs of
gatedClock 3:659ffc90b59e 34 this decoder which are used to provide load-enables to CPU
gatedClock 3:659ffc90b59e 35 resources, must be squelched. this is because we don't want the
gatedClock 3:659ffc90b59e 36 python-written instruction register content to be decoded and
gatedClock 3:659ffc90b59e 37 the decoded signals sent into the CPU. why? because most likely
gatedClock 3:659ffc90b59e 38 the python-write to the IR is only to check that it can be done,
gatedClock 3:659ffc90b59e 39 and if the result of such a write were allowed to propagate, then
gatedClock 3:659ffc90b59e 40 the other registers may be arbitrarily updated, confusing the
gatedClock 3:659ffc90b59e 41 user at the python end.
gatedClock 3:659ffc90b59e 42 ------------------------------------defines-----------------------------------*/
gatedClock 3:659ffc90b59e 43 /*-----------------------------------ports------------------------------------*/
gatedClock 3:659ffc90b59e 44 input iSquelch; // disrupt output enables.
gatedClock 3:659ffc90b59e 45 input [15:0] iIR; // instruction register.
gatedClock 3:659ffc90b59e 46 input [15:0] iBypass; // instruction from SPI.
gatedClock 3:659ffc90b59e 47 input iBypassIR; // override the IR.
gatedClock 3:659ffc90b59e 48 output [ 2:0] oSel; // common data-in selector.
gatedClock 3:659ffc90b59e 49 output oLER0; // R0 load-enable.
gatedClock 3:659ffc90b59e 50 output oLER1; // R1 load-enable.
gatedClock 3:659ffc90b59e 51 output oLER2; // R2 load-enable.
gatedClock 3:659ffc90b59e 52 output oLER3; // R3 load-enable.
gatedClock 3:659ffc90b59e 53 output oLEPC; // PC load-enable.
gatedClock 3:659ffc90b59e 54 output oWE; // write-enable pulse.
gatedClock 3:659ffc90b59e 55 output oCEPC; // PC count-enable.
gatedClock 3:659ffc90b59e 56 output [ 7:0] oImmediate; // immediate data.
gatedClock 3:659ffc90b59e 57 /*-----------------------------------wires------------------------------------*/
gatedClock 3:659ffc90b59e 58 wire iSquelch; // disrupt output enables.
gatedClock 3:659ffc90b59e 59 wire [15:0] iIR; // instruction register.
gatedClock 3:659ffc90b59e 60 wire [15:0] iBypass; // instruction from SPI.
gatedClock 3:659ffc90b59e 61 wire iBypassIR; // override the IR.
gatedClock 3:659ffc90b59e 62 wire [ 2:0] oSel; // common data-in selector.
gatedClock 3:659ffc90b59e 63 wire oLER0; // R0 load-enable.
gatedClock 3:659ffc90b59e 64 wire oLER1; // R1 load-enable.
gatedClock 3:659ffc90b59e 65 wire oLER2; // R2 load-enable.
gatedClock 3:659ffc90b59e 66 wire oLER3; // R3 load-enable.
gatedClock 3:659ffc90b59e 67 wire oLEPC; // PC load-enable.
gatedClock 3:659ffc90b59e 68 wire oWE; // write-enable pulse.
gatedClock 3:659ffc90b59e 69 wire oCEPC; // PC count-enable.
gatedClock 3:659ffc90b59e 70 wire [ 7:0] oImmediate; // immediate data.
gatedClock 3:659ffc90b59e 71 /*---------------------------------registers----------------------------------*/
gatedClock 3:659ffc90b59e 72 reg [15:0] rIR; // instruction.
gatedClock 3:659ffc90b59e 73 reg rLER0; // R0 load-enable.
gatedClock 3:659ffc90b59e 74 reg rLER1; // R1 load-enable.
gatedClock 3:659ffc90b59e 75 reg rLER2; // R2 load-enable.
gatedClock 3:659ffc90b59e 76 reg rLER3; // R3 load-enable.
gatedClock 3:659ffc90b59e 77 reg rLEPC; // PC load-enable.
gatedClock 3:659ffc90b59e 78 /*---------------------------------variables----------------------------------*/
gatedClock 3:659ffc90b59e 79 /*---------------------------------parameters---------------------------------*/
gatedClock 3:659ffc90b59e 80 /*-----------------------------------clocks-----------------------------------*/
gatedClock 3:659ffc90b59e 81 /*---------------------------------instances----------------------------------*/
gatedClock 3:659ffc90b59e 82 /*-----------------------------------logic------------------------------------*/
gatedClock 3:659ffc90b59e 83
gatedClock 3:659ffc90b59e 84
gatedClock 3:659ffc90b59e 85 always @ (rIR)
gatedClock 3:659ffc90b59e 86 case (rIR[12:10]) // decode the load-enables.
gatedClock 3:659ffc90b59e 87
gatedClock 3:659ffc90b59e 88 7 : begin // no register.
gatedClock 3:659ffc90b59e 89 rLER0 = 1'b0;
gatedClock 3:659ffc90b59e 90 rLER1 = 1'b0;
gatedClock 3:659ffc90b59e 91 rLER2 = 1'b0;
gatedClock 3:659ffc90b59e 92 rLER3 = 1'b0;
gatedClock 3:659ffc90b59e 93 rLEPC = 1'b0;
gatedClock 3:659ffc90b59e 94 end
gatedClock 3:659ffc90b59e 95
gatedClock 3:659ffc90b59e 96 6 : begin // no register.
gatedClock 3:659ffc90b59e 97 rLER0 = 1'b0;
gatedClock 3:659ffc90b59e 98 rLER1 = 1'b0;
gatedClock 3:659ffc90b59e 99 rLER2 = 1'b0;
gatedClock 3:659ffc90b59e 100 rLER3 = 1'b0;
gatedClock 3:659ffc90b59e 101 rLEPC = 1'b0;
gatedClock 3:659ffc90b59e 102 end
gatedClock 3:659ffc90b59e 103
gatedClock 3:659ffc90b59e 104 5 : begin // no register.
gatedClock 3:659ffc90b59e 105 rLER0 = 1'b0;
gatedClock 3:659ffc90b59e 106 rLER1 = 1'b0;
gatedClock 3:659ffc90b59e 107 rLER2 = 1'b0;
gatedClock 3:659ffc90b59e 108 rLER3 = 1'b0;
gatedClock 3:659ffc90b59e 109 rLEPC = 1'b0;
gatedClock 3:659ffc90b59e 110 end
gatedClock 3:659ffc90b59e 111
gatedClock 3:659ffc90b59e 112 4 : begin // PC
gatedClock 3:659ffc90b59e 113 rLER0 = 1'b0;
gatedClock 3:659ffc90b59e 114 rLER1 = 1'b0;
gatedClock 3:659ffc90b59e 115 rLER2 = 1'b0;
gatedClock 3:659ffc90b59e 116 rLER3 = 1'b0;
gatedClock 3:659ffc90b59e 117 rLEPC = 1'b1;
gatedClock 3:659ffc90b59e 118 end
gatedClock 3:659ffc90b59e 119
gatedClock 3:659ffc90b59e 120 3 : begin // R3
gatedClock 3:659ffc90b59e 121 rLER0 = 1'b0;
gatedClock 3:659ffc90b59e 122 rLER1 = 1'b0;
gatedClock 3:659ffc90b59e 123 rLER2 = 1'b0;
gatedClock 3:659ffc90b59e 124 rLER3 = 1'b1;
gatedClock 3:659ffc90b59e 125 rLEPC = 1'b0;
gatedClock 3:659ffc90b59e 126 end
gatedClock 3:659ffc90b59e 127
gatedClock 3:659ffc90b59e 128 2 : begin // R2
gatedClock 3:659ffc90b59e 129 rLER0 = 1'b0;
gatedClock 3:659ffc90b59e 130 rLER1 = 1'b0;
gatedClock 3:659ffc90b59e 131 rLER2 = 1'b1;
gatedClock 3:659ffc90b59e 132 rLER3 = 1'b0;
gatedClock 3:659ffc90b59e 133 rLEPC = 1'b0;
gatedClock 3:659ffc90b59e 134 end
gatedClock 3:659ffc90b59e 135
gatedClock 3:659ffc90b59e 136 1 : begin // R1
gatedClock 3:659ffc90b59e 137 rLER0 = 1'b0;
gatedClock 3:659ffc90b59e 138 rLER1 = 1'b1;
gatedClock 3:659ffc90b59e 139 rLER2 = 1'b0;
gatedClock 3:659ffc90b59e 140 rLER3 = 1'b0;
gatedClock 3:659ffc90b59e 141 rLEPC = 1'b0;
gatedClock 3:659ffc90b59e 142 end
gatedClock 3:659ffc90b59e 143
gatedClock 3:659ffc90b59e 144 0 : begin // R0
gatedClock 3:659ffc90b59e 145 rLER0 = 1'b1;
gatedClock 3:659ffc90b59e 146 rLER1 = 1'b0;
gatedClock 3:659ffc90b59e 147 rLER2 = 1'b0;
gatedClock 3:659ffc90b59e 148 rLER3 = 1'b0;
gatedClock 3:659ffc90b59e 149 rLEPC = 1'b0;
gatedClock 3:659ffc90b59e 150 end
gatedClock 3:659ffc90b59e 151
gatedClock 3:659ffc90b59e 152
gatedClock 3:659ffc90b59e 153 endcase
gatedClock 3:659ffc90b59e 154
gatedClock 3:659ffc90b59e 155 assign oSel = rIR[15:13]; // pass-through.
gatedClock 3:659ffc90b59e 156 assign oLER0 = rLER0 & !iSquelch; // decode iIR[12:10].
gatedClock 3:659ffc90b59e 157 assign oLER1 = rLER1 & !iSquelch; // decode iIR[12:10].
gatedClock 3:659ffc90b59e 158 assign oLER2 = rLER2 & !iSquelch; // decode iIR[12:10].
gatedClock 3:659ffc90b59e 159 assign oLER3 = rLER3 & !iSquelch; // decode iIR[12:10].
gatedClock 3:659ffc90b59e 160 assign oLEPC = rLEPC & !iSquelch; // decode iIR[12:10].
gatedClock 3:659ffc90b59e 161 assign oWE = rIR[9] & !iSquelch; // pass-through.
gatedClock 3:659ffc90b59e 162 assign oCEPC = rIR[8] & !iSquelch; // pass-through.
gatedClock 3:659ffc90b59e 163 assign oImmediate = rIR[7:0]; // pass-through.
gatedClock 3:659ffc90b59e 164
gatedClock 3:659ffc90b59e 165
gatedClock 3:659ffc90b59e 166 always @ (iIR or iBypass or iBypassIR)
gatedClock 3:659ffc90b59e 167 if (iBypassIR) rIR = iBypass;
gatedClock 3:659ffc90b59e 168 else rIR = iIR;
gatedClock 3:659ffc90b59e 169 /*-------------------------------*/endmodule/*--------------------------------*/
gatedClock 3:659ffc90b59e 170
gatedClock 3:659ffc90b59e 171
gatedClock 3:659ffc90b59e 172
gatedClock 3:659ffc90b59e 173
gatedClock 3:659ffc90b59e 174
gatedClock 3:659ffc90b59e 175
gatedClock 3:659ffc90b59e 176
gatedClock 3:659ffc90b59e 177
gatedClock 3:659ffc90b59e 178
gatedClock 3:659ffc90b59e 179
gatedClock 3:659ffc90b59e 180
gatedClock 3:659ffc90b59e 181
gatedClock 3:659ffc90b59e 182
gatedClock 3:659ffc90b59e 183
gatedClock 3:659ffc90b59e 184
gatedClock 3:659ffc90b59e 185