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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.h@0:13413ea9a877, 2022-06-12 (annotated)

Committer:: ganlikun
Date:: Sun Jun 12 14:02:44 2022 +0000
Revision:: 0:13413ea9a877

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User	Revision	Line number	New contents of line
ganlikun	0:13413ea9a877	1	/**
ganlikun	0:13413ea9a877	2	******************************************************************************
ganlikun	0:13413ea9a877	3	* @file stm32f4xx_ll_sdmmc.h
ganlikun	0:13413ea9a877	4	* @author MCD Application Team
ganlikun	0:13413ea9a877	5	* @version V1.7.1
ganlikun	0:13413ea9a877	6	* @date 14-April-2017
ganlikun	0:13413ea9a877	7	* @brief Header file of SDMMC HAL module.
ganlikun	0:13413ea9a877	8	******************************************************************************
ganlikun	0:13413ea9a877	9	* @attention
ganlikun	0:13413ea9a877	10	*
ganlikun	0:13413ea9a877	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
ganlikun	0:13413ea9a877	12	*
ganlikun	0:13413ea9a877	13	* Redistribution and use in source and binary forms, with or without modification,
ganlikun	0:13413ea9a877	14	* are permitted provided that the following conditions are met:
ganlikun	0:13413ea9a877	15	* 1. Redistributions of source code must retain the above copyright notice,
ganlikun	0:13413ea9a877	16	* this list of conditions and the following disclaimer.
ganlikun	0:13413ea9a877	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
ganlikun	0:13413ea9a877	18	* this list of conditions and the following disclaimer in the documentation
ganlikun	0:13413ea9a877	19	* and/or other materials provided with the distribution.
ganlikun	0:13413ea9a877	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
ganlikun	0:13413ea9a877	21	* may be used to endorse or promote products derived from this software
ganlikun	0:13413ea9a877	22	* without specific prior written permission.
ganlikun	0:13413ea9a877	23	*
ganlikun	0:13413ea9a877	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ganlikun	0:13413ea9a877	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ganlikun	0:13413ea9a877	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ganlikun	0:13413ea9a877	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ganlikun	0:13413ea9a877	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ganlikun	0:13413ea9a877	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ganlikun	0:13413ea9a877	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ganlikun	0:13413ea9a877	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ganlikun	0:13413ea9a877	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ganlikun	0:13413ea9a877	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ganlikun	0:13413ea9a877	34	*
ganlikun	0:13413ea9a877	35	******************************************************************************
ganlikun	0:13413ea9a877	36	*/
ganlikun	0:13413ea9a877	37
ganlikun	0:13413ea9a877	38	/* Define to prevent recursive inclusion -------------------------------------*/
ganlikun	0:13413ea9a877	39	#ifndef __STM32F4xx_LL_SDMMC_H
ganlikun	0:13413ea9a877	40	#define __STM32F4xx_LL_SDMMC_H
ganlikun	0:13413ea9a877	41
ganlikun	0:13413ea9a877	42	#ifdef __cplusplus
ganlikun	0:13413ea9a877	43	extern "C" {
ganlikun	0:13413ea9a877	44	#endif
ganlikun	0:13413ea9a877	45
ganlikun	0:13413ea9a877	46	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
ganlikun	0:13413ea9a877	47	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
ganlikun	0:13413ea9a877	48	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
ganlikun	0:13413ea9a877	49	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
ganlikun	0:13413ea9a877	50	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
ganlikun	0:13413ea9a877	51
ganlikun	0:13413ea9a877	52	/* Includes ------------------------------------------------------------------*/
ganlikun	0:13413ea9a877	53	#include "stm32f4xx_hal_def.h"
ganlikun	0:13413ea9a877	54
ganlikun	0:13413ea9a877	55	/** @addtogroup STM32F4xx_Driver
ganlikun	0:13413ea9a877	56	* @{
ganlikun	0:13413ea9a877	57	*/
ganlikun	0:13413ea9a877	58
ganlikun	0:13413ea9a877	59	/** @addtogroup SDMMC_LL
ganlikun	0:13413ea9a877	60	* @{
ganlikun	0:13413ea9a877	61	*/
ganlikun	0:13413ea9a877	62
ganlikun	0:13413ea9a877	63	/* Exported types ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	64	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
ganlikun	0:13413ea9a877	65	* @{
ganlikun	0:13413ea9a877	66	*/
ganlikun	0:13413ea9a877	67
ganlikun	0:13413ea9a877	68	/**
ganlikun	0:13413ea9a877	69	* @brief SDMMC Configuration Structure definition
ganlikun	0:13413ea9a877	70	*/
ganlikun	0:13413ea9a877	71	typedef struct
ganlikun	0:13413ea9a877	72	{
ganlikun	0:13413ea9a877	73	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
ganlikun	0:13413ea9a877	74	This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
ganlikun	0:13413ea9a877	75
ganlikun	0:13413ea9a877	76	uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
ganlikun	0:13413ea9a877	77	enabled or disabled.
ganlikun	0:13413ea9a877	78	This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
ganlikun	0:13413ea9a877	79
ganlikun	0:13413ea9a877	80	uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
ganlikun	0:13413ea9a877	81	disabled when the bus is idle.
ganlikun	0:13413ea9a877	82	This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
ganlikun	0:13413ea9a877	83
ganlikun	0:13413ea9a877	84	uint32_t BusWide; /*!< Specifies the SDMMC bus width.
ganlikun	0:13413ea9a877	85	This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
ganlikun	0:13413ea9a877	86
ganlikun	0:13413ea9a877	87	uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
ganlikun	0:13413ea9a877	88	This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
ganlikun	0:13413ea9a877	89
ganlikun	0:13413ea9a877	90	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
ganlikun	0:13413ea9a877	91	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
ganlikun	0:13413ea9a877	92
ganlikun	0:13413ea9a877	93	}SDIO_InitTypeDef;
ganlikun	0:13413ea9a877	94
ganlikun	0:13413ea9a877	95
ganlikun	0:13413ea9a877	96	/**
ganlikun	0:13413ea9a877	97	* @brief SDMMC Command Control structure
ganlikun	0:13413ea9a877	98	*/
ganlikun	0:13413ea9a877	99	typedef struct
ganlikun	0:13413ea9a877	100	{
ganlikun	0:13413ea9a877	101	uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
ganlikun	0:13413ea9a877	102	to a card as part of a command message. If a command
ganlikun	0:13413ea9a877	103	contains an argument, it must be loaded into this register
ganlikun	0:13413ea9a877	104	before writing the command to the command register. */
ganlikun	0:13413ea9a877	105
ganlikun	0:13413ea9a877	106	uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
ganlikun	0:13413ea9a877	107	Max_Data = 64 */
ganlikun	0:13413ea9a877	108
ganlikun	0:13413ea9a877	109	uint32_t Response; /*!< Specifies the SDMMC response type.
ganlikun	0:13413ea9a877	110	This parameter can be a value of @ref SDMMC_LL_Response_Type */
ganlikun	0:13413ea9a877	111
ganlikun	0:13413ea9a877	112	uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
ganlikun	0:13413ea9a877	113	enabled or disabled.
ganlikun	0:13413ea9a877	114	This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
ganlikun	0:13413ea9a877	115
ganlikun	0:13413ea9a877	116	uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
ganlikun	0:13413ea9a877	117	is enabled or disabled.
ganlikun	0:13413ea9a877	118	This parameter can be a value of @ref SDMMC_LL_CPSM_State */
ganlikun	0:13413ea9a877	119	}SDIO_CmdInitTypeDef;
ganlikun	0:13413ea9a877	120
ganlikun	0:13413ea9a877	121
ganlikun	0:13413ea9a877	122	/**
ganlikun	0:13413ea9a877	123	* @brief SDMMC Data Control structure
ganlikun	0:13413ea9a877	124	*/
ganlikun	0:13413ea9a877	125	typedef struct
ganlikun	0:13413ea9a877	126	{
ganlikun	0:13413ea9a877	127	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
ganlikun	0:13413ea9a877	128
ganlikun	0:13413ea9a877	129	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
ganlikun	0:13413ea9a877	130
ganlikun	0:13413ea9a877	131	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
ganlikun	0:13413ea9a877	132	This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
ganlikun	0:13413ea9a877	133
ganlikun	0:13413ea9a877	134	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
ganlikun	0:13413ea9a877	135	is a read or write.
ganlikun	0:13413ea9a877	136	This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
ganlikun	0:13413ea9a877	137
ganlikun	0:13413ea9a877	138	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
ganlikun	0:13413ea9a877	139	This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
ganlikun	0:13413ea9a877	140
ganlikun	0:13413ea9a877	141	uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
ganlikun	0:13413ea9a877	142	is enabled or disabled.
ganlikun	0:13413ea9a877	143	This parameter can be a value of @ref SDMMC_LL_DPSM_State */
ganlikun	0:13413ea9a877	144	}SDIO_DataInitTypeDef;
ganlikun	0:13413ea9a877	145
ganlikun	0:13413ea9a877	146	/**
ganlikun	0:13413ea9a877	147	* @}
ganlikun	0:13413ea9a877	148	*/
ganlikun	0:13413ea9a877	149
ganlikun	0:13413ea9a877	150	/* Exported constants --------------------------------------------------------*/
ganlikun	0:13413ea9a877	151	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
ganlikun	0:13413ea9a877	152	* @{
ganlikun	0:13413ea9a877	153	*/
ganlikun	0:13413ea9a877	154	#define SDMMC_ERROR_NONE 0x00000000U /!< No error /
ganlikun	0:13413ea9a877	155	#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /!< Command response received (but CRC check failed) /
ganlikun	0:13413ea9a877	156	#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /!< Data block sent/received (CRC check failed) /
ganlikun	0:13413ea9a877	157	#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /!< Command response timeout /
ganlikun	0:13413ea9a877	158	#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /!< Data timeout /
ganlikun	0:13413ea9a877	159	#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /!< Transmit FIFO underrun /
ganlikun	0:13413ea9a877	160	#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /!< Receive FIFO overrun /
ganlikun	0:13413ea9a877	161	#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /!< Misaligned address /
ganlikun	0:13413ea9a877	162	#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
ganlikun	0:13413ea9a877	163	number of transferred bytes does not match the block length */
ganlikun	0:13413ea9a877	164	#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /!< An error in the sequence of erase command occurs /
ganlikun	0:13413ea9a877	165	#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /!< An invalid selection for erase groups /
ganlikun	0:13413ea9a877	166	#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /!< Attempt to program a write protect block /
ganlikun	0:13413ea9a877	167	#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
ganlikun	0:13413ea9a877	168	command or if there was an attempt to access a locked card */
ganlikun	0:13413ea9a877	169	#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /!< CRC check of the previous command failed /
ganlikun	0:13413ea9a877	170	#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /!< Command is not legal for the card state /
ganlikun	0:13413ea9a877	171	#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /!< Card internal ECC was applied but failed to correct the data /
ganlikun	0:13413ea9a877	172	#define SDMMC_ERROR_CC_ERR 0x00008000U /!< Internal card controller error /
ganlikun	0:13413ea9a877	173	#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /!< General or unknown error /
ganlikun	0:13413ea9a877	174	#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /!< The card could not sustain data reading in stream rmode /
ganlikun	0:13413ea9a877	175	#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /!< The card could not sustain data programming in stream mode /
ganlikun	0:13413ea9a877	176	#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /!< CID/CSD overwrite error /
ganlikun	0:13413ea9a877	177	#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /!< Only partial address space was erased /
ganlikun	0:13413ea9a877	178	#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /!< Command has been executed without using internal ECC /
ganlikun	0:13413ea9a877	179	#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
ganlikun	0:13413ea9a877	180	of erase sequence command was received */
ganlikun	0:13413ea9a877	181	#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /!< Error in sequence of authentication /
ganlikun	0:13413ea9a877	182	#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /!< Error in case of invalid voltage range /
ganlikun	0:13413ea9a877	183	#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /!< Error when addressed block is out of range /
ganlikun	0:13413ea9a877	184	#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /!< Error when command request is not applicable /
ganlikun	0:13413ea9a877	185	#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /!< the used parameter is not valid /
ganlikun	0:13413ea9a877	186	#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /!< Error when feature is not insupported /
ganlikun	0:13413ea9a877	187	#define SDMMC_ERROR_BUSY 0x20000000U /!< Error when transfer process is busy /
ganlikun	0:13413ea9a877	188	#define SDMMC_ERROR_DMA 0x40000000U /!< Error while DMA transfer /
ganlikun	0:13413ea9a877	189	#define SDMMC_ERROR_TIMEOUT 0x80000000U /!< Timeout error /
ganlikun	0:13413ea9a877	190
ganlikun	0:13413ea9a877	191	/**
ganlikun	0:13413ea9a877	192	* @brief SDMMC Commands Index
ganlikun	0:13413ea9a877	193	*/
ganlikun	0:13413ea9a877	194	#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /!< Resets the SD memory card. /
ganlikun	0:13413ea9a877	195	#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /!< Sends host capacity support information and activates the card's initialization process. /
ganlikun	0:13413ea9a877	196	#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /!< Asks any card connected to the host to send the CID numbers on the CMD line. /
ganlikun	0:13413ea9a877	197	#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /!< Asks the card to publish a new relative address (RCA). /
ganlikun	0:13413ea9a877	198	#define SDMMC_CMD_SET_DSR ((uint8_t)4) /!< Programs the DSR of all cards. /
ganlikun	0:13413ea9a877	199	#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
ganlikun	0:13413ea9a877	200	operating condition register (OCR) content in the response on the CMD line. */
ganlikun	0:13413ea9a877	201	#define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /!< Checks switchable function (mode 0) and switch card function (mode 1). /
ganlikun	0:13413ea9a877	202	#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /!< Selects the card by its own relative address and gets deselected by any other address /
ganlikun	0:13413ea9a877	203	#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
ganlikun	0:13413ea9a877	204	and asks the card whether card supports voltage. */
ganlikun	0:13413ea9a877	205	#define SDMMC_CMD_SEND_CSD ((uint8_t)9) /!< Addressed card sends its card specific data (CSD) on the CMD line. /
ganlikun	0:13413ea9a877	206	#define SDMMC_CMD_SEND_CID ((uint8_t)10) /!< Addressed card sends its card identification (CID) on the CMD line. /
ganlikun	0:13413ea9a877	207	#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /!< SD card doesn't support it. /
ganlikun	0:13413ea9a877	208	#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /!< Forces the card to stop transmission. /
ganlikun	0:13413ea9a877	209	#define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /!< Addressed card sends its status register. /
ganlikun	0:13413ea9a877	210	#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /!< Reserved /
ganlikun	0:13413ea9a877	211	#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /!< Sends an addressed card into the inactive state. /
ganlikun	0:13413ea9a877	212	#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
ganlikun	0:13413ea9a877	213	(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
ganlikun	0:13413ea9a877	214	for SDHS and SDXC. */
ganlikun	0:13413ea9a877	215	#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
ganlikun	0:13413ea9a877	216	fixed 512 bytes in case of SDHC and SDXC. */
ganlikun	0:13413ea9a877	217	#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
ganlikun	0:13413ea9a877	218	STOP_TRANSMISSION command. */
ganlikun	0:13413ea9a877	219	#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /!< 64 bytes tuning pattern is sent for SDR50 and SDR104. /
ganlikun	0:13413ea9a877	220	#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /!< Speed class control command. /
ganlikun	0:13413ea9a877	221	#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /!< Specify block count for CMD18 and CMD25. /
ganlikun	0:13413ea9a877	222	#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
ganlikun	0:13413ea9a877	223	fixed 512 bytes in case of SDHC and SDXC. */
ganlikun	0:13413ea9a877	224	#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. /
ganlikun	0:13413ea9a877	225	#define SDMMC_CMD_PROG_CID ((uint8_t)26) /!< Reserved for manufacturers. /
ganlikun	0:13413ea9a877	226	#define SDMMC_CMD_PROG_CSD ((uint8_t)27) /!< Programming of the programmable bits of the CSD. /
ganlikun	0:13413ea9a877	227	#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /!< Sets the write protection bit of the addressed group. /
ganlikun	0:13413ea9a877	228	#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /!< Clears the write protection bit of the addressed group. /
ganlikun	0:13413ea9a877	229	#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /!< Asks the card to send the status of the write protection bits. /
ganlikun	0:13413ea9a877	230	#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /!< Sets the address of the first write block to be erased. (For SD card only). /
ganlikun	0:13413ea9a877	231	#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /!< Sets the address of the last write block of the continuous range to be erased. /
ganlikun	0:13413ea9a877	232	#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
ganlikun	0:13413ea9a877	233	system set by switch function command (CMD6). */
ganlikun	0:13413ea9a877	234	#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
ganlikun	0:13413ea9a877	235	Reserved for each command system set by switch function command (CMD6). */
ganlikun	0:13413ea9a877	236	#define SDMMC_CMD_ERASE ((uint8_t)38) /!< Reserved for SD security applications. /
ganlikun	0:13413ea9a877	237	#define SDMMC_CMD_FAST_IO ((uint8_t)39) /!< SD card doesn't support it (Reserved). /
ganlikun	0:13413ea9a877	238	#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /!< SD card doesn't support it (Reserved). /
ganlikun	0:13413ea9a877	239	#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
ganlikun	0:13413ea9a877	240	the SET_BLOCK_LEN command. */
ganlikun	0:13413ea9a877	241	#define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
ganlikun	0:13413ea9a877	242	than a standard command. */
ganlikun	0:13413ea9a877	243	#define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
ganlikun	0:13413ea9a877	244	for general purpose/application specific commands. */
ganlikun	0:13413ea9a877	245	#define SDMMC_CMD_NO_CMD ((uint8_t)64) /!< No command /
ganlikun	0:13413ea9a877	246
ganlikun	0:13413ea9a877	247	/**
ganlikun	0:13413ea9a877	248	* @brief Following commands are SD Card Specific commands.
ganlikun	0:13413ea9a877	249	* SDMMC_APP_CMD should be sent before sending these commands.
ganlikun	0:13413ea9a877	250	*/
ganlikun	0:13413ea9a877	251	#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
ganlikun	0:13413ea9a877	252	widths are given in SCR register. */
ganlikun	0:13413ea9a877	253	#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /!< (ACMD13) Sends the SD status. /
ganlikun	0:13413ea9a877	254	#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
ganlikun	0:13413ea9a877	255	32bit+CRC data block. */
ganlikun	0:13413ea9a877	256	#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
ganlikun	0:13413ea9a877	257	send its operating condition register (OCR) content in the response on the CMD line. */
ganlikun	0:13413ea9a877	258	#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card /
ganlikun	0:13413ea9a877	259	#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /!< Reads the SD Configuration Register (SCR). /
ganlikun	0:13413ea9a877	260	#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /!< For SD I/O card only, reserved for security specification. /
ganlikun	0:13413ea9a877	261	#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /!< For SD I/O card only, reserved for security specification. /
ganlikun	0:13413ea9a877	262
ganlikun	0:13413ea9a877	263	/**
ganlikun	0:13413ea9a877	264	* @brief Following commands are SD Card Specific security commands.
ganlikun	0:13413ea9a877	265	* SDMMC_CMD_APP_CMD should be sent before sending these commands.
ganlikun	0:13413ea9a877	266	*/
ganlikun	0:13413ea9a877	267	#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43)
ganlikun	0:13413ea9a877	268	#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44)
ganlikun	0:13413ea9a877	269	#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
ganlikun	0:13413ea9a877	270	#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
ganlikun	0:13413ea9a877	271	#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
ganlikun	0:13413ea9a877	272	#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
ganlikun	0:13413ea9a877	273	#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
ganlikun	0:13413ea9a877	274	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
ganlikun	0:13413ea9a877	275	#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
ganlikun	0:13413ea9a877	276	#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
ganlikun	0:13413ea9a877	277	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
ganlikun	0:13413ea9a877	278
ganlikun	0:13413ea9a877	279	/**
ganlikun	0:13413ea9a877	280	* @brief Masks for errors Card Status R1 (OCR Register)
ganlikun	0:13413ea9a877	281	*/
ganlikun	0:13413ea9a877	282	#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
ganlikun	0:13413ea9a877	283	#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
ganlikun	0:13413ea9a877	284	#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
ganlikun	0:13413ea9a877	285	#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
ganlikun	0:13413ea9a877	286	#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
ganlikun	0:13413ea9a877	287	#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
ganlikun	0:13413ea9a877	288	#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
ganlikun	0:13413ea9a877	289	#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
ganlikun	0:13413ea9a877	290	#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
ganlikun	0:13413ea9a877	291	#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
ganlikun	0:13413ea9a877	292	#define SDMMC_OCR_CC_ERROR 0x00100000U
ganlikun	0:13413ea9a877	293	#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
ganlikun	0:13413ea9a877	294	#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
ganlikun	0:13413ea9a877	295	#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
ganlikun	0:13413ea9a877	296	#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
ganlikun	0:13413ea9a877	297	#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
ganlikun	0:13413ea9a877	298	#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
ganlikun	0:13413ea9a877	299	#define SDMMC_OCR_ERASE_RESET 0x00002000U
ganlikun	0:13413ea9a877	300	#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
ganlikun	0:13413ea9a877	301	#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
ganlikun	0:13413ea9a877	302
ganlikun	0:13413ea9a877	303	/**
ganlikun	0:13413ea9a877	304	* @brief Masks for R6 Response
ganlikun	0:13413ea9a877	305	*/
ganlikun	0:13413ea9a877	306	#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
ganlikun	0:13413ea9a877	307	#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
ganlikun	0:13413ea9a877	308	#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
ganlikun	0:13413ea9a877	309
ganlikun	0:13413ea9a877	310	#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
ganlikun	0:13413ea9a877	311	#define SDMMC_HIGH_CAPACITY 0x40000000U
ganlikun	0:13413ea9a877	312	#define SDMMC_STD_CAPACITY 0x00000000U
ganlikun	0:13413ea9a877	313	#define SDMMC_CHECK_PATTERN 0x000001AAU
ganlikun	0:13413ea9a877	314
ganlikun	0:13413ea9a877	315	#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
ganlikun	0:13413ea9a877	316
ganlikun	0:13413ea9a877	317	#define SDMMC_MAX_TRIAL 0x0000FFFFU
ganlikun	0:13413ea9a877	318
ganlikun	0:13413ea9a877	319	#define SDMMC_ALLZERO 0x00000000U
ganlikun	0:13413ea9a877	320
ganlikun	0:13413ea9a877	321	#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
ganlikun	0:13413ea9a877	322	#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
ganlikun	0:13413ea9a877	323	#define SDMMC_CARD_LOCKED 0x02000000U
ganlikun	0:13413ea9a877	324
ganlikun	0:13413ea9a877	325	#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
ganlikun	0:13413ea9a877	326
ganlikun	0:13413ea9a877	327	#define SDMMC_0TO7BITS 0x000000FFU
ganlikun	0:13413ea9a877	328	#define SDMMC_8TO15BITS 0x0000FF00U
ganlikun	0:13413ea9a877	329	#define SDMMC_16TO23BITS 0x00FF0000U
ganlikun	0:13413ea9a877	330	#define SDMMC_24TO31BITS 0xFF000000U
ganlikun	0:13413ea9a877	331	#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
ganlikun	0:13413ea9a877	332
ganlikun	0:13413ea9a877	333	#define SDMMC_HALFFIFO 0x00000008U
ganlikun	0:13413ea9a877	334	#define SDMMC_HALFFIFOBYTES 0x00000020U
ganlikun	0:13413ea9a877	335
ganlikun	0:13413ea9a877	336	/**
ganlikun	0:13413ea9a877	337	* @brief Command Class supported
ganlikun	0:13413ea9a877	338	*/
ganlikun	0:13413ea9a877	339	#define SDIO_CCCC_ERASE 0x00000020U
ganlikun	0:13413ea9a877	340
ganlikun	0:13413ea9a877	341	#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
ganlikun	0:13413ea9a877	342	#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
ganlikun	0:13413ea9a877	343
ganlikun	0:13413ea9a877	344
ganlikun	0:13413ea9a877	345	/** @defgroup SDIO_LL_Clock_Edge Clock Edge
ganlikun	0:13413ea9a877	346	* @{
ganlikun	0:13413ea9a877	347	*/
ganlikun	0:13413ea9a877	348	#define SDIO_CLOCK_EDGE_RISING 0x00000000U
ganlikun	0:13413ea9a877	349	#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
ganlikun	0:13413ea9a877	350
ganlikun	0:13413ea9a877	351	#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) \|\| \
ganlikun	0:13413ea9a877	352	((EDGE) == SDIO_CLOCK_EDGE_FALLING))
ganlikun	0:13413ea9a877	353	/**
ganlikun	0:13413ea9a877	354	* @}
ganlikun	0:13413ea9a877	355	*/
ganlikun	0:13413ea9a877	356
ganlikun	0:13413ea9a877	357	/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
ganlikun	0:13413ea9a877	358	* @{
ganlikun	0:13413ea9a877	359	*/
ganlikun	0:13413ea9a877	360	#define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	361	#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
ganlikun	0:13413ea9a877	362
ganlikun	0:13413ea9a877	363	#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) \|\| \
ganlikun	0:13413ea9a877	364	((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
ganlikun	0:13413ea9a877	365	/**
ganlikun	0:13413ea9a877	366	* @}
ganlikun	0:13413ea9a877	367	*/
ganlikun	0:13413ea9a877	368
ganlikun	0:13413ea9a877	369	/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
ganlikun	0:13413ea9a877	370	* @{
ganlikun	0:13413ea9a877	371	*/
ganlikun	0:13413ea9a877	372	#define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	373	#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
ganlikun	0:13413ea9a877	374
ganlikun	0:13413ea9a877	375	#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) \|\| \
ganlikun	0:13413ea9a877	376	((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
ganlikun	0:13413ea9a877	377	/**
ganlikun	0:13413ea9a877	378	* @}
ganlikun	0:13413ea9a877	379	*/
ganlikun	0:13413ea9a877	380
ganlikun	0:13413ea9a877	381	/** @defgroup SDIO_LL_Bus_Wide Bus Width
ganlikun	0:13413ea9a877	382	* @{
ganlikun	0:13413ea9a877	383	*/
ganlikun	0:13413ea9a877	384	#define SDIO_BUS_WIDE_1B 0x00000000U
ganlikun	0:13413ea9a877	385	#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
ganlikun	0:13413ea9a877	386	#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
ganlikun	0:13413ea9a877	387
ganlikun	0:13413ea9a877	388	#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) \|\| \
ganlikun	0:13413ea9a877	389	((WIDE) == SDIO_BUS_WIDE_4B) \|\| \
ganlikun	0:13413ea9a877	390	((WIDE) == SDIO_BUS_WIDE_8B))
ganlikun	0:13413ea9a877	391	/**
ganlikun	0:13413ea9a877	392	* @}
ganlikun	0:13413ea9a877	393	*/
ganlikun	0:13413ea9a877	394
ganlikun	0:13413ea9a877	395	/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
ganlikun	0:13413ea9a877	396	* @{
ganlikun	0:13413ea9a877	397	*/
ganlikun	0:13413ea9a877	398	#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	399	#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
ganlikun	0:13413ea9a877	400
ganlikun	0:13413ea9a877	401	#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
ganlikun	0:13413ea9a877	402	((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
ganlikun	0:13413ea9a877	403	/**
ganlikun	0:13413ea9a877	404	* @}
ganlikun	0:13413ea9a877	405	*/
ganlikun	0:13413ea9a877	406
ganlikun	0:13413ea9a877	407	/** @defgroup SDIO_LL_Clock_Division Clock Division
ganlikun	0:13413ea9a877	408	* @{
ganlikun	0:13413ea9a877	409	*/
ganlikun	0:13413ea9a877	410	#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
ganlikun	0:13413ea9a877	411	/**
ganlikun	0:13413ea9a877	412	* @}
ganlikun	0:13413ea9a877	413	*/
ganlikun	0:13413ea9a877	414
ganlikun	0:13413ea9a877	415	/** @defgroup SDIO_LL_Command_Index Command Index
ganlikun	0:13413ea9a877	416	* @{
ganlikun	0:13413ea9a877	417	*/
ganlikun	0:13413ea9a877	418	#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
ganlikun	0:13413ea9a877	419	/**
ganlikun	0:13413ea9a877	420	* @}
ganlikun	0:13413ea9a877	421	*/
ganlikun	0:13413ea9a877	422
ganlikun	0:13413ea9a877	423	/** @defgroup SDIO_LL_Response_Type Response Type
ganlikun	0:13413ea9a877	424	* @{
ganlikun	0:13413ea9a877	425	*/
ganlikun	0:13413ea9a877	426	#define SDIO_RESPONSE_NO 0x00000000U
ganlikun	0:13413ea9a877	427	#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
ganlikun	0:13413ea9a877	428	#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
ganlikun	0:13413ea9a877	429
ganlikun	0:13413ea9a877	430	#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) \|\| \
ganlikun	0:13413ea9a877	431	((RESPONSE) == SDIO_RESPONSE_SHORT) \|\| \
ganlikun	0:13413ea9a877	432	((RESPONSE) == SDIO_RESPONSE_LONG))
ganlikun	0:13413ea9a877	433	/**
ganlikun	0:13413ea9a877	434	* @}
ganlikun	0:13413ea9a877	435	*/
ganlikun	0:13413ea9a877	436
ganlikun	0:13413ea9a877	437	/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
ganlikun	0:13413ea9a877	438	* @{
ganlikun	0:13413ea9a877	439	*/
ganlikun	0:13413ea9a877	440	#define SDIO_WAIT_NO 0x00000000U
ganlikun	0:13413ea9a877	441	#define SDIO_WAIT_IT SDIO_CMD_WAITINT
ganlikun	0:13413ea9a877	442	#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
ganlikun	0:13413ea9a877	443
ganlikun	0:13413ea9a877	444	#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) \|\| \
ganlikun	0:13413ea9a877	445	((WAIT) == SDIO_WAIT_IT) \|\| \
ganlikun	0:13413ea9a877	446	((WAIT) == SDIO_WAIT_PEND))
ganlikun	0:13413ea9a877	447	/**
ganlikun	0:13413ea9a877	448	* @}
ganlikun	0:13413ea9a877	449	*/
ganlikun	0:13413ea9a877	450
ganlikun	0:13413ea9a877	451	/** @defgroup SDIO_LL_CPSM_State CPSM State
ganlikun	0:13413ea9a877	452	* @{
ganlikun	0:13413ea9a877	453	*/
ganlikun	0:13413ea9a877	454	#define SDIO_CPSM_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	455	#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
ganlikun	0:13413ea9a877	456
ganlikun	0:13413ea9a877	457	#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) \|\| \
ganlikun	0:13413ea9a877	458	((CPSM) == SDIO_CPSM_ENABLE))
ganlikun	0:13413ea9a877	459	/**
ganlikun	0:13413ea9a877	460	* @}
ganlikun	0:13413ea9a877	461	*/
ganlikun	0:13413ea9a877	462
ganlikun	0:13413ea9a877	463	/** @defgroup SDIO_LL_Response_Registers Response Register
ganlikun	0:13413ea9a877	464	* @{
ganlikun	0:13413ea9a877	465	*/
ganlikun	0:13413ea9a877	466	#define SDIO_RESP1 0x00000000U
ganlikun	0:13413ea9a877	467	#define SDIO_RESP2 0x00000004U
ganlikun	0:13413ea9a877	468	#define SDIO_RESP3 0x00000008U
ganlikun	0:13413ea9a877	469	#define SDIO_RESP4 0x0000000CU
ganlikun	0:13413ea9a877	470
ganlikun	0:13413ea9a877	471	#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) \|\| \
ganlikun	0:13413ea9a877	472	((RESP) == SDIO_RESP2) \|\| \
ganlikun	0:13413ea9a877	473	((RESP) == SDIO_RESP3) \|\| \
ganlikun	0:13413ea9a877	474	((RESP) == SDIO_RESP4))
ganlikun	0:13413ea9a877	475	/**
ganlikun	0:13413ea9a877	476	* @}
ganlikun	0:13413ea9a877	477	*/
ganlikun	0:13413ea9a877	478
ganlikun	0:13413ea9a877	479	/** @defgroup SDIO_LL_Data_Length Data Lenght
ganlikun	0:13413ea9a877	480	* @{
ganlikun	0:13413ea9a877	481	*/
ganlikun	0:13413ea9a877	482	#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
ganlikun	0:13413ea9a877	483	/**
ganlikun	0:13413ea9a877	484	* @}
ganlikun	0:13413ea9a877	485	*/
ganlikun	0:13413ea9a877	486
ganlikun	0:13413ea9a877	487	/** @defgroup SDIO_LL_Data_Block_Size Data Block Size
ganlikun	0:13413ea9a877	488	* @{
ganlikun	0:13413ea9a877	489	*/
ganlikun	0:13413ea9a877	490	#define SDIO_DATABLOCK_SIZE_1B 0x00000000U
ganlikun	0:13413ea9a877	491	#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
ganlikun	0:13413ea9a877	492	#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
ganlikun	0:13413ea9a877	493	#define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1)
ganlikun	0:13413ea9a877	494	#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
ganlikun	0:13413ea9a877	495	#define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_2)
ganlikun	0:13413ea9a877	496	#define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2)
ganlikun	0:13413ea9a877	497	#define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2)
ganlikun	0:13413ea9a877	498	#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
ganlikun	0:13413ea9a877	499	#define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_3)
ganlikun	0:13413ea9a877	500	#define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_3)
ganlikun	0:13413ea9a877	501	#define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_3)
ganlikun	0:13413ea9a877	502	#define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
ganlikun	0:13413ea9a877	503	#define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
ganlikun	0:13413ea9a877	504	#define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
ganlikun	0:13413ea9a877	505
ganlikun	0:13413ea9a877	506	#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) \|\| \
ganlikun	0:13413ea9a877	507	((SIZE) == SDIO_DATABLOCK_SIZE_2B) \|\| \
ganlikun	0:13413ea9a877	508	((SIZE) == SDIO_DATABLOCK_SIZE_4B) \|\| \
ganlikun	0:13413ea9a877	509	((SIZE) == SDIO_DATABLOCK_SIZE_8B) \|\| \
ganlikun	0:13413ea9a877	510	((SIZE) == SDIO_DATABLOCK_SIZE_16B) \|\| \
ganlikun	0:13413ea9a877	511	((SIZE) == SDIO_DATABLOCK_SIZE_32B) \|\| \
ganlikun	0:13413ea9a877	512	((SIZE) == SDIO_DATABLOCK_SIZE_64B) \|\| \
ganlikun	0:13413ea9a877	513	((SIZE) == SDIO_DATABLOCK_SIZE_128B) \|\| \
ganlikun	0:13413ea9a877	514	((SIZE) == SDIO_DATABLOCK_SIZE_256B) \|\| \
ganlikun	0:13413ea9a877	515	((SIZE) == SDIO_DATABLOCK_SIZE_512B) \|\| \
ganlikun	0:13413ea9a877	516	((SIZE) == SDIO_DATABLOCK_SIZE_1024B) \|\| \
ganlikun	0:13413ea9a877	517	((SIZE) == SDIO_DATABLOCK_SIZE_2048B) \|\| \
ganlikun	0:13413ea9a877	518	((SIZE) == SDIO_DATABLOCK_SIZE_4096B) \|\| \
ganlikun	0:13413ea9a877	519	((SIZE) == SDIO_DATABLOCK_SIZE_8192B) \|\| \
ganlikun	0:13413ea9a877	520	((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
ganlikun	0:13413ea9a877	521	/**
ganlikun	0:13413ea9a877	522	* @}
ganlikun	0:13413ea9a877	523	*/
ganlikun	0:13413ea9a877	524
ganlikun	0:13413ea9a877	525	/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
ganlikun	0:13413ea9a877	526	* @{
ganlikun	0:13413ea9a877	527	*/
ganlikun	0:13413ea9a877	528	#define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U
ganlikun	0:13413ea9a877	529	#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
ganlikun	0:13413ea9a877	530
ganlikun	0:13413ea9a877	531	#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) \|\| \
ganlikun	0:13413ea9a877	532	((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
ganlikun	0:13413ea9a877	533	/**
ganlikun	0:13413ea9a877	534	* @}
ganlikun	0:13413ea9a877	535	*/
ganlikun	0:13413ea9a877	536
ganlikun	0:13413ea9a877	537	/** @defgroup SDIO_LL_Transfer_Type Transfer Type
ganlikun	0:13413ea9a877	538	* @{
ganlikun	0:13413ea9a877	539	*/
ganlikun	0:13413ea9a877	540	#define SDIO_TRANSFER_MODE_BLOCK 0x00000000U
ganlikun	0:13413ea9a877	541	#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
ganlikun	0:13413ea9a877	542
ganlikun	0:13413ea9a877	543	#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) \|\| \
ganlikun	0:13413ea9a877	544	((MODE) == SDIO_TRANSFER_MODE_STREAM))
ganlikun	0:13413ea9a877	545	/**
ganlikun	0:13413ea9a877	546	* @}
ganlikun	0:13413ea9a877	547	*/
ganlikun	0:13413ea9a877	548
ganlikun	0:13413ea9a877	549	/** @defgroup SDIO_LL_DPSM_State DPSM State
ganlikun	0:13413ea9a877	550	* @{
ganlikun	0:13413ea9a877	551	*/
ganlikun	0:13413ea9a877	552	#define SDIO_DPSM_DISABLE 0x00000000U
ganlikun	0:13413ea9a877	553	#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
ganlikun	0:13413ea9a877	554
ganlikun	0:13413ea9a877	555	#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) \|\|\
ganlikun	0:13413ea9a877	556	((DPSM) == SDIO_DPSM_ENABLE))
ganlikun	0:13413ea9a877	557	/**
ganlikun	0:13413ea9a877	558	* @}
ganlikun	0:13413ea9a877	559	*/
ganlikun	0:13413ea9a877	560
ganlikun	0:13413ea9a877	561	/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
ganlikun	0:13413ea9a877	562	* @{
ganlikun	0:13413ea9a877	563	*/
ganlikun	0:13413ea9a877	564	#define SDIO_READ_WAIT_MODE_DATA2 0x00000000U
ganlikun	0:13413ea9a877	565	#define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD)
ganlikun	0:13413ea9a877	566
ganlikun	0:13413ea9a877	567	#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) \|\| \
ganlikun	0:13413ea9a877	568	((MODE) == SDIO_READ_WAIT_MODE_DATA2))
ganlikun	0:13413ea9a877	569	/**
ganlikun	0:13413ea9a877	570	* @}
ganlikun	0:13413ea9a877	571	*/
ganlikun	0:13413ea9a877	572
ganlikun	0:13413ea9a877	573	/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
ganlikun	0:13413ea9a877	574	* @{
ganlikun	0:13413ea9a877	575	*/
ganlikun	0:13413ea9a877	576	#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
ganlikun	0:13413ea9a877	577	#define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
ganlikun	0:13413ea9a877	578	#define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
ganlikun	0:13413ea9a877	579	#define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
ganlikun	0:13413ea9a877	580	#define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
ganlikun	0:13413ea9a877	581	#define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
ganlikun	0:13413ea9a877	582	#define SDIO_IT_CMDREND SDIO_STA_CMDREND
ganlikun	0:13413ea9a877	583	#define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
ganlikun	0:13413ea9a877	584	#define SDIO_IT_DATAEND SDIO_STA_DATAEND
ganlikun	0:13413ea9a877	585	#define SDIO_IT_STBITERR SDIO_STA_STBITERR
ganlikun	0:13413ea9a877	586	#define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
ganlikun	0:13413ea9a877	587	#define SDIO_IT_CMDACT SDIO_STA_CMDACT
ganlikun	0:13413ea9a877	588	#define SDIO_IT_TXACT SDIO_STA_TXACT
ganlikun	0:13413ea9a877	589	#define SDIO_IT_RXACT SDIO_STA_RXACT
ganlikun	0:13413ea9a877	590	#define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
ganlikun	0:13413ea9a877	591	#define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
ganlikun	0:13413ea9a877	592	#define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
ganlikun	0:13413ea9a877	593	#define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
ganlikun	0:13413ea9a877	594	#define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
ganlikun	0:13413ea9a877	595	#define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
ganlikun	0:13413ea9a877	596	#define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
ganlikun	0:13413ea9a877	597	#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
ganlikun	0:13413ea9a877	598	#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
ganlikun	0:13413ea9a877	599	#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
ganlikun	0:13413ea9a877	600	/**
ganlikun	0:13413ea9a877	601	* @}
ganlikun	0:13413ea9a877	602	*/
ganlikun	0:13413ea9a877	603
ganlikun	0:13413ea9a877	604	/** @defgroup SDIO_LL_Flags Flags
ganlikun	0:13413ea9a877	605	* @{
ganlikun	0:13413ea9a877	606	*/
ganlikun	0:13413ea9a877	607	#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
ganlikun	0:13413ea9a877	608	#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
ganlikun	0:13413ea9a877	609	#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
ganlikun	0:13413ea9a877	610	#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
ganlikun	0:13413ea9a877	611	#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
ganlikun	0:13413ea9a877	612	#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
ganlikun	0:13413ea9a877	613	#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
ganlikun	0:13413ea9a877	614	#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
ganlikun	0:13413ea9a877	615	#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
ganlikun	0:13413ea9a877	616	#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
ganlikun	0:13413ea9a877	617	#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
ganlikun	0:13413ea9a877	618	#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
ganlikun	0:13413ea9a877	619	#define SDIO_FLAG_TXACT SDIO_STA_TXACT
ganlikun	0:13413ea9a877	620	#define SDIO_FLAG_RXACT SDIO_STA_RXACT
ganlikun	0:13413ea9a877	621	#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
ganlikun	0:13413ea9a877	622	#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
ganlikun	0:13413ea9a877	623	#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
ganlikun	0:13413ea9a877	624	#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
ganlikun	0:13413ea9a877	625	#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
ganlikun	0:13413ea9a877	626	#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
ganlikun	0:13413ea9a877	627	#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
ganlikun	0:13413ea9a877	628	#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
ganlikun	0:13413ea9a877	629	#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
ganlikun	0:13413ea9a877	630	#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
ganlikun	0:13413ea9a877	631	#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL \| SDIO_FLAG_DCRCFAIL \| SDIO_FLAG_CTIMEOUT \|\
ganlikun	0:13413ea9a877	632	SDIO_FLAG_DTIMEOUT \| SDIO_FLAG_TXUNDERR \| SDIO_FLAG_RXOVERR \|\
ganlikun	0:13413ea9a877	633	SDIO_FLAG_CMDREND \| SDIO_FLAG_CMDSENT \| SDIO_FLAG_DATAEND \|\
ganlikun	0:13413ea9a877	634	SDIO_FLAG_DBCKEND))
ganlikun	0:13413ea9a877	635	/**
ganlikun	0:13413ea9a877	636	* @}
ganlikun	0:13413ea9a877	637	*/
ganlikun	0:13413ea9a877	638
ganlikun	0:13413ea9a877	639	/**
ganlikun	0:13413ea9a877	640	* @}
ganlikun	0:13413ea9a877	641	*/
ganlikun	0:13413ea9a877	642
ganlikun	0:13413ea9a877	643	/* Exported macro ------------------------------------------------------------*/
ganlikun	0:13413ea9a877	644	/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
ganlikun	0:13413ea9a877	645	* @{
ganlikun	0:13413ea9a877	646	*/
ganlikun	0:13413ea9a877	647
ganlikun	0:13413ea9a877	648	/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
ganlikun	0:13413ea9a877	649	* @{
ganlikun	0:13413ea9a877	650	*/
ganlikun	0:13413ea9a877	651	/* ------------ SDIO registers bit address in the alias region -------------- */
ganlikun	0:13413ea9a877	652	#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
ganlikun	0:13413ea9a877	653
ganlikun	0:13413ea9a877	654	/* --- CLKCR Register ---*/
ganlikun	0:13413ea9a877	655	/* Alias word address of CLKEN bit */
ganlikun	0:13413ea9a877	656	#define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
ganlikun	0:13413ea9a877	657	#define CLKEN_BITNUMBER 0x08U
ganlikun	0:13413ea9a877	658	#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
ganlikun	0:13413ea9a877	659
ganlikun	0:13413ea9a877	660	/* --- CMD Register ---*/
ganlikun	0:13413ea9a877	661	/* Alias word address of SDIOSUSPEND bit */
ganlikun	0:13413ea9a877	662	#define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
ganlikun	0:13413ea9a877	663	#define SDIOSUSPEND_BITNUMBER 0x0BU
ganlikun	0:13413ea9a877	664	#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
ganlikun	0:13413ea9a877	665
ganlikun	0:13413ea9a877	666	/* Alias word address of ENCMDCOMPL bit */
ganlikun	0:13413ea9a877	667	#define ENCMDCOMPL_BITNUMBER 0x0CU
ganlikun	0:13413ea9a877	668	#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
ganlikun	0:13413ea9a877	669
ganlikun	0:13413ea9a877	670	/* Alias word address of NIEN bit */
ganlikun	0:13413ea9a877	671	#define NIEN_BITNUMBER 0x0DU
ganlikun	0:13413ea9a877	672	#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
ganlikun	0:13413ea9a877	673
ganlikun	0:13413ea9a877	674	/* Alias word address of ATACMD bit */
ganlikun	0:13413ea9a877	675	#define ATACMD_BITNUMBER 0x0EU
ganlikun	0:13413ea9a877	676	#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
ganlikun	0:13413ea9a877	677
ganlikun	0:13413ea9a877	678	/* --- DCTRL Register ---*/
ganlikun	0:13413ea9a877	679	/* Alias word address of DMAEN bit */
ganlikun	0:13413ea9a877	680	#define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
ganlikun	0:13413ea9a877	681	#define DMAEN_BITNUMBER 0x03U
ganlikun	0:13413ea9a877	682	#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
ganlikun	0:13413ea9a877	683
ganlikun	0:13413ea9a877	684	/* Alias word address of RWSTART bit */
ganlikun	0:13413ea9a877	685	#define RWSTART_BITNUMBER 0x08U
ganlikun	0:13413ea9a877	686	#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
ganlikun	0:13413ea9a877	687
ganlikun	0:13413ea9a877	688	/* Alias word address of RWSTOP bit */
ganlikun	0:13413ea9a877	689	#define RWSTOP_BITNUMBER 0x09U
ganlikun	0:13413ea9a877	690	#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
ganlikun	0:13413ea9a877	691
ganlikun	0:13413ea9a877	692	/* Alias word address of RWMOD bit */
ganlikun	0:13413ea9a877	693	#define RWMOD_BITNUMBER 0x0AU
ganlikun	0:13413ea9a877	694	#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
ganlikun	0:13413ea9a877	695
ganlikun	0:13413ea9a877	696	/* Alias word address of SDIOEN bit */
ganlikun	0:13413ea9a877	697	#define SDIOEN_BITNUMBER 0x0BU
ganlikun	0:13413ea9a877	698	#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
ganlikun	0:13413ea9a877	699	/**
ganlikun	0:13413ea9a877	700	* @}
ganlikun	0:13413ea9a877	701	*/
ganlikun	0:13413ea9a877	702
ganlikun	0:13413ea9a877	703	/** @defgroup SDIO_LL_Register Bits And Addresses Definitions
ganlikun	0:13413ea9a877	704	* @brief SDIO_LL registers bit address in the alias region
ganlikun	0:13413ea9a877	705	* @{
ganlikun	0:13413ea9a877	706	*/
ganlikun	0:13413ea9a877	707	/* ---------------------- SDIO registers bit mask --------------------------- */
ganlikun	0:13413ea9a877	708	/* --- CLKCR Register ---*/
ganlikun	0:13413ea9a877	709	/* CLKCR register clear mask */
ganlikun	0:13413ea9a877	710	#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV \| SDIO_CLKCR_PWRSAV \|\
ganlikun	0:13413ea9a877	711	SDIO_CLKCR_BYPASS \| SDIO_CLKCR_WIDBUS \|\
ganlikun	0:13413ea9a877	712	SDIO_CLKCR_NEGEDGE \| SDIO_CLKCR_HWFC_EN))
ganlikun	0:13413ea9a877	713
ganlikun	0:13413ea9a877	714	/* --- DCTRL Register ---*/
ganlikun	0:13413ea9a877	715	/* SDIO DCTRL Clear Mask */
ganlikun	0:13413ea9a877	716	#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN \| SDIO_DCTRL_DTDIR \|\
ganlikun	0:13413ea9a877	717	SDIO_DCTRL_DTMODE \| SDIO_DCTRL_DBLOCKSIZE))
ganlikun	0:13413ea9a877	718
ganlikun	0:13413ea9a877	719	/* --- CMD Register ---*/
ganlikun	0:13413ea9a877	720	/* CMD Register clear mask */
ganlikun	0:13413ea9a877	721	#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX \| SDIO_CMD_WAITRESP \|\
ganlikun	0:13413ea9a877	722	SDIO_CMD_WAITINT \| SDIO_CMD_WAITPEND \|\
ganlikun	0:13413ea9a877	723	SDIO_CMD_CPSMEN \| SDIO_CMD_SDIOSUSPEND))
ganlikun	0:13413ea9a877	724
ganlikun	0:13413ea9a877	725	/* SDIO Initialization Frequency (400KHz max) */
ganlikun	0:13413ea9a877	726	#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
ganlikun	0:13413ea9a877	727
ganlikun	0:13413ea9a877	728	/* SDIO Data Transfer Frequency (25MHz max) */
ganlikun	0:13413ea9a877	729	#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
ganlikun	0:13413ea9a877	730
ganlikun	0:13413ea9a877	731	/**
ganlikun	0:13413ea9a877	732	* @}
ganlikun	0:13413ea9a877	733	*/
ganlikun	0:13413ea9a877	734
ganlikun	0:13413ea9a877	735	/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
ganlikun	0:13413ea9a877	736	* @brief macros to handle interrupts and specific clock configurations
ganlikun	0:13413ea9a877	737	* @{
ganlikun	0:13413ea9a877	738	*/
ganlikun	0:13413ea9a877	739
ganlikun	0:13413ea9a877	740	/**
ganlikun	0:13413ea9a877	741	* @brief Enable the SDIO device.
ganlikun	0:13413ea9a877	742	* @param __INSTANCE__: SDIO Instance
ganlikun	0:13413ea9a877	743	* @retval None
ganlikun	0:13413ea9a877	744	*/
ganlikun	0:13413ea9a877	745	#define __SDIO_ENABLE(__INSTANCE__) ((__IO uint32_t )CLKCR_CLKEN_BB = ENABLE)
ganlikun	0:13413ea9a877	746
ganlikun	0:13413ea9a877	747	/**
ganlikun	0:13413ea9a877	748	* @brief Disable the SDIO device.
ganlikun	0:13413ea9a877	749	* @param __INSTANCE__: SDIO Instance
ganlikun	0:13413ea9a877	750	* @retval None
ganlikun	0:13413ea9a877	751	*/
ganlikun	0:13413ea9a877	752	#define __SDIO_DISABLE(__INSTANCE__) ((__IO uint32_t )CLKCR_CLKEN_BB = DISABLE)
ganlikun	0:13413ea9a877	753
ganlikun	0:13413ea9a877	754	/**
ganlikun	0:13413ea9a877	755	* @brief Enable the SDIO DMA transfer.
ganlikun	0:13413ea9a877	756	* @param __INSTANCE__: SDIO Instance
ganlikun	0:13413ea9a877	757	* @retval None
ganlikun	0:13413ea9a877	758	*/
ganlikun	0:13413ea9a877	759	#define __SDIO_DMA_ENABLE(__INSTANCE__) ((__IO uint32_t )DCTRL_DMAEN_BB = ENABLE)
ganlikun	0:13413ea9a877	760	/**
ganlikun	0:13413ea9a877	761	* @brief Disable the SDIO DMA transfer.
ganlikun	0:13413ea9a877	762	* @param __INSTANCE__: SDIO Instance
ganlikun	0:13413ea9a877	763	* @retval None
ganlikun	0:13413ea9a877	764	*/
ganlikun	0:13413ea9a877	765	#define __SDIO_DMA_DISABLE(__INSTANCE__) ((__IO uint32_t )DCTRL_DMAEN_BB = DISABLE)
ganlikun	0:13413ea9a877	766
ganlikun	0:13413ea9a877	767	/**
ganlikun	0:13413ea9a877	768	* @brief Enable the SDIO device interrupt.
ganlikun	0:13413ea9a877	769	* @param __INSTANCE__ : Pointer to SDIO register base
ganlikun	0:13413ea9a877	770	* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
ganlikun	0:13413ea9a877	771	* This parameter can be one or a combination of the following values:
ganlikun	0:13413ea9a877	772	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
ganlikun	0:13413ea9a877	773	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
ganlikun	0:13413ea9a877	774	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
ganlikun	0:13413ea9a877	775	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
ganlikun	0:13413ea9a877	776	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
ganlikun	0:13413ea9a877	777	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
ganlikun	0:13413ea9a877	778	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
ganlikun	0:13413ea9a877	779	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
ganlikun	0:13413ea9a877	780	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
ganlikun	0:13413ea9a877	781	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
ganlikun	0:13413ea9a877	782	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
ganlikun	0:13413ea9a877	783	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
ganlikun	0:13413ea9a877	784	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
ganlikun	0:13413ea9a877	785	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
ganlikun	0:13413ea9a877	786	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
ganlikun	0:13413ea9a877	787	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
ganlikun	0:13413ea9a877	788	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
ganlikun	0:13413ea9a877	789	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
ganlikun	0:13413ea9a877	790	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
ganlikun	0:13413ea9a877	791	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
ganlikun	0:13413ea9a877	792	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
ganlikun	0:13413ea9a877	793	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
ganlikun	0:13413ea9a877	794	* @retval None
ganlikun	0:13413ea9a877	795	*/
ganlikun	0:13413ea9a877	796	#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
ganlikun	0:13413ea9a877	797
ganlikun	0:13413ea9a877	798	/**
ganlikun	0:13413ea9a877	799	* @brief Disable the SDIO device interrupt.
ganlikun	0:13413ea9a877	800	* @param __INSTANCE__ : Pointer to SDIO register base
ganlikun	0:13413ea9a877	801	* @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
ganlikun	0:13413ea9a877	802	* This parameter can be one or a combination of the following values:
ganlikun	0:13413ea9a877	803	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
ganlikun	0:13413ea9a877	804	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
ganlikun	0:13413ea9a877	805	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
ganlikun	0:13413ea9a877	806	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
ganlikun	0:13413ea9a877	807	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
ganlikun	0:13413ea9a877	808	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
ganlikun	0:13413ea9a877	809	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
ganlikun	0:13413ea9a877	810	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
ganlikun	0:13413ea9a877	811	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
ganlikun	0:13413ea9a877	812	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
ganlikun	0:13413ea9a877	813	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
ganlikun	0:13413ea9a877	814	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
ganlikun	0:13413ea9a877	815	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
ganlikun	0:13413ea9a877	816	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
ganlikun	0:13413ea9a877	817	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
ganlikun	0:13413ea9a877	818	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
ganlikun	0:13413ea9a877	819	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
ganlikun	0:13413ea9a877	820	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
ganlikun	0:13413ea9a877	821	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
ganlikun	0:13413ea9a877	822	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
ganlikun	0:13413ea9a877	823	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
ganlikun	0:13413ea9a877	824	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
ganlikun	0:13413ea9a877	825	* @retval None
ganlikun	0:13413ea9a877	826	*/
ganlikun	0:13413ea9a877	827	#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
ganlikun	0:13413ea9a877	828
ganlikun	0:13413ea9a877	829	/**
ganlikun	0:13413ea9a877	830	* @brief Checks whether the specified SDIO flag is set or not.
ganlikun	0:13413ea9a877	831	* @param __INSTANCE__ : Pointer to SDIO register base
ganlikun	0:13413ea9a877	832	* @param __FLAG__: specifies the flag to check.
ganlikun	0:13413ea9a877	833	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	834	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
ganlikun	0:13413ea9a877	835	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
ganlikun	0:13413ea9a877	836	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
ganlikun	0:13413ea9a877	837	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
ganlikun	0:13413ea9a877	838	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
ganlikun	0:13413ea9a877	839	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
ganlikun	0:13413ea9a877	840	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
ganlikun	0:13413ea9a877	841	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
ganlikun	0:13413ea9a877	842	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
ganlikun	0:13413ea9a877	843	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
ganlikun	0:13413ea9a877	844	* @arg SDIO_FLAG_CMDACT: Command transfer in progress
ganlikun	0:13413ea9a877	845	* @arg SDIO_FLAG_TXACT: Data transmit in progress
ganlikun	0:13413ea9a877	846	* @arg SDIO_FLAG_RXACT: Data receive in progress
ganlikun	0:13413ea9a877	847	* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
ganlikun	0:13413ea9a877	848	* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
ganlikun	0:13413ea9a877	849	* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
ganlikun	0:13413ea9a877	850	* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
ganlikun	0:13413ea9a877	851	* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
ganlikun	0:13413ea9a877	852	* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
ganlikun	0:13413ea9a877	853	* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
ganlikun	0:13413ea9a877	854	* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
ganlikun	0:13413ea9a877	855	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
ganlikun	0:13413ea9a877	856	* @retval The new state of SDIO_FLAG (SET or RESET).
ganlikun	0:13413ea9a877	857	*/
ganlikun	0:13413ea9a877	858	#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
ganlikun	0:13413ea9a877	859
ganlikun	0:13413ea9a877	860
ganlikun	0:13413ea9a877	861	/**
ganlikun	0:13413ea9a877	862	* @brief Clears the SDIO pending flags.
ganlikun	0:13413ea9a877	863	* @param __INSTANCE__ : Pointer to SDIO register base
ganlikun	0:13413ea9a877	864	* @param __FLAG__: specifies the flag to clear.
ganlikun	0:13413ea9a877	865	* This parameter can be one or a combination of the following values:
ganlikun	0:13413ea9a877	866	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
ganlikun	0:13413ea9a877	867	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
ganlikun	0:13413ea9a877	868	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
ganlikun	0:13413ea9a877	869	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
ganlikun	0:13413ea9a877	870	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
ganlikun	0:13413ea9a877	871	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
ganlikun	0:13413ea9a877	872	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
ganlikun	0:13413ea9a877	873	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
ganlikun	0:13413ea9a877	874	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
ganlikun	0:13413ea9a877	875	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
ganlikun	0:13413ea9a877	876	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
ganlikun	0:13413ea9a877	877	* @retval None
ganlikun	0:13413ea9a877	878	*/
ganlikun	0:13413ea9a877	879	#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
ganlikun	0:13413ea9a877	880
ganlikun	0:13413ea9a877	881	/**
ganlikun	0:13413ea9a877	882	* @brief Checks whether the specified SDIO interrupt has occurred or not.
ganlikun	0:13413ea9a877	883	* @param __INSTANCE__ : Pointer to SDIO register base
ganlikun	0:13413ea9a877	884	* @param __INTERRUPT__: specifies the SDIO interrupt source to check.
ganlikun	0:13413ea9a877	885	* This parameter can be one of the following values:
ganlikun	0:13413ea9a877	886	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
ganlikun	0:13413ea9a877	887	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
ganlikun	0:13413ea9a877	888	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
ganlikun	0:13413ea9a877	889	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
ganlikun	0:13413ea9a877	890	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
ganlikun	0:13413ea9a877	891	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
ganlikun	0:13413ea9a877	892	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
ganlikun	0:13413ea9a877	893	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
ganlikun	0:13413ea9a877	894	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
ganlikun	0:13413ea9a877	895	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
ganlikun	0:13413ea9a877	896	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
ganlikun	0:13413ea9a877	897	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
ganlikun	0:13413ea9a877	898	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
ganlikun	0:13413ea9a877	899	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
ganlikun	0:13413ea9a877	900	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
ganlikun	0:13413ea9a877	901	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
ganlikun	0:13413ea9a877	902	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
ganlikun	0:13413ea9a877	903	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
ganlikun	0:13413ea9a877	904	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
ganlikun	0:13413ea9a877	905	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
ganlikun	0:13413ea9a877	906	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
ganlikun	0:13413ea9a877	907	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
ganlikun	0:13413ea9a877	908	* @retval The new state of SDIO_IT (SET or RESET).
ganlikun	0:13413ea9a877	909	*/
ganlikun	0:13413ea9a877	910	#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
ganlikun	0:13413ea9a877	911
ganlikun	0:13413ea9a877	912	/**
ganlikun	0:13413ea9a877	913	* @brief Clears the SDIO's interrupt pending bits.
ganlikun	0:13413ea9a877	914	* @param __INSTANCE__ : Pointer to SDIO register base
ganlikun	0:13413ea9a877	915	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
ganlikun	0:13413ea9a877	916	* This parameter can be one or a combination of the following values:
ganlikun	0:13413ea9a877	917	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
ganlikun	0:13413ea9a877	918	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
ganlikun	0:13413ea9a877	919	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
ganlikun	0:13413ea9a877	920	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
ganlikun	0:13413ea9a877	921	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
ganlikun	0:13413ea9a877	922	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
ganlikun	0:13413ea9a877	923	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
ganlikun	0:13413ea9a877	924	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
ganlikun	0:13413ea9a877	925	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
ganlikun	0:13413ea9a877	926	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
ganlikun	0:13413ea9a877	927	* @retval None
ganlikun	0:13413ea9a877	928	*/
ganlikun	0:13413ea9a877	929	#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
ganlikun	0:13413ea9a877	930
ganlikun	0:13413ea9a877	931	/**
ganlikun	0:13413ea9a877	932	* @brief Enable Start the SD I/O Read Wait operation.
ganlikun	0:13413ea9a877	933	* @param __INSTANCE__ : Pointer to SDIO register base
ganlikun	0:13413ea9a877	934	* @retval None
ganlikun	0:13413ea9a877	935	*/
ganlikun	0:13413ea9a877	936	#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTART_BB = ENABLE)
ganlikun	0:13413ea9a877	937
ganlikun	0:13413ea9a877	938	/**
ganlikun	0:13413ea9a877	939	* @brief Disable Start the SD I/O Read Wait operations.
ganlikun	0:13413ea9a877	940	* @param __INSTANCE__ : Pointer to SDIO register base
ganlikun	0:13413ea9a877	941	* @retval None
ganlikun	0:13413ea9a877	942	*/
ganlikun	0:13413ea9a877	943	#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTART_BB = DISABLE)
ganlikun	0:13413ea9a877	944
ganlikun	0:13413ea9a877	945	/**
ganlikun	0:13413ea9a877	946	* @brief Enable Start the SD I/O Read Wait operation.
ganlikun	0:13413ea9a877	947	* @param __INSTANCE__ : Pointer to SDIO register base
ganlikun	0:13413ea9a877	948	* @retval None
ganlikun	0:13413ea9a877	949	*/
ganlikun	0:13413ea9a877	950	#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTOP_BB = ENABLE)
ganlikun	0:13413ea9a877	951
ganlikun	0:13413ea9a877	952	/**
ganlikun	0:13413ea9a877	953	* @brief Disable Stop the SD I/O Read Wait operations.
ganlikun	0:13413ea9a877	954	* @param __INSTANCE__ : Pointer to SDIO register base
ganlikun	0:13413ea9a877	955	* @retval None
ganlikun	0:13413ea9a877	956	*/
ganlikun	0:13413ea9a877	957	#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTOP_BB = DISABLE)
ganlikun	0:13413ea9a877	958
ganlikun	0:13413ea9a877	959	/**
ganlikun	0:13413ea9a877	960	* @brief Enable the SD I/O Mode Operation.
ganlikun	0:13413ea9a877	961	* @param __INSTANCE__ : Pointer to SDIO register base
ganlikun	0:13413ea9a877	962	* @retval None
ganlikun	0:13413ea9a877	963	*/
ganlikun	0:13413ea9a877	964	#define __SDIO_OPERATION_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_SDIOEN_BB = ENABLE)
ganlikun	0:13413ea9a877	965
ganlikun	0:13413ea9a877	966	/**
ganlikun	0:13413ea9a877	967	* @brief Disable the SD I/O Mode Operation.
ganlikun	0:13413ea9a877	968	* @param __INSTANCE__ : Pointer to SDIO register base
ganlikun	0:13413ea9a877	969	* @retval None
ganlikun	0:13413ea9a877	970	*/
ganlikun	0:13413ea9a877	971	#define __SDIO_OPERATION_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_SDIOEN_BB = DISABLE)
ganlikun	0:13413ea9a877	972
ganlikun	0:13413ea9a877	973	/**
ganlikun	0:13413ea9a877	974	* @brief Enable the SD I/O Suspend command sending.
ganlikun	0:13413ea9a877	975	* @param __INSTANCE__ : Pointer to SDIO register base
ganlikun	0:13413ea9a877	976	* @retval None
ganlikun	0:13413ea9a877	977	*/
ganlikun	0:13413ea9a877	978	#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = ENABLE)
ganlikun	0:13413ea9a877	979
ganlikun	0:13413ea9a877	980	/**
ganlikun	0:13413ea9a877	981	* @brief Disable the SD I/O Suspend command sending.
ganlikun	0:13413ea9a877	982	* @param __INSTANCE__ : Pointer to SDIO register base
ganlikun	0:13413ea9a877	983	* @retval None
ganlikun	0:13413ea9a877	984	*/
ganlikun	0:13413ea9a877	985	#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = DISABLE)
ganlikun	0:13413ea9a877	986
ganlikun	0:13413ea9a877	987	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
ganlikun	0:13413ea9a877	988	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
ganlikun	0:13413ea9a877	989	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
ganlikun	0:13413ea9a877	990	/**
ganlikun	0:13413ea9a877	991	* @brief Enable the command completion signal.
ganlikun	0:13413ea9a877	992	* @retval None
ganlikun	0:13413ea9a877	993	*/
ganlikun	0:13413ea9a877	994	#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = ENABLE)
ganlikun	0:13413ea9a877	995
ganlikun	0:13413ea9a877	996	/**
ganlikun	0:13413ea9a877	997	* @brief Disable the command completion signal.
ganlikun	0:13413ea9a877	998	* @retval None
ganlikun	0:13413ea9a877	999	*/
ganlikun	0:13413ea9a877	1000	#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = DISABLE)
ganlikun	0:13413ea9a877	1001
ganlikun	0:13413ea9a877	1002	/**
ganlikun	0:13413ea9a877	1003	* @brief Enable the CE-ATA interrupt.
ganlikun	0:13413ea9a877	1004	* @retval None
ganlikun	0:13413ea9a877	1005	*/
ganlikun	0:13413ea9a877	1006	#define __SDIO_CEATA_ENABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)0U)
ganlikun	0:13413ea9a877	1007
ganlikun	0:13413ea9a877	1008	/**
ganlikun	0:13413ea9a877	1009	* @brief Disable the CE-ATA interrupt.
ganlikun	0:13413ea9a877	1010	* @retval None
ganlikun	0:13413ea9a877	1011	*/
ganlikun	0:13413ea9a877	1012	#define __SDIO_CEATA_DISABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)1U)
ganlikun	0:13413ea9a877	1013
ganlikun	0:13413ea9a877	1014	/**
ganlikun	0:13413ea9a877	1015	* @brief Enable send CE-ATA command (CMD61).
ganlikun	0:13413ea9a877	1016	* @retval None
ganlikun	0:13413ea9a877	1017	*/
ganlikun	0:13413ea9a877	1018	#define __SDIO_CEATA_SENDCMD_ENABLE() ((__IO uint32_t ) CMD_ATACMD_BB = ENABLE)
ganlikun	0:13413ea9a877	1019
ganlikun	0:13413ea9a877	1020	/**
ganlikun	0:13413ea9a877	1021	* @brief Disable send CE-ATA command (CMD61).
ganlikun	0:13413ea9a877	1022	* @retval None
ganlikun	0:13413ea9a877	1023	*/
ganlikun	0:13413ea9a877	1024	#define __SDIO_CEATA_SENDCMD_DISABLE() ((__IO uint32_t ) CMD_ATACMD_BB = DISABLE)
ganlikun	0:13413ea9a877	1025	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\|\
ganlikun	0:13413ea9a877	1026	STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
ganlikun	0:13413ea9a877	1027
ganlikun	0:13413ea9a877	1028	/**
ganlikun	0:13413ea9a877	1029	* @}
ganlikun	0:13413ea9a877	1030	*/
ganlikun	0:13413ea9a877	1031
ganlikun	0:13413ea9a877	1032	/**
ganlikun	0:13413ea9a877	1033	* @}
ganlikun	0:13413ea9a877	1034	*/
ganlikun	0:13413ea9a877	1035
ganlikun	0:13413ea9a877	1036	/* Exported functions --------------------------------------------------------*/
ganlikun	0:13413ea9a877	1037	/** @addtogroup SDMMC_LL_Exported_Functions
ganlikun	0:13413ea9a877	1038	* @{
ganlikun	0:13413ea9a877	1039	*/
ganlikun	0:13413ea9a877	1040
ganlikun	0:13413ea9a877	1041	/* Initialization/de-initialization functions **********************************/
ganlikun	0:13413ea9a877	1042	/** @addtogroup HAL_SDMMC_LL_Group1
ganlikun	0:13413ea9a877	1043	* @{
ganlikun	0:13413ea9a877	1044	*/
ganlikun	0:13413ea9a877	1045	HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
ganlikun	0:13413ea9a877	1046	/**
ganlikun	0:13413ea9a877	1047	* @}
ganlikun	0:13413ea9a877	1048	*/
ganlikun	0:13413ea9a877	1049
ganlikun	0:13413ea9a877	1050	/* I/O operation functions *****************************************************/
ganlikun	0:13413ea9a877	1051	/** @addtogroup HAL_SDMMC_LL_Group2
ganlikun	0:13413ea9a877	1052	* @{
ganlikun	0:13413ea9a877	1053	*/
ganlikun	0:13413ea9a877	1054	uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
ganlikun	0:13413ea9a877	1055	HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef SDIOx, uint32_t pWriteData);
ganlikun	0:13413ea9a877	1056	/**
ganlikun	0:13413ea9a877	1057	* @}
ganlikun	0:13413ea9a877	1058	*/
ganlikun	0:13413ea9a877	1059
ganlikun	0:13413ea9a877	1060	/* Peripheral Control functions ************************************************/
ganlikun	0:13413ea9a877	1061	/** @addtogroup HAL_SDMMC_LL_Group3
ganlikun	0:13413ea9a877	1062	* @{
ganlikun	0:13413ea9a877	1063	*/
ganlikun	0:13413ea9a877	1064	HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
ganlikun	0:13413ea9a877	1065	HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
ganlikun	0:13413ea9a877	1066	uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
ganlikun	0:13413ea9a877	1067
ganlikun	0:13413ea9a877	1068	/* Command path state machine (CPSM) management functions */
ganlikun	0:13413ea9a877	1069	HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef SDIOx, SDIO_CmdInitTypeDef Command);
ganlikun	0:13413ea9a877	1070	uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
ganlikun	0:13413ea9a877	1071	uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
ganlikun	0:13413ea9a877	1072
ganlikun	0:13413ea9a877	1073	/* Data path state machine (DPSM) management functions */
ganlikun	0:13413ea9a877	1074	HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef SDIOx, SDIO_DataInitTypeDef Data);
ganlikun	0:13413ea9a877	1075	uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
ganlikun	0:13413ea9a877	1076	uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
ganlikun	0:13413ea9a877	1077
ganlikun	0:13413ea9a877	1078	/* SDMMC Cards mode management functions */
ganlikun	0:13413ea9a877	1079	HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
ganlikun	0:13413ea9a877	1080
ganlikun	0:13413ea9a877	1081	/* SDMMC Commands management functions */
ganlikun	0:13413ea9a877	1082	uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
ganlikun	0:13413ea9a877	1083	uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
ganlikun	0:13413ea9a877	1084	uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
ganlikun	0:13413ea9a877	1085	uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
ganlikun	0:13413ea9a877	1086	uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
ganlikun	0:13413ea9a877	1087	uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
ganlikun	0:13413ea9a877	1088	uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
ganlikun	0:13413ea9a877	1089	uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
ganlikun	0:13413ea9a877	1090	uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
ganlikun	0:13413ea9a877	1091	uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
ganlikun	0:13413ea9a877	1092	uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
ganlikun	0:13413ea9a877	1093	uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
ganlikun	0:13413ea9a877	1094	uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
ganlikun	0:13413ea9a877	1095	uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType);
ganlikun	0:13413ea9a877	1096	uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
ganlikun	0:13413ea9a877	1097	uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
ganlikun	0:13413ea9a877	1098	uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
ganlikun	0:13413ea9a877	1099	uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
ganlikun	0:13413ea9a877	1100	uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef SDIOx, uint16_t pRCA);
ganlikun	0:13413ea9a877	1101	uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
ganlikun	0:13413ea9a877	1102	uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
ganlikun	0:13413ea9a877	1103
ganlikun	0:13413ea9a877	1104	uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
ganlikun	0:13413ea9a877	1105	uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
ganlikun	0:13413ea9a877	1106	uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
ganlikun	0:13413ea9a877	1107	uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
ganlikun	0:13413ea9a877	1108
ganlikun	0:13413ea9a877	1109	/**
ganlikun	0:13413ea9a877	1110	* @}
ganlikun	0:13413ea9a877	1111	*/
ganlikun	0:13413ea9a877	1112
ganlikun	0:13413ea9a877	1113	/**
ganlikun	0:13413ea9a877	1114	* @}
ganlikun	0:13413ea9a877	1115	*/
ganlikun	0:13413ea9a877	1116
ganlikun	0:13413ea9a877	1117	/**
ganlikun	0:13413ea9a877	1118	* @}
ganlikun	0:13413ea9a877	1119	*/
ganlikun	0:13413ea9a877	1120
ganlikun	0:13413ea9a877	1121	/**
ganlikun	0:13413ea9a877	1122	* @}
ganlikun	0:13413ea9a877	1123	*/
ganlikun	0:13413ea9a877	1124
ganlikun	0:13413ea9a877	1125	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
ganlikun	0:13413ea9a877	1126	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
ganlikun	0:13413ea9a877	1127	STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
ganlikun	0:13413ea9a877	1128
ganlikun	0:13413ea9a877	1129	#ifdef __cplusplus
ganlikun	0:13413ea9a877	1130	}
ganlikun	0:13413ea9a877	1131	#endif
ganlikun	0:13413ea9a877	1132
ganlikun	0:13413ea9a877	1133	#endif /* __STM32F4xx_LL_SDMMC_H */
ganlikun	0:13413ea9a877	1134
ganlikun	0:13413ea9a877	1135	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
ganlikun	0:13413ea9a877	1136

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Type:	Library
Created:	05 Jul 2022
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	1

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.h@0:13413ea9a877, 2022-06-12 (annotated)

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