tan lulu / nRF24L01P

RADIO nRF24L01

Fork of nRF24L01P by Pablo Rodriguez

nRF24L01P.cpp@1:d6b43a63580a, 2016-07-04 (annotated)

Committer:
fytanlulu
Date:
Mon Jul 04 01:41:56 2016 +0000
Revision:
1:d6b43a63580a
Parent:
0:8d55f1f49a33 
AD5254???nRF??????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
pabloamr 0:8d55f1f49a33 1 /**
pabloamr 0:8d55f1f49a33 2 * @file nRF24L01P.cpp
pabloamr 0:8d55f1f49a33 3 *
pabloamr 0:8d55f1f49a33 4 * @author Owen Edwards
pabloamr 0:8d55f1f49a33 5 *
pabloamr 0:8d55f1f49a33 6 * @section LICENSE
pabloamr 0:8d55f1f49a33 7 *
pabloamr 0:8d55f1f49a33 8 * Copyright (c) 2010 Owen Edwards
pabloamr 0:8d55f1f49a33 9 *
pabloamr 0:8d55f1f49a33 10 * This program is free software: you can redistribute it and/or modify
pabloamr 0:8d55f1f49a33 11 * it under the terms of the GNU General Public License as published by
pabloamr 0:8d55f1f49a33 12 * the Free Software Foundation, either version 3 of the License, or
pabloamr 0:8d55f1f49a33 13 * (at your option) any later version.
pabloamr 0:8d55f1f49a33 14 *
pabloamr 0:8d55f1f49a33 15 * This program is distributed in the hope that it will be useful,
pabloamr 0:8d55f1f49a33 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
pabloamr 0:8d55f1f49a33 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
pabloamr 0:8d55f1f49a33 18 * GNU General Public License for more details.
pabloamr 0:8d55f1f49a33 19 *
pabloamr 0:8d55f1f49a33 20 * You should have received a copy of the GNU General Public License
pabloamr 0:8d55f1f49a33 21 * along with this program. If not, see <http://www.gnu.org/licenses/>.
pabloamr 0:8d55f1f49a33 22 *
pabloamr 0:8d55f1f49a33 23 * The above copyright notice and this permission notice shall be included in
pabloamr 0:8d55f1f49a33 24 * all copies or substantial portions of the Software.
pabloamr 0:8d55f1f49a33 25 *
pabloamr 0:8d55f1f49a33 26 * @section DESCRIPTION
pabloamr 0:8d55f1f49a33 27 *
pabloamr 0:8d55f1f49a33 28 * nRF24L01+ Single Chip 2.4GHz Transceiver from Nordic Semiconductor.
pabloamr 0:8d55f1f49a33 29 *
pabloamr 0:8d55f1f49a33 30 * Datasheet:
pabloamr 0:8d55f1f49a33 31 *
pabloamr 0:8d55f1f49a33 32 * http://www.nordicsemi.no/files/Product/data_sheet/nRF24L01P_Product_Specification_1_0.pdf
pabloamr 0:8d55f1f49a33 33 */
pabloamr 0:8d55f1f49a33 34
pabloamr 0:8d55f1f49a33 35 /**
pabloamr 0:8d55f1f49a33 36 * Includes
pabloamr 0:8d55f1f49a33 37 */
pabloamr 0:8d55f1f49a33 38 #include "nRF24L01P.h"
fytanlulu 1:d6b43a63580a 39 #define DEBUG
fytanlulu 1:d6b43a63580a 40 //#define address nRF_Address
pabloamr 0:8d55f1f49a33 41 /**
pabloamr 0:8d55f1f49a33 42 * Defines
pabloamr 0:8d55f1f49a33 43 *
pabloamr 0:8d55f1f49a33 44 * (Note that all defines here start with an underscore, e.g. '_NRF24L01P_MODE_UNKNOWN',
pabloamr 0:8d55f1f49a33 45 * and are local to this library. The defines in the nRF24L01P.h file do not start
pabloamr 0:8d55f1f49a33 46 * with the underscore, and can be used by code to access this library.)
pabloamr 0:8d55f1f49a33 47 */
pabloamr 0:8d55f1f49a33 48
pabloamr 0:8d55f1f49a33 49 typedef enum {
pabloamr 0:8d55f1f49a33 50 _NRF24L01P_MODE_UNKNOWN,
pabloamr 0:8d55f1f49a33 51 _NRF24L01P_MODE_POWER_DOWN,
pabloamr 0:8d55f1f49a33 52 _NRF24L01P_MODE_STANDBY,
pabloamr 0:8d55f1f49a33 53 _NRF24L01P_MODE_RX,
pabloamr 0:8d55f1f49a33 54 _NRF24L01P_MODE_TX,
pabloamr 0:8d55f1f49a33 55 } nRF24L01P_Mode_Type;
pabloamr 0:8d55f1f49a33 56
pabloamr 0:8d55f1f49a33 57 /*
pabloamr 0:8d55f1f49a33 58 * The following FIFOs are present in nRF24L01+:
pabloamr 0:8d55f1f49a33 59 * TX three level, 32 byte FIFO
pabloamr 0:8d55f1f49a33 60 * RX three level, 32 byte FIFO
pabloamr 0:8d55f1f49a33 61 */
pabloamr 0:8d55f1f49a33 62 #define _NRF24L01P_TX_FIFO_COUNT 33
pabloamr 0:8d55f1f49a33 63 #define _NRF24L01P_RX_FIFO_COUNT 33
pabloamr 0:8d55f1f49a33 64
pabloamr 0:8d55f1f49a33 65 #define _NRF24L01P_TX_FIFO_SIZE 32
pabloamr 0:8d55f1f49a33 66 #define _NRF24L01P_RX_FIFO_SIZE 32
pabloamr 0:8d55f1f49a33 67
pabloamr 0:8d55f1f49a33 68 #define _NRF24L01P_SPI_MAX_DATA_RATE 10000000
pabloamr 0:8d55f1f49a33 69
pabloamr 0:8d55f1f49a33 70 #define _NRF24L01P_SPI_CMD_RD_REG 0x00
pabloamr 0:8d55f1f49a33 71 #define _NRF24L01P_SPI_CMD_WR_REG 0x20
pabloamr 0:8d55f1f49a33 72 #define _NRF24L01P_SPI_CMD_RD_RX_PAYLOAD 0x61
pabloamr 0:8d55f1f49a33 73 #define _NRF24L01P_SPI_CMD_WR_TX_PAYLOAD 0xa0
pabloamr 0:8d55f1f49a33 74 #define _NRF24L01P_SPI_CMD_FLUSH_TX 0xe1
pabloamr 0:8d55f1f49a33 75 #define _NRF24L01P_SPI_CMD_FLUSH_RX 0xe2
pabloamr 0:8d55f1f49a33 76 #define _NRF24L01P_SPI_CMD_REUSE_TX_PL 0xe3
pabloamr 0:8d55f1f49a33 77 #define _NRF24L01P_SPI_CMD_R_RX_PL_WID 0x60
pabloamr 0:8d55f1f49a33 78 #define _NRF24L01P_SPI_CMD_W_ACK_PAYLOAD 0xa8
pabloamr 0:8d55f1f49a33 79 #define _NRF24L01P_SPI_CMD_W_TX_PYLD_NO_ACK 0xb0
pabloamr 0:8d55f1f49a33 80 #define _NRF24L01P_SPI_CMD_NOP 0xff
pabloamr 0:8d55f1f49a33 81
pabloamr 0:8d55f1f49a33 82
pabloamr 0:8d55f1f49a33 83 #define _NRF24L01P_REG_CONFIG 0x00
pabloamr 0:8d55f1f49a33 84 #define _NRF24L01P_REG_EN_AA 0x01
pabloamr 0:8d55f1f49a33 85 #define _NRF24L01P_REG_EN_RXADDR 0x02
pabloamr 0:8d55f1f49a33 86 #define _NRF24L01P_REG_SETUP_AW 0x03
pabloamr 0:8d55f1f49a33 87 #define _NRF24L01P_REG_SETUP_RETR 0x04
pabloamr 0:8d55f1f49a33 88 #define _NRF24L01P_REG_RF_CH 0x05
pabloamr 0:8d55f1f49a33 89 #define _NRF24L01P_REG_RF_SETUP 0x06
pabloamr 0:8d55f1f49a33 90 #define _NRF24L01P_REG_STATUS 0x07
pabloamr 0:8d55f1f49a33 91 #define _NRF24L01P_REG_OBSERVE_TX 0x08
pabloamr 0:8d55f1f49a33 92 #define _NRF24L01P_REG_RPD 0x09
pabloamr 0:8d55f1f49a33 93 #define _NRF24L01P_REG_RX_ADDR_P0 0x0a
pabloamr 0:8d55f1f49a33 94 #define _NRF24L01P_REG_RX_ADDR_P1 0x0b
pabloamr 0:8d55f1f49a33 95 #define _NRF24L01P_REG_RX_ADDR_P2 0x0c
pabloamr 0:8d55f1f49a33 96 #define _NRF24L01P_REG_RX_ADDR_P3 0x0d
pabloamr 0:8d55f1f49a33 97 #define _NRF24L01P_REG_RX_ADDR_P4 0x0e
pabloamr 0:8d55f1f49a33 98 #define _NRF24L01P_REG_RX_ADDR_P5 0x0f
pabloamr 0:8d55f1f49a33 99 #define _NRF24L01P_REG_TX_ADDR 0x10
pabloamr 0:8d55f1f49a33 100 #define _NRF24L01P_REG_RX_PW_P0 0x11
pabloamr 0:8d55f1f49a33 101 #define _NRF24L01P_REG_RX_PW_P1 0x12
pabloamr 0:8d55f1f49a33 102 #define _NRF24L01P_REG_RX_PW_P2 0x13
pabloamr 0:8d55f1f49a33 103 #define _NRF24L01P_REG_RX_PW_P3 0x14
pabloamr 0:8d55f1f49a33 104 #define _NRF24L01P_REG_RX_PW_P4 0x15
pabloamr 0:8d55f1f49a33 105 #define _NRF24L01P_REG_RX_PW_P5 0x16
pabloamr 0:8d55f1f49a33 106 #define _NRF24L01P_REG_FIFO_STATUS 0x17
pabloamr 0:8d55f1f49a33 107 #define _NRF24L01P_REG_DYNPD 0x1c
pabloamr 0:8d55f1f49a33 108 #define _NRF24L01P_REG_FEATURE 0x1d
pabloamr 0:8d55f1f49a33 109
pabloamr 0:8d55f1f49a33 110 #define _NRF24L01P_REG_ADDRESS_MASK 0x1f
pabloamr 0:8d55f1f49a33 111
pabloamr 0:8d55f1f49a33 112 // CONFIG register:
pabloamr 0:8d55f1f49a33 113 #define _NRF24L01P_CONFIG_PRIM_RX (1<<0)
pabloamr 0:8d55f1f49a33 114 #define _NRF24L01P_CONFIG_PWR_UP (1<<1)
pabloamr 0:8d55f1f49a33 115 #define _NRF24L01P_CONFIG_CRC0 (1<<2)
pabloamr 0:8d55f1f49a33 116 #define _NRF24L01P_CONFIG_EN_CRC (1<<3)
pabloamr 0:8d55f1f49a33 117 #define _NRF24L01P_CONFIG_MASK_MAX_RT (1<<4)
pabloamr 0:8d55f1f49a33 118 #define _NRF24L01P_CONFIG_MASK_TX_DS (1<<5)
pabloamr 0:8d55f1f49a33 119 #define _NRF24L01P_CONFIG_MASK_RX_DR (1<<6)
pabloamr 0:8d55f1f49a33 120
pabloamr 0:8d55f1f49a33 121 #define _NRF24L01P_CONFIG_CRC_MASK (_NRF24L01P_CONFIG_EN_CRC|_NRF24L01P_CONFIG_CRC0)
pabloamr 0:8d55f1f49a33 122 #define _NRF24L01P_CONFIG_CRC_NONE (0)
pabloamr 0:8d55f1f49a33 123 #define _NRF24L01P_CONFIG_CRC_8BIT (_NRF24L01P_CONFIG_EN_CRC)
pabloamr 0:8d55f1f49a33 124 #define _NRF24L01P_CONFIG_CRC_16BIT (_NRF24L01P_CONFIG_EN_CRC|_NRF24L01P_CONFIG_CRC0)
pabloamr 0:8d55f1f49a33 125
pabloamr 0:8d55f1f49a33 126 // EN_AA register:
pabloamr 0:8d55f1f49a33 127 #define _NRF24L01P_EN_AA_NONE 0
pabloamr 0:8d55f1f49a33 128
pabloamr 0:8d55f1f49a33 129 // EN_RXADDR register:
pabloamr 0:8d55f1f49a33 130 #define _NRF24L01P_EN_RXADDR_NONE 0
pabloamr 0:8d55f1f49a33 131
pabloamr 0:8d55f1f49a33 132 // SETUP_AW register:
pabloamr 0:8d55f1f49a33 133 #define _NRF24L01P_SETUP_AW_AW_MASK (0x3<<0)
pabloamr 0:8d55f1f49a33 134 #define _NRF24L01P_SETUP_AW_AW_3BYTE (0x1<<0)
pabloamr 0:8d55f1f49a33 135 #define _NRF24L01P_SETUP_AW_AW_4BYTE (0x2<<0)
pabloamr 0:8d55f1f49a33 136 #define _NRF24L01P_SETUP_AW_AW_5BYTE (0x3<<0)
pabloamr 0:8d55f1f49a33 137
pabloamr 0:8d55f1f49a33 138 // SETUP_RETR register:
pabloamr 0:8d55f1f49a33 139 #define _NRF24L01P_SETUP_RETR_NONE 0
pabloamr 0:8d55f1f49a33 140
pabloamr 0:8d55f1f49a33 141 // RF_SETUP register:
pabloamr 0:8d55f1f49a33 142 #define _NRF24L01P_RF_SETUP_RF_PWR_MASK (0x3<<1)
pabloamr 0:8d55f1f49a33 143 #define _NRF24L01P_RF_SETUP_RF_PWR_0DBM (0x3<<1)
pabloamr 0:8d55f1f49a33 144 #define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM (0x2<<1)
pabloamr 0:8d55f1f49a33 145 #define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM (0x1<<1)
pabloamr 0:8d55f1f49a33 146 #define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM (0x0<<1)
pabloamr 0:8d55f1f49a33 147
pabloamr 0:8d55f1f49a33 148 #define _NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT (1 << 3)
pabloamr 0:8d55f1f49a33 149 #define _NRF24L01P_RF_SETUP_RF_DR_LOW_BIT (1 << 5)
pabloamr 0:8d55f1f49a33 150 #define _NRF24L01P_RF_SETUP_RF_DR_MASK (_NRF24L01P_RF_SETUP_RF_DR_LOW_BIT|_NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT)
pabloamr 0:8d55f1f49a33 151 #define _NRF24L01P_RF_SETUP_RF_DR_250KBPS (_NRF24L01P_RF_SETUP_RF_DR_LOW_BIT)
pabloamr 0:8d55f1f49a33 152 #define _NRF24L01P_RF_SETUP_RF_DR_1MBPS (0)
pabloamr 0:8d55f1f49a33 153 #define _NRF24L01P_RF_SETUP_RF_DR_2MBPS (_NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT)
pabloamr 0:8d55f1f49a33 154
pabloamr 0:8d55f1f49a33 155 // STATUS register:
pabloamr 0:8d55f1f49a33 156 #define _NRF24L01P_STATUS_TX_FULL (1<<0)
pabloamr 0:8d55f1f49a33 157 #define _NRF24L01P_STATUS_RX_P_NO (0x7<<1)
pabloamr 0:8d55f1f49a33 158 #define _NRF24L01P_STATUS_MAX_RT (1<<4)
pabloamr 0:8d55f1f49a33 159 #define _NRF24L01P_STATUS_TX_DS (1<<5)
pabloamr 0:8d55f1f49a33 160 #define _NRF24L01P_STATUS_RX_DR (1<<6)
pabloamr 0:8d55f1f49a33 161
pabloamr 0:8d55f1f49a33 162 // RX_PW_P0..RX_PW_P5 registers:
pabloamr 0:8d55f1f49a33 163 #define _NRF24L01P_RX_PW_Px_MASK 0x3F
pabloamr 0:8d55f1f49a33 164
pabloamr 0:8d55f1f49a33 165 #define _NRF24L01P_TIMING_Tundef2pd_us 100000 // 100mS
pabloamr 0:8d55f1f49a33 166 #define _NRF24L01P_TIMING_Tstby2a_us 130 // 130uS
pabloamr 0:8d55f1f49a33 167 #define _NRF24L01P_TIMING_Thce_us 10 // 10uS
pabloamr 0:8d55f1f49a33 168 #define _NRF24L01P_TIMING_Tpd2stby_us 4500 // 4.5mS worst case
pabloamr 0:8d55f1f49a33 169 #define _NRF24L01P_TIMING_Tpece2csn_us 4 // 4uS
pabloamr 0:8d55f1f49a33 170
pabloamr 0:8d55f1f49a33 171 /**
pabloamr 0:8d55f1f49a33 172 * Methods
pabloamr 0:8d55f1f49a33 173 */
pabloamr 0:8d55f1f49a33 174
pabloamr 0:8d55f1f49a33 175 nRF24L01P::nRF24L01P(PinName mosi,
pabloamr 0:8d55f1f49a33 176 PinName miso,
pabloamr 0:8d55f1f49a33 177 PinName sck,
pabloamr 0:8d55f1f49a33 178 PinName csn,
pabloamr 0:8d55f1f49a33 179 PinName ce,
pabloamr 0:8d55f1f49a33 180 PinName irq) : spi_(mosi, miso, sck), nCS_(csn), ce_(ce), nIRQ_(irq) {
pabloamr 0:8d55f1f49a33 181
pabloamr 0:8d55f1f49a33 182 mode = _NRF24L01P_MODE_UNKNOWN;
pabloamr 0:8d55f1f49a33 183
pabloamr 0:8d55f1f49a33 184 disable();
pabloamr 0:8d55f1f49a33 185
pabloamr 0:8d55f1f49a33 186 nCS_ = 1;
pabloamr 0:8d55f1f49a33 187
pabloamr 0:8d55f1f49a33 188 spi_.frequency(_NRF24L01P_SPI_MAX_DATA_RATE/5); // 2Mbit, 1/5th the maximum transfer rate for the SPI bus
pabloamr 0:8d55f1f49a33 189 spi_.format(8,0); // 8-bit, ClockPhase = 0, ClockPolarity = 0
pabloamr 0:8d55f1f49a33 190
pabloamr 0:8d55f1f49a33 191 wait_us(_NRF24L01P_TIMING_Tundef2pd_us); // Wait for Power-on reset
pabloamr 0:8d55f1f49a33 192
pabloamr 0:8d55f1f49a33 193 setRegister(_NRF24L01P_REG_CONFIG, 0); // Power Down
pabloamr 0:8d55f1f49a33 194
pabloamr 0:8d55f1f49a33 195 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_MAX_RT|_NRF24L01P_STATUS_TX_DS|_NRF24L01P_STATUS_RX_DR); // Clear any pending interrupts
pabloamr 0:8d55f1f49a33 196
pabloamr 0:8d55f1f49a33 197 //
pabloamr 0:8d55f1f49a33 198 // Setup default configuration
pabloamr 0:8d55f1f49a33 199 //
pabloamr 0:8d55f1f49a33 200 disableAllRxPipes();
pabloamr 0:8d55f1f49a33 201 setRfFrequency();
pabloamr 0:8d55f1f49a33 202 setRfOutputPower();
pabloamr 0:8d55f1f49a33 203 setAirDataRate();
pabloamr 0:8d55f1f49a33 204 setCrcWidth();
fytanlulu 1:d6b43a63580a 205 setTxAddress(0xffffffffffULL,5);
pabloamr 0:8d55f1f49a33 206 setRxAddress();
pabloamr 0:8d55f1f49a33 207 disableAutoAcknowledge();
pabloamr 0:8d55f1f49a33 208 disableAutoRetransmit();
pabloamr 0:8d55f1f49a33 209 setTransferSize();
pabloamr 0:8d55f1f49a33 210
pabloamr 0:8d55f1f49a33 211 mode = _NRF24L01P_MODE_POWER_DOWN;
pabloamr 0:8d55f1f49a33 212
pabloamr 0:8d55f1f49a33 213 }
pabloamr 0:8d55f1f49a33 214
pabloamr 0:8d55f1f49a33 215
pabloamr 0:8d55f1f49a33 216 void nRF24L01P::powerUp(void) {
pabloamr 0:8d55f1f49a33 217
pabloamr 0:8d55f1f49a33 218 int config = getRegister(_NRF24L01P_REG_CONFIG);
pabloamr 0:8d55f1f49a33 219
pabloamr 0:8d55f1f49a33 220 config |= _NRF24L01P_CONFIG_PWR_UP;
pabloamr 0:8d55f1f49a33 221
pabloamr 0:8d55f1f49a33 222 setRegister(_NRF24L01P_REG_CONFIG, config);
pabloamr 0:8d55f1f49a33 223
pabloamr 0:8d55f1f49a33 224 // Wait until the nRF24L01+ powers up
pabloamr 0:8d55f1f49a33 225 wait_us( _NRF24L01P_TIMING_Tpd2stby_us );
pabloamr 0:8d55f1f49a33 226
pabloamr 0:8d55f1f49a33 227 mode = _NRF24L01P_MODE_STANDBY;
pabloamr 0:8d55f1f49a33 228
pabloamr 0:8d55f1f49a33 229 }
pabloamr 0:8d55f1f49a33 230
pabloamr 0:8d55f1f49a33 231
pabloamr 0:8d55f1f49a33 232 void nRF24L01P::powerDown(void) {
pabloamr 0:8d55f1f49a33 233
pabloamr 0:8d55f1f49a33 234 int config = getRegister(_NRF24L01P_REG_CONFIG);
pabloamr 0:8d55f1f49a33 235
pabloamr 0:8d55f1f49a33 236 config &= ~_NRF24L01P_CONFIG_PWR_UP;
pabloamr 0:8d55f1f49a33 237
pabloamr 0:8d55f1f49a33 238 setRegister(_NRF24L01P_REG_CONFIG, config);
pabloamr 0:8d55f1f49a33 239
pabloamr 0:8d55f1f49a33 240 // Wait until the nRF24L01+ powers down
pabloamr 0:8d55f1f49a33 241 wait_us( _NRF24L01P_TIMING_Tpd2stby_us ); // This *may* not be necessary (no timing is shown in the Datasheet), but just to be safe
pabloamr 0:8d55f1f49a33 242
pabloamr 0:8d55f1f49a33 243 mode = _NRF24L01P_MODE_POWER_DOWN;
pabloamr 0:8d55f1f49a33 244
pabloamr 0:8d55f1f49a33 245 }
pabloamr 0:8d55f1f49a33 246
pabloamr 0:8d55f1f49a33 247
pabloamr 0:8d55f1f49a33 248 void nRF24L01P::setReceiveMode(void) {
pabloamr 0:8d55f1f49a33 249
pabloamr 0:8d55f1f49a33 250 if ( _NRF24L01P_MODE_POWER_DOWN == mode ) powerUp();
pabloamr 0:8d55f1f49a33 251
pabloamr 0:8d55f1f49a33 252 int config = getRegister(_NRF24L01P_REG_CONFIG);
pabloamr 0:8d55f1f49a33 253
pabloamr 0:8d55f1f49a33 254 config |= _NRF24L01P_CONFIG_PRIM_RX;
pabloamr 0:8d55f1f49a33 255
pabloamr 0:8d55f1f49a33 256 setRegister(_NRF24L01P_REG_CONFIG, config);
pabloamr 0:8d55f1f49a33 257
pabloamr 0:8d55f1f49a33 258 mode = _NRF24L01P_MODE_RX;
pabloamr 0:8d55f1f49a33 259
pabloamr 0:8d55f1f49a33 260 }
pabloamr 0:8d55f1f49a33 261
pabloamr 0:8d55f1f49a33 262
pabloamr 0:8d55f1f49a33 263 void nRF24L01P::setTransmitMode(void) {
pabloamr 0:8d55f1f49a33 264
pabloamr 0:8d55f1f49a33 265 if ( _NRF24L01P_MODE_POWER_DOWN == mode ) powerUp();
pabloamr 0:8d55f1f49a33 266
pabloamr 0:8d55f1f49a33 267 int config = getRegister(_NRF24L01P_REG_CONFIG);
pabloamr 0:8d55f1f49a33 268
pabloamr 0:8d55f1f49a33 269 config &= ~_NRF24L01P_CONFIG_PRIM_RX;
pabloamr 0:8d55f1f49a33 270
pabloamr 0:8d55f1f49a33 271 setRegister(_NRF24L01P_REG_CONFIG, config);
pabloamr 0:8d55f1f49a33 272
pabloamr 0:8d55f1f49a33 273 mode = _NRF24L01P_MODE_TX;
pabloamr 0:8d55f1f49a33 274
pabloamr 0:8d55f1f49a33 275 }
pabloamr 0:8d55f1f49a33 276
pabloamr 0:8d55f1f49a33 277
pabloamr 0:8d55f1f49a33 278 void nRF24L01P::enable(void) {
pabloamr 0:8d55f1f49a33 279
pabloamr 0:8d55f1f49a33 280 ce_ = 1;
pabloamr 0:8d55f1f49a33 281 wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
pabloamr 0:8d55f1f49a33 282
pabloamr 0:8d55f1f49a33 283 }
pabloamr 0:8d55f1f49a33 284
pabloamr 0:8d55f1f49a33 285
pabloamr 0:8d55f1f49a33 286 void nRF24L01P::disable(void) {
pabloamr 0:8d55f1f49a33 287
pabloamr 0:8d55f1f49a33 288 ce_ = 0;
pabloamr 0:8d55f1f49a33 289
pabloamr 0:8d55f1f49a33 290 }
pabloamr 0:8d55f1f49a33 291
pabloamr 0:8d55f1f49a33 292 void nRF24L01P::setRfFrequency(int frequency) {
pabloamr 0:8d55f1f49a33 293
pabloamr 0:8d55f1f49a33 294 if ( ( frequency < NRF24L01P_MIN_RF_FREQUENCY ) || ( frequency > NRF24L01P_MAX_RF_FREQUENCY ) ) {
pabloamr 0:8d55f1f49a33 295
pabloamr 0:8d55f1f49a33 296 error( "nRF24L01P: Invalid RF Frequency setting %d\r\n", frequency );
pabloamr 0:8d55f1f49a33 297 return;
pabloamr 0:8d55f1f49a33 298
pabloamr 0:8d55f1f49a33 299 }
pabloamr 0:8d55f1f49a33 300
pabloamr 0:8d55f1f49a33 301 int channel = ( frequency - NRF24L01P_MIN_RF_FREQUENCY ) & 0x7F;
pabloamr 0:8d55f1f49a33 302
pabloamr 0:8d55f1f49a33 303 setRegister(_NRF24L01P_REG_RF_CH, channel);
pabloamr 0:8d55f1f49a33 304
pabloamr 0:8d55f1f49a33 305 }
pabloamr 0:8d55f1f49a33 306
pabloamr 0:8d55f1f49a33 307
pabloamr 0:8d55f1f49a33 308 int nRF24L01P::getRfFrequency(void) {
pabloamr 0:8d55f1f49a33 309
pabloamr 0:8d55f1f49a33 310 int channel = getRegister(_NRF24L01P_REG_RF_CH) & 0x7F;
pabloamr 0:8d55f1f49a33 311
pabloamr 0:8d55f1f49a33 312 return ( channel + NRF24L01P_MIN_RF_FREQUENCY );
pabloamr 0:8d55f1f49a33 313
pabloamr 0:8d55f1f49a33 314 }
pabloamr 0:8d55f1f49a33 315
pabloamr 0:8d55f1f49a33 316
pabloamr 0:8d55f1f49a33 317 void nRF24L01P::setRfOutputPower(int power) {
pabloamr 0:8d55f1f49a33 318
pabloamr 0:8d55f1f49a33 319 int rfSetup = getRegister(_NRF24L01P_REG_RF_SETUP) & ~_NRF24L01P_RF_SETUP_RF_PWR_MASK;
pabloamr 0:8d55f1f49a33 320
pabloamr 0:8d55f1f49a33 321 switch ( power ) {
pabloamr 0:8d55f1f49a33 322
pabloamr 0:8d55f1f49a33 323 case NRF24L01P_TX_PWR_ZERO_DB:
pabloamr 0:8d55f1f49a33 324 rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_0DBM;
pabloamr 0:8d55f1f49a33 325 break;
pabloamr 0:8d55f1f49a33 326
pabloamr 0:8d55f1f49a33 327 case NRF24L01P_TX_PWR_MINUS_6_DB:
pabloamr 0:8d55f1f49a33 328 rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM;
pabloamr 0:8d55f1f49a33 329 break;
pabloamr 0:8d55f1f49a33 330
pabloamr 0:8d55f1f49a33 331 case NRF24L01P_TX_PWR_MINUS_12_DB:
pabloamr 0:8d55f1f49a33 332 rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM;
pabloamr 0:8d55f1f49a33 333 break;
pabloamr 0:8d55f1f49a33 334
pabloamr 0:8d55f1f49a33 335 case NRF24L01P_TX_PWR_MINUS_18_DB:
pabloamr 0:8d55f1f49a33 336 rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM;
pabloamr 0:8d55f1f49a33 337 break;
pabloamr 0:8d55f1f49a33 338
pabloamr 0:8d55f1f49a33 339 default:
pabloamr 0:8d55f1f49a33 340 error( "nRF24L01P: Invalid RF Output Power setting %d\r\n", power );
pabloamr 0:8d55f1f49a33 341 return;
pabloamr 0:8d55f1f49a33 342
pabloamr 0:8d55f1f49a33 343 }
pabloamr 0:8d55f1f49a33 344
pabloamr 0:8d55f1f49a33 345 setRegister(_NRF24L01P_REG_RF_SETUP, rfSetup);
pabloamr 0:8d55f1f49a33 346
pabloamr 0:8d55f1f49a33 347 }
pabloamr 0:8d55f1f49a33 348
pabloamr 0:8d55f1f49a33 349
pabloamr 0:8d55f1f49a33 350 int nRF24L01P::getRfOutputPower(void) {
pabloamr 0:8d55f1f49a33 351
pabloamr 0:8d55f1f49a33 352 int rfPwr = getRegister(_NRF24L01P_REG_RF_SETUP) & _NRF24L01P_RF_SETUP_RF_PWR_MASK;
pabloamr 0:8d55f1f49a33 353
pabloamr 0:8d55f1f49a33 354 switch ( rfPwr ) {
pabloamr 0:8d55f1f49a33 355
pabloamr 0:8d55f1f49a33 356 case _NRF24L01P_RF_SETUP_RF_PWR_0DBM:
pabloamr 0:8d55f1f49a33 357 return NRF24L01P_TX_PWR_ZERO_DB;
pabloamr 0:8d55f1f49a33 358
pabloamr 0:8d55f1f49a33 359 case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM:
pabloamr 0:8d55f1f49a33 360 return NRF24L01P_TX_PWR_MINUS_6_DB;
pabloamr 0:8d55f1f49a33 361
pabloamr 0:8d55f1f49a33 362 case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM:
pabloamr 0:8d55f1f49a33 363 return NRF24L01P_TX_PWR_MINUS_12_DB;
pabloamr 0:8d55f1f49a33 364
pabloamr 0:8d55f1f49a33 365 case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM:
pabloamr 0:8d55f1f49a33 366 return NRF24L01P_TX_PWR_MINUS_18_DB;
pabloamr 0:8d55f1f49a33 367
pabloamr 0:8d55f1f49a33 368 default:
pabloamr 0:8d55f1f49a33 369 error( "nRF24L01P: Unknown RF Output Power value %d\r\n", rfPwr );
pabloamr 0:8d55f1f49a33 370 return 0;
pabloamr 0:8d55f1f49a33 371
pabloamr 0:8d55f1f49a33 372 }
pabloamr 0:8d55f1f49a33 373 }
pabloamr 0:8d55f1f49a33 374
pabloamr 0:8d55f1f49a33 375
pabloamr 0:8d55f1f49a33 376 void nRF24L01P::setAirDataRate(int rate) {
pabloamr 0:8d55f1f49a33 377
pabloamr 0:8d55f1f49a33 378 int rfSetup = getRegister(_NRF24L01P_REG_RF_SETUP) & ~_NRF24L01P_RF_SETUP_RF_DR_MASK;
pabloamr 0:8d55f1f49a33 379
pabloamr 0:8d55f1f49a33 380 switch ( rate ) {
pabloamr 0:8d55f1f49a33 381
pabloamr 0:8d55f1f49a33 382 case NRF24L01P_DATARATE_250_KBPS:
pabloamr 0:8d55f1f49a33 383 rfSetup |= _NRF24L01P_RF_SETUP_RF_DR_250KBPS;
pabloamr 0:8d55f1f49a33 384 break;
pabloamr 0:8d55f1f49a33 385
pabloamr 0:8d55f1f49a33 386 case NRF24L01P_DATARATE_1_MBPS:
pabloamr 0:8d55f1f49a33 387 rfSetup |= _NRF24L01P_RF_SETUP_RF_DR_1MBPS;
pabloamr 0:8d55f1f49a33 388 break;
pabloamr 0:8d55f1f49a33 389
pabloamr 0:8d55f1f49a33 390 case NRF24L01P_DATARATE_2_MBPS:
pabloamr 0:8d55f1f49a33 391 rfSetup |= _NRF24L01P_RF_SETUP_RF_DR_2MBPS;
pabloamr 0:8d55f1f49a33 392 break;
pabloamr 0:8d55f1f49a33 393
pabloamr 0:8d55f1f49a33 394 default:
pabloamr 0:8d55f1f49a33 395 error( "nRF24L01P: Invalid Air Data Rate setting %d\r\n", rate );
pabloamr 0:8d55f1f49a33 396 return;
pabloamr 0:8d55f1f49a33 397
pabloamr 0:8d55f1f49a33 398 }
pabloamr 0:8d55f1f49a33 399
pabloamr 0:8d55f1f49a33 400 setRegister(_NRF24L01P_REG_RF_SETUP, rfSetup);
pabloamr 0:8d55f1f49a33 401
pabloamr 0:8d55f1f49a33 402 }
pabloamr 0:8d55f1f49a33 403
pabloamr 0:8d55f1f49a33 404
pabloamr 0:8d55f1f49a33 405 int nRF24L01P::getAirDataRate(void) {
pabloamr 0:8d55f1f49a33 406
pabloamr 0:8d55f1f49a33 407 int rfDataRate = getRegister(_NRF24L01P_REG_RF_SETUP) & _NRF24L01P_RF_SETUP_RF_DR_MASK;
pabloamr 0:8d55f1f49a33 408
pabloamr 0:8d55f1f49a33 409 switch ( rfDataRate ) {
pabloamr 0:8d55f1f49a33 410
pabloamr 0:8d55f1f49a33 411 case _NRF24L01P_RF_SETUP_RF_DR_250KBPS:
pabloamr 0:8d55f1f49a33 412 return NRF24L01P_DATARATE_250_KBPS;
pabloamr 0:8d55f1f49a33 413
pabloamr 0:8d55f1f49a33 414 case _NRF24L01P_RF_SETUP_RF_DR_1MBPS:
pabloamr 0:8d55f1f49a33 415 return NRF24L01P_DATARATE_1_MBPS;
pabloamr 0:8d55f1f49a33 416
pabloamr 0:8d55f1f49a33 417 case _NRF24L01P_RF_SETUP_RF_DR_2MBPS:
pabloamr 0:8d55f1f49a33 418 return NRF24L01P_DATARATE_2_MBPS;
pabloamr 0:8d55f1f49a33 419
pabloamr 0:8d55f1f49a33 420 default:
pabloamr 0:8d55f1f49a33 421 error( "nRF24L01P: Unknown Air Data Rate value %d\r\n", rfDataRate );
pabloamr 0:8d55f1f49a33 422 return 0;
pabloamr 0:8d55f1f49a33 423
pabloamr 0:8d55f1f49a33 424 }
pabloamr 0:8d55f1f49a33 425 }
pabloamr 0:8d55f1f49a33 426
pabloamr 0:8d55f1f49a33 427
pabloamr 0:8d55f1f49a33 428 void nRF24L01P::setCrcWidth(int width) {
pabloamr 0:8d55f1f49a33 429
pabloamr 0:8d55f1f49a33 430 int config = getRegister(_NRF24L01P_REG_CONFIG) & ~_NRF24L01P_CONFIG_CRC_MASK;
pabloamr 0:8d55f1f49a33 431
pabloamr 0:8d55f1f49a33 432 switch ( width ) {
pabloamr 0:8d55f1f49a33 433
pabloamr 0:8d55f1f49a33 434 case NRF24L01P_CRC_NONE:
pabloamr 0:8d55f1f49a33 435 config |= _NRF24L01P_CONFIG_CRC_NONE;
pabloamr 0:8d55f1f49a33 436 break;
pabloamr 0:8d55f1f49a33 437
pabloamr 0:8d55f1f49a33 438 case NRF24L01P_CRC_8_BIT:
pabloamr 0:8d55f1f49a33 439 config |= _NRF24L01P_CONFIG_CRC_8BIT;
pabloamr 0:8d55f1f49a33 440 break;
pabloamr 0:8d55f1f49a33 441
pabloamr 0:8d55f1f49a33 442 case NRF24L01P_CRC_16_BIT:
pabloamr 0:8d55f1f49a33 443 config |= _NRF24L01P_CONFIG_CRC_16BIT;
pabloamr 0:8d55f1f49a33 444 break;
pabloamr 0:8d55f1f49a33 445
pabloamr 0:8d55f1f49a33 446 default:
pabloamr 0:8d55f1f49a33 447 error( "nRF24L01P: Invalid CRC Width setting %d\r\n", width );
pabloamr 0:8d55f1f49a33 448 return;
pabloamr 0:8d55f1f49a33 449
pabloamr 0:8d55f1f49a33 450 }
pabloamr 0:8d55f1f49a33 451
pabloamr 0:8d55f1f49a33 452 setRegister(_NRF24L01P_REG_CONFIG, config);
pabloamr 0:8d55f1f49a33 453
pabloamr 0:8d55f1f49a33 454 }
pabloamr 0:8d55f1f49a33 455
pabloamr 0:8d55f1f49a33 456
pabloamr 0:8d55f1f49a33 457 int nRF24L01P::getCrcWidth(void) {
pabloamr 0:8d55f1f49a33 458
pabloamr 0:8d55f1f49a33 459 int crcWidth = getRegister(_NRF24L01P_REG_CONFIG) & _NRF24L01P_CONFIG_CRC_MASK;
pabloamr 0:8d55f1f49a33 460
pabloamr 0:8d55f1f49a33 461 switch ( crcWidth ) {
pabloamr 0:8d55f1f49a33 462
pabloamr 0:8d55f1f49a33 463 case _NRF24L01P_CONFIG_CRC_NONE:
pabloamr 0:8d55f1f49a33 464 return NRF24L01P_CRC_NONE;
pabloamr 0:8d55f1f49a33 465
pabloamr 0:8d55f1f49a33 466 case _NRF24L01P_CONFIG_CRC_8BIT:
pabloamr 0:8d55f1f49a33 467 return NRF24L01P_CRC_8_BIT;
pabloamr 0:8d55f1f49a33 468
pabloamr 0:8d55f1f49a33 469 case _NRF24L01P_CONFIG_CRC_16BIT:
pabloamr 0:8d55f1f49a33 470 return NRF24L01P_CRC_16_BIT;
pabloamr 0:8d55f1f49a33 471
pabloamr 0:8d55f1f49a33 472 default:
pabloamr 0:8d55f1f49a33 473 error( "nRF24L01P: Unknown CRC Width value %d\r\n", crcWidth );
pabloamr 0:8d55f1f49a33 474 return 0;
pabloamr 0:8d55f1f49a33 475
pabloamr 0:8d55f1f49a33 476 }
pabloamr 0:8d55f1f49a33 477 }
pabloamr 0:8d55f1f49a33 478
pabloamr 0:8d55f1f49a33 479
pabloamr 0:8d55f1f49a33 480 void nRF24L01P::setTransferSize(int size, int pipe) {
pabloamr 0:8d55f1f49a33 481
pabloamr 0:8d55f1f49a33 482 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
pabloamr 0:8d55f1f49a33 483
pabloamr 0:8d55f1f49a33 484 error( "nRF24L01P: Invalid Transfer Size pipe number %d\r\n", pipe );
pabloamr 0:8d55f1f49a33 485 return;
pabloamr 0:8d55f1f49a33 486
pabloamr 0:8d55f1f49a33 487 }
pabloamr 0:8d55f1f49a33 488
pabloamr 0:8d55f1f49a33 489 if ( ( size < 0 ) || ( size > _NRF24L01P_RX_FIFO_SIZE ) ) {
pabloamr 0:8d55f1f49a33 490
pabloamr 0:8d55f1f49a33 491 error( "nRF24L01P: Invalid Transfer Size setting %d\r\n", size );
pabloamr 0:8d55f1f49a33 492 return;
pabloamr 0:8d55f1f49a33 493
pabloamr 0:8d55f1f49a33 494 }
pabloamr 0:8d55f1f49a33 495
pabloamr 0:8d55f1f49a33 496 int rxPwPxRegister = _NRF24L01P_REG_RX_PW_P0 + ( pipe - NRF24L01P_PIPE_P0 );
pabloamr 0:8d55f1f49a33 497
pabloamr 0:8d55f1f49a33 498 setRegister(rxPwPxRegister, ( size & _NRF24L01P_RX_PW_Px_MASK ) );
pabloamr 0:8d55f1f49a33 499
pabloamr 0:8d55f1f49a33 500 }
pabloamr 0:8d55f1f49a33 501
pabloamr 0:8d55f1f49a33 502
pabloamr 0:8d55f1f49a33 503 int nRF24L01P::getTransferSize(int pipe) {
pabloamr 0:8d55f1f49a33 504
pabloamr 0:8d55f1f49a33 505 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
pabloamr 0:8d55f1f49a33 506
pabloamr 0:8d55f1f49a33 507 error( "nRF24L01P: Invalid Transfer Size pipe number %d\r\n", pipe );
pabloamr 0:8d55f1f49a33 508 return 0;
pabloamr 0:8d55f1f49a33 509
pabloamr 0:8d55f1f49a33 510 }
pabloamr 0:8d55f1f49a33 511
pabloamr 0:8d55f1f49a33 512 int rxPwPxRegister = _NRF24L01P_REG_RX_PW_P0 + ( pipe - NRF24L01P_PIPE_P0 );
pabloamr 0:8d55f1f49a33 513
pabloamr 0:8d55f1f49a33 514 int size = getRegister(rxPwPxRegister);
pabloamr 0:8d55f1f49a33 515
pabloamr 0:8d55f1f49a33 516 return ( size & _NRF24L01P_RX_PW_Px_MASK );
pabloamr 0:8d55f1f49a33 517
pabloamr 0:8d55f1f49a33 518 }
pabloamr 0:8d55f1f49a33 519
pabloamr 0:8d55f1f49a33 520
pabloamr 0:8d55f1f49a33 521 void nRF24L01P::disableAllRxPipes(void) {
pabloamr 0:8d55f1f49a33 522
pabloamr 0:8d55f1f49a33 523 setRegister(_NRF24L01P_REG_EN_RXADDR, _NRF24L01P_EN_RXADDR_NONE);
pabloamr 0:8d55f1f49a33 524
pabloamr 0:8d55f1f49a33 525 }
pabloamr 0:8d55f1f49a33 526
pabloamr 0:8d55f1f49a33 527
pabloamr 0:8d55f1f49a33 528 void nRF24L01P::disableAutoAcknowledge(void) {
pabloamr 0:8d55f1f49a33 529
pabloamr 0:8d55f1f49a33 530 setRegister(_NRF24L01P_REG_EN_AA, _NRF24L01P_EN_AA_NONE);
pabloamr 0:8d55f1f49a33 531
pabloamr 0:8d55f1f49a33 532 }
pabloamr 0:8d55f1f49a33 533
pabloamr 0:8d55f1f49a33 534
pabloamr 0:8d55f1f49a33 535 void nRF24L01P::enableAutoAcknowledge(int pipe) {
pabloamr 0:8d55f1f49a33 536
pabloamr 0:8d55f1f49a33 537 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
pabloamr 0:8d55f1f49a33 538
pabloamr 0:8d55f1f49a33 539 error( "nRF24L01P: Invalid Enable AutoAcknowledge pipe number %d\r\n", pipe );
pabloamr 0:8d55f1f49a33 540 return;
pabloamr 0:8d55f1f49a33 541
pabloamr 0:8d55f1f49a33 542 }
pabloamr 0:8d55f1f49a33 543
pabloamr 0:8d55f1f49a33 544 int enAA = getRegister(_NRF24L01P_REG_EN_AA);
pabloamr 0:8d55f1f49a33 545
pabloamr 0:8d55f1f49a33 546 enAA |= ( 1 << (pipe - NRF24L01P_PIPE_P0) );
pabloamr 0:8d55f1f49a33 547
pabloamr 0:8d55f1f49a33 548 setRegister(_NRF24L01P_REG_EN_AA, enAA);
pabloamr 0:8d55f1f49a33 549
pabloamr 0:8d55f1f49a33 550 }
pabloamr 0:8d55f1f49a33 551
pabloamr 0:8d55f1f49a33 552
pabloamr 0:8d55f1f49a33 553 void nRF24L01P::disableAutoRetransmit(void) {
pabloamr 0:8d55f1f49a33 554
pabloamr 0:8d55f1f49a33 555 setRegister(_NRF24L01P_REG_SETUP_RETR, _NRF24L01P_SETUP_RETR_NONE);
pabloamr 0:8d55f1f49a33 556
pabloamr 0:8d55f1f49a33 557 }
pabloamr 0:8d55f1f49a33 558
pabloamr 0:8d55f1f49a33 559 void nRF24L01P::setRxAddress(unsigned long long address, int width, int pipe) {
pabloamr 0:8d55f1f49a33 560
pabloamr 0:8d55f1f49a33 561 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
pabloamr 0:8d55f1f49a33 562
pabloamr 0:8d55f1f49a33 563 error( "nRF24L01P: Invalid setRxAddress pipe number %d\r\n", pipe );
pabloamr 0:8d55f1f49a33 564 return;
pabloamr 0:8d55f1f49a33 565
pabloamr 0:8d55f1f49a33 566 }
pabloamr 0:8d55f1f49a33 567
pabloamr 0:8d55f1f49a33 568 if ( ( pipe == NRF24L01P_PIPE_P0 ) || ( pipe == NRF24L01P_PIPE_P1 ) ) {
pabloamr 0:8d55f1f49a33 569
pabloamr 0:8d55f1f49a33 570 int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & ~_NRF24L01P_SETUP_AW_AW_MASK;
pabloamr 0:8d55f1f49a33 571
pabloamr 0:8d55f1f49a33 572 switch ( width ) {
pabloamr 0:8d55f1f49a33 573
pabloamr 0:8d55f1f49a33 574 case 3:
pabloamr 0:8d55f1f49a33 575 setupAw |= _NRF24L01P_SETUP_AW_AW_3BYTE;
pabloamr 0:8d55f1f49a33 576 break;
pabloamr 0:8d55f1f49a33 577
pabloamr 0:8d55f1f49a33 578 case 4:
pabloamr 0:8d55f1f49a33 579 setupAw |= _NRF24L01P_SETUP_AW_AW_4BYTE;
pabloamr 0:8d55f1f49a33 580 break;
pabloamr 0:8d55f1f49a33 581
pabloamr 0:8d55f1f49a33 582 case 5:
pabloamr 0:8d55f1f49a33 583 setupAw |= _NRF24L01P_SETUP_AW_AW_5BYTE;
pabloamr 0:8d55f1f49a33 584 break;
pabloamr 0:8d55f1f49a33 585
pabloamr 0:8d55f1f49a33 586 default:
pabloamr 0:8d55f1f49a33 587 error( "nRF24L01P: Invalid setRxAddress width setting %d\r\n", width );
pabloamr 0:8d55f1f49a33 588 return;
pabloamr 0:8d55f1f49a33 589
pabloamr 0:8d55f1f49a33 590 }
pabloamr 0:8d55f1f49a33 591
pabloamr 0:8d55f1f49a33 592 setRegister(_NRF24L01P_REG_SETUP_AW, setupAw);
pabloamr 0:8d55f1f49a33 593
pabloamr 0:8d55f1f49a33 594 } else {
pabloamr 0:8d55f1f49a33 595
pabloamr 0:8d55f1f49a33 596 width = 1;
pabloamr 0:8d55f1f49a33 597
pabloamr 0:8d55f1f49a33 598 }
pabloamr 0:8d55f1f49a33 599
pabloamr 0:8d55f1f49a33 600 int rxAddrPxRegister = _NRF24L01P_REG_RX_ADDR_P0 + ( pipe - NRF24L01P_PIPE_P0 );
pabloamr 0:8d55f1f49a33 601
pabloamr 0:8d55f1f49a33 602 int cn = (_NRF24L01P_SPI_CMD_WR_REG | (rxAddrPxRegister & _NRF24L01P_REG_ADDRESS_MASK));
pabloamr 0:8d55f1f49a33 603
pabloamr 0:8d55f1f49a33 604 nCS_ = 0;
pabloamr 0:8d55f1f49a33 605
pabloamr 0:8d55f1f49a33 606 int status = spi_.write(cn);
pabloamr 0:8d55f1f49a33 607
pabloamr 0:8d55f1f49a33 608 while ( width-- > 0 ) {
pabloamr 0:8d55f1f49a33 609
pabloamr 0:8d55f1f49a33 610 //
pabloamr 0:8d55f1f49a33 611 // LSByte first
pabloamr 0:8d55f1f49a33 612 //
pabloamr 0:8d55f1f49a33 613 spi_.write((int) (address & 0xFF));
pabloamr 0:8d55f1f49a33 614 address >>= 8;
pabloamr 0:8d55f1f49a33 615
pabloamr 0:8d55f1f49a33 616 }
pabloamr 0:8d55f1f49a33 617
pabloamr 0:8d55f1f49a33 618 nCS_ = 1;
pabloamr 0:8d55f1f49a33 619
pabloamr 0:8d55f1f49a33 620 int enRxAddr = getRegister(_NRF24L01P_REG_EN_RXADDR);
pabloamr 0:8d55f1f49a33 621
pabloamr 0:8d55f1f49a33 622 enRxAddr |= (1 << ( pipe - NRF24L01P_PIPE_P0 ) );
pabloamr 0:8d55f1f49a33 623
pabloamr 0:8d55f1f49a33 624 setRegister(_NRF24L01P_REG_EN_RXADDR, enRxAddr);
pabloamr 0:8d55f1f49a33 625 }
pabloamr 0:8d55f1f49a33 626
pabloamr 0:8d55f1f49a33 627 /*
pabloamr 0:8d55f1f49a33 628 * This version of setRxAddress is just a wrapper for the version that takes 'long long's,
pabloamr 0:8d55f1f49a33 629 * in case the main code doesn't want to deal with long long's.
pabloamr 0:8d55f1f49a33 630 */
pabloamr 0:8d55f1f49a33 631 void nRF24L01P::setRxAddress(unsigned long msb_address, unsigned long lsb_address, int width, int pipe) {
pabloamr 0:8d55f1f49a33 632
pabloamr 0:8d55f1f49a33 633 unsigned long long address = ( ( (unsigned long long) msb_address ) << 32 ) | ( ( (unsigned long long) lsb_address ) << 0 );
pabloamr 0:8d55f1f49a33 634
pabloamr 0:8d55f1f49a33 635 setRxAddress(address, width, pipe);
pabloamr 0:8d55f1f49a33 636
pabloamr 0:8d55f1f49a33 637 }
pabloamr 0:8d55f1f49a33 638
pabloamr 0:8d55f1f49a33 639
pabloamr 0:8d55f1f49a33 640 /*
pabloamr 0:8d55f1f49a33 641 * This version of setTxAddress is just a wrapper for the version that takes 'long long's,
pabloamr 0:8d55f1f49a33 642 * in case the main code doesn't want to deal with long long's.
pabloamr 0:8d55f1f49a33 643 */
pabloamr 0:8d55f1f49a33 644 void nRF24L01P::setTxAddress(unsigned long msb_address, unsigned long lsb_address, int width) {
pabloamr 0:8d55f1f49a33 645
pabloamr 0:8d55f1f49a33 646 unsigned long long address = ( ( (unsigned long long) msb_address ) << 32 ) | ( ( (unsigned long long) lsb_address ) << 0 );
fytanlulu 1:d6b43a63580a 647 #ifdef DEBUG
fytanlulu 1:d6b43a63580a 648 printf("0x%05x\n",address);
fytanlulu 1:d6b43a63580a 649 #endif
pabloamr 0:8d55f1f49a33 650
pabloamr 0:8d55f1f49a33 651 setTxAddress(address, width);
pabloamr 0:8d55f1f49a33 652
pabloamr 0:8d55f1f49a33 653 }
pabloamr 0:8d55f1f49a33 654
pabloamr 0:8d55f1f49a33 655
pabloamr 0:8d55f1f49a33 656 void nRF24L01P::setTxAddress(unsigned long long address, int width) {
pabloamr 0:8d55f1f49a33 657
pabloamr 0:8d55f1f49a33 658 int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & ~_NRF24L01P_SETUP_AW_AW_MASK;
fytanlulu 1:d6b43a63580a 659 #ifdef DEBUG
fytanlulu 1:d6b43a63580a 660 printf("0x%x\n",setupAw);
fytanlulu 1:d6b43a63580a 661 #endif
fytanlulu 1:d6b43a63580a 662
fytanlulu 1:d6b43a63580a 663
pabloamr 0:8d55f1f49a33 664 switch ( width ) {
pabloamr 0:8d55f1f49a33 665
pabloamr 0:8d55f1f49a33 666 case 3:
pabloamr 0:8d55f1f49a33 667 setupAw |= _NRF24L01P_SETUP_AW_AW_3BYTE;
pabloamr 0:8d55f1f49a33 668 break;
pabloamr 0:8d55f1f49a33 669
pabloamr 0:8d55f1f49a33 670 case 4:
pabloamr 0:8d55f1f49a33 671 setupAw |= _NRF24L01P_SETUP_AW_AW_4BYTE;
pabloamr 0:8d55f1f49a33 672 break;
pabloamr 0:8d55f1f49a33 673
pabloamr 0:8d55f1f49a33 674 case 5:
pabloamr 0:8d55f1f49a33 675 setupAw |= _NRF24L01P_SETUP_AW_AW_5BYTE;
pabloamr 0:8d55f1f49a33 676 break;
pabloamr 0:8d55f1f49a33 677
pabloamr 0:8d55f1f49a33 678 default:
pabloamr 0:8d55f1f49a33 679 error( "nRF24L01P: Invalid setTxAddress width setting %d\r\n", width );
pabloamr 0:8d55f1f49a33 680 return;
pabloamr 0:8d55f1f49a33 681
pabloamr 0:8d55f1f49a33 682 }
pabloamr 0:8d55f1f49a33 683
pabloamr 0:8d55f1f49a33 684 setRegister(_NRF24L01P_REG_SETUP_AW, setupAw);
pabloamr 0:8d55f1f49a33 685
pabloamr 0:8d55f1f49a33 686 int cn = (_NRF24L01P_SPI_CMD_WR_REG | (_NRF24L01P_REG_TX_ADDR & _NRF24L01P_REG_ADDRESS_MASK));
fytanlulu 1:d6b43a63580a 687 #ifdef DEBUG
fytanlulu 1:d6b43a63580a 688 printf("0X%x\n",cn);
fytanlulu 1:d6b43a63580a 689 printf("0X%ullx\n",address);
fytanlulu 1:d6b43a63580a 690 #endif
pabloamr 0:8d55f1f49a33 691
pabloamr 0:8d55f1f49a33 692 nCS_ = 0;
pabloamr 0:8d55f1f49a33 693
pabloamr 0:8d55f1f49a33 694 int status = spi_.write(cn);
pabloamr 0:8d55f1f49a33 695
pabloamr 0:8d55f1f49a33 696 while ( width-- > 0 ) {
pabloamr 0:8d55f1f49a33 697
pabloamr 0:8d55f1f49a33 698 //
pabloamr 0:8d55f1f49a33 699 // LSByte first
pabloamr 0:8d55f1f49a33 700 //
pabloamr 0:8d55f1f49a33 701 spi_.write((int) (address & 0xFF));
pabloamr 0:8d55f1f49a33 702 address >>= 8;
pabloamr 0:8d55f1f49a33 703
pabloamr 0:8d55f1f49a33 704 }
pabloamr 0:8d55f1f49a33 705
pabloamr 0:8d55f1f49a33 706 nCS_ = 1;
pabloamr 0:8d55f1f49a33 707
pabloamr 0:8d55f1f49a33 708 }
pabloamr 0:8d55f1f49a33 709
pabloamr 0:8d55f1f49a33 710
pabloamr 0:8d55f1f49a33 711 unsigned long long nRF24L01P::getRxAddress(int pipe) {
pabloamr 0:8d55f1f49a33 712
pabloamr 0:8d55f1f49a33 713 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
pabloamr 0:8d55f1f49a33 714
pabloamr 0:8d55f1f49a33 715 error( "nRF24L01P: Invalid setRxAddress pipe number %d\r\n", pipe );
pabloamr 0:8d55f1f49a33 716 return 0;
pabloamr 0:8d55f1f49a33 717
pabloamr 0:8d55f1f49a33 718 }
pabloamr 0:8d55f1f49a33 719
pabloamr 0:8d55f1f49a33 720 int width;
pabloamr 0:8d55f1f49a33 721
pabloamr 0:8d55f1f49a33 722 if ( ( pipe == NRF24L01P_PIPE_P0 ) || ( pipe == NRF24L01P_PIPE_P1 ) ) {
pabloamr 0:8d55f1f49a33 723
pabloamr 0:8d55f1f49a33 724 int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & _NRF24L01P_SETUP_AW_AW_MASK;
pabloamr 0:8d55f1f49a33 725
pabloamr 0:8d55f1f49a33 726 switch ( setupAw ) {
pabloamr 0:8d55f1f49a33 727
pabloamr 0:8d55f1f49a33 728 case _NRF24L01P_SETUP_AW_AW_3BYTE:
pabloamr 0:8d55f1f49a33 729 width = 3;
pabloamr 0:8d55f1f49a33 730 break;
pabloamr 0:8d55f1f49a33 731
pabloamr 0:8d55f1f49a33 732 case _NRF24L01P_SETUP_AW_AW_4BYTE:
pabloamr 0:8d55f1f49a33 733 width = 4;
pabloamr 0:8d55f1f49a33 734 break;
pabloamr 0:8d55f1f49a33 735
pabloamr 0:8d55f1f49a33 736 case _NRF24L01P_SETUP_AW_AW_5BYTE:
pabloamr 0:8d55f1f49a33 737 width = 5;
pabloamr 0:8d55f1f49a33 738 break;
pabloamr 0:8d55f1f49a33 739
pabloamr 0:8d55f1f49a33 740 default:
pabloamr 0:8d55f1f49a33 741 error( "nRF24L01P: Unknown getRxAddress width value %d\r\n", setupAw );
pabloamr 0:8d55f1f49a33 742 return 0;
pabloamr 0:8d55f1f49a33 743
pabloamr 0:8d55f1f49a33 744 }
pabloamr 0:8d55f1f49a33 745
pabloamr 0:8d55f1f49a33 746 } else {
pabloamr 0:8d55f1f49a33 747
pabloamr 0:8d55f1f49a33 748 width = 1;
pabloamr 0:8d55f1f49a33 749
pabloamr 0:8d55f1f49a33 750 }
pabloamr 0:8d55f1f49a33 751
pabloamr 0:8d55f1f49a33 752 int rxAddrPxRegister = _NRF24L01P_REG_RX_ADDR_P0 + ( pipe - NRF24L01P_PIPE_P0 );
pabloamr 0:8d55f1f49a33 753
pabloamr 0:8d55f1f49a33 754 int cn = (_NRF24L01P_SPI_CMD_RD_REG | (rxAddrPxRegister & _NRF24L01P_REG_ADDRESS_MASK));
pabloamr 0:8d55f1f49a33 755
pabloamr 0:8d55f1f49a33 756 unsigned long long address = 0;
pabloamr 0:8d55f1f49a33 757
pabloamr 0:8d55f1f49a33 758 nCS_ = 0;
pabloamr 0:8d55f1f49a33 759
pabloamr 0:8d55f1f49a33 760 int status = spi_.write(cn);
pabloamr 0:8d55f1f49a33 761
pabloamr 0:8d55f1f49a33 762 for ( int i=0; i<width; i++ ) {
pabloamr 0:8d55f1f49a33 763
pabloamr 0:8d55f1f49a33 764 //
pabloamr 0:8d55f1f49a33 765 // LSByte first
pabloamr 0:8d55f1f49a33 766 //
pabloamr 0:8d55f1f49a33 767 address |= ( ( (unsigned long long)( spi_.write(_NRF24L01P_SPI_CMD_NOP) & 0xFF ) ) << (i*8) );
pabloamr 0:8d55f1f49a33 768
pabloamr 0:8d55f1f49a33 769 }
pabloamr 0:8d55f1f49a33 770
pabloamr 0:8d55f1f49a33 771 nCS_ = 1;
pabloamr 0:8d55f1f49a33 772
pabloamr 0:8d55f1f49a33 773 if ( !( ( pipe == NRF24L01P_PIPE_P0 ) || ( pipe == NRF24L01P_PIPE_P1 ) ) ) {
pabloamr 0:8d55f1f49a33 774
pabloamr 0:8d55f1f49a33 775 address |= ( getRxAddress(NRF24L01P_PIPE_P1) & ~((unsigned long long) 0xFF) );
pabloamr 0:8d55f1f49a33 776
pabloamr 0:8d55f1f49a33 777 }
pabloamr 0:8d55f1f49a33 778
pabloamr 0:8d55f1f49a33 779 return address;
pabloamr 0:8d55f1f49a33 780
pabloamr 0:8d55f1f49a33 781 }
pabloamr 0:8d55f1f49a33 782
pabloamr 0:8d55f1f49a33 783
pabloamr 0:8d55f1f49a33 784 unsigned long long nRF24L01P::getTxAddress(void) {
pabloamr 0:8d55f1f49a33 785
pabloamr 0:8d55f1f49a33 786 int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & _NRF24L01P_SETUP_AW_AW_MASK;
pabloamr 0:8d55f1f49a33 787
pabloamr 0:8d55f1f49a33 788 int width;
pabloamr 0:8d55f1f49a33 789
pabloamr 0:8d55f1f49a33 790 switch ( setupAw ) {
pabloamr 0:8d55f1f49a33 791
pabloamr 0:8d55f1f49a33 792 case _NRF24L01P_SETUP_AW_AW_3BYTE:
pabloamr 0:8d55f1f49a33 793 width = 3;
pabloamr 0:8d55f1f49a33 794 break;
pabloamr 0:8d55f1f49a33 795
pabloamr 0:8d55f1f49a33 796 case _NRF24L01P_SETUP_AW_AW_4BYTE:
pabloamr 0:8d55f1f49a33 797 width = 4;
pabloamr 0:8d55f1f49a33 798 break;
pabloamr 0:8d55f1f49a33 799
pabloamr 0:8d55f1f49a33 800 case _NRF24L01P_SETUP_AW_AW_5BYTE:
pabloamr 0:8d55f1f49a33 801 width = 5;
pabloamr 0:8d55f1f49a33 802 break;
pabloamr 0:8d55f1f49a33 803
pabloamr 0:8d55f1f49a33 804 default:
pabloamr 0:8d55f1f49a33 805 error( "nRF24L01P: Unknown getTxAddress width value %d\r\n", setupAw );
pabloamr 0:8d55f1f49a33 806 return 0;
pabloamr 0:8d55f1f49a33 807
pabloamr 0:8d55f1f49a33 808 }
pabloamr 0:8d55f1f49a33 809
pabloamr 0:8d55f1f49a33 810 int cn = (_NRF24L01P_SPI_CMD_RD_REG | (_NRF24L01P_REG_TX_ADDR & _NRF24L01P_REG_ADDRESS_MASK));
pabloamr 0:8d55f1f49a33 811
pabloamr 0:8d55f1f49a33 812 unsigned long long address = 0;
pabloamr 0:8d55f1f49a33 813
pabloamr 0:8d55f1f49a33 814 nCS_ = 0;
pabloamr 0:8d55f1f49a33 815
pabloamr 0:8d55f1f49a33 816 int status = spi_.write(cn);
pabloamr 0:8d55f1f49a33 817
pabloamr 0:8d55f1f49a33 818 for ( int i=0; i<width; i++ ) {
pabloamr 0:8d55f1f49a33 819
pabloamr 0:8d55f1f49a33 820 //
pabloamr 0:8d55f1f49a33 821 // LSByte first
pabloamr 0:8d55f1f49a33 822 //
pabloamr 0:8d55f1f49a33 823 address |= ( ( (unsigned long long)( spi_.write(_NRF24L01P_SPI_CMD_NOP) & 0xFF ) ) << (i*8) );
pabloamr 0:8d55f1f49a33 824
pabloamr 0:8d55f1f49a33 825 }
pabloamr 0:8d55f1f49a33 826
pabloamr 0:8d55f1f49a33 827 nCS_ = 1;
pabloamr 0:8d55f1f49a33 828
pabloamr 0:8d55f1f49a33 829 return address;
pabloamr 0:8d55f1f49a33 830 }
pabloamr 0:8d55f1f49a33 831
pabloamr 0:8d55f1f49a33 832
pabloamr 0:8d55f1f49a33 833 bool nRF24L01P::readable(int pipe) {
pabloamr 0:8d55f1f49a33 834
pabloamr 0:8d55f1f49a33 835 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
pabloamr 0:8d55f1f49a33 836
pabloamr 0:8d55f1f49a33 837 error( "nRF24L01P: Invalid readable pipe number %d\r\n", pipe );
pabloamr 0:8d55f1f49a33 838 return false;
pabloamr 0:8d55f1f49a33 839
pabloamr 0:8d55f1f49a33 840 }
pabloamr 0:8d55f1f49a33 841
pabloamr 0:8d55f1f49a33 842 int status = getStatusRegister();
pabloamr 0:8d55f1f49a33 843
pabloamr 0:8d55f1f49a33 844 return ( ( status & _NRF24L01P_STATUS_RX_DR ) && ( ( ( status & _NRF24L01P_STATUS_RX_P_NO ) >> 1 ) == ( pipe & 0x7 ) ) );
pabloamr 0:8d55f1f49a33 845
pabloamr 0:8d55f1f49a33 846 }
pabloamr 0:8d55f1f49a33 847
pabloamr 0:8d55f1f49a33 848
pabloamr 0:8d55f1f49a33 849 int nRF24L01P::write(int pipe, char *data, int count) {
pabloamr 0:8d55f1f49a33 850
pabloamr 0:8d55f1f49a33 851 // Note: the pipe number is ignored in a Transmit / write
pabloamr 0:8d55f1f49a33 852
pabloamr 0:8d55f1f49a33 853 //
pabloamr 0:8d55f1f49a33 854 // Save the CE state
pabloamr 0:8d55f1f49a33 855 //
pabloamr 0:8d55f1f49a33 856 int originalCe = ce_;
pabloamr 0:8d55f1f49a33 857 disable();
pabloamr 0:8d55f1f49a33 858
pabloamr 0:8d55f1f49a33 859 if ( count <= 0 ) return 0;
pabloamr 0:8d55f1f49a33 860
pabloamr 0:8d55f1f49a33 861 if ( count > _NRF24L01P_TX_FIFO_SIZE ) count = _NRF24L01P_TX_FIFO_SIZE;
pabloamr 0:8d55f1f49a33 862
pabloamr 0:8d55f1f49a33 863 // Clear the Status bit
pabloamr 0:8d55f1f49a33 864 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_TX_DS);
pabloamr 0:8d55f1f49a33 865
pabloamr 0:8d55f1f49a33 866 nCS_ = 0;
pabloamr 0:8d55f1f49a33 867
pabloamr 0:8d55f1f49a33 868 int status = spi_.write(_NRF24L01P_SPI_CMD_WR_TX_PAYLOAD);
pabloamr 0:8d55f1f49a33 869
pabloamr 0:8d55f1f49a33 870 for ( int i = 0; i < count; i++ ) {
pabloamr 0:8d55f1f49a33 871
pabloamr 0:8d55f1f49a33 872 spi_.write(*data++);
pabloamr 0:8d55f1f49a33 873
pabloamr 0:8d55f1f49a33 874 }
pabloamr 0:8d55f1f49a33 875
pabloamr 0:8d55f1f49a33 876 nCS_ = 1;
pabloamr 0:8d55f1f49a33 877
pabloamr 0:8d55f1f49a33 878 int originalMode = mode;
pabloamr 0:8d55f1f49a33 879 setTransmitMode();
pabloamr 0:8d55f1f49a33 880
pabloamr 0:8d55f1f49a33 881 enable();
pabloamr 0:8d55f1f49a33 882 wait_us(_NRF24L01P_TIMING_Thce_us);
pabloamr 0:8d55f1f49a33 883 disable();
pabloamr 0:8d55f1f49a33 884
pabloamr 0:8d55f1f49a33 885 while ( !( getStatusRegister() & _NRF24L01P_STATUS_TX_DS ) ) {
pabloamr 0:8d55f1f49a33 886
pabloamr 0:8d55f1f49a33 887 // Wait for the transfer to complete
pabloamr 0:8d55f1f49a33 888
pabloamr 0:8d55f1f49a33 889 }
pabloamr 0:8d55f1f49a33 890
pabloamr 0:8d55f1f49a33 891 // Clear the Status bit
pabloamr 0:8d55f1f49a33 892 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_TX_DS);
pabloamr 0:8d55f1f49a33 893
pabloamr 0:8d55f1f49a33 894 if ( originalMode == _NRF24L01P_MODE_RX ) {
pabloamr 0:8d55f1f49a33 895
pabloamr 0:8d55f1f49a33 896 setReceiveMode();
pabloamr 0:8d55f1f49a33 897
pabloamr 0:8d55f1f49a33 898 }
pabloamr 0:8d55f1f49a33 899
pabloamr 0:8d55f1f49a33 900 ce_ = originalCe;
pabloamr 0:8d55f1f49a33 901 wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
pabloamr 0:8d55f1f49a33 902
pabloamr 0:8d55f1f49a33 903 return count;
pabloamr 0:8d55f1f49a33 904
pabloamr 0:8d55f1f49a33 905 }
pabloamr 0:8d55f1f49a33 906
pabloamr 0:8d55f1f49a33 907
pabloamr 0:8d55f1f49a33 908 int nRF24L01P::read(int pipe, char *data, int count) {
pabloamr 0:8d55f1f49a33 909
pabloamr 0:8d55f1f49a33 910 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
pabloamr 0:8d55f1f49a33 911
pabloamr 0:8d55f1f49a33 912 error( "nRF24L01P: Invalid read pipe number %d\r\n", pipe );
pabloamr 0:8d55f1f49a33 913 return -1;
pabloamr 0:8d55f1f49a33 914
pabloamr 0:8d55f1f49a33 915 }
pabloamr 0:8d55f1f49a33 916
pabloamr 0:8d55f1f49a33 917 if ( count <= 0 ) return 0;
pabloamr 0:8d55f1f49a33 918
pabloamr 0:8d55f1f49a33 919 if ( count > _NRF24L01P_RX_FIFO_SIZE ) count = _NRF24L01P_RX_FIFO_SIZE;
pabloamr 0:8d55f1f49a33 920
pabloamr 0:8d55f1f49a33 921 if ( readable(pipe) ) {
pabloamr 0:8d55f1f49a33 922
pabloamr 0:8d55f1f49a33 923 nCS_ = 0;
pabloamr 0:8d55f1f49a33 924
pabloamr 0:8d55f1f49a33 925 int status = spi_.write(_NRF24L01P_SPI_CMD_R_RX_PL_WID);
pabloamr 0:8d55f1f49a33 926
pabloamr 0:8d55f1f49a33 927 int rxPayloadWidth = spi_.write(_NRF24L01P_SPI_CMD_NOP);
pabloamr 0:8d55f1f49a33 928
pabloamr 0:8d55f1f49a33 929 nCS_ = 1;
pabloamr 0:8d55f1f49a33 930
pabloamr 0:8d55f1f49a33 931 if ( ( rxPayloadWidth < 0 ) || ( rxPayloadWidth > _NRF24L01P_RX_FIFO_SIZE ) ) {
pabloamr 0:8d55f1f49a33 932
pabloamr 0:8d55f1f49a33 933 // Received payload error: need to flush the FIFO
pabloamr 0:8d55f1f49a33 934
pabloamr 0:8d55f1f49a33 935 nCS_ = 0;
pabloamr 0:8d55f1f49a33 936
pabloamr 0:8d55f1f49a33 937 int status = spi_.write(_NRF24L01P_SPI_CMD_FLUSH_RX);
pabloamr 0:8d55f1f49a33 938
pabloamr 0:8d55f1f49a33 939 int rxPayloadWidth = spi_.write(_NRF24L01P_SPI_CMD_NOP);
pabloamr 0:8d55f1f49a33 940
pabloamr 0:8d55f1f49a33 941 nCS_ = 1;
pabloamr 0:8d55f1f49a33 942
pabloamr 0:8d55f1f49a33 943 //
pabloamr 0:8d55f1f49a33 944 // At this point, we should retry the reception,
pabloamr 0:8d55f1f49a33 945 // but for now we'll just fall through...
pabloamr 0:8d55f1f49a33 946 //
pabloamr 0:8d55f1f49a33 947
pabloamr 0:8d55f1f49a33 948 } else {
pabloamr 0:8d55f1f49a33 949
pabloamr 0:8d55f1f49a33 950 if ( rxPayloadWidth < count ) count = rxPayloadWidth;
pabloamr 0:8d55f1f49a33 951
pabloamr 0:8d55f1f49a33 952 nCS_ = 0;
pabloamr 0:8d55f1f49a33 953
pabloamr 0:8d55f1f49a33 954 int status = spi_.write(_NRF24L01P_SPI_CMD_RD_RX_PAYLOAD);
pabloamr 0:8d55f1f49a33 955
pabloamr 0:8d55f1f49a33 956 for ( int i = 0; i < count; i++ ) {
pabloamr 0:8d55f1f49a33 957
pabloamr 0:8d55f1f49a33 958 *data++ = spi_.write(_NRF24L01P_SPI_CMD_NOP);
pabloamr 0:8d55f1f49a33 959
pabloamr 0:8d55f1f49a33 960 }
pabloamr 0:8d55f1f49a33 961
pabloamr 0:8d55f1f49a33 962 nCS_ = 1;
pabloamr 0:8d55f1f49a33 963
pabloamr 0:8d55f1f49a33 964 // Clear the Status bit
pabloamr 0:8d55f1f49a33 965 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_RX_DR);
pabloamr 0:8d55f1f49a33 966
pabloamr 0:8d55f1f49a33 967 return count;
pabloamr 0:8d55f1f49a33 968
pabloamr 0:8d55f1f49a33 969 }
pabloamr 0:8d55f1f49a33 970
pabloamr 0:8d55f1f49a33 971 } else {
pabloamr 0:8d55f1f49a33 972
pabloamr 0:8d55f1f49a33 973 //
pabloamr 0:8d55f1f49a33 974 // What should we do if there is no 'readable' data?
pabloamr 0:8d55f1f49a33 975 // We could wait for data to arrive, but for now, we'll
pabloamr 0:8d55f1f49a33 976 // just return with no data.
pabloamr 0:8d55f1f49a33 977 //
pabloamr 0:8d55f1f49a33 978 return 0;
pabloamr 0:8d55f1f49a33 979
pabloamr 0:8d55f1f49a33 980 }
pabloamr 0:8d55f1f49a33 981
pabloamr 0:8d55f1f49a33 982 //
pabloamr 0:8d55f1f49a33 983 // We get here because an error condition occured;
pabloamr 0:8d55f1f49a33 984 // We could wait for data to arrive, but for now, we'll
pabloamr 0:8d55f1f49a33 985 // just return with no data.
pabloamr 0:8d55f1f49a33 986 //
pabloamr 0:8d55f1f49a33 987 return -1;
pabloamr 0:8d55f1f49a33 988
pabloamr 0:8d55f1f49a33 989 }
pabloamr 0:8d55f1f49a33 990
pabloamr 0:8d55f1f49a33 991 void nRF24L01P::setRegister(int regAddress, int regData) {
pabloamr 0:8d55f1f49a33 992
pabloamr 0:8d55f1f49a33 993 //
pabloamr 0:8d55f1f49a33 994 // Save the CE state
pabloamr 0:8d55f1f49a33 995 //
pabloamr 0:8d55f1f49a33 996 int originalCe = ce_;
pabloamr 0:8d55f1f49a33 997 disable();
pabloamr 0:8d55f1f49a33 998
pabloamr 0:8d55f1f49a33 999 int cn = (_NRF24L01P_SPI_CMD_WR_REG | (regAddress & _NRF24L01P_REG_ADDRESS_MASK));
pabloamr 0:8d55f1f49a33 1000
pabloamr 0:8d55f1f49a33 1001 nCS_ = 0;
pabloamr 0:8d55f1f49a33 1002
pabloamr 0:8d55f1f49a33 1003 int status = spi_.write(cn);
pabloamr 0:8d55f1f49a33 1004
pabloamr 0:8d55f1f49a33 1005 spi_.write(regData & 0xFF);
pabloamr 0:8d55f1f49a33 1006
pabloamr 0:8d55f1f49a33 1007 nCS_ = 1;
pabloamr 0:8d55f1f49a33 1008
pabloamr 0:8d55f1f49a33 1009 ce_ = originalCe;
pabloamr 0:8d55f1f49a33 1010 wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
pabloamr 0:8d55f1f49a33 1011
pabloamr 0:8d55f1f49a33 1012 }
pabloamr 0:8d55f1f49a33 1013
pabloamr 0:8d55f1f49a33 1014
pabloamr 0:8d55f1f49a33 1015 int nRF24L01P::getRegister(int regAddress) {
pabloamr 0:8d55f1f49a33 1016
pabloamr 0:8d55f1f49a33 1017 int cn = (_NRF24L01P_SPI_CMD_RD_REG | (regAddress & _NRF24L01P_REG_ADDRESS_MASK));
pabloamr 0:8d55f1f49a33 1018
pabloamr 0:8d55f1f49a33 1019 nCS_ = 0;
pabloamr 0:8d55f1f49a33 1020
pabloamr 0:8d55f1f49a33 1021 int status = spi_.write(cn);
pabloamr 0:8d55f1f49a33 1022
pabloamr 0:8d55f1f49a33 1023 int dn = spi_.write(_NRF24L01P_SPI_CMD_NOP);
pabloamr 0:8d55f1f49a33 1024
pabloamr 0:8d55f1f49a33 1025 nCS_ = 1;
pabloamr 0:8d55f1f49a33 1026
pabloamr 0:8d55f1f49a33 1027 return dn;
pabloamr 0:8d55f1f49a33 1028
pabloamr 0:8d55f1f49a33 1029 }
pabloamr 0:8d55f1f49a33 1030
pabloamr 0:8d55f1f49a33 1031 int nRF24L01P::getStatusRegister(void) {
pabloamr 0:8d55f1f49a33 1032
pabloamr 0:8d55f1f49a33 1033 nCS_ = 0;
pabloamr 0:8d55f1f49a33 1034
pabloamr 0:8d55f1f49a33 1035 int status = spi_.write(_NRF24L01P_SPI_CMD_NOP);
pabloamr 0:8d55f1f49a33 1036
pabloamr 0:8d55f1f49a33 1037 nCS_ = 1;
pabloamr 0:8d55f1f49a33 1038
pabloamr 0:8d55f1f49a33 1039 return status;
pabloamr 0:8d55f1f49a33 1040
pabloamr 0:8d55f1f49a33 1041 }