nRF24L01P - RADIO nRF24L01

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RADIO nRF24L01

Fork of nRF24L01P by Pablo Rodriguez

nRF24L01P.cpp@0:8d55f1f49a33, 2011-04-21 (annotated)

Committer:: pabloamr
Date:: Thu Apr 21 23:14:43 2011 +0000
Revision:: 0:8d55f1f49a33
Child:: 1:d6b43a63580a

Who changed what in which revision?

User	Revision	Line number	New contents of line
pabloamr	0:8d55f1f49a33	1	/**
pabloamr	0:8d55f1f49a33	2	* @file nRF24L01P.cpp
pabloamr	0:8d55f1f49a33	3	*
pabloamr	0:8d55f1f49a33	4	* @author Owen Edwards
pabloamr	0:8d55f1f49a33	5	*
pabloamr	0:8d55f1f49a33	6	* @section LICENSE
pabloamr	0:8d55f1f49a33	7	*
pabloamr	0:8d55f1f49a33	8	* Copyright (c) 2010 Owen Edwards
pabloamr	0:8d55f1f49a33	9	*
pabloamr	0:8d55f1f49a33	10	* This program is free software: you can redistribute it and/or modify
pabloamr	0:8d55f1f49a33	11	* it under the terms of the GNU General Public License as published by
pabloamr	0:8d55f1f49a33	12	* the Free Software Foundation, either version 3 of the License, or
pabloamr	0:8d55f1f49a33	13	* (at your option) any later version.
pabloamr	0:8d55f1f49a33	14	*
pabloamr	0:8d55f1f49a33	15	* This program is distributed in the hope that it will be useful,
pabloamr	0:8d55f1f49a33	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
pabloamr	0:8d55f1f49a33	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
pabloamr	0:8d55f1f49a33	18	* GNU General Public License for more details.
pabloamr	0:8d55f1f49a33	19	*
pabloamr	0:8d55f1f49a33	20	* You should have received a copy of the GNU General Public License
pabloamr	0:8d55f1f49a33	21	* along with this program. If not, see <http://www.gnu.org/licenses/>.
pabloamr	0:8d55f1f49a33	22	*
pabloamr	0:8d55f1f49a33	23	* The above copyright notice and this permission notice shall be included in
pabloamr	0:8d55f1f49a33	24	* all copies or substantial portions of the Software.
pabloamr	0:8d55f1f49a33	25	*
pabloamr	0:8d55f1f49a33	26	* @section DESCRIPTION
pabloamr	0:8d55f1f49a33	27	*
pabloamr	0:8d55f1f49a33	28	* nRF24L01+ Single Chip 2.4GHz Transceiver from Nordic Semiconductor.
pabloamr	0:8d55f1f49a33	29	*
pabloamr	0:8d55f1f49a33	30	* Datasheet:
pabloamr	0:8d55f1f49a33	31	*
pabloamr	0:8d55f1f49a33	32	* http://www.nordicsemi.no/files/Product/data_sheet/nRF24L01P_Product_Specification_1_0.pdf
pabloamr	0:8d55f1f49a33	33	*/
pabloamr	0:8d55f1f49a33	34
pabloamr	0:8d55f1f49a33	35	/**
pabloamr	0:8d55f1f49a33	36	* Includes
pabloamr	0:8d55f1f49a33	37	*/
pabloamr	0:8d55f1f49a33	38	#include "nRF24L01P.h"
pabloamr	0:8d55f1f49a33	39
pabloamr	0:8d55f1f49a33	40	/**
pabloamr	0:8d55f1f49a33	41	* Defines
pabloamr	0:8d55f1f49a33	42	*
pabloamr	0:8d55f1f49a33	43	* (Note that all defines here start with an underscore, e.g. '_NRF24L01P_MODE_UNKNOWN',
pabloamr	0:8d55f1f49a33	44	* and are local to this library. The defines in the nRF24L01P.h file do not start
pabloamr	0:8d55f1f49a33	45	* with the underscore, and can be used by code to access this library.)
pabloamr	0:8d55f1f49a33	46	*/
pabloamr	0:8d55f1f49a33	47
pabloamr	0:8d55f1f49a33	48	typedef enum {
pabloamr	0:8d55f1f49a33	49	_NRF24L01P_MODE_UNKNOWN,
pabloamr	0:8d55f1f49a33	50	_NRF24L01P_MODE_POWER_DOWN,
pabloamr	0:8d55f1f49a33	51	_NRF24L01P_MODE_STANDBY,
pabloamr	0:8d55f1f49a33	52	_NRF24L01P_MODE_RX,
pabloamr	0:8d55f1f49a33	53	_NRF24L01P_MODE_TX,
pabloamr	0:8d55f1f49a33	54	} nRF24L01P_Mode_Type;
pabloamr	0:8d55f1f49a33	55
pabloamr	0:8d55f1f49a33	56	/*
pabloamr	0:8d55f1f49a33	57	* The following FIFOs are present in nRF24L01+:
pabloamr	0:8d55f1f49a33	58	* TX three level, 32 byte FIFO
pabloamr	0:8d55f1f49a33	59	* RX three level, 32 byte FIFO
pabloamr	0:8d55f1f49a33	60	*/
pabloamr	0:8d55f1f49a33	61	#define _NRF24L01P_TX_FIFO_COUNT 33
pabloamr	0:8d55f1f49a33	62	#define _NRF24L01P_RX_FIFO_COUNT 33
pabloamr	0:8d55f1f49a33	63
pabloamr	0:8d55f1f49a33	64	#define _NRF24L01P_TX_FIFO_SIZE 32
pabloamr	0:8d55f1f49a33	65	#define _NRF24L01P_RX_FIFO_SIZE 32
pabloamr	0:8d55f1f49a33	66
pabloamr	0:8d55f1f49a33	67	#define _NRF24L01P_SPI_MAX_DATA_RATE 10000000
pabloamr	0:8d55f1f49a33	68
pabloamr	0:8d55f1f49a33	69	#define _NRF24L01P_SPI_CMD_RD_REG 0x00
pabloamr	0:8d55f1f49a33	70	#define _NRF24L01P_SPI_CMD_WR_REG 0x20
pabloamr	0:8d55f1f49a33	71	#define _NRF24L01P_SPI_CMD_RD_RX_PAYLOAD 0x61
pabloamr	0:8d55f1f49a33	72	#define _NRF24L01P_SPI_CMD_WR_TX_PAYLOAD 0xa0
pabloamr	0:8d55f1f49a33	73	#define _NRF24L01P_SPI_CMD_FLUSH_TX 0xe1
pabloamr	0:8d55f1f49a33	74	#define _NRF24L01P_SPI_CMD_FLUSH_RX 0xe2
pabloamr	0:8d55f1f49a33	75	#define _NRF24L01P_SPI_CMD_REUSE_TX_PL 0xe3
pabloamr	0:8d55f1f49a33	76	#define _NRF24L01P_SPI_CMD_R_RX_PL_WID 0x60
pabloamr	0:8d55f1f49a33	77	#define _NRF24L01P_SPI_CMD_W_ACK_PAYLOAD 0xa8
pabloamr	0:8d55f1f49a33	78	#define _NRF24L01P_SPI_CMD_W_TX_PYLD_NO_ACK 0xb0
pabloamr	0:8d55f1f49a33	79	#define _NRF24L01P_SPI_CMD_NOP 0xff
pabloamr	0:8d55f1f49a33	80
pabloamr	0:8d55f1f49a33	81
pabloamr	0:8d55f1f49a33	82	#define _NRF24L01P_REG_CONFIG 0x00
pabloamr	0:8d55f1f49a33	83	#define _NRF24L01P_REG_EN_AA 0x01
pabloamr	0:8d55f1f49a33	84	#define _NRF24L01P_REG_EN_RXADDR 0x02
pabloamr	0:8d55f1f49a33	85	#define _NRF24L01P_REG_SETUP_AW 0x03
pabloamr	0:8d55f1f49a33	86	#define _NRF24L01P_REG_SETUP_RETR 0x04
pabloamr	0:8d55f1f49a33	87	#define _NRF24L01P_REG_RF_CH 0x05
pabloamr	0:8d55f1f49a33	88	#define _NRF24L01P_REG_RF_SETUP 0x06
pabloamr	0:8d55f1f49a33	89	#define _NRF24L01P_REG_STATUS 0x07
pabloamr	0:8d55f1f49a33	90	#define _NRF24L01P_REG_OBSERVE_TX 0x08
pabloamr	0:8d55f1f49a33	91	#define _NRF24L01P_REG_RPD 0x09
pabloamr	0:8d55f1f49a33	92	#define _NRF24L01P_REG_RX_ADDR_P0 0x0a
pabloamr	0:8d55f1f49a33	93	#define _NRF24L01P_REG_RX_ADDR_P1 0x0b
pabloamr	0:8d55f1f49a33	94	#define _NRF24L01P_REG_RX_ADDR_P2 0x0c
pabloamr	0:8d55f1f49a33	95	#define _NRF24L01P_REG_RX_ADDR_P3 0x0d
pabloamr	0:8d55f1f49a33	96	#define _NRF24L01P_REG_RX_ADDR_P4 0x0e
pabloamr	0:8d55f1f49a33	97	#define _NRF24L01P_REG_RX_ADDR_P5 0x0f
pabloamr	0:8d55f1f49a33	98	#define _NRF24L01P_REG_TX_ADDR 0x10
pabloamr	0:8d55f1f49a33	99	#define _NRF24L01P_REG_RX_PW_P0 0x11
pabloamr	0:8d55f1f49a33	100	#define _NRF24L01P_REG_RX_PW_P1 0x12
pabloamr	0:8d55f1f49a33	101	#define _NRF24L01P_REG_RX_PW_P2 0x13
pabloamr	0:8d55f1f49a33	102	#define _NRF24L01P_REG_RX_PW_P3 0x14
pabloamr	0:8d55f1f49a33	103	#define _NRF24L01P_REG_RX_PW_P4 0x15
pabloamr	0:8d55f1f49a33	104	#define _NRF24L01P_REG_RX_PW_P5 0x16
pabloamr	0:8d55f1f49a33	105	#define _NRF24L01P_REG_FIFO_STATUS 0x17
pabloamr	0:8d55f1f49a33	106	#define _NRF24L01P_REG_DYNPD 0x1c
pabloamr	0:8d55f1f49a33	107	#define _NRF24L01P_REG_FEATURE 0x1d
pabloamr	0:8d55f1f49a33	108
pabloamr	0:8d55f1f49a33	109	#define _NRF24L01P_REG_ADDRESS_MASK 0x1f
pabloamr	0:8d55f1f49a33	110
pabloamr	0:8d55f1f49a33	111	// CONFIG register:
pabloamr	0:8d55f1f49a33	112	#define _NRF24L01P_CONFIG_PRIM_RX (1<<0)
pabloamr	0:8d55f1f49a33	113	#define _NRF24L01P_CONFIG_PWR_UP (1<<1)
pabloamr	0:8d55f1f49a33	114	#define _NRF24L01P_CONFIG_CRC0 (1<<2)
pabloamr	0:8d55f1f49a33	115	#define _NRF24L01P_CONFIG_EN_CRC (1<<3)
pabloamr	0:8d55f1f49a33	116	#define _NRF24L01P_CONFIG_MASK_MAX_RT (1<<4)
pabloamr	0:8d55f1f49a33	117	#define _NRF24L01P_CONFIG_MASK_TX_DS (1<<5)
pabloamr	0:8d55f1f49a33	118	#define _NRF24L01P_CONFIG_MASK_RX_DR (1<<6)
pabloamr	0:8d55f1f49a33	119
pabloamr	0:8d55f1f49a33	120	#define _NRF24L01P_CONFIG_CRC_MASK (_NRF24L01P_CONFIG_EN_CRC\|_NRF24L01P_CONFIG_CRC0)
pabloamr	0:8d55f1f49a33	121	#define _NRF24L01P_CONFIG_CRC_NONE (0)
pabloamr	0:8d55f1f49a33	122	#define _NRF24L01P_CONFIG_CRC_8BIT (_NRF24L01P_CONFIG_EN_CRC)
pabloamr	0:8d55f1f49a33	123	#define _NRF24L01P_CONFIG_CRC_16BIT (_NRF24L01P_CONFIG_EN_CRC\|_NRF24L01P_CONFIG_CRC0)
pabloamr	0:8d55f1f49a33	124
pabloamr	0:8d55f1f49a33	125	// EN_AA register:
pabloamr	0:8d55f1f49a33	126	#define _NRF24L01P_EN_AA_NONE 0
pabloamr	0:8d55f1f49a33	127
pabloamr	0:8d55f1f49a33	128	// EN_RXADDR register:
pabloamr	0:8d55f1f49a33	129	#define _NRF24L01P_EN_RXADDR_NONE 0
pabloamr	0:8d55f1f49a33	130
pabloamr	0:8d55f1f49a33	131	// SETUP_AW register:
pabloamr	0:8d55f1f49a33	132	#define _NRF24L01P_SETUP_AW_AW_MASK (0x3<<0)
pabloamr	0:8d55f1f49a33	133	#define _NRF24L01P_SETUP_AW_AW_3BYTE (0x1<<0)
pabloamr	0:8d55f1f49a33	134	#define _NRF24L01P_SETUP_AW_AW_4BYTE (0x2<<0)
pabloamr	0:8d55f1f49a33	135	#define _NRF24L01P_SETUP_AW_AW_5BYTE (0x3<<0)
pabloamr	0:8d55f1f49a33	136
pabloamr	0:8d55f1f49a33	137	// SETUP_RETR register:
pabloamr	0:8d55f1f49a33	138	#define _NRF24L01P_SETUP_RETR_NONE 0
pabloamr	0:8d55f1f49a33	139
pabloamr	0:8d55f1f49a33	140	// RF_SETUP register:
pabloamr	0:8d55f1f49a33	141	#define _NRF24L01P_RF_SETUP_RF_PWR_MASK (0x3<<1)
pabloamr	0:8d55f1f49a33	142	#define _NRF24L01P_RF_SETUP_RF_PWR_0DBM (0x3<<1)
pabloamr	0:8d55f1f49a33	143	#define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM (0x2<<1)
pabloamr	0:8d55f1f49a33	144	#define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM (0x1<<1)
pabloamr	0:8d55f1f49a33	145	#define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM (0x0<<1)
pabloamr	0:8d55f1f49a33	146
pabloamr	0:8d55f1f49a33	147	#define _NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT (1 << 3)
pabloamr	0:8d55f1f49a33	148	#define _NRF24L01P_RF_SETUP_RF_DR_LOW_BIT (1 << 5)
pabloamr	0:8d55f1f49a33	149	#define _NRF24L01P_RF_SETUP_RF_DR_MASK (_NRF24L01P_RF_SETUP_RF_DR_LOW_BIT\|_NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT)
pabloamr	0:8d55f1f49a33	150	#define _NRF24L01P_RF_SETUP_RF_DR_250KBPS (_NRF24L01P_RF_SETUP_RF_DR_LOW_BIT)
pabloamr	0:8d55f1f49a33	151	#define _NRF24L01P_RF_SETUP_RF_DR_1MBPS (0)
pabloamr	0:8d55f1f49a33	152	#define _NRF24L01P_RF_SETUP_RF_DR_2MBPS (_NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT)
pabloamr	0:8d55f1f49a33	153
pabloamr	0:8d55f1f49a33	154	// STATUS register:
pabloamr	0:8d55f1f49a33	155	#define _NRF24L01P_STATUS_TX_FULL (1<<0)
pabloamr	0:8d55f1f49a33	156	#define _NRF24L01P_STATUS_RX_P_NO (0x7<<1)
pabloamr	0:8d55f1f49a33	157	#define _NRF24L01P_STATUS_MAX_RT (1<<4)
pabloamr	0:8d55f1f49a33	158	#define _NRF24L01P_STATUS_TX_DS (1<<5)
pabloamr	0:8d55f1f49a33	159	#define _NRF24L01P_STATUS_RX_DR (1<<6)
pabloamr	0:8d55f1f49a33	160
pabloamr	0:8d55f1f49a33	161	// RX_PW_P0..RX_PW_P5 registers:
pabloamr	0:8d55f1f49a33	162	#define _NRF24L01P_RX_PW_Px_MASK 0x3F
pabloamr	0:8d55f1f49a33	163
pabloamr	0:8d55f1f49a33	164	#define _NRF24L01P_TIMING_Tundef2pd_us 100000 // 100mS
pabloamr	0:8d55f1f49a33	165	#define _NRF24L01P_TIMING_Tstby2a_us 130 // 130uS
pabloamr	0:8d55f1f49a33	166	#define _NRF24L01P_TIMING_Thce_us 10 // 10uS
pabloamr	0:8d55f1f49a33	167	#define _NRF24L01P_TIMING_Tpd2stby_us 4500 // 4.5mS worst case
pabloamr	0:8d55f1f49a33	168	#define _NRF24L01P_TIMING_Tpece2csn_us 4 // 4uS
pabloamr	0:8d55f1f49a33	169
pabloamr	0:8d55f1f49a33	170	/**
pabloamr	0:8d55f1f49a33	171	* Methods
pabloamr	0:8d55f1f49a33	172	*/
pabloamr	0:8d55f1f49a33	173
pabloamr	0:8d55f1f49a33	174	nRF24L01P::nRF24L01P(PinName mosi,
pabloamr	0:8d55f1f49a33	175	PinName miso,
pabloamr	0:8d55f1f49a33	176	PinName sck,
pabloamr	0:8d55f1f49a33	177	PinName csn,
pabloamr	0:8d55f1f49a33	178	PinName ce,
pabloamr	0:8d55f1f49a33	179	PinName irq) : spi_(mosi, miso, sck), nCS_(csn), ce_(ce), nIRQ_(irq) {
pabloamr	0:8d55f1f49a33	180
pabloamr	0:8d55f1f49a33	181	mode = _NRF24L01P_MODE_UNKNOWN;
pabloamr	0:8d55f1f49a33	182
pabloamr	0:8d55f1f49a33	183	disable();
pabloamr	0:8d55f1f49a33	184
pabloamr	0:8d55f1f49a33	185	nCS_ = 1;
pabloamr	0:8d55f1f49a33	186
pabloamr	0:8d55f1f49a33	187	spi_.frequency(_NRF24L01P_SPI_MAX_DATA_RATE/5); // 2Mbit, 1/5th the maximum transfer rate for the SPI bus
pabloamr	0:8d55f1f49a33	188	spi_.format(8,0); // 8-bit, ClockPhase = 0, ClockPolarity = 0
pabloamr	0:8d55f1f49a33	189
pabloamr	0:8d55f1f49a33	190	wait_us(_NRF24L01P_TIMING_Tundef2pd_us); // Wait for Power-on reset
pabloamr	0:8d55f1f49a33	191
pabloamr	0:8d55f1f49a33	192	setRegister(_NRF24L01P_REG_CONFIG, 0); // Power Down
pabloamr	0:8d55f1f49a33	193
pabloamr	0:8d55f1f49a33	194	setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_MAX_RT\|_NRF24L01P_STATUS_TX_DS\|_NRF24L01P_STATUS_RX_DR); // Clear any pending interrupts
pabloamr	0:8d55f1f49a33	195
pabloamr	0:8d55f1f49a33	196	//
pabloamr	0:8d55f1f49a33	197	// Setup default configuration
pabloamr	0:8d55f1f49a33	198	//
pabloamr	0:8d55f1f49a33	199	disableAllRxPipes();
pabloamr	0:8d55f1f49a33	200	setRfFrequency();
pabloamr	0:8d55f1f49a33	201	setRfOutputPower();
pabloamr	0:8d55f1f49a33	202	setAirDataRate();
pabloamr	0:8d55f1f49a33	203	setCrcWidth();
pabloamr	0:8d55f1f49a33	204	setTxAddress();
pabloamr	0:8d55f1f49a33	205	setRxAddress();
pabloamr	0:8d55f1f49a33	206	disableAutoAcknowledge();
pabloamr	0:8d55f1f49a33	207	disableAutoRetransmit();
pabloamr	0:8d55f1f49a33	208	setTransferSize();
pabloamr	0:8d55f1f49a33	209
pabloamr	0:8d55f1f49a33	210	mode = _NRF24L01P_MODE_POWER_DOWN;
pabloamr	0:8d55f1f49a33	211
pabloamr	0:8d55f1f49a33	212	}
pabloamr	0:8d55f1f49a33	213
pabloamr	0:8d55f1f49a33	214
pabloamr	0:8d55f1f49a33	215	void nRF24L01P::powerUp(void) {
pabloamr	0:8d55f1f49a33	216
pabloamr	0:8d55f1f49a33	217	int config = getRegister(_NRF24L01P_REG_CONFIG);
pabloamr	0:8d55f1f49a33	218
pabloamr	0:8d55f1f49a33	219	config \|= _NRF24L01P_CONFIG_PWR_UP;
pabloamr	0:8d55f1f49a33	220
pabloamr	0:8d55f1f49a33	221	setRegister(_NRF24L01P_REG_CONFIG, config);
pabloamr	0:8d55f1f49a33	222
pabloamr	0:8d55f1f49a33	223	// Wait until the nRF24L01+ powers up
pabloamr	0:8d55f1f49a33	224	wait_us( _NRF24L01P_TIMING_Tpd2stby_us );
pabloamr	0:8d55f1f49a33	225
pabloamr	0:8d55f1f49a33	226	mode = _NRF24L01P_MODE_STANDBY;
pabloamr	0:8d55f1f49a33	227
pabloamr	0:8d55f1f49a33	228	}
pabloamr	0:8d55f1f49a33	229
pabloamr	0:8d55f1f49a33	230
pabloamr	0:8d55f1f49a33	231	void nRF24L01P::powerDown(void) {
pabloamr	0:8d55f1f49a33	232
pabloamr	0:8d55f1f49a33	233	int config = getRegister(_NRF24L01P_REG_CONFIG);
pabloamr	0:8d55f1f49a33	234
pabloamr	0:8d55f1f49a33	235	config &= ~_NRF24L01P_CONFIG_PWR_UP;
pabloamr	0:8d55f1f49a33	236
pabloamr	0:8d55f1f49a33	237	setRegister(_NRF24L01P_REG_CONFIG, config);
pabloamr	0:8d55f1f49a33	238
pabloamr	0:8d55f1f49a33	239	// Wait until the nRF24L01+ powers down
pabloamr	0:8d55f1f49a33	240	wait_us( _NRF24L01P_TIMING_Tpd2stby_us ); // This may not be necessary (no timing is shown in the Datasheet), but just to be safe
pabloamr	0:8d55f1f49a33	241
pabloamr	0:8d55f1f49a33	242	mode = _NRF24L01P_MODE_POWER_DOWN;
pabloamr	0:8d55f1f49a33	243
pabloamr	0:8d55f1f49a33	244	}
pabloamr	0:8d55f1f49a33	245
pabloamr	0:8d55f1f49a33	246
pabloamr	0:8d55f1f49a33	247	void nRF24L01P::setReceiveMode(void) {
pabloamr	0:8d55f1f49a33	248
pabloamr	0:8d55f1f49a33	249	if ( _NRF24L01P_MODE_POWER_DOWN == mode ) powerUp();
pabloamr	0:8d55f1f49a33	250
pabloamr	0:8d55f1f49a33	251	int config = getRegister(_NRF24L01P_REG_CONFIG);
pabloamr	0:8d55f1f49a33	252
pabloamr	0:8d55f1f49a33	253	config \|= _NRF24L01P_CONFIG_PRIM_RX;
pabloamr	0:8d55f1f49a33	254
pabloamr	0:8d55f1f49a33	255	setRegister(_NRF24L01P_REG_CONFIG, config);
pabloamr	0:8d55f1f49a33	256
pabloamr	0:8d55f1f49a33	257	mode = _NRF24L01P_MODE_RX;
pabloamr	0:8d55f1f49a33	258
pabloamr	0:8d55f1f49a33	259	}
pabloamr	0:8d55f1f49a33	260
pabloamr	0:8d55f1f49a33	261
pabloamr	0:8d55f1f49a33	262	void nRF24L01P::setTransmitMode(void) {
pabloamr	0:8d55f1f49a33	263
pabloamr	0:8d55f1f49a33	264	if ( _NRF24L01P_MODE_POWER_DOWN == mode ) powerUp();
pabloamr	0:8d55f1f49a33	265
pabloamr	0:8d55f1f49a33	266	int config = getRegister(_NRF24L01P_REG_CONFIG);
pabloamr	0:8d55f1f49a33	267
pabloamr	0:8d55f1f49a33	268	config &= ~_NRF24L01P_CONFIG_PRIM_RX;
pabloamr	0:8d55f1f49a33	269
pabloamr	0:8d55f1f49a33	270	setRegister(_NRF24L01P_REG_CONFIG, config);
pabloamr	0:8d55f1f49a33	271
pabloamr	0:8d55f1f49a33	272	mode = _NRF24L01P_MODE_TX;
pabloamr	0:8d55f1f49a33	273
pabloamr	0:8d55f1f49a33	274	}
pabloamr	0:8d55f1f49a33	275
pabloamr	0:8d55f1f49a33	276
pabloamr	0:8d55f1f49a33	277	void nRF24L01P::enable(void) {
pabloamr	0:8d55f1f49a33	278
pabloamr	0:8d55f1f49a33	279	ce_ = 1;
pabloamr	0:8d55f1f49a33	280	wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
pabloamr	0:8d55f1f49a33	281
pabloamr	0:8d55f1f49a33	282	}
pabloamr	0:8d55f1f49a33	283
pabloamr	0:8d55f1f49a33	284
pabloamr	0:8d55f1f49a33	285	void nRF24L01P::disable(void) {
pabloamr	0:8d55f1f49a33	286
pabloamr	0:8d55f1f49a33	287	ce_ = 0;
pabloamr	0:8d55f1f49a33	288
pabloamr	0:8d55f1f49a33	289	}
pabloamr	0:8d55f1f49a33	290
pabloamr	0:8d55f1f49a33	291	void nRF24L01P::setRfFrequency(int frequency) {
pabloamr	0:8d55f1f49a33	292
pabloamr	0:8d55f1f49a33	293	if ( ( frequency < NRF24L01P_MIN_RF_FREQUENCY ) \|\| ( frequency > NRF24L01P_MAX_RF_FREQUENCY ) ) {
pabloamr	0:8d55f1f49a33	294
pabloamr	0:8d55f1f49a33	295	error( "nRF24L01P: Invalid RF Frequency setting %d\r\n", frequency );
pabloamr	0:8d55f1f49a33	296	return;
pabloamr	0:8d55f1f49a33	297
pabloamr	0:8d55f1f49a33	298	}
pabloamr	0:8d55f1f49a33	299
pabloamr	0:8d55f1f49a33	300	int channel = ( frequency - NRF24L01P_MIN_RF_FREQUENCY ) & 0x7F;
pabloamr	0:8d55f1f49a33	301
pabloamr	0:8d55f1f49a33	302	setRegister(_NRF24L01P_REG_RF_CH, channel);
pabloamr	0:8d55f1f49a33	303
pabloamr	0:8d55f1f49a33	304	}
pabloamr	0:8d55f1f49a33	305
pabloamr	0:8d55f1f49a33	306
pabloamr	0:8d55f1f49a33	307	int nRF24L01P::getRfFrequency(void) {
pabloamr	0:8d55f1f49a33	308
pabloamr	0:8d55f1f49a33	309	int channel = getRegister(_NRF24L01P_REG_RF_CH) & 0x7F;
pabloamr	0:8d55f1f49a33	310
pabloamr	0:8d55f1f49a33	311	return ( channel + NRF24L01P_MIN_RF_FREQUENCY );
pabloamr	0:8d55f1f49a33	312
pabloamr	0:8d55f1f49a33	313	}
pabloamr	0:8d55f1f49a33	314
pabloamr	0:8d55f1f49a33	315
pabloamr	0:8d55f1f49a33	316	void nRF24L01P::setRfOutputPower(int power) {
pabloamr	0:8d55f1f49a33	317
pabloamr	0:8d55f1f49a33	318	int rfSetup = getRegister(_NRF24L01P_REG_RF_SETUP) & ~_NRF24L01P_RF_SETUP_RF_PWR_MASK;
pabloamr	0:8d55f1f49a33	319
pabloamr	0:8d55f1f49a33	320	switch ( power ) {
pabloamr	0:8d55f1f49a33	321
pabloamr	0:8d55f1f49a33	322	case NRF24L01P_TX_PWR_ZERO_DB:
pabloamr	0:8d55f1f49a33	323	rfSetup \|= _NRF24L01P_RF_SETUP_RF_PWR_0DBM;
pabloamr	0:8d55f1f49a33	324	break;
pabloamr	0:8d55f1f49a33	325
pabloamr	0:8d55f1f49a33	326	case NRF24L01P_TX_PWR_MINUS_6_DB:
pabloamr	0:8d55f1f49a33	327	rfSetup \|= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM;
pabloamr	0:8d55f1f49a33	328	break;
pabloamr	0:8d55f1f49a33	329
pabloamr	0:8d55f1f49a33	330	case NRF24L01P_TX_PWR_MINUS_12_DB:
pabloamr	0:8d55f1f49a33	331	rfSetup \|= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM;
pabloamr	0:8d55f1f49a33	332	break;
pabloamr	0:8d55f1f49a33	333
pabloamr	0:8d55f1f49a33	334	case NRF24L01P_TX_PWR_MINUS_18_DB:
pabloamr	0:8d55f1f49a33	335	rfSetup \|= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM;
pabloamr	0:8d55f1f49a33	336	break;
pabloamr	0:8d55f1f49a33	337
pabloamr	0:8d55f1f49a33	338	default:
pabloamr	0:8d55f1f49a33	339	error( "nRF24L01P: Invalid RF Output Power setting %d\r\n", power );
pabloamr	0:8d55f1f49a33	340	return;
pabloamr	0:8d55f1f49a33	341
pabloamr	0:8d55f1f49a33	342	}
pabloamr	0:8d55f1f49a33	343
pabloamr	0:8d55f1f49a33	344	setRegister(_NRF24L01P_REG_RF_SETUP, rfSetup);
pabloamr	0:8d55f1f49a33	345
pabloamr	0:8d55f1f49a33	346	}
pabloamr	0:8d55f1f49a33	347
pabloamr	0:8d55f1f49a33	348
pabloamr	0:8d55f1f49a33	349	int nRF24L01P::getRfOutputPower(void) {
pabloamr	0:8d55f1f49a33	350
pabloamr	0:8d55f1f49a33	351	int rfPwr = getRegister(_NRF24L01P_REG_RF_SETUP) & _NRF24L01P_RF_SETUP_RF_PWR_MASK;
pabloamr	0:8d55f1f49a33	352
pabloamr	0:8d55f1f49a33	353	switch ( rfPwr ) {
pabloamr	0:8d55f1f49a33	354
pabloamr	0:8d55f1f49a33	355	case _NRF24L01P_RF_SETUP_RF_PWR_0DBM:
pabloamr	0:8d55f1f49a33	356	return NRF24L01P_TX_PWR_ZERO_DB;
pabloamr	0:8d55f1f49a33	357
pabloamr	0:8d55f1f49a33	358	case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM:
pabloamr	0:8d55f1f49a33	359	return NRF24L01P_TX_PWR_MINUS_6_DB;
pabloamr	0:8d55f1f49a33	360
pabloamr	0:8d55f1f49a33	361	case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM:
pabloamr	0:8d55f1f49a33	362	return NRF24L01P_TX_PWR_MINUS_12_DB;
pabloamr	0:8d55f1f49a33	363
pabloamr	0:8d55f1f49a33	364	case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM:
pabloamr	0:8d55f1f49a33	365	return NRF24L01P_TX_PWR_MINUS_18_DB;
pabloamr	0:8d55f1f49a33	366
pabloamr	0:8d55f1f49a33	367	default:
pabloamr	0:8d55f1f49a33	368	error( "nRF24L01P: Unknown RF Output Power value %d\r\n", rfPwr );
pabloamr	0:8d55f1f49a33	369	return 0;
pabloamr	0:8d55f1f49a33	370
pabloamr	0:8d55f1f49a33	371	}
pabloamr	0:8d55f1f49a33	372	}
pabloamr	0:8d55f1f49a33	373
pabloamr	0:8d55f1f49a33	374
pabloamr	0:8d55f1f49a33	375	void nRF24L01P::setAirDataRate(int rate) {
pabloamr	0:8d55f1f49a33	376
pabloamr	0:8d55f1f49a33	377	int rfSetup = getRegister(_NRF24L01P_REG_RF_SETUP) & ~_NRF24L01P_RF_SETUP_RF_DR_MASK;
pabloamr	0:8d55f1f49a33	378
pabloamr	0:8d55f1f49a33	379	switch ( rate ) {
pabloamr	0:8d55f1f49a33	380
pabloamr	0:8d55f1f49a33	381	case NRF24L01P_DATARATE_250_KBPS:
pabloamr	0:8d55f1f49a33	382	rfSetup \|= _NRF24L01P_RF_SETUP_RF_DR_250KBPS;
pabloamr	0:8d55f1f49a33	383	break;
pabloamr	0:8d55f1f49a33	384
pabloamr	0:8d55f1f49a33	385	case NRF24L01P_DATARATE_1_MBPS:
pabloamr	0:8d55f1f49a33	386	rfSetup \|= _NRF24L01P_RF_SETUP_RF_DR_1MBPS;
pabloamr	0:8d55f1f49a33	387	break;
pabloamr	0:8d55f1f49a33	388
pabloamr	0:8d55f1f49a33	389	case NRF24L01P_DATARATE_2_MBPS:
pabloamr	0:8d55f1f49a33	390	rfSetup \|= _NRF24L01P_RF_SETUP_RF_DR_2MBPS;
pabloamr	0:8d55f1f49a33	391	break;
pabloamr	0:8d55f1f49a33	392
pabloamr	0:8d55f1f49a33	393	default:
pabloamr	0:8d55f1f49a33	394	error( "nRF24L01P: Invalid Air Data Rate setting %d\r\n", rate );
pabloamr	0:8d55f1f49a33	395	return;
pabloamr	0:8d55f1f49a33	396
pabloamr	0:8d55f1f49a33	397	}
pabloamr	0:8d55f1f49a33	398
pabloamr	0:8d55f1f49a33	399	setRegister(_NRF24L01P_REG_RF_SETUP, rfSetup);
pabloamr	0:8d55f1f49a33	400
pabloamr	0:8d55f1f49a33	401	}
pabloamr	0:8d55f1f49a33	402
pabloamr	0:8d55f1f49a33	403
pabloamr	0:8d55f1f49a33	404	int nRF24L01P::getAirDataRate(void) {
pabloamr	0:8d55f1f49a33	405
pabloamr	0:8d55f1f49a33	406	int rfDataRate = getRegister(_NRF24L01P_REG_RF_SETUP) & _NRF24L01P_RF_SETUP_RF_DR_MASK;
pabloamr	0:8d55f1f49a33	407
pabloamr	0:8d55f1f49a33	408	switch ( rfDataRate ) {
pabloamr	0:8d55f1f49a33	409
pabloamr	0:8d55f1f49a33	410	case _NRF24L01P_RF_SETUP_RF_DR_250KBPS:
pabloamr	0:8d55f1f49a33	411	return NRF24L01P_DATARATE_250_KBPS;
pabloamr	0:8d55f1f49a33	412
pabloamr	0:8d55f1f49a33	413	case _NRF24L01P_RF_SETUP_RF_DR_1MBPS:
pabloamr	0:8d55f1f49a33	414	return NRF24L01P_DATARATE_1_MBPS;
pabloamr	0:8d55f1f49a33	415
pabloamr	0:8d55f1f49a33	416	case _NRF24L01P_RF_SETUP_RF_DR_2MBPS:
pabloamr	0:8d55f1f49a33	417	return NRF24L01P_DATARATE_2_MBPS;
pabloamr	0:8d55f1f49a33	418
pabloamr	0:8d55f1f49a33	419	default:
pabloamr	0:8d55f1f49a33	420	error( "nRF24L01P: Unknown Air Data Rate value %d\r\n", rfDataRate );
pabloamr	0:8d55f1f49a33	421	return 0;
pabloamr	0:8d55f1f49a33	422
pabloamr	0:8d55f1f49a33	423	}
pabloamr	0:8d55f1f49a33	424	}
pabloamr	0:8d55f1f49a33	425
pabloamr	0:8d55f1f49a33	426
pabloamr	0:8d55f1f49a33	427	void nRF24L01P::setCrcWidth(int width) {
pabloamr	0:8d55f1f49a33	428
pabloamr	0:8d55f1f49a33	429	int config = getRegister(_NRF24L01P_REG_CONFIG) & ~_NRF24L01P_CONFIG_CRC_MASK;
pabloamr	0:8d55f1f49a33	430
pabloamr	0:8d55f1f49a33	431	switch ( width ) {
pabloamr	0:8d55f1f49a33	432
pabloamr	0:8d55f1f49a33	433	case NRF24L01P_CRC_NONE:
pabloamr	0:8d55f1f49a33	434	config \|= _NRF24L01P_CONFIG_CRC_NONE;
pabloamr	0:8d55f1f49a33	435	break;
pabloamr	0:8d55f1f49a33	436
pabloamr	0:8d55f1f49a33	437	case NRF24L01P_CRC_8_BIT:
pabloamr	0:8d55f1f49a33	438	config \|= _NRF24L01P_CONFIG_CRC_8BIT;
pabloamr	0:8d55f1f49a33	439	break;
pabloamr	0:8d55f1f49a33	440
pabloamr	0:8d55f1f49a33	441	case NRF24L01P_CRC_16_BIT:
pabloamr	0:8d55f1f49a33	442	config \|= _NRF24L01P_CONFIG_CRC_16BIT;
pabloamr	0:8d55f1f49a33	443	break;
pabloamr	0:8d55f1f49a33	444
pabloamr	0:8d55f1f49a33	445	default:
pabloamr	0:8d55f1f49a33	446	error( "nRF24L01P: Invalid CRC Width setting %d\r\n", width );
pabloamr	0:8d55f1f49a33	447	return;
pabloamr	0:8d55f1f49a33	448
pabloamr	0:8d55f1f49a33	449	}
pabloamr	0:8d55f1f49a33	450
pabloamr	0:8d55f1f49a33	451	setRegister(_NRF24L01P_REG_CONFIG, config);
pabloamr	0:8d55f1f49a33	452
pabloamr	0:8d55f1f49a33	453	}
pabloamr	0:8d55f1f49a33	454
pabloamr	0:8d55f1f49a33	455
pabloamr	0:8d55f1f49a33	456	int nRF24L01P::getCrcWidth(void) {
pabloamr	0:8d55f1f49a33	457
pabloamr	0:8d55f1f49a33	458	int crcWidth = getRegister(_NRF24L01P_REG_CONFIG) & _NRF24L01P_CONFIG_CRC_MASK;
pabloamr	0:8d55f1f49a33	459
pabloamr	0:8d55f1f49a33	460	switch ( crcWidth ) {
pabloamr	0:8d55f1f49a33	461
pabloamr	0:8d55f1f49a33	462	case _NRF24L01P_CONFIG_CRC_NONE:
pabloamr	0:8d55f1f49a33	463	return NRF24L01P_CRC_NONE;
pabloamr	0:8d55f1f49a33	464
pabloamr	0:8d55f1f49a33	465	case _NRF24L01P_CONFIG_CRC_8BIT:
pabloamr	0:8d55f1f49a33	466	return NRF24L01P_CRC_8_BIT;
pabloamr	0:8d55f1f49a33	467
pabloamr	0:8d55f1f49a33	468	case _NRF24L01P_CONFIG_CRC_16BIT:
pabloamr	0:8d55f1f49a33	469	return NRF24L01P_CRC_16_BIT;
pabloamr	0:8d55f1f49a33	470
pabloamr	0:8d55f1f49a33	471	default:
pabloamr	0:8d55f1f49a33	472	error( "nRF24L01P: Unknown CRC Width value %d\r\n", crcWidth );
pabloamr	0:8d55f1f49a33	473	return 0;
pabloamr	0:8d55f1f49a33	474
pabloamr	0:8d55f1f49a33	475	}
pabloamr	0:8d55f1f49a33	476	}
pabloamr	0:8d55f1f49a33	477
pabloamr	0:8d55f1f49a33	478
pabloamr	0:8d55f1f49a33	479	void nRF24L01P::setTransferSize(int size, int pipe) {
pabloamr	0:8d55f1f49a33	480
pabloamr	0:8d55f1f49a33	481	if ( ( pipe < NRF24L01P_PIPE_P0 ) \|\| ( pipe > NRF24L01P_PIPE_P5 ) ) {
pabloamr	0:8d55f1f49a33	482
pabloamr	0:8d55f1f49a33	483	error( "nRF24L01P: Invalid Transfer Size pipe number %d\r\n", pipe );
pabloamr	0:8d55f1f49a33	484	return;
pabloamr	0:8d55f1f49a33	485
pabloamr	0:8d55f1f49a33	486	}
pabloamr	0:8d55f1f49a33	487
pabloamr	0:8d55f1f49a33	488	if ( ( size < 0 ) \|\| ( size > _NRF24L01P_RX_FIFO_SIZE ) ) {
pabloamr	0:8d55f1f49a33	489
pabloamr	0:8d55f1f49a33	490	error( "nRF24L01P: Invalid Transfer Size setting %d\r\n", size );
pabloamr	0:8d55f1f49a33	491	return;
pabloamr	0:8d55f1f49a33	492
pabloamr	0:8d55f1f49a33	493	}
pabloamr	0:8d55f1f49a33	494
pabloamr	0:8d55f1f49a33	495	int rxPwPxRegister = _NRF24L01P_REG_RX_PW_P0 + ( pipe - NRF24L01P_PIPE_P0 );
pabloamr	0:8d55f1f49a33	496
pabloamr	0:8d55f1f49a33	497	setRegister(rxPwPxRegister, ( size & _NRF24L01P_RX_PW_Px_MASK ) );
pabloamr	0:8d55f1f49a33	498
pabloamr	0:8d55f1f49a33	499	}
pabloamr	0:8d55f1f49a33	500
pabloamr	0:8d55f1f49a33	501
pabloamr	0:8d55f1f49a33	502	int nRF24L01P::getTransferSize(int pipe) {
pabloamr	0:8d55f1f49a33	503
pabloamr	0:8d55f1f49a33	504	if ( ( pipe < NRF24L01P_PIPE_P0 ) \|\| ( pipe > NRF24L01P_PIPE_P5 ) ) {
pabloamr	0:8d55f1f49a33	505
pabloamr	0:8d55f1f49a33	506	error( "nRF24L01P: Invalid Transfer Size pipe number %d\r\n", pipe );
pabloamr	0:8d55f1f49a33	507	return 0;
pabloamr	0:8d55f1f49a33	508
pabloamr	0:8d55f1f49a33	509	}
pabloamr	0:8d55f1f49a33	510
pabloamr	0:8d55f1f49a33	511	int rxPwPxRegister = _NRF24L01P_REG_RX_PW_P0 + ( pipe - NRF24L01P_PIPE_P0 );
pabloamr	0:8d55f1f49a33	512
pabloamr	0:8d55f1f49a33	513	int size = getRegister(rxPwPxRegister);
pabloamr	0:8d55f1f49a33	514
pabloamr	0:8d55f1f49a33	515	return ( size & _NRF24L01P_RX_PW_Px_MASK );
pabloamr	0:8d55f1f49a33	516
pabloamr	0:8d55f1f49a33	517	}
pabloamr	0:8d55f1f49a33	518
pabloamr	0:8d55f1f49a33	519
pabloamr	0:8d55f1f49a33	520	void nRF24L01P::disableAllRxPipes(void) {
pabloamr	0:8d55f1f49a33	521
pabloamr	0:8d55f1f49a33	522	setRegister(_NRF24L01P_REG_EN_RXADDR, _NRF24L01P_EN_RXADDR_NONE);
pabloamr	0:8d55f1f49a33	523
pabloamr	0:8d55f1f49a33	524	}
pabloamr	0:8d55f1f49a33	525
pabloamr	0:8d55f1f49a33	526
pabloamr	0:8d55f1f49a33	527	void nRF24L01P::disableAutoAcknowledge(void) {
pabloamr	0:8d55f1f49a33	528
pabloamr	0:8d55f1f49a33	529	setRegister(_NRF24L01P_REG_EN_AA, _NRF24L01P_EN_AA_NONE);
pabloamr	0:8d55f1f49a33	530
pabloamr	0:8d55f1f49a33	531	}
pabloamr	0:8d55f1f49a33	532
pabloamr	0:8d55f1f49a33	533
pabloamr	0:8d55f1f49a33	534	void nRF24L01P::enableAutoAcknowledge(int pipe) {
pabloamr	0:8d55f1f49a33	535
pabloamr	0:8d55f1f49a33	536	if ( ( pipe < NRF24L01P_PIPE_P0 ) \|\| ( pipe > NRF24L01P_PIPE_P5 ) ) {
pabloamr	0:8d55f1f49a33	537
pabloamr	0:8d55f1f49a33	538	error( "nRF24L01P: Invalid Enable AutoAcknowledge pipe number %d\r\n", pipe );
pabloamr	0:8d55f1f49a33	539	return;
pabloamr	0:8d55f1f49a33	540
pabloamr	0:8d55f1f49a33	541	}
pabloamr	0:8d55f1f49a33	542
pabloamr	0:8d55f1f49a33	543	int enAA = getRegister(_NRF24L01P_REG_EN_AA);
pabloamr	0:8d55f1f49a33	544
pabloamr	0:8d55f1f49a33	545	enAA \|= ( 1 << (pipe - NRF24L01P_PIPE_P0) );
pabloamr	0:8d55f1f49a33	546
pabloamr	0:8d55f1f49a33	547	setRegister(_NRF24L01P_REG_EN_AA, enAA);
pabloamr	0:8d55f1f49a33	548
pabloamr	0:8d55f1f49a33	549	}
pabloamr	0:8d55f1f49a33	550
pabloamr	0:8d55f1f49a33	551
pabloamr	0:8d55f1f49a33	552	void nRF24L01P::disableAutoRetransmit(void) {
pabloamr	0:8d55f1f49a33	553
pabloamr	0:8d55f1f49a33	554	setRegister(_NRF24L01P_REG_SETUP_RETR, _NRF24L01P_SETUP_RETR_NONE);
pabloamr	0:8d55f1f49a33	555
pabloamr	0:8d55f1f49a33	556	}
pabloamr	0:8d55f1f49a33	557
pabloamr	0:8d55f1f49a33	558	void nRF24L01P::setRxAddress(unsigned long long address, int width, int pipe) {
pabloamr	0:8d55f1f49a33	559
pabloamr	0:8d55f1f49a33	560	if ( ( pipe < NRF24L01P_PIPE_P0 ) \|\| ( pipe > NRF24L01P_PIPE_P5 ) ) {
pabloamr	0:8d55f1f49a33	561
pabloamr	0:8d55f1f49a33	562	error( "nRF24L01P: Invalid setRxAddress pipe number %d\r\n", pipe );
pabloamr	0:8d55f1f49a33	563	return;
pabloamr	0:8d55f1f49a33	564
pabloamr	0:8d55f1f49a33	565	}
pabloamr	0:8d55f1f49a33	566
pabloamr	0:8d55f1f49a33	567	if ( ( pipe == NRF24L01P_PIPE_P0 ) \|\| ( pipe == NRF24L01P_PIPE_P1 ) ) {
pabloamr	0:8d55f1f49a33	568
pabloamr	0:8d55f1f49a33	569	int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & ~_NRF24L01P_SETUP_AW_AW_MASK;
pabloamr	0:8d55f1f49a33	570
pabloamr	0:8d55f1f49a33	571	switch ( width ) {
pabloamr	0:8d55f1f49a33	572
pabloamr	0:8d55f1f49a33	573	case 3:
pabloamr	0:8d55f1f49a33	574	setupAw \|= _NRF24L01P_SETUP_AW_AW_3BYTE;
pabloamr	0:8d55f1f49a33	575	break;
pabloamr	0:8d55f1f49a33	576
pabloamr	0:8d55f1f49a33	577	case 4:
pabloamr	0:8d55f1f49a33	578	setupAw \|= _NRF24L01P_SETUP_AW_AW_4BYTE;
pabloamr	0:8d55f1f49a33	579	break;
pabloamr	0:8d55f1f49a33	580
pabloamr	0:8d55f1f49a33	581	case 5:
pabloamr	0:8d55f1f49a33	582	setupAw \|= _NRF24L01P_SETUP_AW_AW_5BYTE;
pabloamr	0:8d55f1f49a33	583	break;
pabloamr	0:8d55f1f49a33	584
pabloamr	0:8d55f1f49a33	585	default:
pabloamr	0:8d55f1f49a33	586	error( "nRF24L01P: Invalid setRxAddress width setting %d\r\n", width );
pabloamr	0:8d55f1f49a33	587	return;
pabloamr	0:8d55f1f49a33	588
pabloamr	0:8d55f1f49a33	589	}
pabloamr	0:8d55f1f49a33	590
pabloamr	0:8d55f1f49a33	591	setRegister(_NRF24L01P_REG_SETUP_AW, setupAw);
pabloamr	0:8d55f1f49a33	592
pabloamr	0:8d55f1f49a33	593	} else {
pabloamr	0:8d55f1f49a33	594
pabloamr	0:8d55f1f49a33	595	width = 1;
pabloamr	0:8d55f1f49a33	596
pabloamr	0:8d55f1f49a33	597	}
pabloamr	0:8d55f1f49a33	598
pabloamr	0:8d55f1f49a33	599	int rxAddrPxRegister = _NRF24L01P_REG_RX_ADDR_P0 + ( pipe - NRF24L01P_PIPE_P0 );
pabloamr	0:8d55f1f49a33	600
pabloamr	0:8d55f1f49a33	601	int cn = (_NRF24L01P_SPI_CMD_WR_REG \| (rxAddrPxRegister & _NRF24L01P_REG_ADDRESS_MASK));
pabloamr	0:8d55f1f49a33	602
pabloamr	0:8d55f1f49a33	603	nCS_ = 0;
pabloamr	0:8d55f1f49a33	604
pabloamr	0:8d55f1f49a33	605	int status = spi_.write(cn);
pabloamr	0:8d55f1f49a33	606
pabloamr	0:8d55f1f49a33	607	while ( width-- > 0 ) {
pabloamr	0:8d55f1f49a33	608
pabloamr	0:8d55f1f49a33	609	//
pabloamr	0:8d55f1f49a33	610	// LSByte first
pabloamr	0:8d55f1f49a33	611	//
pabloamr	0:8d55f1f49a33	612	spi_.write((int) (address & 0xFF));
pabloamr	0:8d55f1f49a33	613	address >>= 8;
pabloamr	0:8d55f1f49a33	614
pabloamr	0:8d55f1f49a33	615	}
pabloamr	0:8d55f1f49a33	616
pabloamr	0:8d55f1f49a33	617	nCS_ = 1;
pabloamr	0:8d55f1f49a33	618
pabloamr	0:8d55f1f49a33	619	int enRxAddr = getRegister(_NRF24L01P_REG_EN_RXADDR);
pabloamr	0:8d55f1f49a33	620
pabloamr	0:8d55f1f49a33	621	enRxAddr \|= (1 << ( pipe - NRF24L01P_PIPE_P0 ) );
pabloamr	0:8d55f1f49a33	622
pabloamr	0:8d55f1f49a33	623	setRegister(_NRF24L01P_REG_EN_RXADDR, enRxAddr);
pabloamr	0:8d55f1f49a33	624	}
pabloamr	0:8d55f1f49a33	625
pabloamr	0:8d55f1f49a33	626	/*
pabloamr	0:8d55f1f49a33	627	* This version of setRxAddress is just a wrapper for the version that takes 'long long's,
pabloamr	0:8d55f1f49a33	628	* in case the main code doesn't want to deal with long long's.
pabloamr	0:8d55f1f49a33	629	*/
pabloamr	0:8d55f1f49a33	630	void nRF24L01P::setRxAddress(unsigned long msb_address, unsigned long lsb_address, int width, int pipe) {
pabloamr	0:8d55f1f49a33	631
pabloamr	0:8d55f1f49a33	632	unsigned long long address = ( ( (unsigned long long) msb_address ) << 32 ) \| ( ( (unsigned long long) lsb_address ) << 0 );
pabloamr	0:8d55f1f49a33	633
pabloamr	0:8d55f1f49a33	634	setRxAddress(address, width, pipe);
pabloamr	0:8d55f1f49a33	635
pabloamr	0:8d55f1f49a33	636	}
pabloamr	0:8d55f1f49a33	637
pabloamr	0:8d55f1f49a33	638
pabloamr	0:8d55f1f49a33	639	/*
pabloamr	0:8d55f1f49a33	640	* This version of setTxAddress is just a wrapper for the version that takes 'long long's,
pabloamr	0:8d55f1f49a33	641	* in case the main code doesn't want to deal with long long's.
pabloamr	0:8d55f1f49a33	642	*/
pabloamr	0:8d55f1f49a33	643	void nRF24L01P::setTxAddress(unsigned long msb_address, unsigned long lsb_address, int width) {
pabloamr	0:8d55f1f49a33	644
pabloamr	0:8d55f1f49a33	645	unsigned long long address = ( ( (unsigned long long) msb_address ) << 32 ) \| ( ( (unsigned long long) lsb_address ) << 0 );
pabloamr	0:8d55f1f49a33	646
pabloamr	0:8d55f1f49a33	647	setTxAddress(address, width);
pabloamr	0:8d55f1f49a33	648
pabloamr	0:8d55f1f49a33	649	}
pabloamr	0:8d55f1f49a33	650
pabloamr	0:8d55f1f49a33	651
pabloamr	0:8d55f1f49a33	652	void nRF24L01P::setTxAddress(unsigned long long address, int width) {
pabloamr	0:8d55f1f49a33	653
pabloamr	0:8d55f1f49a33	654	int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & ~_NRF24L01P_SETUP_AW_AW_MASK;
pabloamr	0:8d55f1f49a33	655
pabloamr	0:8d55f1f49a33	656	switch ( width ) {
pabloamr	0:8d55f1f49a33	657
pabloamr	0:8d55f1f49a33	658	case 3:
pabloamr	0:8d55f1f49a33	659	setupAw \|= _NRF24L01P_SETUP_AW_AW_3BYTE;
pabloamr	0:8d55f1f49a33	660	break;
pabloamr	0:8d55f1f49a33	661
pabloamr	0:8d55f1f49a33	662	case 4:
pabloamr	0:8d55f1f49a33	663	setupAw \|= _NRF24L01P_SETUP_AW_AW_4BYTE;
pabloamr	0:8d55f1f49a33	664	break;
pabloamr	0:8d55f1f49a33	665
pabloamr	0:8d55f1f49a33	666	case 5:
pabloamr	0:8d55f1f49a33	667	setupAw \|= _NRF24L01P_SETUP_AW_AW_5BYTE;
pabloamr	0:8d55f1f49a33	668	break;
pabloamr	0:8d55f1f49a33	669
pabloamr	0:8d55f1f49a33	670	default:
pabloamr	0:8d55f1f49a33	671	error( "nRF24L01P: Invalid setTxAddress width setting %d\r\n", width );
pabloamr	0:8d55f1f49a33	672	return;
pabloamr	0:8d55f1f49a33	673
pabloamr	0:8d55f1f49a33	674	}
pabloamr	0:8d55f1f49a33	675
pabloamr	0:8d55f1f49a33	676	setRegister(_NRF24L01P_REG_SETUP_AW, setupAw);
pabloamr	0:8d55f1f49a33	677
pabloamr	0:8d55f1f49a33	678	int cn = (_NRF24L01P_SPI_CMD_WR_REG \| (_NRF24L01P_REG_TX_ADDR & _NRF24L01P_REG_ADDRESS_MASK));
pabloamr	0:8d55f1f49a33	679
pabloamr	0:8d55f1f49a33	680	nCS_ = 0;
pabloamr	0:8d55f1f49a33	681
pabloamr	0:8d55f1f49a33	682	int status = spi_.write(cn);
pabloamr	0:8d55f1f49a33	683
pabloamr	0:8d55f1f49a33	684	while ( width-- > 0 ) {
pabloamr	0:8d55f1f49a33	685
pabloamr	0:8d55f1f49a33	686	//
pabloamr	0:8d55f1f49a33	687	// LSByte first
pabloamr	0:8d55f1f49a33	688	//
pabloamr	0:8d55f1f49a33	689	spi_.write((int) (address & 0xFF));
pabloamr	0:8d55f1f49a33	690	address >>= 8;
pabloamr	0:8d55f1f49a33	691
pabloamr	0:8d55f1f49a33	692	}
pabloamr	0:8d55f1f49a33	693
pabloamr	0:8d55f1f49a33	694	nCS_ = 1;
pabloamr	0:8d55f1f49a33	695
pabloamr	0:8d55f1f49a33	696	}
pabloamr	0:8d55f1f49a33	697
pabloamr	0:8d55f1f49a33	698
pabloamr	0:8d55f1f49a33	699	unsigned long long nRF24L01P::getRxAddress(int pipe) {
pabloamr	0:8d55f1f49a33	700
pabloamr	0:8d55f1f49a33	701	if ( ( pipe < NRF24L01P_PIPE_P0 ) \|\| ( pipe > NRF24L01P_PIPE_P5 ) ) {
pabloamr	0:8d55f1f49a33	702
pabloamr	0:8d55f1f49a33	703	error( "nRF24L01P: Invalid setRxAddress pipe number %d\r\n", pipe );
pabloamr	0:8d55f1f49a33	704	return 0;
pabloamr	0:8d55f1f49a33	705
pabloamr	0:8d55f1f49a33	706	}
pabloamr	0:8d55f1f49a33	707
pabloamr	0:8d55f1f49a33	708	int width;
pabloamr	0:8d55f1f49a33	709
pabloamr	0:8d55f1f49a33	710	if ( ( pipe == NRF24L01P_PIPE_P0 ) \|\| ( pipe == NRF24L01P_PIPE_P1 ) ) {
pabloamr	0:8d55f1f49a33	711
pabloamr	0:8d55f1f49a33	712	int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & _NRF24L01P_SETUP_AW_AW_MASK;
pabloamr	0:8d55f1f49a33	713
pabloamr	0:8d55f1f49a33	714	switch ( setupAw ) {
pabloamr	0:8d55f1f49a33	715
pabloamr	0:8d55f1f49a33	716	case _NRF24L01P_SETUP_AW_AW_3BYTE:
pabloamr	0:8d55f1f49a33	717	width = 3;
pabloamr	0:8d55f1f49a33	718	break;
pabloamr	0:8d55f1f49a33	719
pabloamr	0:8d55f1f49a33	720	case _NRF24L01P_SETUP_AW_AW_4BYTE:
pabloamr	0:8d55f1f49a33	721	width = 4;
pabloamr	0:8d55f1f49a33	722	break;
pabloamr	0:8d55f1f49a33	723
pabloamr	0:8d55f1f49a33	724	case _NRF24L01P_SETUP_AW_AW_5BYTE:
pabloamr	0:8d55f1f49a33	725	width = 5;
pabloamr	0:8d55f1f49a33	726	break;
pabloamr	0:8d55f1f49a33	727
pabloamr	0:8d55f1f49a33	728	default:
pabloamr	0:8d55f1f49a33	729	error( "nRF24L01P: Unknown getRxAddress width value %d\r\n", setupAw );
pabloamr	0:8d55f1f49a33	730	return 0;
pabloamr	0:8d55f1f49a33	731
pabloamr	0:8d55f1f49a33	732	}
pabloamr	0:8d55f1f49a33	733
pabloamr	0:8d55f1f49a33	734	} else {
pabloamr	0:8d55f1f49a33	735
pabloamr	0:8d55f1f49a33	736	width = 1;
pabloamr	0:8d55f1f49a33	737
pabloamr	0:8d55f1f49a33	738	}
pabloamr	0:8d55f1f49a33	739
pabloamr	0:8d55f1f49a33	740	int rxAddrPxRegister = _NRF24L01P_REG_RX_ADDR_P0 + ( pipe - NRF24L01P_PIPE_P0 );
pabloamr	0:8d55f1f49a33	741
pabloamr	0:8d55f1f49a33	742	int cn = (_NRF24L01P_SPI_CMD_RD_REG \| (rxAddrPxRegister & _NRF24L01P_REG_ADDRESS_MASK));
pabloamr	0:8d55f1f49a33	743
pabloamr	0:8d55f1f49a33	744	unsigned long long address = 0;
pabloamr	0:8d55f1f49a33	745
pabloamr	0:8d55f1f49a33	746	nCS_ = 0;
pabloamr	0:8d55f1f49a33	747
pabloamr	0:8d55f1f49a33	748	int status = spi_.write(cn);
pabloamr	0:8d55f1f49a33	749
pabloamr	0:8d55f1f49a33	750	for ( int i=0; i<width; i++ ) {
pabloamr	0:8d55f1f49a33	751
pabloamr	0:8d55f1f49a33	752	//
pabloamr	0:8d55f1f49a33	753	// LSByte first
pabloamr	0:8d55f1f49a33	754	//
pabloamr	0:8d55f1f49a33	755	address \|= ( ( (unsigned long long)( spi_.write(_NRF24L01P_SPI_CMD_NOP) & 0xFF ) ) << (i*8) );
pabloamr	0:8d55f1f49a33	756
pabloamr	0:8d55f1f49a33	757	}
pabloamr	0:8d55f1f49a33	758
pabloamr	0:8d55f1f49a33	759	nCS_ = 1;
pabloamr	0:8d55f1f49a33	760
pabloamr	0:8d55f1f49a33	761	if ( !( ( pipe == NRF24L01P_PIPE_P0 ) \|\| ( pipe == NRF24L01P_PIPE_P1 ) ) ) {
pabloamr	0:8d55f1f49a33	762
pabloamr	0:8d55f1f49a33	763	address \|= ( getRxAddress(NRF24L01P_PIPE_P1) & ~((unsigned long long) 0xFF) );
pabloamr	0:8d55f1f49a33	764
pabloamr	0:8d55f1f49a33	765	}
pabloamr	0:8d55f1f49a33	766
pabloamr	0:8d55f1f49a33	767	return address;
pabloamr	0:8d55f1f49a33	768
pabloamr	0:8d55f1f49a33	769	}
pabloamr	0:8d55f1f49a33	770
pabloamr	0:8d55f1f49a33	771
pabloamr	0:8d55f1f49a33	772	unsigned long long nRF24L01P::getTxAddress(void) {
pabloamr	0:8d55f1f49a33	773
pabloamr	0:8d55f1f49a33	774	int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & _NRF24L01P_SETUP_AW_AW_MASK;
pabloamr	0:8d55f1f49a33	775
pabloamr	0:8d55f1f49a33	776	int width;
pabloamr	0:8d55f1f49a33	777
pabloamr	0:8d55f1f49a33	778	switch ( setupAw ) {
pabloamr	0:8d55f1f49a33	779
pabloamr	0:8d55f1f49a33	780	case _NRF24L01P_SETUP_AW_AW_3BYTE:
pabloamr	0:8d55f1f49a33	781	width = 3;
pabloamr	0:8d55f1f49a33	782	break;
pabloamr	0:8d55f1f49a33	783
pabloamr	0:8d55f1f49a33	784	case _NRF24L01P_SETUP_AW_AW_4BYTE:
pabloamr	0:8d55f1f49a33	785	width = 4;
pabloamr	0:8d55f1f49a33	786	break;
pabloamr	0:8d55f1f49a33	787
pabloamr	0:8d55f1f49a33	788	case _NRF24L01P_SETUP_AW_AW_5BYTE:
pabloamr	0:8d55f1f49a33	789	width = 5;
pabloamr	0:8d55f1f49a33	790	break;
pabloamr	0:8d55f1f49a33	791
pabloamr	0:8d55f1f49a33	792	default:
pabloamr	0:8d55f1f49a33	793	error( "nRF24L01P: Unknown getTxAddress width value %d\r\n", setupAw );
pabloamr	0:8d55f1f49a33	794	return 0;
pabloamr	0:8d55f1f49a33	795
pabloamr	0:8d55f1f49a33	796	}
pabloamr	0:8d55f1f49a33	797
pabloamr	0:8d55f1f49a33	798	int cn = (_NRF24L01P_SPI_CMD_RD_REG \| (_NRF24L01P_REG_TX_ADDR & _NRF24L01P_REG_ADDRESS_MASK));
pabloamr	0:8d55f1f49a33	799
pabloamr	0:8d55f1f49a33	800	unsigned long long address = 0;
pabloamr	0:8d55f1f49a33	801
pabloamr	0:8d55f1f49a33	802	nCS_ = 0;
pabloamr	0:8d55f1f49a33	803
pabloamr	0:8d55f1f49a33	804	int status = spi_.write(cn);
pabloamr	0:8d55f1f49a33	805
pabloamr	0:8d55f1f49a33	806	for ( int i=0; i<width; i++ ) {
pabloamr	0:8d55f1f49a33	807
pabloamr	0:8d55f1f49a33	808	//
pabloamr	0:8d55f1f49a33	809	// LSByte first
pabloamr	0:8d55f1f49a33	810	//
pabloamr	0:8d55f1f49a33	811	address \|= ( ( (unsigned long long)( spi_.write(_NRF24L01P_SPI_CMD_NOP) & 0xFF ) ) << (i*8) );
pabloamr	0:8d55f1f49a33	812
pabloamr	0:8d55f1f49a33	813	}
pabloamr	0:8d55f1f49a33	814
pabloamr	0:8d55f1f49a33	815	nCS_ = 1;
pabloamr	0:8d55f1f49a33	816
pabloamr	0:8d55f1f49a33	817	return address;
pabloamr	0:8d55f1f49a33	818	}
pabloamr	0:8d55f1f49a33	819
pabloamr	0:8d55f1f49a33	820
pabloamr	0:8d55f1f49a33	821	bool nRF24L01P::readable(int pipe) {
pabloamr	0:8d55f1f49a33	822
pabloamr	0:8d55f1f49a33	823	if ( ( pipe < NRF24L01P_PIPE_P0 ) \|\| ( pipe > NRF24L01P_PIPE_P5 ) ) {
pabloamr	0:8d55f1f49a33	824
pabloamr	0:8d55f1f49a33	825	error( "nRF24L01P: Invalid readable pipe number %d\r\n", pipe );
pabloamr	0:8d55f1f49a33	826	return false;
pabloamr	0:8d55f1f49a33	827
pabloamr	0:8d55f1f49a33	828	}
pabloamr	0:8d55f1f49a33	829
pabloamr	0:8d55f1f49a33	830	int status = getStatusRegister();
pabloamr	0:8d55f1f49a33	831
pabloamr	0:8d55f1f49a33	832	return ( ( status & _NRF24L01P_STATUS_RX_DR ) && ( ( ( status & _NRF24L01P_STATUS_RX_P_NO ) >> 1 ) == ( pipe & 0x7 ) ) );
pabloamr	0:8d55f1f49a33	833
pabloamr	0:8d55f1f49a33	834	}
pabloamr	0:8d55f1f49a33	835
pabloamr	0:8d55f1f49a33	836
pabloamr	0:8d55f1f49a33	837	int nRF24L01P::write(int pipe, char *data, int count) {
pabloamr	0:8d55f1f49a33	838
pabloamr	0:8d55f1f49a33	839	// Note: the pipe number is ignored in a Transmit / write
pabloamr	0:8d55f1f49a33	840
pabloamr	0:8d55f1f49a33	841	//
pabloamr	0:8d55f1f49a33	842	// Save the CE state
pabloamr	0:8d55f1f49a33	843	//
pabloamr	0:8d55f1f49a33	844	int originalCe = ce_;
pabloamr	0:8d55f1f49a33	845	disable();
pabloamr	0:8d55f1f49a33	846
pabloamr	0:8d55f1f49a33	847	if ( count <= 0 ) return 0;
pabloamr	0:8d55f1f49a33	848
pabloamr	0:8d55f1f49a33	849	if ( count > _NRF24L01P_TX_FIFO_SIZE ) count = _NRF24L01P_TX_FIFO_SIZE;
pabloamr	0:8d55f1f49a33	850
pabloamr	0:8d55f1f49a33	851	// Clear the Status bit
pabloamr	0:8d55f1f49a33	852	setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_TX_DS);
pabloamr	0:8d55f1f49a33	853
pabloamr	0:8d55f1f49a33	854	nCS_ = 0;
pabloamr	0:8d55f1f49a33	855
pabloamr	0:8d55f1f49a33	856	int status = spi_.write(_NRF24L01P_SPI_CMD_WR_TX_PAYLOAD);
pabloamr	0:8d55f1f49a33	857
pabloamr	0:8d55f1f49a33	858	for ( int i = 0; i < count; i++ ) {
pabloamr	0:8d55f1f49a33	859
pabloamr	0:8d55f1f49a33	860	spi_.write(*data++);
pabloamr	0:8d55f1f49a33	861
pabloamr	0:8d55f1f49a33	862	}
pabloamr	0:8d55f1f49a33	863
pabloamr	0:8d55f1f49a33	864	nCS_ = 1;
pabloamr	0:8d55f1f49a33	865
pabloamr	0:8d55f1f49a33	866	int originalMode = mode;
pabloamr	0:8d55f1f49a33	867	setTransmitMode();
pabloamr	0:8d55f1f49a33	868
pabloamr	0:8d55f1f49a33	869	enable();
pabloamr	0:8d55f1f49a33	870	wait_us(_NRF24L01P_TIMING_Thce_us);
pabloamr	0:8d55f1f49a33	871	disable();
pabloamr	0:8d55f1f49a33	872
pabloamr	0:8d55f1f49a33	873	while ( !( getStatusRegister() & _NRF24L01P_STATUS_TX_DS ) ) {
pabloamr	0:8d55f1f49a33	874
pabloamr	0:8d55f1f49a33	875	// Wait for the transfer to complete
pabloamr	0:8d55f1f49a33	876
pabloamr	0:8d55f1f49a33	877	}
pabloamr	0:8d55f1f49a33	878
pabloamr	0:8d55f1f49a33	879	// Clear the Status bit
pabloamr	0:8d55f1f49a33	880	setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_TX_DS);
pabloamr	0:8d55f1f49a33	881
pabloamr	0:8d55f1f49a33	882	if ( originalMode == _NRF24L01P_MODE_RX ) {
pabloamr	0:8d55f1f49a33	883
pabloamr	0:8d55f1f49a33	884	setReceiveMode();
pabloamr	0:8d55f1f49a33	885
pabloamr	0:8d55f1f49a33	886	}
pabloamr	0:8d55f1f49a33	887
pabloamr	0:8d55f1f49a33	888	ce_ = originalCe;
pabloamr	0:8d55f1f49a33	889	wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
pabloamr	0:8d55f1f49a33	890
pabloamr	0:8d55f1f49a33	891	return count;
pabloamr	0:8d55f1f49a33	892
pabloamr	0:8d55f1f49a33	893	}
pabloamr	0:8d55f1f49a33	894
pabloamr	0:8d55f1f49a33	895
pabloamr	0:8d55f1f49a33	896	int nRF24L01P::read(int pipe, char *data, int count) {
pabloamr	0:8d55f1f49a33	897
pabloamr	0:8d55f1f49a33	898	if ( ( pipe < NRF24L01P_PIPE_P0 ) \|\| ( pipe > NRF24L01P_PIPE_P5 ) ) {
pabloamr	0:8d55f1f49a33	899
pabloamr	0:8d55f1f49a33	900	error( "nRF24L01P: Invalid read pipe number %d\r\n", pipe );
pabloamr	0:8d55f1f49a33	901	return -1;
pabloamr	0:8d55f1f49a33	902
pabloamr	0:8d55f1f49a33	903	}
pabloamr	0:8d55f1f49a33	904
pabloamr	0:8d55f1f49a33	905	if ( count <= 0 ) return 0;
pabloamr	0:8d55f1f49a33	906
pabloamr	0:8d55f1f49a33	907	if ( count > _NRF24L01P_RX_FIFO_SIZE ) count = _NRF24L01P_RX_FIFO_SIZE;
pabloamr	0:8d55f1f49a33	908
pabloamr	0:8d55f1f49a33	909	if ( readable(pipe) ) {
pabloamr	0:8d55f1f49a33	910
pabloamr	0:8d55f1f49a33	911	nCS_ = 0;
pabloamr	0:8d55f1f49a33	912
pabloamr	0:8d55f1f49a33	913	int status = spi_.write(_NRF24L01P_SPI_CMD_R_RX_PL_WID);
pabloamr	0:8d55f1f49a33	914
pabloamr	0:8d55f1f49a33	915	int rxPayloadWidth = spi_.write(_NRF24L01P_SPI_CMD_NOP);
pabloamr	0:8d55f1f49a33	916
pabloamr	0:8d55f1f49a33	917	nCS_ = 1;
pabloamr	0:8d55f1f49a33	918
pabloamr	0:8d55f1f49a33	919	if ( ( rxPayloadWidth < 0 ) \|\| ( rxPayloadWidth > _NRF24L01P_RX_FIFO_SIZE ) ) {
pabloamr	0:8d55f1f49a33	920
pabloamr	0:8d55f1f49a33	921	// Received payload error: need to flush the FIFO
pabloamr	0:8d55f1f49a33	922
pabloamr	0:8d55f1f49a33	923	nCS_ = 0;
pabloamr	0:8d55f1f49a33	924
pabloamr	0:8d55f1f49a33	925	int status = spi_.write(_NRF24L01P_SPI_CMD_FLUSH_RX);
pabloamr	0:8d55f1f49a33	926
pabloamr	0:8d55f1f49a33	927	int rxPayloadWidth = spi_.write(_NRF24L01P_SPI_CMD_NOP);
pabloamr	0:8d55f1f49a33	928
pabloamr	0:8d55f1f49a33	929	nCS_ = 1;
pabloamr	0:8d55f1f49a33	930
pabloamr	0:8d55f1f49a33	931	//
pabloamr	0:8d55f1f49a33	932	// At this point, we should retry the reception,
pabloamr	0:8d55f1f49a33	933	// but for now we'll just fall through...
pabloamr	0:8d55f1f49a33	934	//
pabloamr	0:8d55f1f49a33	935
pabloamr	0:8d55f1f49a33	936	} else {
pabloamr	0:8d55f1f49a33	937
pabloamr	0:8d55f1f49a33	938	if ( rxPayloadWidth < count ) count = rxPayloadWidth;
pabloamr	0:8d55f1f49a33	939
pabloamr	0:8d55f1f49a33	940	nCS_ = 0;
pabloamr	0:8d55f1f49a33	941
pabloamr	0:8d55f1f49a33	942	int status = spi_.write(_NRF24L01P_SPI_CMD_RD_RX_PAYLOAD);
pabloamr	0:8d55f1f49a33	943
pabloamr	0:8d55f1f49a33	944	for ( int i = 0; i < count; i++ ) {
pabloamr	0:8d55f1f49a33	945
pabloamr	0:8d55f1f49a33	946	*data++ = spi_.write(_NRF24L01P_SPI_CMD_NOP);
pabloamr	0:8d55f1f49a33	947
pabloamr	0:8d55f1f49a33	948	}
pabloamr	0:8d55f1f49a33	949
pabloamr	0:8d55f1f49a33	950	nCS_ = 1;
pabloamr	0:8d55f1f49a33	951
pabloamr	0:8d55f1f49a33	952	// Clear the Status bit
pabloamr	0:8d55f1f49a33	953	setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_RX_DR);
pabloamr	0:8d55f1f49a33	954
pabloamr	0:8d55f1f49a33	955	return count;
pabloamr	0:8d55f1f49a33	956
pabloamr	0:8d55f1f49a33	957	}
pabloamr	0:8d55f1f49a33	958
pabloamr	0:8d55f1f49a33	959	} else {
pabloamr	0:8d55f1f49a33	960
pabloamr	0:8d55f1f49a33	961	//
pabloamr	0:8d55f1f49a33	962	// What should we do if there is no 'readable' data?
pabloamr	0:8d55f1f49a33	963	// We could wait for data to arrive, but for now, we'll
pabloamr	0:8d55f1f49a33	964	// just return with no data.
pabloamr	0:8d55f1f49a33	965	//
pabloamr	0:8d55f1f49a33	966	return 0;
pabloamr	0:8d55f1f49a33	967
pabloamr	0:8d55f1f49a33	968	}
pabloamr	0:8d55f1f49a33	969
pabloamr	0:8d55f1f49a33	970	//
pabloamr	0:8d55f1f49a33	971	// We get here because an error condition occured;
pabloamr	0:8d55f1f49a33	972	// We could wait for data to arrive, but for now, we'll
pabloamr	0:8d55f1f49a33	973	// just return with no data.
pabloamr	0:8d55f1f49a33	974	//
pabloamr	0:8d55f1f49a33	975	return -1;
pabloamr	0:8d55f1f49a33	976
pabloamr	0:8d55f1f49a33	977	}
pabloamr	0:8d55f1f49a33	978
pabloamr	0:8d55f1f49a33	979	void nRF24L01P::setRegister(int regAddress, int regData) {
pabloamr	0:8d55f1f49a33	980
pabloamr	0:8d55f1f49a33	981	//
pabloamr	0:8d55f1f49a33	982	// Save the CE state
pabloamr	0:8d55f1f49a33	983	//
pabloamr	0:8d55f1f49a33	984	int originalCe = ce_;
pabloamr	0:8d55f1f49a33	985	disable();
pabloamr	0:8d55f1f49a33	986
pabloamr	0:8d55f1f49a33	987	int cn = (_NRF24L01P_SPI_CMD_WR_REG \| (regAddress & _NRF24L01P_REG_ADDRESS_MASK));
pabloamr	0:8d55f1f49a33	988
pabloamr	0:8d55f1f49a33	989	nCS_ = 0;
pabloamr	0:8d55f1f49a33	990
pabloamr	0:8d55f1f49a33	991	int status = spi_.write(cn);
pabloamr	0:8d55f1f49a33	992
pabloamr	0:8d55f1f49a33	993	spi_.write(regData & 0xFF);
pabloamr	0:8d55f1f49a33	994
pabloamr	0:8d55f1f49a33	995	nCS_ = 1;
pabloamr	0:8d55f1f49a33	996
pabloamr	0:8d55f1f49a33	997	ce_ = originalCe;
pabloamr	0:8d55f1f49a33	998	wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
pabloamr	0:8d55f1f49a33	999
pabloamr	0:8d55f1f49a33	1000	}
pabloamr	0:8d55f1f49a33	1001
pabloamr	0:8d55f1f49a33	1002
pabloamr	0:8d55f1f49a33	1003	int nRF24L01P::getRegister(int regAddress) {
pabloamr	0:8d55f1f49a33	1004
pabloamr	0:8d55f1f49a33	1005	int cn = (_NRF24L01P_SPI_CMD_RD_REG \| (regAddress & _NRF24L01P_REG_ADDRESS_MASK));
pabloamr	0:8d55f1f49a33	1006
pabloamr	0:8d55f1f49a33	1007	nCS_ = 0;
pabloamr	0:8d55f1f49a33	1008
pabloamr	0:8d55f1f49a33	1009	int status = spi_.write(cn);
pabloamr	0:8d55f1f49a33	1010
pabloamr	0:8d55f1f49a33	1011	int dn = spi_.write(_NRF24L01P_SPI_CMD_NOP);
pabloamr	0:8d55f1f49a33	1012
pabloamr	0:8d55f1f49a33	1013	nCS_ = 1;
pabloamr	0:8d55f1f49a33	1014
pabloamr	0:8d55f1f49a33	1015	return dn;
pabloamr	0:8d55f1f49a33	1016
pabloamr	0:8d55f1f49a33	1017	}
pabloamr	0:8d55f1f49a33	1018
pabloamr	0:8d55f1f49a33	1019	int nRF24L01P::getStatusRegister(void) {
pabloamr	0:8d55f1f49a33	1020
pabloamr	0:8d55f1f49a33	1021	nCS_ = 0;
pabloamr	0:8d55f1f49a33	1022
pabloamr	0:8d55f1f49a33	1023	int status = spi_.write(_NRF24L01P_SPI_CMD_NOP);
pabloamr	0:8d55f1f49a33	1024
pabloamr	0:8d55f1f49a33	1025	nCS_ = 1;
pabloamr	0:8d55f1f49a33	1026
pabloamr	0:8d55f1f49a33	1027	return status;
pabloamr	0:8d55f1f49a33	1028
pabloamr	0:8d55f1f49a33	1029	}

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Type:	Library
Created:	04 Jul 2016
Imports:	0
Forks:	0
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nRF24L01P.cpp@0:8d55f1f49a33, 2011-04-21 (annotated)

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