Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nand.c@124:6a4a5b7d7324, 2016-05-09 (annotated)

Committer:
mbed_official
Date:
Mon May 09 18:30:12 2016 +0100
Revision:
124:6a4a5b7d7324
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision ad75bdcde34d7da9d54b7669010c7fb968a99c7c



Full URL: https://github.com/mbedmicro/mbed/commit/ad75bdcde34d7da9d54b7669010c7fb968a99c7c/



[STMF1] Stm32f1_hal_cube update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f1xx_hal_nand.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 124:6a4a5b7d7324 5 * @version V1.0.4
mbed_official 124:6a4a5b7d7324 6 * @date 29-April-2016
bogdanm 0:9b334a45a8ff 7 * @brief NAND HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides a generic firmware to drive NAND memories mounted
bogdanm 0:9b334a45a8ff 9 * as external device.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 @verbatim
bogdanm 0:9b334a45a8ff 12 ==============================================================================
bogdanm 0:9b334a45a8ff 13 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 [..]
bogdanm 0:9b334a45a8ff 16 This driver is a generic layered driver which contains a set of APIs used to
bogdanm 0:9b334a45a8ff 17 control NAND flash memories. It uses the FSMC/FSMC layer functions to interface
bogdanm 0:9b334a45a8ff 18 with NAND devices. This driver is used as follows:
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
bogdanm 0:9b334a45a8ff 21 with control and timing parameters for both common and attribute spaces.
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 (+) Read NAND flash memory maker and device IDs using the function
bogdanm 0:9b334a45a8ff 24 HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
bogdanm 0:9b334a45a8ff 25 structure declared by the function caller.
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 (+) Access NAND flash memory by read/write operations using the functions
bogdanm 0:9b334a45a8ff 28 HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
bogdanm 0:9b334a45a8ff 29 to read/write page(s)/spare area(s). These functions use specific device
bogdanm 0:9b334a45a8ff 30 information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
bogdanm 0:9b334a45a8ff 31 structure. The read/write address information is contained by the Nand_Address_Typedef
bogdanm 0:9b334a45a8ff 32 structure passed as parameter.
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
bogdanm 0:9b334a45a8ff 35
bogdanm 0:9b334a45a8ff 36 (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
bogdanm 0:9b334a45a8ff 37 The erase block address information is contained in the Nand_Address_Typedef
bogdanm 0:9b334a45a8ff 38 structure passed as parameter.
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
bogdanm 0:9b334a45a8ff 43 HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
bogdanm 0:9b334a45a8ff 44 feature or the function HAL_NAND_GetECC() to get the ECC correction code.
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 (+) You can monitor the NAND device HAL state by calling the function
bogdanm 0:9b334a45a8ff 47 HAL_NAND_GetState()
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 [..]
bogdanm 0:9b334a45a8ff 50 (@) This driver is a set of generic APIs which handle standard NAND flash operations.
bogdanm 0:9b334a45a8ff 51 If a NAND flash device contains different operations and/or implementations,
bogdanm 0:9b334a45a8ff 52 it should be implemented separately.
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 @endverbatim
bogdanm 0:9b334a45a8ff 55 ******************************************************************************
bogdanm 0:9b334a45a8ff 56 * @attention
bogdanm 0:9b334a45a8ff 57 *
mbed_official 124:6a4a5b7d7324 58 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 59 *
bogdanm 0:9b334a45a8ff 60 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 61 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 62 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 63 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 65 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 66 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 68 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 69 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 70 *
bogdanm 0:9b334a45a8ff 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 81 *
bogdanm 0:9b334a45a8ff 82 ******************************************************************************
bogdanm 0:9b334a45a8ff 83 */
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 86 #include "stm32f1xx_hal.h"
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 /** @addtogroup STM32F1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 89 * @{
bogdanm 0:9b334a45a8ff 90 */
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 #ifdef HAL_NAND_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 /** @defgroup NAND NAND
bogdanm 0:9b334a45a8ff 97 * @brief NAND HAL module driver
bogdanm 0:9b334a45a8ff 98 * @{
bogdanm 0:9b334a45a8ff 99 */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 102 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 103 /** @defgroup NAND_Private_Constants NAND Private Constants
bogdanm 0:9b334a45a8ff 104 * @{
bogdanm 0:9b334a45a8ff 105 */
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 /**
bogdanm 0:9b334a45a8ff 108 * @}
bogdanm 0:9b334a45a8ff 109 */
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 112 /** @defgroup NAND_Private_Macros NAND Private Macros
bogdanm 0:9b334a45a8ff 113 * @{
bogdanm 0:9b334a45a8ff 114 */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 /**
bogdanm 0:9b334a45a8ff 117 * @}
bogdanm 0:9b334a45a8ff 118 */
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 121 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 122 /** @defgroup NAND_Private_Functions NAND Private Functions
bogdanm 0:9b334a45a8ff 123 * @{
bogdanm 0:9b334a45a8ff 124 */
bogdanm 0:9b334a45a8ff 125 static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address);
bogdanm 0:9b334a45a8ff 126 /**
bogdanm 0:9b334a45a8ff 127 * @}
bogdanm 0:9b334a45a8ff 128 */
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 /* Exported functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 /** @defgroup NAND_Exported_Functions NAND Exported Functions
bogdanm 0:9b334a45a8ff 133 * @{
bogdanm 0:9b334a45a8ff 134 */
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 137 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 138 *
bogdanm 0:9b334a45a8ff 139 @verbatim
bogdanm 0:9b334a45a8ff 140 ==============================================================================
bogdanm 0:9b334a45a8ff 141 ##### NAND Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 142 ==============================================================================
bogdanm 0:9b334a45a8ff 143 [..]
bogdanm 0:9b334a45a8ff 144 This section provides functions allowing to initialize/de-initialize
bogdanm 0:9b334a45a8ff 145 the NAND memory
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 @endverbatim
bogdanm 0:9b334a45a8ff 148 * @{
bogdanm 0:9b334a45a8ff 149 */
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 /**
bogdanm 0:9b334a45a8ff 152 * @brief Perform NAND memory Initialization sequence
bogdanm 0:9b334a45a8ff 153 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 154 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 155 * @param ComSpace_Timing: pointer to Common space timing structure
bogdanm 0:9b334a45a8ff 156 * @param AttSpace_Timing: pointer to Attribute space timing structure
bogdanm 0:9b334a45a8ff 157 * @retval HAL status
bogdanm 0:9b334a45a8ff 158 */
bogdanm 0:9b334a45a8ff 159 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
bogdanm 0:9b334a45a8ff 160 {
bogdanm 0:9b334a45a8ff 161 /* Check the NAND handle state */
bogdanm 0:9b334a45a8ff 162 if(hnand == NULL)
bogdanm 0:9b334a45a8ff 163 {
bogdanm 0:9b334a45a8ff 164 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 165 }
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 if(hnand->State == HAL_NAND_STATE_RESET)
bogdanm 0:9b334a45a8ff 168 {
bogdanm 0:9b334a45a8ff 169 /* Allocate lock resource and initialize it */
mbed_official 124:6a4a5b7d7324 170 hnand->Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 173 HAL_NAND_MspInit(hnand);
bogdanm 0:9b334a45a8ff 174 }
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 /* Initialize NAND control Interface */
bogdanm 0:9b334a45a8ff 177 FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 /* Initialize NAND common space timing Interface */
bogdanm 0:9b334a45a8ff 180 FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 181
bogdanm 0:9b334a45a8ff 182 /* Initialize NAND attribute space timing Interface */
bogdanm 0:9b334a45a8ff 183 FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 /* Enable the NAND device */
bogdanm 0:9b334a45a8ff 186 __FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 189 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 190
bogdanm 0:9b334a45a8ff 191 return HAL_OK;
bogdanm 0:9b334a45a8ff 192 }
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 /**
bogdanm 0:9b334a45a8ff 195 * @brief Perform NAND memory De-Initialization sequence
bogdanm 0:9b334a45a8ff 196 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 197 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 198 * @retval HAL status
bogdanm 0:9b334a45a8ff 199 */
bogdanm 0:9b334a45a8ff 200 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 201 {
bogdanm 0:9b334a45a8ff 202 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 203 HAL_NAND_MspDeInit(hnand);
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 /* Configure the NAND registers with their reset values */
bogdanm 0:9b334a45a8ff 206 FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 /* Reset the NAND controller state */
bogdanm 0:9b334a45a8ff 209 hnand->State = HAL_NAND_STATE_RESET;
bogdanm 0:9b334a45a8ff 210
bogdanm 0:9b334a45a8ff 211 /* Release Lock */
bogdanm 0:9b334a45a8ff 212 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 return HAL_OK;
bogdanm 0:9b334a45a8ff 215 }
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 /**
bogdanm 0:9b334a45a8ff 218 * @brief NAND MSP Init
bogdanm 0:9b334a45a8ff 219 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 220 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 221 * @retval None
bogdanm 0:9b334a45a8ff 222 */
bogdanm 0:9b334a45a8ff 223 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 224 {
mbed_official 124:6a4a5b7d7324 225 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 226 UNUSED(hnand);
bogdanm 0:9b334a45a8ff 227 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 228 the HAL_NAND_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 229 */
bogdanm 0:9b334a45a8ff 230 }
bogdanm 0:9b334a45a8ff 231
bogdanm 0:9b334a45a8ff 232 /**
bogdanm 0:9b334a45a8ff 233 * @brief NAND MSP DeInit
bogdanm 0:9b334a45a8ff 234 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 235 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 236 * @retval None
bogdanm 0:9b334a45a8ff 237 */
bogdanm 0:9b334a45a8ff 238 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 239 {
mbed_official 124:6a4a5b7d7324 240 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 241 UNUSED(hnand);
bogdanm 0:9b334a45a8ff 242 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 243 the HAL_NAND_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 244 */
bogdanm 0:9b334a45a8ff 245 }
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 /**
bogdanm 0:9b334a45a8ff 249 * @brief This function handles NAND device interrupt request.
bogdanm 0:9b334a45a8ff 250 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 251 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 252 * @retval HAL status
bogdanm 0:9b334a45a8ff 253 */
bogdanm 0:9b334a45a8ff 254 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 255 {
bogdanm 0:9b334a45a8ff 256 /* Check NAND interrupt Rising edge flag */
bogdanm 0:9b334a45a8ff 257 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
bogdanm 0:9b334a45a8ff 258 {
bogdanm 0:9b334a45a8ff 259 /* NAND interrupt callback*/
bogdanm 0:9b334a45a8ff 260 HAL_NAND_ITCallback(hnand);
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 /* Clear NAND interrupt Rising edge pending bit */
bogdanm 0:9b334a45a8ff 263 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
bogdanm 0:9b334a45a8ff 264 }
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 /* Check NAND interrupt Level flag */
bogdanm 0:9b334a45a8ff 267 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
bogdanm 0:9b334a45a8ff 268 {
bogdanm 0:9b334a45a8ff 269 /* NAND interrupt callback*/
bogdanm 0:9b334a45a8ff 270 HAL_NAND_ITCallback(hnand);
bogdanm 0:9b334a45a8ff 271
bogdanm 0:9b334a45a8ff 272 /* Clear NAND interrupt Level pending bit */
bogdanm 0:9b334a45a8ff 273 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
bogdanm 0:9b334a45a8ff 274 }
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 /* Check NAND interrupt Falling edge flag */
bogdanm 0:9b334a45a8ff 277 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
bogdanm 0:9b334a45a8ff 278 {
bogdanm 0:9b334a45a8ff 279 /* NAND interrupt callback*/
bogdanm 0:9b334a45a8ff 280 HAL_NAND_ITCallback(hnand);
bogdanm 0:9b334a45a8ff 281
bogdanm 0:9b334a45a8ff 282 /* Clear NAND interrupt Falling edge pending bit */
bogdanm 0:9b334a45a8ff 283 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
bogdanm 0:9b334a45a8ff 284 }
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 /* Check NAND interrupt FIFO empty flag */
bogdanm 0:9b334a45a8ff 287 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
bogdanm 0:9b334a45a8ff 288 {
bogdanm 0:9b334a45a8ff 289 /* NAND interrupt callback*/
bogdanm 0:9b334a45a8ff 290 HAL_NAND_ITCallback(hnand);
bogdanm 0:9b334a45a8ff 291
bogdanm 0:9b334a45a8ff 292 /* Clear NAND interrupt FIFO empty pending bit */
bogdanm 0:9b334a45a8ff 293 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
bogdanm 0:9b334a45a8ff 294 }
bogdanm 0:9b334a45a8ff 295
bogdanm 0:9b334a45a8ff 296 }
bogdanm 0:9b334a45a8ff 297
bogdanm 0:9b334a45a8ff 298 /**
bogdanm 0:9b334a45a8ff 299 * @brief NAND interrupt feature callback
bogdanm 0:9b334a45a8ff 300 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 301 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 302 * @retval None
bogdanm 0:9b334a45a8ff 303 */
bogdanm 0:9b334a45a8ff 304 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 305 {
mbed_official 124:6a4a5b7d7324 306 /* Prevent unused argument(s) compilation warning */
mbed_official 124:6a4a5b7d7324 307 UNUSED(hnand);
bogdanm 0:9b334a45a8ff 308 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 309 the HAL_NAND_ITCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 310 */
bogdanm 0:9b334a45a8ff 311 }
bogdanm 0:9b334a45a8ff 312
bogdanm 0:9b334a45a8ff 313 /**
bogdanm 0:9b334a45a8ff 314 * @}
bogdanm 0:9b334a45a8ff 315 */
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
bogdanm 0:9b334a45a8ff 318 * @brief Input Output and memory control functions
bogdanm 0:9b334a45a8ff 319 *
bogdanm 0:9b334a45a8ff 320 @verbatim
bogdanm 0:9b334a45a8ff 321 ==============================================================================
bogdanm 0:9b334a45a8ff 322 ##### NAND Input and Output functions #####
bogdanm 0:9b334a45a8ff 323 ==============================================================================
bogdanm 0:9b334a45a8ff 324 [..]
bogdanm 0:9b334a45a8ff 325 This section provides functions allowing to use and control the NAND
bogdanm 0:9b334a45a8ff 326 memory
bogdanm 0:9b334a45a8ff 327
bogdanm 0:9b334a45a8ff 328 @endverbatim
bogdanm 0:9b334a45a8ff 329 * @{
bogdanm 0:9b334a45a8ff 330 */
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 /**
bogdanm 0:9b334a45a8ff 333 * @brief Read the NAND memory electronic signature
bogdanm 0:9b334a45a8ff 334 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 335 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 336 * @param pNAND_ID: NAND ID structure
bogdanm 0:9b334a45a8ff 337 * @retval HAL status
bogdanm 0:9b334a45a8ff 338 */
bogdanm 0:9b334a45a8ff 339 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
bogdanm 0:9b334a45a8ff 340 {
bogdanm 0:9b334a45a8ff 341 __IO uint32_t data = 0;
bogdanm 0:9b334a45a8ff 342 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 343
bogdanm 0:9b334a45a8ff 344 /* Process Locked */
bogdanm 0:9b334a45a8ff 345 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 348 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 349 {
bogdanm 0:9b334a45a8ff 350 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 351 }
bogdanm 0:9b334a45a8ff 352
bogdanm 0:9b334a45a8ff 353 /* Identify the device address */
bogdanm 0:9b334a45a8ff 354 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 355 {
bogdanm 0:9b334a45a8ff 356 deviceaddress = NAND_DEVICE1;
bogdanm 0:9b334a45a8ff 357 }
bogdanm 0:9b334a45a8ff 358 else
bogdanm 0:9b334a45a8ff 359 {
bogdanm 0:9b334a45a8ff 360 deviceaddress = NAND_DEVICE2;
bogdanm 0:9b334a45a8ff 361 }
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 364 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 /* Send Read ID command sequence */
bogdanm 0:9b334a45a8ff 367 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
bogdanm 0:9b334a45a8ff 368 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 /* Read the electronic signature from NAND flash */
bogdanm 0:9b334a45a8ff 371 data = *(__IO uint32_t *)deviceaddress;
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 /* Return the data read */
mbed_official 124:6a4a5b7d7324 374 pNAND_ID->Maker_Id = ADDR_1st_CYCLE(data);
mbed_official 124:6a4a5b7d7324 375 pNAND_ID->Device_Id = ADDR_2nd_CYCLE(data);
mbed_official 124:6a4a5b7d7324 376 pNAND_ID->Third_Id = ADDR_3rd_CYCLE(data);
mbed_official 124:6a4a5b7d7324 377 pNAND_ID->Fourth_Id = ADDR_4th_CYCLE(data);
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 380 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 /* Process unlocked */
bogdanm 0:9b334a45a8ff 383 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 384
bogdanm 0:9b334a45a8ff 385 return HAL_OK;
bogdanm 0:9b334a45a8ff 386 }
bogdanm 0:9b334a45a8ff 387
bogdanm 0:9b334a45a8ff 388 /**
bogdanm 0:9b334a45a8ff 389 * @brief NAND memory reset
bogdanm 0:9b334a45a8ff 390 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 391 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 392 * @retval HAL status
bogdanm 0:9b334a45a8ff 393 */
bogdanm 0:9b334a45a8ff 394 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 395 {
bogdanm 0:9b334a45a8ff 396 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 397
bogdanm 0:9b334a45a8ff 398 /* Process Locked */
bogdanm 0:9b334a45a8ff 399 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 402 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 403 {
bogdanm 0:9b334a45a8ff 404 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 405 }
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 /* Identify the device address */
bogdanm 0:9b334a45a8ff 408 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 409 {
bogdanm 0:9b334a45a8ff 410 deviceaddress = NAND_DEVICE1;
bogdanm 0:9b334a45a8ff 411 }
bogdanm 0:9b334a45a8ff 412 else
bogdanm 0:9b334a45a8ff 413 {
bogdanm 0:9b334a45a8ff 414 deviceaddress = NAND_DEVICE2;
bogdanm 0:9b334a45a8ff 415 }
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 418 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 419
bogdanm 0:9b334a45a8ff 420 /* Send NAND reset command */
bogdanm 0:9b334a45a8ff 421 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
bogdanm 0:9b334a45a8ff 422
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 425 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427 /* Process unlocked */
bogdanm 0:9b334a45a8ff 428 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 return HAL_OK;
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 }
bogdanm 0:9b334a45a8ff 433
bogdanm 0:9b334a45a8ff 434 /**
bogdanm 0:9b334a45a8ff 435 * @brief Read Page(s) from NAND memory block
bogdanm 0:9b334a45a8ff 436 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 437 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 438 * @param pAddress : pointer to NAND address structure
bogdanm 0:9b334a45a8ff 439 * @param pBuffer : pointer to destination read buffer
bogdanm 0:9b334a45a8ff 440 * @param NumPageToRead : number of pages to read from block
bogdanm 0:9b334a45a8ff 441 * @retval HAL status
bogdanm 0:9b334a45a8ff 442 */
bogdanm 0:9b334a45a8ff 443 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
bogdanm 0:9b334a45a8ff 444 {
bogdanm 0:9b334a45a8ff 445 __IO uint32_t index = 0;
bogdanm 0:9b334a45a8ff 446 uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 447 NAND_AddressTypeDef nandaddress;
bogdanm 0:9b334a45a8ff 448 uint32_t addressoffset = 0;
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 /* Process Locked */
bogdanm 0:9b334a45a8ff 451 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 454 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 455 {
bogdanm 0:9b334a45a8ff 456 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 457 }
bogdanm 0:9b334a45a8ff 458
bogdanm 0:9b334a45a8ff 459 /* Identify the device address */
bogdanm 0:9b334a45a8ff 460 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 461 {
bogdanm 0:9b334a45a8ff 462 deviceaddress = NAND_DEVICE1;
bogdanm 0:9b334a45a8ff 463 }
bogdanm 0:9b334a45a8ff 464 else
bogdanm 0:9b334a45a8ff 465 {
bogdanm 0:9b334a45a8ff 466 deviceaddress = NAND_DEVICE2;
bogdanm 0:9b334a45a8ff 467 }
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 470 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 471
bogdanm 0:9b334a45a8ff 472 /* Save the content of pAddress as it will be modified */
bogdanm 0:9b334a45a8ff 473 nandaddress.Block = pAddress->Block;
bogdanm 0:9b334a45a8ff 474 nandaddress.Page = pAddress->Page;
bogdanm 0:9b334a45a8ff 475 nandaddress.Zone = pAddress->Zone;
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 /* Page(s) read loop */
bogdanm 0:9b334a45a8ff 478 while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
bogdanm 0:9b334a45a8ff 479 {
bogdanm 0:9b334a45a8ff 480 /* update the buffer size */
bogdanm 0:9b334a45a8ff 481 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483 /* Get the address offset */
mbed_official 124:6a4a5b7d7324 484 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
bogdanm 0:9b334a45a8ff 485
bogdanm 0:9b334a45a8ff 486 /* Send read page command sequence */
bogdanm 0:9b334a45a8ff 487 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
mbed_official 124:6a4a5b7d7324 490 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset);
mbed_official 124:6a4a5b7d7324 491 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset);
mbed_official 124:6a4a5b7d7324 492 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 /* for 512 and 1 GB devices, 4th cycle is required */
bogdanm 0:9b334a45a8ff 495 if(hnand->Info.BlockNbr >= 1024)
bogdanm 0:9b334a45a8ff 496 {
mbed_official 124:6a4a5b7d7324 497 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 498 }
bogdanm 0:9b334a45a8ff 499
bogdanm 0:9b334a45a8ff 500 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 /* Get Data into Buffer */
bogdanm 0:9b334a45a8ff 503 for(; index < size; index++)
bogdanm 0:9b334a45a8ff 504 {
bogdanm 0:9b334a45a8ff 505 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
bogdanm 0:9b334a45a8ff 506 }
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 /* Increment read pages number */
bogdanm 0:9b334a45a8ff 509 numpagesread++;
bogdanm 0:9b334a45a8ff 510
bogdanm 0:9b334a45a8ff 511 /* Decrement pages to read */
bogdanm 0:9b334a45a8ff 512 NumPageToRead--;
bogdanm 0:9b334a45a8ff 513
bogdanm 0:9b334a45a8ff 514 /* Increment the NAND address */
bogdanm 0:9b334a45a8ff 515 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
bogdanm 0:9b334a45a8ff 516 }
bogdanm 0:9b334a45a8ff 517
bogdanm 0:9b334a45a8ff 518 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 519 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 520
bogdanm 0:9b334a45a8ff 521 /* Process unlocked */
bogdanm 0:9b334a45a8ff 522 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 return HAL_OK;
bogdanm 0:9b334a45a8ff 525
bogdanm 0:9b334a45a8ff 526 }
bogdanm 0:9b334a45a8ff 527
bogdanm 0:9b334a45a8ff 528 /**
bogdanm 0:9b334a45a8ff 529 * @brief Write Page(s) to NAND memory block
bogdanm 0:9b334a45a8ff 530 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 531 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 532 * @param pAddress : pointer to NAND address structure
bogdanm 0:9b334a45a8ff 533 * @param pBuffer : pointer to source buffer to write
bogdanm 0:9b334a45a8ff 534 * @param NumPageToWrite : number of pages to write to block
bogdanm 0:9b334a45a8ff 535 * @retval HAL status
bogdanm 0:9b334a45a8ff 536 */
bogdanm 0:9b334a45a8ff 537 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
bogdanm 0:9b334a45a8ff 538 {
bogdanm 0:9b334a45a8ff 539 __IO uint32_t index = 0;
bogdanm 0:9b334a45a8ff 540 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 541 uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 542 NAND_AddressTypeDef nandaddress;
bogdanm 0:9b334a45a8ff 543 uint32_t addressoffset = 0;
bogdanm 0:9b334a45a8ff 544
bogdanm 0:9b334a45a8ff 545 /* Process Locked */
bogdanm 0:9b334a45a8ff 546 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 547
bogdanm 0:9b334a45a8ff 548 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 549 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 550 {
bogdanm 0:9b334a45a8ff 551 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 552 }
bogdanm 0:9b334a45a8ff 553
bogdanm 0:9b334a45a8ff 554 /* Identify the device address */
bogdanm 0:9b334a45a8ff 555 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 556 {
bogdanm 0:9b334a45a8ff 557 deviceaddress = NAND_DEVICE1;
bogdanm 0:9b334a45a8ff 558 }
bogdanm 0:9b334a45a8ff 559 else
bogdanm 0:9b334a45a8ff 560 {
bogdanm 0:9b334a45a8ff 561 deviceaddress = NAND_DEVICE2;
bogdanm 0:9b334a45a8ff 562 }
bogdanm 0:9b334a45a8ff 563
bogdanm 0:9b334a45a8ff 564 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 565 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 566
bogdanm 0:9b334a45a8ff 567 /* Save the content of pAddress as it will be modified */
bogdanm 0:9b334a45a8ff 568 nandaddress.Block = pAddress->Block;
bogdanm 0:9b334a45a8ff 569 nandaddress.Page = pAddress->Page;
bogdanm 0:9b334a45a8ff 570 nandaddress.Zone = pAddress->Zone;
bogdanm 0:9b334a45a8ff 571
bogdanm 0:9b334a45a8ff 572 /* Page(s) write loop */
bogdanm 0:9b334a45a8ff 573 while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
bogdanm 0:9b334a45a8ff 574 {
bogdanm 0:9b334a45a8ff 575 /* update the buffer size */
bogdanm 0:9b334a45a8ff 576 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
bogdanm 0:9b334a45a8ff 577
bogdanm 0:9b334a45a8ff 578 /* Get the address offset */
mbed_official 124:6a4a5b7d7324 579 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
bogdanm 0:9b334a45a8ff 580
bogdanm 0:9b334a45a8ff 581 /* Send write page command sequence */
bogdanm 0:9b334a45a8ff 582 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
bogdanm 0:9b334a45a8ff 583 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
bogdanm 0:9b334a45a8ff 584
bogdanm 0:9b334a45a8ff 585 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
mbed_official 124:6a4a5b7d7324 586 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset);
mbed_official 124:6a4a5b7d7324 587 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset);
mbed_official 124:6a4a5b7d7324 588 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 589
bogdanm 0:9b334a45a8ff 590 /* for 512 and 1 GB devices, 4th cycle is required */
bogdanm 0:9b334a45a8ff 591 if(hnand->Info.BlockNbr >= 1024)
bogdanm 0:9b334a45a8ff 592 {
mbed_official 124:6a4a5b7d7324 593 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 594 }
bogdanm 0:9b334a45a8ff 595
bogdanm 0:9b334a45a8ff 596 /* Write data to memory */
bogdanm 0:9b334a45a8ff 597 for(; index < size; index++)
bogdanm 0:9b334a45a8ff 598 {
bogdanm 0:9b334a45a8ff 599 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
bogdanm 0:9b334a45a8ff 600 }
bogdanm 0:9b334a45a8ff 601
bogdanm 0:9b334a45a8ff 602 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
bogdanm 0:9b334a45a8ff 603
bogdanm 0:9b334a45a8ff 604 /* Get tick */
bogdanm 0:9b334a45a8ff 605 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 606
bogdanm 0:9b334a45a8ff 607 /* Read status until NAND is ready */
bogdanm 0:9b334a45a8ff 608 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
bogdanm 0:9b334a45a8ff 609 {
bogdanm 0:9b334a45a8ff 610 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
bogdanm 0:9b334a45a8ff 611 {
bogdanm 0:9b334a45a8ff 612 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 613 }
bogdanm 0:9b334a45a8ff 614 }
bogdanm 0:9b334a45a8ff 615
bogdanm 0:9b334a45a8ff 616 /* Increment written pages number */
bogdanm 0:9b334a45a8ff 617 numpageswritten++;
bogdanm 0:9b334a45a8ff 618
bogdanm 0:9b334a45a8ff 619 /* Decrement pages to write */
bogdanm 0:9b334a45a8ff 620 NumPageToWrite--;
bogdanm 0:9b334a45a8ff 621
bogdanm 0:9b334a45a8ff 622 /* Increment the NAND address */
bogdanm 0:9b334a45a8ff 623 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
bogdanm 0:9b334a45a8ff 624 }
bogdanm 0:9b334a45a8ff 625
bogdanm 0:9b334a45a8ff 626 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 627 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 628
bogdanm 0:9b334a45a8ff 629 /* Process unlocked */
bogdanm 0:9b334a45a8ff 630 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 631
bogdanm 0:9b334a45a8ff 632 return HAL_OK;
bogdanm 0:9b334a45a8ff 633 }
bogdanm 0:9b334a45a8ff 634
bogdanm 0:9b334a45a8ff 635 /**
bogdanm 0:9b334a45a8ff 636 * @brief Read Spare area(s) from NAND memory
bogdanm 0:9b334a45a8ff 637 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 638 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 639 * @param pAddress : pointer to NAND address structure
bogdanm 0:9b334a45a8ff 640 * @param pBuffer: pointer to source buffer to write
bogdanm 0:9b334a45a8ff 641 * @param NumSpareAreaToRead: Number of spare area to read
bogdanm 0:9b334a45a8ff 642 * @retval HAL status
bogdanm 0:9b334a45a8ff 643 */
bogdanm 0:9b334a45a8ff 644 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
bogdanm 0:9b334a45a8ff 645 {
bogdanm 0:9b334a45a8ff 646 __IO uint32_t index = 0;
bogdanm 0:9b334a45a8ff 647 uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 648 NAND_AddressTypeDef nandaddress;
bogdanm 0:9b334a45a8ff 649 uint32_t addressoffset = 0;
bogdanm 0:9b334a45a8ff 650
bogdanm 0:9b334a45a8ff 651 /* Process Locked */
bogdanm 0:9b334a45a8ff 652 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 653
bogdanm 0:9b334a45a8ff 654 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 655 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 656 {
bogdanm 0:9b334a45a8ff 657 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 658 }
bogdanm 0:9b334a45a8ff 659
bogdanm 0:9b334a45a8ff 660 /* Identify the device address */
bogdanm 0:9b334a45a8ff 661 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 662 {
bogdanm 0:9b334a45a8ff 663 deviceaddress = NAND_DEVICE1;
bogdanm 0:9b334a45a8ff 664 }
bogdanm 0:9b334a45a8ff 665 else
bogdanm 0:9b334a45a8ff 666 {
bogdanm 0:9b334a45a8ff 667 deviceaddress = NAND_DEVICE2;
bogdanm 0:9b334a45a8ff 668 }
bogdanm 0:9b334a45a8ff 669
bogdanm 0:9b334a45a8ff 670 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 671 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 672
bogdanm 0:9b334a45a8ff 673 /* Save the content of pAddress as it will be modified */
bogdanm 0:9b334a45a8ff 674 nandaddress.Block = pAddress->Block;
bogdanm 0:9b334a45a8ff 675 nandaddress.Page = pAddress->Page;
bogdanm 0:9b334a45a8ff 676 nandaddress.Zone = pAddress->Zone;
bogdanm 0:9b334a45a8ff 677
bogdanm 0:9b334a45a8ff 678 /* Spare area(s) read loop */
bogdanm 0:9b334a45a8ff 679 while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
bogdanm 0:9b334a45a8ff 680 {
bogdanm 0:9b334a45a8ff 681 /* update the buffer size */
bogdanm 0:9b334a45a8ff 682 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
bogdanm 0:9b334a45a8ff 683
bogdanm 0:9b334a45a8ff 684 /* Get the address offset */
mbed_official 124:6a4a5b7d7324 685 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
bogdanm 0:9b334a45a8ff 686
bogdanm 0:9b334a45a8ff 687 /* Send read spare area command sequence */
bogdanm 0:9b334a45a8ff 688 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
bogdanm 0:9b334a45a8ff 689
bogdanm 0:9b334a45a8ff 690 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
mbed_official 124:6a4a5b7d7324 691 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset);
mbed_official 124:6a4a5b7d7324 692 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset);
mbed_official 124:6a4a5b7d7324 693 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 694
bogdanm 0:9b334a45a8ff 695 /* for 512 and 1 GB devices, 4th cycle is required */
bogdanm 0:9b334a45a8ff 696 if(hnand->Info.BlockNbr >= 1024)
bogdanm 0:9b334a45a8ff 697 {
mbed_official 124:6a4a5b7d7324 698 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 699 }
bogdanm 0:9b334a45a8ff 700
bogdanm 0:9b334a45a8ff 701 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
bogdanm 0:9b334a45a8ff 702
bogdanm 0:9b334a45a8ff 703 /* Get Data into Buffer */
bogdanm 0:9b334a45a8ff 704 for ( ;index < size; index++)
bogdanm 0:9b334a45a8ff 705 {
bogdanm 0:9b334a45a8ff 706 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
bogdanm 0:9b334a45a8ff 707 }
bogdanm 0:9b334a45a8ff 708
bogdanm 0:9b334a45a8ff 709 /* Increment read spare areas number */
bogdanm 0:9b334a45a8ff 710 num_spare_area_read++;
bogdanm 0:9b334a45a8ff 711
bogdanm 0:9b334a45a8ff 712 /* Decrement spare areas to read */
bogdanm 0:9b334a45a8ff 713 NumSpareAreaToRead--;
bogdanm 0:9b334a45a8ff 714
bogdanm 0:9b334a45a8ff 715 /* Increment the NAND address */
bogdanm 0:9b334a45a8ff 716 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
bogdanm 0:9b334a45a8ff 717 }
bogdanm 0:9b334a45a8ff 718
bogdanm 0:9b334a45a8ff 719 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 720 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 721
bogdanm 0:9b334a45a8ff 722 /* Process unlocked */
bogdanm 0:9b334a45a8ff 723 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 724
bogdanm 0:9b334a45a8ff 725 return HAL_OK;
bogdanm 0:9b334a45a8ff 726 }
bogdanm 0:9b334a45a8ff 727
bogdanm 0:9b334a45a8ff 728 /**
bogdanm 0:9b334a45a8ff 729 * @brief Write Spare area(s) to NAND memory
bogdanm 0:9b334a45a8ff 730 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 731 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 732 * @param pAddress : pointer to NAND address structure
bogdanm 0:9b334a45a8ff 733 * @param pBuffer : pointer to source buffer to write
bogdanm 0:9b334a45a8ff 734 * @param NumSpareAreaTowrite : number of spare areas to write to block
bogdanm 0:9b334a45a8ff 735 * @retval HAL status
bogdanm 0:9b334a45a8ff 736 */
bogdanm 0:9b334a45a8ff 737 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
bogdanm 0:9b334a45a8ff 738 {
bogdanm 0:9b334a45a8ff 739 __IO uint32_t index = 0;
bogdanm 0:9b334a45a8ff 740 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 741 uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 742 NAND_AddressTypeDef nandaddress;
bogdanm 0:9b334a45a8ff 743 uint32_t addressoffset = 0;
bogdanm 0:9b334a45a8ff 744
bogdanm 0:9b334a45a8ff 745 /* Process Locked */
bogdanm 0:9b334a45a8ff 746 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 747
bogdanm 0:9b334a45a8ff 748 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 749 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 750 {
bogdanm 0:9b334a45a8ff 751 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 752 }
bogdanm 0:9b334a45a8ff 753
bogdanm 0:9b334a45a8ff 754 /* Identify the device address */
bogdanm 0:9b334a45a8ff 755 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 756 {
bogdanm 0:9b334a45a8ff 757 deviceaddress = NAND_DEVICE1;
bogdanm 0:9b334a45a8ff 758 }
bogdanm 0:9b334a45a8ff 759 else
bogdanm 0:9b334a45a8ff 760 {
bogdanm 0:9b334a45a8ff 761 deviceaddress = NAND_DEVICE2;
bogdanm 0:9b334a45a8ff 762 }
bogdanm 0:9b334a45a8ff 763
mbed_official 124:6a4a5b7d7324 764 /* Update the FSMC_NAND controller state */
bogdanm 0:9b334a45a8ff 765 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 766
bogdanm 0:9b334a45a8ff 767 /* Save the content of pAddress as it will be modified */
bogdanm 0:9b334a45a8ff 768 nandaddress.Block = pAddress->Block;
bogdanm 0:9b334a45a8ff 769 nandaddress.Page = pAddress->Page;
bogdanm 0:9b334a45a8ff 770 nandaddress.Zone = pAddress->Zone;
bogdanm 0:9b334a45a8ff 771
bogdanm 0:9b334a45a8ff 772 /* Spare area(s) write loop */
bogdanm 0:9b334a45a8ff 773 while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
bogdanm 0:9b334a45a8ff 774 {
bogdanm 0:9b334a45a8ff 775 /* update the buffer size */
bogdanm 0:9b334a45a8ff 776 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
bogdanm 0:9b334a45a8ff 777
bogdanm 0:9b334a45a8ff 778 /* Get the address offset */
mbed_official 124:6a4a5b7d7324 779 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
bogdanm 0:9b334a45a8ff 780
bogdanm 0:9b334a45a8ff 781 /* Send write Spare area command sequence */
bogdanm 0:9b334a45a8ff 782 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
bogdanm 0:9b334a45a8ff 783 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
bogdanm 0:9b334a45a8ff 784
bogdanm 0:9b334a45a8ff 785 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
mbed_official 124:6a4a5b7d7324 786 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset);
mbed_official 124:6a4a5b7d7324 787 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset);
mbed_official 124:6a4a5b7d7324 788 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 789
bogdanm 0:9b334a45a8ff 790 /* for 512 and 1 GB devices, 4th cycle is required */
bogdanm 0:9b334a45a8ff 791 if(hnand->Info.BlockNbr >= 1024)
bogdanm 0:9b334a45a8ff 792 {
mbed_official 124:6a4a5b7d7324 793 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 794 }
bogdanm 0:9b334a45a8ff 795
bogdanm 0:9b334a45a8ff 796 /* Write data to memory */
bogdanm 0:9b334a45a8ff 797 for(; index < size; index++)
bogdanm 0:9b334a45a8ff 798 {
bogdanm 0:9b334a45a8ff 799 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
bogdanm 0:9b334a45a8ff 800 }
bogdanm 0:9b334a45a8ff 801
bogdanm 0:9b334a45a8ff 802 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
bogdanm 0:9b334a45a8ff 803
bogdanm 0:9b334a45a8ff 804 /* Get tick */
bogdanm 0:9b334a45a8ff 805 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 806
bogdanm 0:9b334a45a8ff 807 /* Read status until NAND is ready */
bogdanm 0:9b334a45a8ff 808 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
bogdanm 0:9b334a45a8ff 809 {
bogdanm 0:9b334a45a8ff 810 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
bogdanm 0:9b334a45a8ff 811 {
bogdanm 0:9b334a45a8ff 812 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 813 }
bogdanm 0:9b334a45a8ff 814 }
bogdanm 0:9b334a45a8ff 815
bogdanm 0:9b334a45a8ff 816 /* Increment written spare areas number */
bogdanm 0:9b334a45a8ff 817 num_spare_area_written++;
bogdanm 0:9b334a45a8ff 818
bogdanm 0:9b334a45a8ff 819 /* Decrement spare areas to write */
bogdanm 0:9b334a45a8ff 820 NumSpareAreaTowrite--;
bogdanm 0:9b334a45a8ff 821
bogdanm 0:9b334a45a8ff 822 /* Increment the NAND address */
bogdanm 0:9b334a45a8ff 823 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
bogdanm 0:9b334a45a8ff 824 }
bogdanm 0:9b334a45a8ff 825
bogdanm 0:9b334a45a8ff 826 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 827 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 828
bogdanm 0:9b334a45a8ff 829 /* Process unlocked */
bogdanm 0:9b334a45a8ff 830 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 831
bogdanm 0:9b334a45a8ff 832 return HAL_OK;
bogdanm 0:9b334a45a8ff 833 }
bogdanm 0:9b334a45a8ff 834
bogdanm 0:9b334a45a8ff 835 /**
bogdanm 0:9b334a45a8ff 836 * @brief NAND memory Block erase
bogdanm 0:9b334a45a8ff 837 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 838 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 839 * @param pAddress : pointer to NAND address structure
bogdanm 0:9b334a45a8ff 840 * @retval HAL status
bogdanm 0:9b334a45a8ff 841 */
bogdanm 0:9b334a45a8ff 842 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
bogdanm 0:9b334a45a8ff 843 {
bogdanm 0:9b334a45a8ff 844 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 845 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 846
bogdanm 0:9b334a45a8ff 847 /* Process Locked */
bogdanm 0:9b334a45a8ff 848 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 849
bogdanm 0:9b334a45a8ff 850 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 851 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 852 {
bogdanm 0:9b334a45a8ff 853 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 854 }
bogdanm 0:9b334a45a8ff 855
bogdanm 0:9b334a45a8ff 856 /* Identify the device address */
bogdanm 0:9b334a45a8ff 857 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 858 {
bogdanm 0:9b334a45a8ff 859 deviceaddress = NAND_DEVICE1;
bogdanm 0:9b334a45a8ff 860 }
bogdanm 0:9b334a45a8ff 861 else
bogdanm 0:9b334a45a8ff 862 {
bogdanm 0:9b334a45a8ff 863 deviceaddress = NAND_DEVICE2;
bogdanm 0:9b334a45a8ff 864 }
bogdanm 0:9b334a45a8ff 865
bogdanm 0:9b334a45a8ff 866 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 867 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 868
bogdanm 0:9b334a45a8ff 869 /* Send Erase block command sequence */
bogdanm 0:9b334a45a8ff 870 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
bogdanm 0:9b334a45a8ff 871
mbed_official 124:6a4a5b7d7324 872 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
mbed_official 124:6a4a5b7d7324 873 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
mbed_official 124:6a4a5b7d7324 874 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
bogdanm 0:9b334a45a8ff 875
bogdanm 0:9b334a45a8ff 876 /* for 512 and 1 GB devices, 4th cycle is required */
bogdanm 0:9b334a45a8ff 877 if(hnand->Info.BlockNbr >= 1024)
bogdanm 0:9b334a45a8ff 878 {
mbed_official 124:6a4a5b7d7324 879 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
bogdanm 0:9b334a45a8ff 880 }
bogdanm 0:9b334a45a8ff 881
bogdanm 0:9b334a45a8ff 882 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
bogdanm 0:9b334a45a8ff 883
bogdanm 0:9b334a45a8ff 884 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 885 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 886
bogdanm 0:9b334a45a8ff 887 /* Get tick */
bogdanm 0:9b334a45a8ff 888 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 889
bogdanm 0:9b334a45a8ff 890 /* Read status until NAND is ready */
bogdanm 0:9b334a45a8ff 891 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
bogdanm 0:9b334a45a8ff 892 {
bogdanm 0:9b334a45a8ff 893 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
bogdanm 0:9b334a45a8ff 894 {
bogdanm 0:9b334a45a8ff 895 /* Process unlocked */
bogdanm 0:9b334a45a8ff 896 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 897
bogdanm 0:9b334a45a8ff 898 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 899 }
bogdanm 0:9b334a45a8ff 900 }
bogdanm 0:9b334a45a8ff 901
bogdanm 0:9b334a45a8ff 902 /* Process unlocked */
bogdanm 0:9b334a45a8ff 903 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 904
bogdanm 0:9b334a45a8ff 905 return HAL_OK;
bogdanm 0:9b334a45a8ff 906 }
bogdanm 0:9b334a45a8ff 907
bogdanm 0:9b334a45a8ff 908 /**
bogdanm 0:9b334a45a8ff 909 * @brief NAND memory read status
bogdanm 0:9b334a45a8ff 910 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 911 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 912 * @retval NAND status
bogdanm 0:9b334a45a8ff 913 */
bogdanm 0:9b334a45a8ff 914 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 915 {
bogdanm 0:9b334a45a8ff 916 uint32_t data = 0;
bogdanm 0:9b334a45a8ff 917 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 918
bogdanm 0:9b334a45a8ff 919 /* Identify the device address */
bogdanm 0:9b334a45a8ff 920 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 921 {
bogdanm 0:9b334a45a8ff 922 deviceaddress = NAND_DEVICE1;
bogdanm 0:9b334a45a8ff 923 }
bogdanm 0:9b334a45a8ff 924 else
bogdanm 0:9b334a45a8ff 925 {
bogdanm 0:9b334a45a8ff 926 deviceaddress = NAND_DEVICE2;
bogdanm 0:9b334a45a8ff 927 }
bogdanm 0:9b334a45a8ff 928
bogdanm 0:9b334a45a8ff 929 /* Send Read status operation command */
bogdanm 0:9b334a45a8ff 930 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
bogdanm 0:9b334a45a8ff 931
bogdanm 0:9b334a45a8ff 932 /* Read status register data */
bogdanm 0:9b334a45a8ff 933 data = *(__IO uint8_t *)deviceaddress;
bogdanm 0:9b334a45a8ff 934
bogdanm 0:9b334a45a8ff 935 /* Return the status */
bogdanm 0:9b334a45a8ff 936 if((data & NAND_ERROR) == NAND_ERROR)
bogdanm 0:9b334a45a8ff 937 {
bogdanm 0:9b334a45a8ff 938 return NAND_ERROR;
bogdanm 0:9b334a45a8ff 939 }
bogdanm 0:9b334a45a8ff 940 else if((data & NAND_READY) == NAND_READY)
bogdanm 0:9b334a45a8ff 941 {
bogdanm 0:9b334a45a8ff 942 return NAND_READY;
bogdanm 0:9b334a45a8ff 943 }
bogdanm 0:9b334a45a8ff 944
bogdanm 0:9b334a45a8ff 945 return NAND_BUSY;
bogdanm 0:9b334a45a8ff 946 }
bogdanm 0:9b334a45a8ff 947
bogdanm 0:9b334a45a8ff 948 /**
bogdanm 0:9b334a45a8ff 949 * @brief Increment the NAND memory address
bogdanm 0:9b334a45a8ff 950 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 951 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 952 * @param pAddress: pointer to NAND address structure
bogdanm 0:9b334a45a8ff 953 * @retval The new status of the increment address operation. It can be:
bogdanm 0:9b334a45a8ff 954 * - NAND_VALID_ADDRESS: When the new address is valid address
bogdanm 0:9b334a45a8ff 955 * - NAND_INVALID_ADDRESS: When the new address is invalid address
bogdanm 0:9b334a45a8ff 956 */
bogdanm 0:9b334a45a8ff 957 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
bogdanm 0:9b334a45a8ff 958 {
bogdanm 0:9b334a45a8ff 959 uint32_t status = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 960
bogdanm 0:9b334a45a8ff 961 /* Increment page address */
bogdanm 0:9b334a45a8ff 962 pAddress->Page++;
bogdanm 0:9b334a45a8ff 963
bogdanm 0:9b334a45a8ff 964 /* Check NAND address is valid */
bogdanm 0:9b334a45a8ff 965 if(pAddress->Page == hnand->Info.BlockSize)
bogdanm 0:9b334a45a8ff 966 {
bogdanm 0:9b334a45a8ff 967 pAddress->Page = 0;
bogdanm 0:9b334a45a8ff 968 pAddress->Block++;
bogdanm 0:9b334a45a8ff 969
bogdanm 0:9b334a45a8ff 970 if(pAddress->Block == hnand->Info.ZoneSize)
bogdanm 0:9b334a45a8ff 971 {
bogdanm 0:9b334a45a8ff 972 pAddress->Block = 0;
bogdanm 0:9b334a45a8ff 973 pAddress->Zone++;
bogdanm 0:9b334a45a8ff 974
bogdanm 0:9b334a45a8ff 975 if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
bogdanm 0:9b334a45a8ff 976 {
bogdanm 0:9b334a45a8ff 977 status = NAND_INVALID_ADDRESS;
bogdanm 0:9b334a45a8ff 978 }
bogdanm 0:9b334a45a8ff 979 }
bogdanm 0:9b334a45a8ff 980 }
bogdanm 0:9b334a45a8ff 981
bogdanm 0:9b334a45a8ff 982 return (status);
bogdanm 0:9b334a45a8ff 983 }
bogdanm 0:9b334a45a8ff 984 /**
bogdanm 0:9b334a45a8ff 985 * @}
bogdanm 0:9b334a45a8ff 986 */
bogdanm 0:9b334a45a8ff 987
bogdanm 0:9b334a45a8ff 988 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
bogdanm 0:9b334a45a8ff 989 * @brief management functions
bogdanm 0:9b334a45a8ff 990 *
bogdanm 0:9b334a45a8ff 991 @verbatim
bogdanm 0:9b334a45a8ff 992 ==============================================================================
bogdanm 0:9b334a45a8ff 993 ##### NAND Control functions #####
bogdanm 0:9b334a45a8ff 994 ==============================================================================
bogdanm 0:9b334a45a8ff 995 [..]
bogdanm 0:9b334a45a8ff 996 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 997 the NAND interface.
bogdanm 0:9b334a45a8ff 998
bogdanm 0:9b334a45a8ff 999 @endverbatim
bogdanm 0:9b334a45a8ff 1000 * @{
bogdanm 0:9b334a45a8ff 1001 */
bogdanm 0:9b334a45a8ff 1002
bogdanm 0:9b334a45a8ff 1003
bogdanm 0:9b334a45a8ff 1004 /**
bogdanm 0:9b334a45a8ff 1005 * @brief Enables dynamically NAND ECC feature.
bogdanm 0:9b334a45a8ff 1006 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1007 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 1008 * @retval HAL status
bogdanm 0:9b334a45a8ff 1009 */
bogdanm 0:9b334a45a8ff 1010 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 1011 {
bogdanm 0:9b334a45a8ff 1012 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 1013 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 1014 {
bogdanm 0:9b334a45a8ff 1015 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1016 }
bogdanm 0:9b334a45a8ff 1017
bogdanm 0:9b334a45a8ff 1018 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 1019 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1020
bogdanm 0:9b334a45a8ff 1021 /* Enable ECC feature */
bogdanm 0:9b334a45a8ff 1022 FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 1023
bogdanm 0:9b334a45a8ff 1024 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 1025 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 1026
bogdanm 0:9b334a45a8ff 1027 return HAL_OK;
bogdanm 0:9b334a45a8ff 1028 }
bogdanm 0:9b334a45a8ff 1029
bogdanm 0:9b334a45a8ff 1030 /**
bogdanm 0:9b334a45a8ff 1031 * @brief Disables dynamically FSMC_NAND ECC feature.
bogdanm 0:9b334a45a8ff 1032 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1033 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 1034 * @retval HAL status
bogdanm 0:9b334a45a8ff 1035 */
bogdanm 0:9b334a45a8ff 1036 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 1037 {
bogdanm 0:9b334a45a8ff 1038 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 1039 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 1040 {
bogdanm 0:9b334a45a8ff 1041 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1042 }
bogdanm 0:9b334a45a8ff 1043
bogdanm 0:9b334a45a8ff 1044 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 1045 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1046
bogdanm 0:9b334a45a8ff 1047 /* Disable ECC feature */
bogdanm 0:9b334a45a8ff 1048 FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 1049
bogdanm 0:9b334a45a8ff 1050 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 1051 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 1052
bogdanm 0:9b334a45a8ff 1053 return HAL_OK;
bogdanm 0:9b334a45a8ff 1054 }
bogdanm 0:9b334a45a8ff 1055
bogdanm 0:9b334a45a8ff 1056 /**
bogdanm 0:9b334a45a8ff 1057 * @brief Disables dynamically NAND ECC feature.
bogdanm 0:9b334a45a8ff 1058 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1059 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 1060 * @param ECCval: pointer to ECC value
bogdanm 0:9b334a45a8ff 1061 * @param Timeout: maximum timeout to wait
bogdanm 0:9b334a45a8ff 1062 * @retval HAL status
bogdanm 0:9b334a45a8ff 1063 */
bogdanm 0:9b334a45a8ff 1064 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 1065 {
bogdanm 0:9b334a45a8ff 1066 HAL_StatusTypeDef status = HAL_OK;
bogdanm 0:9b334a45a8ff 1067
bogdanm 0:9b334a45a8ff 1068 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 1069 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 1070 {
bogdanm 0:9b334a45a8ff 1071 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1072 }
bogdanm 0:9b334a45a8ff 1073
bogdanm 0:9b334a45a8ff 1074 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 1075 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1076
bogdanm 0:9b334a45a8ff 1077 /* Get NAND ECC value */
bogdanm 0:9b334a45a8ff 1078 status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
bogdanm 0:9b334a45a8ff 1079
bogdanm 0:9b334a45a8ff 1080 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 1081 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 1082
bogdanm 0:9b334a45a8ff 1083 return status;
bogdanm 0:9b334a45a8ff 1084 }
bogdanm 0:9b334a45a8ff 1085
bogdanm 0:9b334a45a8ff 1086 /**
bogdanm 0:9b334a45a8ff 1087 * @}
bogdanm 0:9b334a45a8ff 1088 */
bogdanm 0:9b334a45a8ff 1089
bogdanm 0:9b334a45a8ff 1090
bogdanm 0:9b334a45a8ff 1091 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
bogdanm 0:9b334a45a8ff 1092 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 1093 *
bogdanm 0:9b334a45a8ff 1094 @verbatim
bogdanm 0:9b334a45a8ff 1095 ==============================================================================
bogdanm 0:9b334a45a8ff 1096 ##### NAND State functions #####
bogdanm 0:9b334a45a8ff 1097 ==============================================================================
bogdanm 0:9b334a45a8ff 1098 [..]
bogdanm 0:9b334a45a8ff 1099 This subsection permits to get in run-time the status of the NAND controller
bogdanm 0:9b334a45a8ff 1100 and the data flow.
bogdanm 0:9b334a45a8ff 1101
bogdanm 0:9b334a45a8ff 1102 @endverbatim
bogdanm 0:9b334a45a8ff 1103 * @{
bogdanm 0:9b334a45a8ff 1104 */
bogdanm 0:9b334a45a8ff 1105
bogdanm 0:9b334a45a8ff 1106 /**
bogdanm 0:9b334a45a8ff 1107 * @brief return the NAND state
bogdanm 0:9b334a45a8ff 1108 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1109 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 1110 * @retval HAL state
bogdanm 0:9b334a45a8ff 1111 */
bogdanm 0:9b334a45a8ff 1112 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 1113 {
bogdanm 0:9b334a45a8ff 1114 return hnand->State;
bogdanm 0:9b334a45a8ff 1115 }
bogdanm 0:9b334a45a8ff 1116
bogdanm 0:9b334a45a8ff 1117 /**
bogdanm 0:9b334a45a8ff 1118 * @}
bogdanm 0:9b334a45a8ff 1119 */
bogdanm 0:9b334a45a8ff 1120
bogdanm 0:9b334a45a8ff 1121 /**
bogdanm 0:9b334a45a8ff 1122 * @}
bogdanm 0:9b334a45a8ff 1123 */
bogdanm 0:9b334a45a8ff 1124
bogdanm 0:9b334a45a8ff 1125 /** @addtogroup NAND_Private_Functions
bogdanm 0:9b334a45a8ff 1126 * @{
bogdanm 0:9b334a45a8ff 1127 */
bogdanm 0:9b334a45a8ff 1128
bogdanm 0:9b334a45a8ff 1129 /**
bogdanm 0:9b334a45a8ff 1130 * @brief Increment the NAND memory address.
bogdanm 0:9b334a45a8ff 1131 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1132 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 1133 * @param Address: address to be incremented.
bogdanm 0:9b334a45a8ff 1134 * @retval The new status of the increment address operation. It can be:
bogdanm 0:9b334a45a8ff 1135 * - NAND_VALID_ADDRESS: When the new address is valid address
bogdanm 0:9b334a45a8ff 1136 * - NAND_INVALID_ADDRESS: When the new address is invalid address
bogdanm 0:9b334a45a8ff 1137 */
bogdanm 0:9b334a45a8ff 1138 static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address)
bogdanm 0:9b334a45a8ff 1139 {
bogdanm 0:9b334a45a8ff 1140 uint32_t status = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 1141
bogdanm 0:9b334a45a8ff 1142 Address->Page++;
bogdanm 0:9b334a45a8ff 1143
bogdanm 0:9b334a45a8ff 1144 if(Address->Page == hnand->Info.BlockSize)
bogdanm 0:9b334a45a8ff 1145 {
bogdanm 0:9b334a45a8ff 1146 Address->Page = 0;
bogdanm 0:9b334a45a8ff 1147 Address->Block++;
bogdanm 0:9b334a45a8ff 1148
bogdanm 0:9b334a45a8ff 1149 if(Address->Block == hnand->Info.ZoneSize)
bogdanm 0:9b334a45a8ff 1150 {
bogdanm 0:9b334a45a8ff 1151 Address->Block = 0;
bogdanm 0:9b334a45a8ff 1152 Address->Zone++;
bogdanm 0:9b334a45a8ff 1153
bogdanm 0:9b334a45a8ff 1154 if(Address->Zone == hnand->Info.BlockNbr)
bogdanm 0:9b334a45a8ff 1155 {
bogdanm 0:9b334a45a8ff 1156 status = NAND_INVALID_ADDRESS;
bogdanm 0:9b334a45a8ff 1157 }
bogdanm 0:9b334a45a8ff 1158 }
bogdanm 0:9b334a45a8ff 1159 }
bogdanm 0:9b334a45a8ff 1160
bogdanm 0:9b334a45a8ff 1161 return (status);
bogdanm 0:9b334a45a8ff 1162 }
bogdanm 0:9b334a45a8ff 1163
bogdanm 0:9b334a45a8ff 1164 /**
bogdanm 0:9b334a45a8ff 1165 * @}
bogdanm 0:9b334a45a8ff 1166 */
bogdanm 0:9b334a45a8ff 1167
bogdanm 0:9b334a45a8ff 1168 /**
bogdanm 0:9b334a45a8ff 1169 * @}
bogdanm 0:9b334a45a8ff 1170 */
bogdanm 0:9b334a45a8ff 1171
bogdanm 0:9b334a45a8ff 1172 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
bogdanm 0:9b334a45a8ff 1173 #endif /* HAL_NAND_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1174
bogdanm 0:9b334a45a8ff 1175 /**
bogdanm 0:9b334a45a8ff 1176 * @}
bogdanm 0:9b334a45a8ff 1177 */
bogdanm 0:9b334a45a8ff 1178
bogdanm 0:9b334a45a8ff 1179 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/