Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nand.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
124:6a4a5b7d7324 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_nand.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief NAND HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides a generic firmware to drive NAND memories mounted
<> 144:ef7eb2e8f9f7 9 * as external device.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 This driver is a generic layered driver which contains a set of APIs used to
<> 144:ef7eb2e8f9f7 17 control NAND flash memories. It uses the FSMC/FSMC layer functions to interface
<> 144:ef7eb2e8f9f7 18 with NAND devices. This driver is used as follows:
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
<> 144:ef7eb2e8f9f7 21 with control and timing parameters for both common and attribute spaces.
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (+) Read NAND flash memory maker and device IDs using the function
<> 144:ef7eb2e8f9f7 24 HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
<> 144:ef7eb2e8f9f7 25 structure declared by the function caller.
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 (+) Access NAND flash memory by read/write operations using the functions
<> 144:ef7eb2e8f9f7 28 HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
<> 144:ef7eb2e8f9f7 29 to read/write page(s)/spare area(s). These functions use specific device
<> 144:ef7eb2e8f9f7 30 information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
<> 144:ef7eb2e8f9f7 31 structure. The read/write address information is contained by the Nand_Address_Typedef
<> 144:ef7eb2e8f9f7 32 structure passed as parameter.
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
<> 144:ef7eb2e8f9f7 37 The erase block address information is contained in the Nand_Address_Typedef
<> 144:ef7eb2e8f9f7 38 structure passed as parameter.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
<> 144:ef7eb2e8f9f7 43 HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
<> 144:ef7eb2e8f9f7 44 feature or the function HAL_NAND_GetECC() to get the ECC correction code.
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 (+) You can monitor the NAND device HAL state by calling the function
<> 144:ef7eb2e8f9f7 47 HAL_NAND_GetState()
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 [..]
<> 144:ef7eb2e8f9f7 50 (@) This driver is a set of generic APIs which handle standard NAND flash operations.
<> 144:ef7eb2e8f9f7 51 If a NAND flash device contains different operations and/or implementations,
<> 144:ef7eb2e8f9f7 52 it should be implemented separately.
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 @endverbatim
<> 144:ef7eb2e8f9f7 55 ******************************************************************************
<> 144:ef7eb2e8f9f7 56 * @attention
<> 144:ef7eb2e8f9f7 57 *
<> 144:ef7eb2e8f9f7 58 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 59 *
<> 144:ef7eb2e8f9f7 60 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 61 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 62 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 63 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 65 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 66 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 68 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 69 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 70 *
<> 144:ef7eb2e8f9f7 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 81 *
<> 144:ef7eb2e8f9f7 82 ******************************************************************************
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 86 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 89 * @{
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 #ifdef HAL_NAND_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /** @defgroup NAND NAND
<> 144:ef7eb2e8f9f7 97 * @brief NAND HAL module driver
<> 144:ef7eb2e8f9f7 98 * @{
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 102 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 103 /** @defgroup NAND_Private_Constants NAND Private Constants
<> 144:ef7eb2e8f9f7 104 * @{
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /**
<> 144:ef7eb2e8f9f7 108 * @}
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 112 /** @defgroup NAND_Private_Macros NAND Private Macros
<> 144:ef7eb2e8f9f7 113 * @{
<> 144:ef7eb2e8f9f7 114 */
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /**
<> 144:ef7eb2e8f9f7 117 * @}
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 121 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 122 /** @defgroup NAND_Private_Functions NAND Private Functions
<> 144:ef7eb2e8f9f7 123 * @{
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125 static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address);
<> 144:ef7eb2e8f9f7 126 /**
<> 144:ef7eb2e8f9f7 127 * @}
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /** @defgroup NAND_Exported_Functions NAND Exported Functions
<> 144:ef7eb2e8f9f7 133 * @{
<> 144:ef7eb2e8f9f7 134 */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 137 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 138 *
<> 144:ef7eb2e8f9f7 139 @verbatim
<> 144:ef7eb2e8f9f7 140 ==============================================================================
<> 144:ef7eb2e8f9f7 141 ##### NAND Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 142 ==============================================================================
<> 144:ef7eb2e8f9f7 143 [..]
<> 144:ef7eb2e8f9f7 144 This section provides functions allowing to initialize/de-initialize
<> 144:ef7eb2e8f9f7 145 the NAND memory
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 @endverbatim
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /**
<> 144:ef7eb2e8f9f7 152 * @brief Perform NAND memory Initialization sequence
<> 144:ef7eb2e8f9f7 153 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 154 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 155 * @param ComSpace_Timing: pointer to Common space timing structure
<> 144:ef7eb2e8f9f7 156 * @param AttSpace_Timing: pointer to Attribute space timing structure
<> 144:ef7eb2e8f9f7 157 * @retval HAL status
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
<> 144:ef7eb2e8f9f7 160 {
<> 144:ef7eb2e8f9f7 161 /* Check the NAND handle state */
<> 144:ef7eb2e8f9f7 162 if(hnand == NULL)
<> 144:ef7eb2e8f9f7 163 {
<> 144:ef7eb2e8f9f7 164 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 if(hnand->State == HAL_NAND_STATE_RESET)
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 170 hnand->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 173 HAL_NAND_MspInit(hnand);
<> 144:ef7eb2e8f9f7 174 }
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /* Initialize NAND control Interface */
<> 144:ef7eb2e8f9f7 177 FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /* Initialize NAND common space timing Interface */
<> 144:ef7eb2e8f9f7 180 FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Initialize NAND attribute space timing Interface */
<> 144:ef7eb2e8f9f7 183 FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* Enable the NAND device */
<> 144:ef7eb2e8f9f7 186 __FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 189 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 return HAL_OK;
<> 144:ef7eb2e8f9f7 192 }
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /**
<> 144:ef7eb2e8f9f7 195 * @brief Perform NAND memory De-Initialization sequence
<> 144:ef7eb2e8f9f7 196 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 197 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 198 * @retval HAL status
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 201 {
<> 144:ef7eb2e8f9f7 202 /* Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 203 HAL_NAND_MspDeInit(hnand);
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /* Configure the NAND registers with their reset values */
<> 144:ef7eb2e8f9f7 206 FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Reset the NAND controller state */
<> 144:ef7eb2e8f9f7 209 hnand->State = HAL_NAND_STATE_RESET;
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /* Release Lock */
<> 144:ef7eb2e8f9f7 212 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 return HAL_OK;
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @brief NAND MSP Init
<> 144:ef7eb2e8f9f7 219 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 220 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 221 * @retval None
<> 144:ef7eb2e8f9f7 222 */
<> 144:ef7eb2e8f9f7 223 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 224 {
<> 144:ef7eb2e8f9f7 225 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 226 UNUSED(hnand);
<> 144:ef7eb2e8f9f7 227 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 228 the HAL_NAND_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 }
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /**
<> 144:ef7eb2e8f9f7 233 * @brief NAND MSP DeInit
<> 144:ef7eb2e8f9f7 234 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 235 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 236 * @retval None
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 239 {
<> 144:ef7eb2e8f9f7 240 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 241 UNUSED(hnand);
<> 144:ef7eb2e8f9f7 242 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 243 the HAL_NAND_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245 }
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /**
<> 144:ef7eb2e8f9f7 249 * @brief This function handles NAND device interrupt request.
<> 144:ef7eb2e8f9f7 250 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 251 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 252 * @retval HAL status
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 255 {
<> 144:ef7eb2e8f9f7 256 /* Check NAND interrupt Rising edge flag */
<> 144:ef7eb2e8f9f7 257 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 /* NAND interrupt callback*/
<> 144:ef7eb2e8f9f7 260 HAL_NAND_ITCallback(hnand);
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /* Clear NAND interrupt Rising edge pending bit */
<> 144:ef7eb2e8f9f7 263 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
<> 144:ef7eb2e8f9f7 264 }
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /* Check NAND interrupt Level flag */
<> 144:ef7eb2e8f9f7 267 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 /* NAND interrupt callback*/
<> 144:ef7eb2e8f9f7 270 HAL_NAND_ITCallback(hnand);
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /* Clear NAND interrupt Level pending bit */
<> 144:ef7eb2e8f9f7 273 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* Check NAND interrupt Falling edge flag */
<> 144:ef7eb2e8f9f7 277 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
<> 144:ef7eb2e8f9f7 278 {
<> 144:ef7eb2e8f9f7 279 /* NAND interrupt callback*/
<> 144:ef7eb2e8f9f7 280 HAL_NAND_ITCallback(hnand);
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* Clear NAND interrupt Falling edge pending bit */
<> 144:ef7eb2e8f9f7 283 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* Check NAND interrupt FIFO empty flag */
<> 144:ef7eb2e8f9f7 287 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 /* NAND interrupt callback*/
<> 144:ef7eb2e8f9f7 290 HAL_NAND_ITCallback(hnand);
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /* Clear NAND interrupt FIFO empty pending bit */
<> 144:ef7eb2e8f9f7 293 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 }
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /**
<> 144:ef7eb2e8f9f7 299 * @brief NAND interrupt feature callback
<> 144:ef7eb2e8f9f7 300 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 301 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 302 * @retval None
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 305 {
<> 144:ef7eb2e8f9f7 306 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 307 UNUSED(hnand);
<> 144:ef7eb2e8f9f7 308 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 309 the HAL_NAND_ITCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 310 */
<> 144:ef7eb2e8f9f7 311 }
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /**
<> 144:ef7eb2e8f9f7 314 * @}
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
<> 144:ef7eb2e8f9f7 318 * @brief Input Output and memory control functions
<> 144:ef7eb2e8f9f7 319 *
<> 144:ef7eb2e8f9f7 320 @verbatim
<> 144:ef7eb2e8f9f7 321 ==============================================================================
<> 144:ef7eb2e8f9f7 322 ##### NAND Input and Output functions #####
<> 144:ef7eb2e8f9f7 323 ==============================================================================
<> 144:ef7eb2e8f9f7 324 [..]
<> 144:ef7eb2e8f9f7 325 This section provides functions allowing to use and control the NAND
<> 144:ef7eb2e8f9f7 326 memory
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 @endverbatim
<> 144:ef7eb2e8f9f7 329 * @{
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /**
<> 144:ef7eb2e8f9f7 333 * @brief Read the NAND memory electronic signature
<> 144:ef7eb2e8f9f7 334 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 335 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 336 * @param pNAND_ID: NAND ID structure
<> 144:ef7eb2e8f9f7 337 * @retval HAL status
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 __IO uint32_t data = 0;
<> 144:ef7eb2e8f9f7 342 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /* Process Locked */
<> 144:ef7eb2e8f9f7 345 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 348 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 349 {
<> 144:ef7eb2e8f9f7 350 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 351 }
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /* Identify the device address */
<> 144:ef7eb2e8f9f7 354 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 deviceaddress = NAND_DEVICE1;
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358 else
<> 144:ef7eb2e8f9f7 359 {
<> 144:ef7eb2e8f9f7 360 deviceaddress = NAND_DEVICE2;
<> 144:ef7eb2e8f9f7 361 }
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 364 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /* Send Read ID command sequence */
<> 144:ef7eb2e8f9f7 367 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
<> 144:ef7eb2e8f9f7 368 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Read the electronic signature from NAND flash */
<> 144:ef7eb2e8f9f7 371 data = *(__IO uint32_t *)deviceaddress;
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /* Return the data read */
<> 144:ef7eb2e8f9f7 374 pNAND_ID->Maker_Id = ADDR_1st_CYCLE(data);
<> 144:ef7eb2e8f9f7 375 pNAND_ID->Device_Id = ADDR_2nd_CYCLE(data);
<> 144:ef7eb2e8f9f7 376 pNAND_ID->Third_Id = ADDR_3rd_CYCLE(data);
<> 144:ef7eb2e8f9f7 377 pNAND_ID->Fourth_Id = ADDR_4th_CYCLE(data);
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 380 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /* Process unlocked */
<> 144:ef7eb2e8f9f7 383 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 return HAL_OK;
<> 144:ef7eb2e8f9f7 386 }
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /**
<> 144:ef7eb2e8f9f7 389 * @brief NAND memory reset
<> 144:ef7eb2e8f9f7 390 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 391 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 392 * @retval HAL status
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 395 {
<> 144:ef7eb2e8f9f7 396 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /* Process Locked */
<> 144:ef7eb2e8f9f7 399 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 402 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /* Identify the device address */
<> 144:ef7eb2e8f9f7 408 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 409 {
<> 144:ef7eb2e8f9f7 410 deviceaddress = NAND_DEVICE1;
<> 144:ef7eb2e8f9f7 411 }
<> 144:ef7eb2e8f9f7 412 else
<> 144:ef7eb2e8f9f7 413 {
<> 144:ef7eb2e8f9f7 414 deviceaddress = NAND_DEVICE2;
<> 144:ef7eb2e8f9f7 415 }
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 418 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Send NAND reset command */
<> 144:ef7eb2e8f9f7 421 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 425 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /* Process unlocked */
<> 144:ef7eb2e8f9f7 428 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 return HAL_OK;
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /**
<> 144:ef7eb2e8f9f7 435 * @brief Read Page(s) from NAND memory block
<> 144:ef7eb2e8f9f7 436 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 437 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 438 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 439 * @param pBuffer : pointer to destination read buffer
<> 144:ef7eb2e8f9f7 440 * @param NumPageToRead : number of pages to read from block
<> 144:ef7eb2e8f9f7 441 * @retval HAL status
<> 144:ef7eb2e8f9f7 442 */
<> 144:ef7eb2e8f9f7 443 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
<> 144:ef7eb2e8f9f7 444 {
<> 144:ef7eb2e8f9f7 445 __IO uint32_t index = 0;
<> 144:ef7eb2e8f9f7 446 uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
<> 144:ef7eb2e8f9f7 447 NAND_AddressTypeDef nandaddress;
<> 144:ef7eb2e8f9f7 448 uint32_t addressoffset = 0;
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /* Process Locked */
<> 144:ef7eb2e8f9f7 451 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 454 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 455 {
<> 144:ef7eb2e8f9f7 456 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /* Identify the device address */
<> 144:ef7eb2e8f9f7 460 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 461 {
<> 144:ef7eb2e8f9f7 462 deviceaddress = NAND_DEVICE1;
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464 else
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 deviceaddress = NAND_DEVICE2;
<> 144:ef7eb2e8f9f7 467 }
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 470 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* Save the content of pAddress as it will be modified */
<> 144:ef7eb2e8f9f7 473 nandaddress.Block = pAddress->Block;
<> 144:ef7eb2e8f9f7 474 nandaddress.Page = pAddress->Page;
<> 144:ef7eb2e8f9f7 475 nandaddress.Zone = pAddress->Zone;
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /* Page(s) read loop */
<> 144:ef7eb2e8f9f7 478 while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
<> 144:ef7eb2e8f9f7 479 {
<> 144:ef7eb2e8f9f7 480 /* update the buffer size */
<> 144:ef7eb2e8f9f7 481 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /* Get the address offset */
<> 144:ef7eb2e8f9f7 484 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 /* Send read page command sequence */
<> 144:ef7eb2e8f9f7 487 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
<> 144:ef7eb2e8f9f7 490 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 491 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 492 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 495 if(hnand->Info.BlockNbr >= 1024)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 498 }
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /* Get Data into Buffer */
<> 144:ef7eb2e8f9f7 503 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 504 {
<> 144:ef7eb2e8f9f7 505 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
<> 144:ef7eb2e8f9f7 506 }
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* Increment read pages number */
<> 144:ef7eb2e8f9f7 509 numpagesread++;
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /* Decrement pages to read */
<> 144:ef7eb2e8f9f7 512 NumPageToRead--;
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* Increment the NAND address */
<> 144:ef7eb2e8f9f7 515 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
<> 144:ef7eb2e8f9f7 516 }
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 519 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /* Process unlocked */
<> 144:ef7eb2e8f9f7 522 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 return HAL_OK;
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /**
<> 144:ef7eb2e8f9f7 529 * @brief Write Page(s) to NAND memory block
<> 144:ef7eb2e8f9f7 530 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 531 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 532 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 533 * @param pBuffer : pointer to source buffer to write
<> 144:ef7eb2e8f9f7 534 * @param NumPageToWrite : number of pages to write to block
<> 144:ef7eb2e8f9f7 535 * @retval HAL status
<> 144:ef7eb2e8f9f7 536 */
<> 144:ef7eb2e8f9f7 537 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
<> 144:ef7eb2e8f9f7 538 {
<> 144:ef7eb2e8f9f7 539 __IO uint32_t index = 0;
<> 144:ef7eb2e8f9f7 540 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 541 uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS;
<> 144:ef7eb2e8f9f7 542 NAND_AddressTypeDef nandaddress;
<> 144:ef7eb2e8f9f7 543 uint32_t addressoffset = 0;
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /* Process Locked */
<> 144:ef7eb2e8f9f7 546 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 549 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 550 {
<> 144:ef7eb2e8f9f7 551 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 552 }
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /* Identify the device address */
<> 144:ef7eb2e8f9f7 555 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 556 {
<> 144:ef7eb2e8f9f7 557 deviceaddress = NAND_DEVICE1;
<> 144:ef7eb2e8f9f7 558 }
<> 144:ef7eb2e8f9f7 559 else
<> 144:ef7eb2e8f9f7 560 {
<> 144:ef7eb2e8f9f7 561 deviceaddress = NAND_DEVICE2;
<> 144:ef7eb2e8f9f7 562 }
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 565 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /* Save the content of pAddress as it will be modified */
<> 144:ef7eb2e8f9f7 568 nandaddress.Block = pAddress->Block;
<> 144:ef7eb2e8f9f7 569 nandaddress.Page = pAddress->Page;
<> 144:ef7eb2e8f9f7 570 nandaddress.Zone = pAddress->Zone;
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /* Page(s) write loop */
<> 144:ef7eb2e8f9f7 573 while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
<> 144:ef7eb2e8f9f7 574 {
<> 144:ef7eb2e8f9f7 575 /* update the buffer size */
<> 144:ef7eb2e8f9f7 576 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /* Get the address offset */
<> 144:ef7eb2e8f9f7 579 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /* Send write page command sequence */
<> 144:ef7eb2e8f9f7 582 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
<> 144:ef7eb2e8f9f7 583 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
<> 144:ef7eb2e8f9f7 586 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 587 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 588 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 591 if(hnand->Info.BlockNbr >= 1024)
<> 144:ef7eb2e8f9f7 592 {
<> 144:ef7eb2e8f9f7 593 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 594 }
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /* Write data to memory */
<> 144:ef7eb2e8f9f7 597 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 598 {
<> 144:ef7eb2e8f9f7 599 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
<> 144:ef7eb2e8f9f7 600 }
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Get tick */
<> 144:ef7eb2e8f9f7 605 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /* Read status until NAND is ready */
<> 144:ef7eb2e8f9f7 608 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<> 144:ef7eb2e8f9f7 609 {
<> 144:ef7eb2e8f9f7 610 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<> 144:ef7eb2e8f9f7 611 {
<> 144:ef7eb2e8f9f7 612 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 613 }
<> 144:ef7eb2e8f9f7 614 }
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /* Increment written pages number */
<> 144:ef7eb2e8f9f7 617 numpageswritten++;
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /* Decrement pages to write */
<> 144:ef7eb2e8f9f7 620 NumPageToWrite--;
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /* Increment the NAND address */
<> 144:ef7eb2e8f9f7 623 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
<> 144:ef7eb2e8f9f7 624 }
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 627 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /* Process unlocked */
<> 144:ef7eb2e8f9f7 630 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 return HAL_OK;
<> 144:ef7eb2e8f9f7 633 }
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /**
<> 144:ef7eb2e8f9f7 636 * @brief Read Spare area(s) from NAND memory
<> 144:ef7eb2e8f9f7 637 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 638 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 639 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 640 * @param pBuffer: pointer to source buffer to write
<> 144:ef7eb2e8f9f7 641 * @param NumSpareAreaToRead: Number of spare area to read
<> 144:ef7eb2e8f9f7 642 * @retval HAL status
<> 144:ef7eb2e8f9f7 643 */
<> 144:ef7eb2e8f9f7 644 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
<> 144:ef7eb2e8f9f7 645 {
<> 144:ef7eb2e8f9f7 646 __IO uint32_t index = 0;
<> 144:ef7eb2e8f9f7 647 uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
<> 144:ef7eb2e8f9f7 648 NAND_AddressTypeDef nandaddress;
<> 144:ef7eb2e8f9f7 649 uint32_t addressoffset = 0;
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /* Process Locked */
<> 144:ef7eb2e8f9f7 652 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 655 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 656 {
<> 144:ef7eb2e8f9f7 657 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 658 }
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /* Identify the device address */
<> 144:ef7eb2e8f9f7 661 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 662 {
<> 144:ef7eb2e8f9f7 663 deviceaddress = NAND_DEVICE1;
<> 144:ef7eb2e8f9f7 664 }
<> 144:ef7eb2e8f9f7 665 else
<> 144:ef7eb2e8f9f7 666 {
<> 144:ef7eb2e8f9f7 667 deviceaddress = NAND_DEVICE2;
<> 144:ef7eb2e8f9f7 668 }
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 671 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /* Save the content of pAddress as it will be modified */
<> 144:ef7eb2e8f9f7 674 nandaddress.Block = pAddress->Block;
<> 144:ef7eb2e8f9f7 675 nandaddress.Page = pAddress->Page;
<> 144:ef7eb2e8f9f7 676 nandaddress.Zone = pAddress->Zone;
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /* Spare area(s) read loop */
<> 144:ef7eb2e8f9f7 679 while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
<> 144:ef7eb2e8f9f7 680 {
<> 144:ef7eb2e8f9f7 681 /* update the buffer size */
<> 144:ef7eb2e8f9f7 682 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /* Get the address offset */
<> 144:ef7eb2e8f9f7 685 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /* Send read spare area command sequence */
<> 144:ef7eb2e8f9f7 688 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
<> 144:ef7eb2e8f9f7 691 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 692 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 693 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 696 if(hnand->Info.BlockNbr >= 1024)
<> 144:ef7eb2e8f9f7 697 {
<> 144:ef7eb2e8f9f7 698 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 699 }
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /* Get Data into Buffer */
<> 144:ef7eb2e8f9f7 704 for ( ;index < size; index++)
<> 144:ef7eb2e8f9f7 705 {
<> 144:ef7eb2e8f9f7 706 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
<> 144:ef7eb2e8f9f7 707 }
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /* Increment read spare areas number */
<> 144:ef7eb2e8f9f7 710 num_spare_area_read++;
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 /* Decrement spare areas to read */
<> 144:ef7eb2e8f9f7 713 NumSpareAreaToRead--;
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /* Increment the NAND address */
<> 144:ef7eb2e8f9f7 716 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
<> 144:ef7eb2e8f9f7 717 }
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 720 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 /* Process unlocked */
<> 144:ef7eb2e8f9f7 723 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 return HAL_OK;
<> 144:ef7eb2e8f9f7 726 }
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /**
<> 144:ef7eb2e8f9f7 729 * @brief Write Spare area(s) to NAND memory
<> 144:ef7eb2e8f9f7 730 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 731 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 732 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 733 * @param pBuffer : pointer to source buffer to write
<> 144:ef7eb2e8f9f7 734 * @param NumSpareAreaTowrite : number of spare areas to write to block
<> 144:ef7eb2e8f9f7 735 * @retval HAL status
<> 144:ef7eb2e8f9f7 736 */
<> 144:ef7eb2e8f9f7 737 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
<> 144:ef7eb2e8f9f7 738 {
<> 144:ef7eb2e8f9f7 739 __IO uint32_t index = 0;
<> 144:ef7eb2e8f9f7 740 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 741 uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
<> 144:ef7eb2e8f9f7 742 NAND_AddressTypeDef nandaddress;
<> 144:ef7eb2e8f9f7 743 uint32_t addressoffset = 0;
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /* Process Locked */
<> 144:ef7eb2e8f9f7 746 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 749 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 750 {
<> 144:ef7eb2e8f9f7 751 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 752 }
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /* Identify the device address */
<> 144:ef7eb2e8f9f7 755 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 756 {
<> 144:ef7eb2e8f9f7 757 deviceaddress = NAND_DEVICE1;
<> 144:ef7eb2e8f9f7 758 }
<> 144:ef7eb2e8f9f7 759 else
<> 144:ef7eb2e8f9f7 760 {
<> 144:ef7eb2e8f9f7 761 deviceaddress = NAND_DEVICE2;
<> 144:ef7eb2e8f9f7 762 }
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /* Update the FSMC_NAND controller state */
<> 144:ef7eb2e8f9f7 765 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /* Save the content of pAddress as it will be modified */
<> 144:ef7eb2e8f9f7 768 nandaddress.Block = pAddress->Block;
<> 144:ef7eb2e8f9f7 769 nandaddress.Page = pAddress->Page;
<> 144:ef7eb2e8f9f7 770 nandaddress.Zone = pAddress->Zone;
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 /* Spare area(s) write loop */
<> 144:ef7eb2e8f9f7 773 while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
<> 144:ef7eb2e8f9f7 774 {
<> 144:ef7eb2e8f9f7 775 /* update the buffer size */
<> 144:ef7eb2e8f9f7 776 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 /* Get the address offset */
<> 144:ef7eb2e8f9f7 779 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 /* Send write Spare area command sequence */
<> 144:ef7eb2e8f9f7 782 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
<> 144:ef7eb2e8f9f7 783 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
<> 144:ef7eb2e8f9f7 786 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 787 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 788 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 791 if(hnand->Info.BlockNbr >= 1024)
<> 144:ef7eb2e8f9f7 792 {
<> 144:ef7eb2e8f9f7 793 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 794 }
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /* Write data to memory */
<> 144:ef7eb2e8f9f7 797 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 798 {
<> 144:ef7eb2e8f9f7 799 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
<> 144:ef7eb2e8f9f7 800 }
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /* Get tick */
<> 144:ef7eb2e8f9f7 805 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 /* Read status until NAND is ready */
<> 144:ef7eb2e8f9f7 808 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<> 144:ef7eb2e8f9f7 809 {
<> 144:ef7eb2e8f9f7 810 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<> 144:ef7eb2e8f9f7 811 {
<> 144:ef7eb2e8f9f7 812 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 813 }
<> 144:ef7eb2e8f9f7 814 }
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /* Increment written spare areas number */
<> 144:ef7eb2e8f9f7 817 num_spare_area_written++;
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 /* Decrement spare areas to write */
<> 144:ef7eb2e8f9f7 820 NumSpareAreaTowrite--;
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /* Increment the NAND address */
<> 144:ef7eb2e8f9f7 823 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
<> 144:ef7eb2e8f9f7 824 }
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 827 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /* Process unlocked */
<> 144:ef7eb2e8f9f7 830 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 return HAL_OK;
<> 144:ef7eb2e8f9f7 833 }
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 /**
<> 144:ef7eb2e8f9f7 836 * @brief NAND memory Block erase
<> 144:ef7eb2e8f9f7 837 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 838 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 839 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 840 * @retval HAL status
<> 144:ef7eb2e8f9f7 841 */
<> 144:ef7eb2e8f9f7 842 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
<> 144:ef7eb2e8f9f7 843 {
<> 144:ef7eb2e8f9f7 844 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 845 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /* Process Locked */
<> 144:ef7eb2e8f9f7 848 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 851 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 852 {
<> 144:ef7eb2e8f9f7 853 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 854 }
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /* Identify the device address */
<> 144:ef7eb2e8f9f7 857 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 858 {
<> 144:ef7eb2e8f9f7 859 deviceaddress = NAND_DEVICE1;
<> 144:ef7eb2e8f9f7 860 }
<> 144:ef7eb2e8f9f7 861 else
<> 144:ef7eb2e8f9f7 862 {
<> 144:ef7eb2e8f9f7 863 deviceaddress = NAND_DEVICE2;
<> 144:ef7eb2e8f9f7 864 }
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 867 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /* Send Erase block command sequence */
<> 144:ef7eb2e8f9f7 870 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<> 144:ef7eb2e8f9f7 873 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<> 144:ef7eb2e8f9f7 874 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 877 if(hnand->Info.BlockNbr >= 1024)
<> 144:ef7eb2e8f9f7 878 {
<> 144:ef7eb2e8f9f7 879 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<> 144:ef7eb2e8f9f7 880 }
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 885 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 /* Get tick */
<> 144:ef7eb2e8f9f7 888 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /* Read status until NAND is ready */
<> 144:ef7eb2e8f9f7 891 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<> 144:ef7eb2e8f9f7 892 {
<> 144:ef7eb2e8f9f7 893 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<> 144:ef7eb2e8f9f7 894 {
<> 144:ef7eb2e8f9f7 895 /* Process unlocked */
<> 144:ef7eb2e8f9f7 896 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 899 }
<> 144:ef7eb2e8f9f7 900 }
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902 /* Process unlocked */
<> 144:ef7eb2e8f9f7 903 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 return HAL_OK;
<> 144:ef7eb2e8f9f7 906 }
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 /**
<> 144:ef7eb2e8f9f7 909 * @brief NAND memory read status
<> 144:ef7eb2e8f9f7 910 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 911 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 912 * @retval NAND status
<> 144:ef7eb2e8f9f7 913 */
<> 144:ef7eb2e8f9f7 914 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 915 {
<> 144:ef7eb2e8f9f7 916 uint32_t data = 0;
<> 144:ef7eb2e8f9f7 917 uint32_t deviceaddress = 0;
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /* Identify the device address */
<> 144:ef7eb2e8f9f7 920 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 921 {
<> 144:ef7eb2e8f9f7 922 deviceaddress = NAND_DEVICE1;
<> 144:ef7eb2e8f9f7 923 }
<> 144:ef7eb2e8f9f7 924 else
<> 144:ef7eb2e8f9f7 925 {
<> 144:ef7eb2e8f9f7 926 deviceaddress = NAND_DEVICE2;
<> 144:ef7eb2e8f9f7 927 }
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /* Send Read status operation command */
<> 144:ef7eb2e8f9f7 930 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 /* Read status register data */
<> 144:ef7eb2e8f9f7 933 data = *(__IO uint8_t *)deviceaddress;
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /* Return the status */
<> 144:ef7eb2e8f9f7 936 if((data & NAND_ERROR) == NAND_ERROR)
<> 144:ef7eb2e8f9f7 937 {
<> 144:ef7eb2e8f9f7 938 return NAND_ERROR;
<> 144:ef7eb2e8f9f7 939 }
<> 144:ef7eb2e8f9f7 940 else if((data & NAND_READY) == NAND_READY)
<> 144:ef7eb2e8f9f7 941 {
<> 144:ef7eb2e8f9f7 942 return NAND_READY;
<> 144:ef7eb2e8f9f7 943 }
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 return NAND_BUSY;
<> 144:ef7eb2e8f9f7 946 }
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 /**
<> 144:ef7eb2e8f9f7 949 * @brief Increment the NAND memory address
<> 144:ef7eb2e8f9f7 950 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 951 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 952 * @param pAddress: pointer to NAND address structure
<> 144:ef7eb2e8f9f7 953 * @retval The new status of the increment address operation. It can be:
<> 144:ef7eb2e8f9f7 954 * - NAND_VALID_ADDRESS: When the new address is valid address
<> 144:ef7eb2e8f9f7 955 * - NAND_INVALID_ADDRESS: When the new address is invalid address
<> 144:ef7eb2e8f9f7 956 */
<> 144:ef7eb2e8f9f7 957 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
<> 144:ef7eb2e8f9f7 958 {
<> 144:ef7eb2e8f9f7 959 uint32_t status = NAND_VALID_ADDRESS;
<> 144:ef7eb2e8f9f7 960
<> 144:ef7eb2e8f9f7 961 /* Increment page address */
<> 144:ef7eb2e8f9f7 962 pAddress->Page++;
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 /* Check NAND address is valid */
<> 144:ef7eb2e8f9f7 965 if(pAddress->Page == hnand->Info.BlockSize)
<> 144:ef7eb2e8f9f7 966 {
<> 144:ef7eb2e8f9f7 967 pAddress->Page = 0;
<> 144:ef7eb2e8f9f7 968 pAddress->Block++;
<> 144:ef7eb2e8f9f7 969
<> 144:ef7eb2e8f9f7 970 if(pAddress->Block == hnand->Info.ZoneSize)
<> 144:ef7eb2e8f9f7 971 {
<> 144:ef7eb2e8f9f7 972 pAddress->Block = 0;
<> 144:ef7eb2e8f9f7 973 pAddress->Zone++;
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
<> 144:ef7eb2e8f9f7 976 {
<> 144:ef7eb2e8f9f7 977 status = NAND_INVALID_ADDRESS;
<> 144:ef7eb2e8f9f7 978 }
<> 144:ef7eb2e8f9f7 979 }
<> 144:ef7eb2e8f9f7 980 }
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982 return (status);
<> 144:ef7eb2e8f9f7 983 }
<> 144:ef7eb2e8f9f7 984 /**
<> 144:ef7eb2e8f9f7 985 * @}
<> 144:ef7eb2e8f9f7 986 */
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 989 * @brief management functions
<> 144:ef7eb2e8f9f7 990 *
<> 144:ef7eb2e8f9f7 991 @verbatim
<> 144:ef7eb2e8f9f7 992 ==============================================================================
<> 144:ef7eb2e8f9f7 993 ##### NAND Control functions #####
<> 144:ef7eb2e8f9f7 994 ==============================================================================
<> 144:ef7eb2e8f9f7 995 [..]
<> 144:ef7eb2e8f9f7 996 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 997 the NAND interface.
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 @endverbatim
<> 144:ef7eb2e8f9f7 1000 * @{
<> 144:ef7eb2e8f9f7 1001 */
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 /**
<> 144:ef7eb2e8f9f7 1005 * @brief Enables dynamically NAND ECC feature.
<> 144:ef7eb2e8f9f7 1006 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1007 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 1008 * @retval HAL status
<> 144:ef7eb2e8f9f7 1009 */
<> 144:ef7eb2e8f9f7 1010 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 1011 {
<> 144:ef7eb2e8f9f7 1012 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 1013 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 1014 {
<> 144:ef7eb2e8f9f7 1015 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1016 }
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1019 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 /* Enable ECC feature */
<> 144:ef7eb2e8f9f7 1022 FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 1023
<> 144:ef7eb2e8f9f7 1024 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1025 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 return HAL_OK;
<> 144:ef7eb2e8f9f7 1028 }
<> 144:ef7eb2e8f9f7 1029
<> 144:ef7eb2e8f9f7 1030 /**
<> 144:ef7eb2e8f9f7 1031 * @brief Disables dynamically FSMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 1032 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1033 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 1034 * @retval HAL status
<> 144:ef7eb2e8f9f7 1035 */
<> 144:ef7eb2e8f9f7 1036 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 1037 {
<> 144:ef7eb2e8f9f7 1038 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 1039 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 1040 {
<> 144:ef7eb2e8f9f7 1041 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1042 }
<> 144:ef7eb2e8f9f7 1043
<> 144:ef7eb2e8f9f7 1044 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1045 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 /* Disable ECC feature */
<> 144:ef7eb2e8f9f7 1048 FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 1049
<> 144:ef7eb2e8f9f7 1050 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1051 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 1052
<> 144:ef7eb2e8f9f7 1053 return HAL_OK;
<> 144:ef7eb2e8f9f7 1054 }
<> 144:ef7eb2e8f9f7 1055
<> 144:ef7eb2e8f9f7 1056 /**
<> 144:ef7eb2e8f9f7 1057 * @brief Disables dynamically NAND ECC feature.
<> 144:ef7eb2e8f9f7 1058 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1059 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 1060 * @param ECCval: pointer to ECC value
<> 144:ef7eb2e8f9f7 1061 * @param Timeout: maximum timeout to wait
<> 144:ef7eb2e8f9f7 1062 * @retval HAL status
<> 144:ef7eb2e8f9f7 1063 */
<> 144:ef7eb2e8f9f7 1064 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1065 {
<> 144:ef7eb2e8f9f7 1066 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1067
<> 144:ef7eb2e8f9f7 1068 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 1069 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 1070 {
<> 144:ef7eb2e8f9f7 1071 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1072 }
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1075 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1076
<> 144:ef7eb2e8f9f7 1077 /* Get NAND ECC value */
<> 144:ef7eb2e8f9f7 1078 status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
<> 144:ef7eb2e8f9f7 1079
<> 144:ef7eb2e8f9f7 1080 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1081 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 1082
<> 144:ef7eb2e8f9f7 1083 return status;
<> 144:ef7eb2e8f9f7 1084 }
<> 144:ef7eb2e8f9f7 1085
<> 144:ef7eb2e8f9f7 1086 /**
<> 144:ef7eb2e8f9f7 1087 * @}
<> 144:ef7eb2e8f9f7 1088 */
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090
<> 144:ef7eb2e8f9f7 1091 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
<> 144:ef7eb2e8f9f7 1092 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 1093 *
<> 144:ef7eb2e8f9f7 1094 @verbatim
<> 144:ef7eb2e8f9f7 1095 ==============================================================================
<> 144:ef7eb2e8f9f7 1096 ##### NAND State functions #####
<> 144:ef7eb2e8f9f7 1097 ==============================================================================
<> 144:ef7eb2e8f9f7 1098 [..]
<> 144:ef7eb2e8f9f7 1099 This subsection permits to get in run-time the status of the NAND controller
<> 144:ef7eb2e8f9f7 1100 and the data flow.
<> 144:ef7eb2e8f9f7 1101
<> 144:ef7eb2e8f9f7 1102 @endverbatim
<> 144:ef7eb2e8f9f7 1103 * @{
<> 144:ef7eb2e8f9f7 1104 */
<> 144:ef7eb2e8f9f7 1105
<> 144:ef7eb2e8f9f7 1106 /**
<> 144:ef7eb2e8f9f7 1107 * @brief return the NAND state
<> 144:ef7eb2e8f9f7 1108 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1109 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 1110 * @retval HAL state
<> 144:ef7eb2e8f9f7 1111 */
<> 144:ef7eb2e8f9f7 1112 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 1113 {
<> 144:ef7eb2e8f9f7 1114 return hnand->State;
<> 144:ef7eb2e8f9f7 1115 }
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 /**
<> 144:ef7eb2e8f9f7 1118 * @}
<> 144:ef7eb2e8f9f7 1119 */
<> 144:ef7eb2e8f9f7 1120
<> 144:ef7eb2e8f9f7 1121 /**
<> 144:ef7eb2e8f9f7 1122 * @}
<> 144:ef7eb2e8f9f7 1123 */
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 /** @addtogroup NAND_Private_Functions
<> 144:ef7eb2e8f9f7 1126 * @{
<> 144:ef7eb2e8f9f7 1127 */
<> 144:ef7eb2e8f9f7 1128
<> 144:ef7eb2e8f9f7 1129 /**
<> 144:ef7eb2e8f9f7 1130 * @brief Increment the NAND memory address.
<> 144:ef7eb2e8f9f7 1131 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1132 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 1133 * @param Address: address to be incremented.
<> 144:ef7eb2e8f9f7 1134 * @retval The new status of the increment address operation. It can be:
<> 144:ef7eb2e8f9f7 1135 * - NAND_VALID_ADDRESS: When the new address is valid address
<> 144:ef7eb2e8f9f7 1136 * - NAND_INVALID_ADDRESS: When the new address is invalid address
<> 144:ef7eb2e8f9f7 1137 */
<> 144:ef7eb2e8f9f7 1138 static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address)
<> 144:ef7eb2e8f9f7 1139 {
<> 144:ef7eb2e8f9f7 1140 uint32_t status = NAND_VALID_ADDRESS;
<> 144:ef7eb2e8f9f7 1141
<> 144:ef7eb2e8f9f7 1142 Address->Page++;
<> 144:ef7eb2e8f9f7 1143
<> 144:ef7eb2e8f9f7 1144 if(Address->Page == hnand->Info.BlockSize)
<> 144:ef7eb2e8f9f7 1145 {
<> 144:ef7eb2e8f9f7 1146 Address->Page = 0;
<> 144:ef7eb2e8f9f7 1147 Address->Block++;
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 if(Address->Block == hnand->Info.ZoneSize)
<> 144:ef7eb2e8f9f7 1150 {
<> 144:ef7eb2e8f9f7 1151 Address->Block = 0;
<> 144:ef7eb2e8f9f7 1152 Address->Zone++;
<> 144:ef7eb2e8f9f7 1153
<> 144:ef7eb2e8f9f7 1154 if(Address->Zone == hnand->Info.BlockNbr)
<> 144:ef7eb2e8f9f7 1155 {
<> 144:ef7eb2e8f9f7 1156 status = NAND_INVALID_ADDRESS;
<> 144:ef7eb2e8f9f7 1157 }
<> 144:ef7eb2e8f9f7 1158 }
<> 144:ef7eb2e8f9f7 1159 }
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 return (status);
<> 144:ef7eb2e8f9f7 1162 }
<> 144:ef7eb2e8f9f7 1163
<> 144:ef7eb2e8f9f7 1164 /**
<> 144:ef7eb2e8f9f7 1165 * @}
<> 144:ef7eb2e8f9f7 1166 */
<> 144:ef7eb2e8f9f7 1167
<> 144:ef7eb2e8f9f7 1168 /**
<> 144:ef7eb2e8f9f7 1169 * @}
<> 144:ef7eb2e8f9f7 1170 */
<> 144:ef7eb2e8f9f7 1171
<> 144:ef7eb2e8f9f7 1172 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
<> 144:ef7eb2e8f9f7 1173 #endif /* HAL_NAND_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1174
<> 144:ef7eb2e8f9f7 1175 /**
<> 144:ef7eb2e8f9f7 1176 * @}
<> 144:ef7eb2e8f9f7 1177 */
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/