Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_nand.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
124:6a4a5b7d7324
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f1xx_hal_nand.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 15-December-2014
bogdanm 0:9b334a45a8ff 7 * @brief NAND HAL module driver.
bogdanm 0:9b334a45a8ff 8 * This file provides a generic firmware to drive NAND memories mounted
bogdanm 0:9b334a45a8ff 9 * as external device.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 @verbatim
bogdanm 0:9b334a45a8ff 12 ==============================================================================
bogdanm 0:9b334a45a8ff 13 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 14 ==============================================================================
bogdanm 0:9b334a45a8ff 15 [..]
bogdanm 0:9b334a45a8ff 16 This driver is a generic layered driver which contains a set of APIs used to
bogdanm 0:9b334a45a8ff 17 control NAND flash memories. It uses the FSMC/FSMC layer functions to interface
bogdanm 0:9b334a45a8ff 18 with NAND devices. This driver is used as follows:
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
bogdanm 0:9b334a45a8ff 21 with control and timing parameters for both common and attribute spaces.
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 (+) Read NAND flash memory maker and device IDs using the function
bogdanm 0:9b334a45a8ff 24 HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
bogdanm 0:9b334a45a8ff 25 structure declared by the function caller.
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 (+) Access NAND flash memory by read/write operations using the functions
bogdanm 0:9b334a45a8ff 28 HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
bogdanm 0:9b334a45a8ff 29 to read/write page(s)/spare area(s). These functions use specific device
bogdanm 0:9b334a45a8ff 30 information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
bogdanm 0:9b334a45a8ff 31 structure. The read/write address information is contained by the Nand_Address_Typedef
bogdanm 0:9b334a45a8ff 32 structure passed as parameter.
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
bogdanm 0:9b334a45a8ff 35
bogdanm 0:9b334a45a8ff 36 (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
bogdanm 0:9b334a45a8ff 37 The erase block address information is contained in the Nand_Address_Typedef
bogdanm 0:9b334a45a8ff 38 structure passed as parameter.
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
bogdanm 0:9b334a45a8ff 43 HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
bogdanm 0:9b334a45a8ff 44 feature or the function HAL_NAND_GetECC() to get the ECC correction code.
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 (+) You can monitor the NAND device HAL state by calling the function
bogdanm 0:9b334a45a8ff 47 HAL_NAND_GetState()
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 [..]
bogdanm 0:9b334a45a8ff 50 (@) This driver is a set of generic APIs which handle standard NAND flash operations.
bogdanm 0:9b334a45a8ff 51 If a NAND flash device contains different operations and/or implementations,
bogdanm 0:9b334a45a8ff 52 it should be implemented separately.
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 @endverbatim
bogdanm 0:9b334a45a8ff 55 ******************************************************************************
bogdanm 0:9b334a45a8ff 56 * @attention
bogdanm 0:9b334a45a8ff 57 *
bogdanm 0:9b334a45a8ff 58 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 59 *
bogdanm 0:9b334a45a8ff 60 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 61 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 62 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 63 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 65 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 66 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 68 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 69 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 70 *
bogdanm 0:9b334a45a8ff 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 81 *
bogdanm 0:9b334a45a8ff 82 ******************************************************************************
bogdanm 0:9b334a45a8ff 83 */
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 86 #include "stm32f1xx_hal.h"
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 /** @addtogroup STM32F1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 89 * @{
bogdanm 0:9b334a45a8ff 90 */
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 #ifdef HAL_NAND_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 /** @defgroup NAND NAND
bogdanm 0:9b334a45a8ff 97 * @brief NAND HAL module driver
bogdanm 0:9b334a45a8ff 98 * @{
bogdanm 0:9b334a45a8ff 99 */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 102 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 103 /** @defgroup NAND_Private_Constants NAND Private Constants
bogdanm 0:9b334a45a8ff 104 * @{
bogdanm 0:9b334a45a8ff 105 */
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 /**
bogdanm 0:9b334a45a8ff 108 * @}
bogdanm 0:9b334a45a8ff 109 */
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 112 /** @defgroup NAND_Private_Macros NAND Private Macros
bogdanm 0:9b334a45a8ff 113 * @{
bogdanm 0:9b334a45a8ff 114 */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 /**
bogdanm 0:9b334a45a8ff 117 * @}
bogdanm 0:9b334a45a8ff 118 */
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 121 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 122 /** @defgroup NAND_Private_Functions NAND Private Functions
bogdanm 0:9b334a45a8ff 123 * @{
bogdanm 0:9b334a45a8ff 124 */
bogdanm 0:9b334a45a8ff 125 static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address);
bogdanm 0:9b334a45a8ff 126 /**
bogdanm 0:9b334a45a8ff 127 * @}
bogdanm 0:9b334a45a8ff 128 */
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 /* Exported functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 /** @defgroup NAND_Exported_Functions NAND Exported Functions
bogdanm 0:9b334a45a8ff 133 * @{
bogdanm 0:9b334a45a8ff 134 */
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 137 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 138 *
bogdanm 0:9b334a45a8ff 139 @verbatim
bogdanm 0:9b334a45a8ff 140 ==============================================================================
bogdanm 0:9b334a45a8ff 141 ##### NAND Initialization and de-initialization functions #####
bogdanm 0:9b334a45a8ff 142 ==============================================================================
bogdanm 0:9b334a45a8ff 143 [..]
bogdanm 0:9b334a45a8ff 144 This section provides functions allowing to initialize/de-initialize
bogdanm 0:9b334a45a8ff 145 the NAND memory
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 @endverbatim
bogdanm 0:9b334a45a8ff 148 * @{
bogdanm 0:9b334a45a8ff 149 */
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 /**
bogdanm 0:9b334a45a8ff 152 * @brief Perform NAND memory Initialization sequence
bogdanm 0:9b334a45a8ff 153 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 154 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 155 * @param ComSpace_Timing: pointer to Common space timing structure
bogdanm 0:9b334a45a8ff 156 * @param AttSpace_Timing: pointer to Attribute space timing structure
bogdanm 0:9b334a45a8ff 157 * @retval HAL status
bogdanm 0:9b334a45a8ff 158 */
bogdanm 0:9b334a45a8ff 159 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
bogdanm 0:9b334a45a8ff 160 {
bogdanm 0:9b334a45a8ff 161 /* Check the NAND handle state */
bogdanm 0:9b334a45a8ff 162 if(hnand == NULL)
bogdanm 0:9b334a45a8ff 163 {
bogdanm 0:9b334a45a8ff 164 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 165 }
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 if(hnand->State == HAL_NAND_STATE_RESET)
bogdanm 0:9b334a45a8ff 168 {
bogdanm 0:9b334a45a8ff 169 /* Allocate lock resource and initialize it */
bogdanm 0:9b334a45a8ff 170 hnand-> Lock = HAL_UNLOCKED;
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 173 HAL_NAND_MspInit(hnand);
bogdanm 0:9b334a45a8ff 174 }
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 /* Initialize NAND control Interface */
bogdanm 0:9b334a45a8ff 177 FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 /* Initialize NAND common space timing Interface */
bogdanm 0:9b334a45a8ff 180 FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 181
bogdanm 0:9b334a45a8ff 182 /* Initialize NAND attribute space timing Interface */
bogdanm 0:9b334a45a8ff 183 FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 /* Enable the NAND device */
bogdanm 0:9b334a45a8ff 186 __FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 189 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 190
bogdanm 0:9b334a45a8ff 191 return HAL_OK;
bogdanm 0:9b334a45a8ff 192 }
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 /**
bogdanm 0:9b334a45a8ff 195 * @brief Perform NAND memory De-Initialization sequence
bogdanm 0:9b334a45a8ff 196 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 197 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 198 * @retval HAL status
bogdanm 0:9b334a45a8ff 199 */
bogdanm 0:9b334a45a8ff 200 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 201 {
bogdanm 0:9b334a45a8ff 202 /* Initialize the low level hardware (MSP) */
bogdanm 0:9b334a45a8ff 203 HAL_NAND_MspDeInit(hnand);
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 /* Configure the NAND registers with their reset values */
bogdanm 0:9b334a45a8ff 206 FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 /* Reset the NAND controller state */
bogdanm 0:9b334a45a8ff 209 hnand->State = HAL_NAND_STATE_RESET;
bogdanm 0:9b334a45a8ff 210
bogdanm 0:9b334a45a8ff 211 /* Release Lock */
bogdanm 0:9b334a45a8ff 212 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 return HAL_OK;
bogdanm 0:9b334a45a8ff 215 }
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 /**
bogdanm 0:9b334a45a8ff 218 * @brief NAND MSP Init
bogdanm 0:9b334a45a8ff 219 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 220 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 221 * @retval None
bogdanm 0:9b334a45a8ff 222 */
bogdanm 0:9b334a45a8ff 223 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 224 {
bogdanm 0:9b334a45a8ff 225 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 226 the HAL_NAND_MspInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 227 */
bogdanm 0:9b334a45a8ff 228 }
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 /**
bogdanm 0:9b334a45a8ff 231 * @brief NAND MSP DeInit
bogdanm 0:9b334a45a8ff 232 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 233 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 234 * @retval None
bogdanm 0:9b334a45a8ff 235 */
bogdanm 0:9b334a45a8ff 236 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 237 {
bogdanm 0:9b334a45a8ff 238 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 239 the HAL_NAND_MspDeInit could be implemented in the user file
bogdanm 0:9b334a45a8ff 240 */
bogdanm 0:9b334a45a8ff 241 }
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243
bogdanm 0:9b334a45a8ff 244 /**
bogdanm 0:9b334a45a8ff 245 * @brief This function handles NAND device interrupt request.
bogdanm 0:9b334a45a8ff 246 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 247 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 248 * @retval HAL status
bogdanm 0:9b334a45a8ff 249 */
bogdanm 0:9b334a45a8ff 250 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 251 {
bogdanm 0:9b334a45a8ff 252 /* Check NAND interrupt Rising edge flag */
bogdanm 0:9b334a45a8ff 253 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
bogdanm 0:9b334a45a8ff 254 {
bogdanm 0:9b334a45a8ff 255 /* NAND interrupt callback*/
bogdanm 0:9b334a45a8ff 256 HAL_NAND_ITCallback(hnand);
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 /* Clear NAND interrupt Rising edge pending bit */
bogdanm 0:9b334a45a8ff 259 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
bogdanm 0:9b334a45a8ff 260 }
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 /* Check NAND interrupt Level flag */
bogdanm 0:9b334a45a8ff 263 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
bogdanm 0:9b334a45a8ff 264 {
bogdanm 0:9b334a45a8ff 265 /* NAND interrupt callback*/
bogdanm 0:9b334a45a8ff 266 HAL_NAND_ITCallback(hnand);
bogdanm 0:9b334a45a8ff 267
bogdanm 0:9b334a45a8ff 268 /* Clear NAND interrupt Level pending bit */
bogdanm 0:9b334a45a8ff 269 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
bogdanm 0:9b334a45a8ff 270 }
bogdanm 0:9b334a45a8ff 271
bogdanm 0:9b334a45a8ff 272 /* Check NAND interrupt Falling edge flag */
bogdanm 0:9b334a45a8ff 273 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
bogdanm 0:9b334a45a8ff 274 {
bogdanm 0:9b334a45a8ff 275 /* NAND interrupt callback*/
bogdanm 0:9b334a45a8ff 276 HAL_NAND_ITCallback(hnand);
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 /* Clear NAND interrupt Falling edge pending bit */
bogdanm 0:9b334a45a8ff 279 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
bogdanm 0:9b334a45a8ff 280 }
bogdanm 0:9b334a45a8ff 281
bogdanm 0:9b334a45a8ff 282 /* Check NAND interrupt FIFO empty flag */
bogdanm 0:9b334a45a8ff 283 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
bogdanm 0:9b334a45a8ff 284 {
bogdanm 0:9b334a45a8ff 285 /* NAND interrupt callback*/
bogdanm 0:9b334a45a8ff 286 HAL_NAND_ITCallback(hnand);
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288 /* Clear NAND interrupt FIFO empty pending bit */
bogdanm 0:9b334a45a8ff 289 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
bogdanm 0:9b334a45a8ff 290 }
bogdanm 0:9b334a45a8ff 291
bogdanm 0:9b334a45a8ff 292 }
bogdanm 0:9b334a45a8ff 293
bogdanm 0:9b334a45a8ff 294 /**
bogdanm 0:9b334a45a8ff 295 * @brief NAND interrupt feature callback
bogdanm 0:9b334a45a8ff 296 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 297 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 298 * @retval None
bogdanm 0:9b334a45a8ff 299 */
bogdanm 0:9b334a45a8ff 300 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 301 {
bogdanm 0:9b334a45a8ff 302 /* NOTE : This function Should not be modified, when the callback is needed,
bogdanm 0:9b334a45a8ff 303 the HAL_NAND_ITCallback could be implemented in the user file
bogdanm 0:9b334a45a8ff 304 */
bogdanm 0:9b334a45a8ff 305 }
bogdanm 0:9b334a45a8ff 306
bogdanm 0:9b334a45a8ff 307 /**
bogdanm 0:9b334a45a8ff 308 * @}
bogdanm 0:9b334a45a8ff 309 */
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
bogdanm 0:9b334a45a8ff 312 * @brief Input Output and memory control functions
bogdanm 0:9b334a45a8ff 313 *
bogdanm 0:9b334a45a8ff 314 @verbatim
bogdanm 0:9b334a45a8ff 315 ==============================================================================
bogdanm 0:9b334a45a8ff 316 ##### NAND Input and Output functions #####
bogdanm 0:9b334a45a8ff 317 ==============================================================================
bogdanm 0:9b334a45a8ff 318 [..]
bogdanm 0:9b334a45a8ff 319 This section provides functions allowing to use and control the NAND
bogdanm 0:9b334a45a8ff 320 memory
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 @endverbatim
bogdanm 0:9b334a45a8ff 323 * @{
bogdanm 0:9b334a45a8ff 324 */
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 /**
bogdanm 0:9b334a45a8ff 327 * @brief Read the NAND memory electronic signature
bogdanm 0:9b334a45a8ff 328 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 329 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 330 * @param pNAND_ID: NAND ID structure
bogdanm 0:9b334a45a8ff 331 * @retval HAL status
bogdanm 0:9b334a45a8ff 332 */
bogdanm 0:9b334a45a8ff 333 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
bogdanm 0:9b334a45a8ff 334 {
bogdanm 0:9b334a45a8ff 335 __IO uint32_t data = 0;
bogdanm 0:9b334a45a8ff 336 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 337
bogdanm 0:9b334a45a8ff 338 /* Process Locked */
bogdanm 0:9b334a45a8ff 339 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 340
bogdanm 0:9b334a45a8ff 341 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 342 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 343 {
bogdanm 0:9b334a45a8ff 344 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 345 }
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 /* Identify the device address */
bogdanm 0:9b334a45a8ff 348 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 349 {
bogdanm 0:9b334a45a8ff 350 deviceaddress = NAND_DEVICE1;
bogdanm 0:9b334a45a8ff 351 }
bogdanm 0:9b334a45a8ff 352 else
bogdanm 0:9b334a45a8ff 353 {
bogdanm 0:9b334a45a8ff 354 deviceaddress = NAND_DEVICE2;
bogdanm 0:9b334a45a8ff 355 }
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 358 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 359
bogdanm 0:9b334a45a8ff 360 /* Send Read ID command sequence */
bogdanm 0:9b334a45a8ff 361 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
bogdanm 0:9b334a45a8ff 362 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
bogdanm 0:9b334a45a8ff 363
bogdanm 0:9b334a45a8ff 364 /* Read the electronic signature from NAND flash */
bogdanm 0:9b334a45a8ff 365 data = *(__IO uint32_t *)deviceaddress;
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 /* Return the data read */
bogdanm 0:9b334a45a8ff 368 pNAND_ID->Maker_Id = __ADDR_1st_CYCLE(data);
bogdanm 0:9b334a45a8ff 369 pNAND_ID->Device_Id = __ADDR_2nd_CYCLE(data);
bogdanm 0:9b334a45a8ff 370 pNAND_ID->Third_Id = __ADDR_3rd_CYCLE(data);
bogdanm 0:9b334a45a8ff 371 pNAND_ID->Fourth_Id = __ADDR_4th_CYCLE(data);
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 374 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /* Process unlocked */
bogdanm 0:9b334a45a8ff 377 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379 return HAL_OK;
bogdanm 0:9b334a45a8ff 380 }
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 /**
bogdanm 0:9b334a45a8ff 383 * @brief NAND memory reset
bogdanm 0:9b334a45a8ff 384 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 385 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 386 * @retval HAL status
bogdanm 0:9b334a45a8ff 387 */
bogdanm 0:9b334a45a8ff 388 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 389 {
bogdanm 0:9b334a45a8ff 390 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 /* Process Locked */
bogdanm 0:9b334a45a8ff 393 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 396 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 397 {
bogdanm 0:9b334a45a8ff 398 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 399 }
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 /* Identify the device address */
bogdanm 0:9b334a45a8ff 402 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 403 {
bogdanm 0:9b334a45a8ff 404 deviceaddress = NAND_DEVICE1;
bogdanm 0:9b334a45a8ff 405 }
bogdanm 0:9b334a45a8ff 406 else
bogdanm 0:9b334a45a8ff 407 {
bogdanm 0:9b334a45a8ff 408 deviceaddress = NAND_DEVICE2;
bogdanm 0:9b334a45a8ff 409 }
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 412 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 413
bogdanm 0:9b334a45a8ff 414 /* Send NAND reset command */
bogdanm 0:9b334a45a8ff 415 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417
bogdanm 0:9b334a45a8ff 418 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 419 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 420
bogdanm 0:9b334a45a8ff 421 /* Process unlocked */
bogdanm 0:9b334a45a8ff 422 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 return HAL_OK;
bogdanm 0:9b334a45a8ff 425
bogdanm 0:9b334a45a8ff 426 }
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 /**
bogdanm 0:9b334a45a8ff 429 * @brief Read Page(s) from NAND memory block
bogdanm 0:9b334a45a8ff 430 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 431 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 432 * @param pAddress : pointer to NAND address structure
bogdanm 0:9b334a45a8ff 433 * @param pBuffer : pointer to destination read buffer
bogdanm 0:9b334a45a8ff 434 * @param NumPageToRead : number of pages to read from block
bogdanm 0:9b334a45a8ff 435 * @retval HAL status
bogdanm 0:9b334a45a8ff 436 */
bogdanm 0:9b334a45a8ff 437 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
bogdanm 0:9b334a45a8ff 438 {
bogdanm 0:9b334a45a8ff 439 __IO uint32_t index = 0;
bogdanm 0:9b334a45a8ff 440 uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 441 NAND_AddressTypeDef nandaddress;
bogdanm 0:9b334a45a8ff 442 uint32_t addressoffset = 0;
bogdanm 0:9b334a45a8ff 443
bogdanm 0:9b334a45a8ff 444 /* Process Locked */
bogdanm 0:9b334a45a8ff 445 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 448 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 449 {
bogdanm 0:9b334a45a8ff 450 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 451 }
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 /* Identify the device address */
bogdanm 0:9b334a45a8ff 454 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 455 {
bogdanm 0:9b334a45a8ff 456 deviceaddress = NAND_DEVICE1;
bogdanm 0:9b334a45a8ff 457 }
bogdanm 0:9b334a45a8ff 458 else
bogdanm 0:9b334a45a8ff 459 {
bogdanm 0:9b334a45a8ff 460 deviceaddress = NAND_DEVICE2;
bogdanm 0:9b334a45a8ff 461 }
bogdanm 0:9b334a45a8ff 462
bogdanm 0:9b334a45a8ff 463 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 464 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 /* Save the content of pAddress as it will be modified */
bogdanm 0:9b334a45a8ff 467 nandaddress.Block = pAddress->Block;
bogdanm 0:9b334a45a8ff 468 nandaddress.Page = pAddress->Page;
bogdanm 0:9b334a45a8ff 469 nandaddress.Zone = pAddress->Zone;
bogdanm 0:9b334a45a8ff 470
bogdanm 0:9b334a45a8ff 471 /* Page(s) read loop */
bogdanm 0:9b334a45a8ff 472 while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
bogdanm 0:9b334a45a8ff 473 {
bogdanm 0:9b334a45a8ff 474 /* update the buffer size */
bogdanm 0:9b334a45a8ff 475 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 /* Get the address offset */
bogdanm 0:9b334a45a8ff 478 addressoffset = __ARRAY_ADDRESS(&nandaddress, hnand);
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 /* Send read page command sequence */
bogdanm 0:9b334a45a8ff 481 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
bogdanm 0:9b334a45a8ff 484 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_1st_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 485 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 486 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 487
bogdanm 0:9b334a45a8ff 488 /* for 512 and 1 GB devices, 4th cycle is required */
bogdanm 0:9b334a45a8ff 489 if(hnand->Info.BlockNbr >= 1024)
bogdanm 0:9b334a45a8ff 490 {
bogdanm 0:9b334a45a8ff 491 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_4th_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 492 }
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
bogdanm 0:9b334a45a8ff 495
bogdanm 0:9b334a45a8ff 496 /* Get Data into Buffer */
bogdanm 0:9b334a45a8ff 497 for(; index < size; index++)
bogdanm 0:9b334a45a8ff 498 {
bogdanm 0:9b334a45a8ff 499 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
bogdanm 0:9b334a45a8ff 500 }
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 /* Increment read pages number */
bogdanm 0:9b334a45a8ff 503 numpagesread++;
bogdanm 0:9b334a45a8ff 504
bogdanm 0:9b334a45a8ff 505 /* Decrement pages to read */
bogdanm 0:9b334a45a8ff 506 NumPageToRead--;
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 /* Increment the NAND address */
bogdanm 0:9b334a45a8ff 509 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
bogdanm 0:9b334a45a8ff 510 }
bogdanm 0:9b334a45a8ff 511
bogdanm 0:9b334a45a8ff 512 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 513 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 514
bogdanm 0:9b334a45a8ff 515 /* Process unlocked */
bogdanm 0:9b334a45a8ff 516 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 517
bogdanm 0:9b334a45a8ff 518 return HAL_OK;
bogdanm 0:9b334a45a8ff 519
bogdanm 0:9b334a45a8ff 520 }
bogdanm 0:9b334a45a8ff 521
bogdanm 0:9b334a45a8ff 522 /**
bogdanm 0:9b334a45a8ff 523 * @brief Write Page(s) to NAND memory block
bogdanm 0:9b334a45a8ff 524 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 525 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 526 * @param pAddress : pointer to NAND address structure
bogdanm 0:9b334a45a8ff 527 * @param pBuffer : pointer to source buffer to write
bogdanm 0:9b334a45a8ff 528 * @param NumPageToWrite : number of pages to write to block
bogdanm 0:9b334a45a8ff 529 * @retval HAL status
bogdanm 0:9b334a45a8ff 530 */
bogdanm 0:9b334a45a8ff 531 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
bogdanm 0:9b334a45a8ff 532 {
bogdanm 0:9b334a45a8ff 533 __IO uint32_t index = 0;
bogdanm 0:9b334a45a8ff 534 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 535 uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 536 NAND_AddressTypeDef nandaddress;
bogdanm 0:9b334a45a8ff 537 uint32_t addressoffset = 0;
bogdanm 0:9b334a45a8ff 538
bogdanm 0:9b334a45a8ff 539 /* Process Locked */
bogdanm 0:9b334a45a8ff 540 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 543 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 544 {
bogdanm 0:9b334a45a8ff 545 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 546 }
bogdanm 0:9b334a45a8ff 547
bogdanm 0:9b334a45a8ff 548 /* Identify the device address */
bogdanm 0:9b334a45a8ff 549 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 550 {
bogdanm 0:9b334a45a8ff 551 deviceaddress = NAND_DEVICE1;
bogdanm 0:9b334a45a8ff 552 }
bogdanm 0:9b334a45a8ff 553 else
bogdanm 0:9b334a45a8ff 554 {
bogdanm 0:9b334a45a8ff 555 deviceaddress = NAND_DEVICE2;
bogdanm 0:9b334a45a8ff 556 }
bogdanm 0:9b334a45a8ff 557
bogdanm 0:9b334a45a8ff 558 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 559 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 560
bogdanm 0:9b334a45a8ff 561 /* Save the content of pAddress as it will be modified */
bogdanm 0:9b334a45a8ff 562 nandaddress.Block = pAddress->Block;
bogdanm 0:9b334a45a8ff 563 nandaddress.Page = pAddress->Page;
bogdanm 0:9b334a45a8ff 564 nandaddress.Zone = pAddress->Zone;
bogdanm 0:9b334a45a8ff 565
bogdanm 0:9b334a45a8ff 566 /* Page(s) write loop */
bogdanm 0:9b334a45a8ff 567 while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
bogdanm 0:9b334a45a8ff 568 {
bogdanm 0:9b334a45a8ff 569 /* update the buffer size */
bogdanm 0:9b334a45a8ff 570 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
bogdanm 0:9b334a45a8ff 571
bogdanm 0:9b334a45a8ff 572 /* Get the address offset */
bogdanm 0:9b334a45a8ff 573 addressoffset = __ARRAY_ADDRESS(&nandaddress, hnand);
bogdanm 0:9b334a45a8ff 574
bogdanm 0:9b334a45a8ff 575 /* Send write page command sequence */
bogdanm 0:9b334a45a8ff 576 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
bogdanm 0:9b334a45a8ff 577 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
bogdanm 0:9b334a45a8ff 580 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_1st_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 581 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 582 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 583
bogdanm 0:9b334a45a8ff 584 /* for 512 and 1 GB devices, 4th cycle is required */
bogdanm 0:9b334a45a8ff 585 if(hnand->Info.BlockNbr >= 1024)
bogdanm 0:9b334a45a8ff 586 {
bogdanm 0:9b334a45a8ff 587 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_4th_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 588 }
bogdanm 0:9b334a45a8ff 589
bogdanm 0:9b334a45a8ff 590 /* Write data to memory */
bogdanm 0:9b334a45a8ff 591 for(; index < size; index++)
bogdanm 0:9b334a45a8ff 592 {
bogdanm 0:9b334a45a8ff 593 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
bogdanm 0:9b334a45a8ff 594 }
bogdanm 0:9b334a45a8ff 595
bogdanm 0:9b334a45a8ff 596 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
bogdanm 0:9b334a45a8ff 597
bogdanm 0:9b334a45a8ff 598 /* Get tick */
bogdanm 0:9b334a45a8ff 599 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 600
bogdanm 0:9b334a45a8ff 601 /* Read status until NAND is ready */
bogdanm 0:9b334a45a8ff 602 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
bogdanm 0:9b334a45a8ff 603 {
bogdanm 0:9b334a45a8ff 604 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
bogdanm 0:9b334a45a8ff 605 {
bogdanm 0:9b334a45a8ff 606 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 607 }
bogdanm 0:9b334a45a8ff 608 }
bogdanm 0:9b334a45a8ff 609
bogdanm 0:9b334a45a8ff 610 /* Increment written pages number */
bogdanm 0:9b334a45a8ff 611 numpageswritten++;
bogdanm 0:9b334a45a8ff 612
bogdanm 0:9b334a45a8ff 613 /* Decrement pages to write */
bogdanm 0:9b334a45a8ff 614 NumPageToWrite--;
bogdanm 0:9b334a45a8ff 615
bogdanm 0:9b334a45a8ff 616 /* Increment the NAND address */
bogdanm 0:9b334a45a8ff 617 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
bogdanm 0:9b334a45a8ff 618 }
bogdanm 0:9b334a45a8ff 619
bogdanm 0:9b334a45a8ff 620 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 621 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 622
bogdanm 0:9b334a45a8ff 623 /* Process unlocked */
bogdanm 0:9b334a45a8ff 624 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 625
bogdanm 0:9b334a45a8ff 626 return HAL_OK;
bogdanm 0:9b334a45a8ff 627 }
bogdanm 0:9b334a45a8ff 628
bogdanm 0:9b334a45a8ff 629 /**
bogdanm 0:9b334a45a8ff 630 * @brief Read Spare area(s) from NAND memory
bogdanm 0:9b334a45a8ff 631 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 632 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 633 * @param pAddress : pointer to NAND address structure
bogdanm 0:9b334a45a8ff 634 * @param pBuffer: pointer to source buffer to write
bogdanm 0:9b334a45a8ff 635 * @param NumSpareAreaToRead: Number of spare area to read
bogdanm 0:9b334a45a8ff 636 * @retval HAL status
bogdanm 0:9b334a45a8ff 637 */
bogdanm 0:9b334a45a8ff 638 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
bogdanm 0:9b334a45a8ff 639 {
bogdanm 0:9b334a45a8ff 640 __IO uint32_t index = 0;
bogdanm 0:9b334a45a8ff 641 uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 642 NAND_AddressTypeDef nandaddress;
bogdanm 0:9b334a45a8ff 643 uint32_t addressoffset = 0;
bogdanm 0:9b334a45a8ff 644
bogdanm 0:9b334a45a8ff 645 /* Process Locked */
bogdanm 0:9b334a45a8ff 646 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 647
bogdanm 0:9b334a45a8ff 648 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 649 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 650 {
bogdanm 0:9b334a45a8ff 651 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 652 }
bogdanm 0:9b334a45a8ff 653
bogdanm 0:9b334a45a8ff 654 /* Identify the device address */
bogdanm 0:9b334a45a8ff 655 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 656 {
bogdanm 0:9b334a45a8ff 657 deviceaddress = NAND_DEVICE1;
bogdanm 0:9b334a45a8ff 658 }
bogdanm 0:9b334a45a8ff 659 else
bogdanm 0:9b334a45a8ff 660 {
bogdanm 0:9b334a45a8ff 661 deviceaddress = NAND_DEVICE2;
bogdanm 0:9b334a45a8ff 662 }
bogdanm 0:9b334a45a8ff 663
bogdanm 0:9b334a45a8ff 664 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 665 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 666
bogdanm 0:9b334a45a8ff 667 /* Save the content of pAddress as it will be modified */
bogdanm 0:9b334a45a8ff 668 nandaddress.Block = pAddress->Block;
bogdanm 0:9b334a45a8ff 669 nandaddress.Page = pAddress->Page;
bogdanm 0:9b334a45a8ff 670 nandaddress.Zone = pAddress->Zone;
bogdanm 0:9b334a45a8ff 671
bogdanm 0:9b334a45a8ff 672 /* Spare area(s) read loop */
bogdanm 0:9b334a45a8ff 673 while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
bogdanm 0:9b334a45a8ff 674 {
bogdanm 0:9b334a45a8ff 675 /* update the buffer size */
bogdanm 0:9b334a45a8ff 676 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
bogdanm 0:9b334a45a8ff 677
bogdanm 0:9b334a45a8ff 678 /* Get the address offset */
bogdanm 0:9b334a45a8ff 679 addressoffset = __ARRAY_ADDRESS(&nandaddress, hnand);
bogdanm 0:9b334a45a8ff 680
bogdanm 0:9b334a45a8ff 681 /* Send read spare area command sequence */
bogdanm 0:9b334a45a8ff 682 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
bogdanm 0:9b334a45a8ff 683
bogdanm 0:9b334a45a8ff 684 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
bogdanm 0:9b334a45a8ff 685 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_1st_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 686 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 687 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 688
bogdanm 0:9b334a45a8ff 689 /* for 512 and 1 GB devices, 4th cycle is required */
bogdanm 0:9b334a45a8ff 690 if(hnand->Info.BlockNbr >= 1024)
bogdanm 0:9b334a45a8ff 691 {
bogdanm 0:9b334a45a8ff 692 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_4th_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 693 }
bogdanm 0:9b334a45a8ff 694
bogdanm 0:9b334a45a8ff 695 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
bogdanm 0:9b334a45a8ff 696
bogdanm 0:9b334a45a8ff 697 /* Get Data into Buffer */
bogdanm 0:9b334a45a8ff 698 for ( ;index < size; index++)
bogdanm 0:9b334a45a8ff 699 {
bogdanm 0:9b334a45a8ff 700 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
bogdanm 0:9b334a45a8ff 701 }
bogdanm 0:9b334a45a8ff 702
bogdanm 0:9b334a45a8ff 703 /* Increment read spare areas number */
bogdanm 0:9b334a45a8ff 704 num_spare_area_read++;
bogdanm 0:9b334a45a8ff 705
bogdanm 0:9b334a45a8ff 706 /* Decrement spare areas to read */
bogdanm 0:9b334a45a8ff 707 NumSpareAreaToRead--;
bogdanm 0:9b334a45a8ff 708
bogdanm 0:9b334a45a8ff 709 /* Increment the NAND address */
bogdanm 0:9b334a45a8ff 710 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
bogdanm 0:9b334a45a8ff 711 }
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 714 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 715
bogdanm 0:9b334a45a8ff 716 /* Process unlocked */
bogdanm 0:9b334a45a8ff 717 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 718
bogdanm 0:9b334a45a8ff 719 return HAL_OK;
bogdanm 0:9b334a45a8ff 720 }
bogdanm 0:9b334a45a8ff 721
bogdanm 0:9b334a45a8ff 722 /**
bogdanm 0:9b334a45a8ff 723 * @brief Write Spare area(s) to NAND memory
bogdanm 0:9b334a45a8ff 724 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 725 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 726 * @param pAddress : pointer to NAND address structure
bogdanm 0:9b334a45a8ff 727 * @param pBuffer : pointer to source buffer to write
bogdanm 0:9b334a45a8ff 728 * @param NumSpareAreaTowrite : number of spare areas to write to block
bogdanm 0:9b334a45a8ff 729 * @retval HAL status
bogdanm 0:9b334a45a8ff 730 */
bogdanm 0:9b334a45a8ff 731 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
bogdanm 0:9b334a45a8ff 732 {
bogdanm 0:9b334a45a8ff 733 __IO uint32_t index = 0;
bogdanm 0:9b334a45a8ff 734 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 735 uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 736 NAND_AddressTypeDef nandaddress;
bogdanm 0:9b334a45a8ff 737 uint32_t addressoffset = 0;
bogdanm 0:9b334a45a8ff 738
bogdanm 0:9b334a45a8ff 739 /* Process Locked */
bogdanm 0:9b334a45a8ff 740 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 741
bogdanm 0:9b334a45a8ff 742 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 743 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 744 {
bogdanm 0:9b334a45a8ff 745 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 746 }
bogdanm 0:9b334a45a8ff 747
bogdanm 0:9b334a45a8ff 748 /* Identify the device address */
bogdanm 0:9b334a45a8ff 749 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 750 {
bogdanm 0:9b334a45a8ff 751 deviceaddress = NAND_DEVICE1;
bogdanm 0:9b334a45a8ff 752 }
bogdanm 0:9b334a45a8ff 753 else
bogdanm 0:9b334a45a8ff 754 {
bogdanm 0:9b334a45a8ff 755 deviceaddress = NAND_DEVICE2;
bogdanm 0:9b334a45a8ff 756 }
bogdanm 0:9b334a45a8ff 757
bogdanm 0:9b334a45a8ff 758 /* Update the FMC_NAND controller state */
bogdanm 0:9b334a45a8ff 759 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 760
bogdanm 0:9b334a45a8ff 761 /* Save the content of pAddress as it will be modified */
bogdanm 0:9b334a45a8ff 762 nandaddress.Block = pAddress->Block;
bogdanm 0:9b334a45a8ff 763 nandaddress.Page = pAddress->Page;
bogdanm 0:9b334a45a8ff 764 nandaddress.Zone = pAddress->Zone;
bogdanm 0:9b334a45a8ff 765
bogdanm 0:9b334a45a8ff 766 /* Spare area(s) write loop */
bogdanm 0:9b334a45a8ff 767 while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
bogdanm 0:9b334a45a8ff 768 {
bogdanm 0:9b334a45a8ff 769 /* update the buffer size */
bogdanm 0:9b334a45a8ff 770 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
bogdanm 0:9b334a45a8ff 771
bogdanm 0:9b334a45a8ff 772 /* Get the address offset */
bogdanm 0:9b334a45a8ff 773 addressoffset = __ARRAY_ADDRESS(&nandaddress, hnand);
bogdanm 0:9b334a45a8ff 774
bogdanm 0:9b334a45a8ff 775 /* Send write Spare area command sequence */
bogdanm 0:9b334a45a8ff 776 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
bogdanm 0:9b334a45a8ff 777 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
bogdanm 0:9b334a45a8ff 778
bogdanm 0:9b334a45a8ff 779 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
bogdanm 0:9b334a45a8ff 780 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_1st_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 781 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 782 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 783
bogdanm 0:9b334a45a8ff 784 /* for 512 and 1 GB devices, 4th cycle is required */
bogdanm 0:9b334a45a8ff 785 if(hnand->Info.BlockNbr >= 1024)
bogdanm 0:9b334a45a8ff 786 {
bogdanm 0:9b334a45a8ff 787 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_4th_CYCLE(addressoffset);
bogdanm 0:9b334a45a8ff 788 }
bogdanm 0:9b334a45a8ff 789
bogdanm 0:9b334a45a8ff 790 /* Write data to memory */
bogdanm 0:9b334a45a8ff 791 for(; index < size; index++)
bogdanm 0:9b334a45a8ff 792 {
bogdanm 0:9b334a45a8ff 793 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
bogdanm 0:9b334a45a8ff 794 }
bogdanm 0:9b334a45a8ff 795
bogdanm 0:9b334a45a8ff 796 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
bogdanm 0:9b334a45a8ff 797
bogdanm 0:9b334a45a8ff 798 /* Get tick */
bogdanm 0:9b334a45a8ff 799 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 800
bogdanm 0:9b334a45a8ff 801 /* Read status until NAND is ready */
bogdanm 0:9b334a45a8ff 802 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
bogdanm 0:9b334a45a8ff 803 {
bogdanm 0:9b334a45a8ff 804 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
bogdanm 0:9b334a45a8ff 805 {
bogdanm 0:9b334a45a8ff 806 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 807 }
bogdanm 0:9b334a45a8ff 808 }
bogdanm 0:9b334a45a8ff 809
bogdanm 0:9b334a45a8ff 810 /* Increment written spare areas number */
bogdanm 0:9b334a45a8ff 811 num_spare_area_written++;
bogdanm 0:9b334a45a8ff 812
bogdanm 0:9b334a45a8ff 813 /* Decrement spare areas to write */
bogdanm 0:9b334a45a8ff 814 NumSpareAreaTowrite--;
bogdanm 0:9b334a45a8ff 815
bogdanm 0:9b334a45a8ff 816 /* Increment the NAND address */
bogdanm 0:9b334a45a8ff 817 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
bogdanm 0:9b334a45a8ff 818 }
bogdanm 0:9b334a45a8ff 819
bogdanm 0:9b334a45a8ff 820 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 821 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 822
bogdanm 0:9b334a45a8ff 823 /* Process unlocked */
bogdanm 0:9b334a45a8ff 824 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 825
bogdanm 0:9b334a45a8ff 826 return HAL_OK;
bogdanm 0:9b334a45a8ff 827 }
bogdanm 0:9b334a45a8ff 828
bogdanm 0:9b334a45a8ff 829 /**
bogdanm 0:9b334a45a8ff 830 * @brief NAND memory Block erase
bogdanm 0:9b334a45a8ff 831 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 832 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 833 * @param pAddress : pointer to NAND address structure
bogdanm 0:9b334a45a8ff 834 * @retval HAL status
bogdanm 0:9b334a45a8ff 835 */
bogdanm 0:9b334a45a8ff 836 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
bogdanm 0:9b334a45a8ff 837 {
bogdanm 0:9b334a45a8ff 838 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 839 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 840
bogdanm 0:9b334a45a8ff 841 /* Process Locked */
bogdanm 0:9b334a45a8ff 842 __HAL_LOCK(hnand);
bogdanm 0:9b334a45a8ff 843
bogdanm 0:9b334a45a8ff 844 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 845 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 846 {
bogdanm 0:9b334a45a8ff 847 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 848 }
bogdanm 0:9b334a45a8ff 849
bogdanm 0:9b334a45a8ff 850 /* Identify the device address */
bogdanm 0:9b334a45a8ff 851 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 852 {
bogdanm 0:9b334a45a8ff 853 deviceaddress = NAND_DEVICE1;
bogdanm 0:9b334a45a8ff 854 }
bogdanm 0:9b334a45a8ff 855 else
bogdanm 0:9b334a45a8ff 856 {
bogdanm 0:9b334a45a8ff 857 deviceaddress = NAND_DEVICE2;
bogdanm 0:9b334a45a8ff 858 }
bogdanm 0:9b334a45a8ff 859
bogdanm 0:9b334a45a8ff 860 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 861 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 862
bogdanm 0:9b334a45a8ff 863 /* Send Erase block command sequence */
bogdanm 0:9b334a45a8ff 864 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
bogdanm 0:9b334a45a8ff 865
bogdanm 0:9b334a45a8ff 866 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_1st_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
bogdanm 0:9b334a45a8ff 867 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
bogdanm 0:9b334a45a8ff 868 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
bogdanm 0:9b334a45a8ff 869
bogdanm 0:9b334a45a8ff 870 /* for 512 and 1 GB devices, 4th cycle is required */
bogdanm 0:9b334a45a8ff 871 if(hnand->Info.BlockNbr >= 1024)
bogdanm 0:9b334a45a8ff 872 {
bogdanm 0:9b334a45a8ff 873 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = __ADDR_4th_CYCLE(__ARRAY_ADDRESS(pAddress, hnand));
bogdanm 0:9b334a45a8ff 874 }
bogdanm 0:9b334a45a8ff 875
bogdanm 0:9b334a45a8ff 876 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
bogdanm 0:9b334a45a8ff 877
bogdanm 0:9b334a45a8ff 878 /* Update the NAND controller state */
bogdanm 0:9b334a45a8ff 879 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 880
bogdanm 0:9b334a45a8ff 881 /* Get tick */
bogdanm 0:9b334a45a8ff 882 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 883
bogdanm 0:9b334a45a8ff 884 /* Read status until NAND is ready */
bogdanm 0:9b334a45a8ff 885 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
bogdanm 0:9b334a45a8ff 886 {
bogdanm 0:9b334a45a8ff 887 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
bogdanm 0:9b334a45a8ff 888 {
bogdanm 0:9b334a45a8ff 889 /* Process unlocked */
bogdanm 0:9b334a45a8ff 890 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 891
bogdanm 0:9b334a45a8ff 892 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 893 }
bogdanm 0:9b334a45a8ff 894 }
bogdanm 0:9b334a45a8ff 895
bogdanm 0:9b334a45a8ff 896 /* Process unlocked */
bogdanm 0:9b334a45a8ff 897 __HAL_UNLOCK(hnand);
bogdanm 0:9b334a45a8ff 898
bogdanm 0:9b334a45a8ff 899 return HAL_OK;
bogdanm 0:9b334a45a8ff 900 }
bogdanm 0:9b334a45a8ff 901
bogdanm 0:9b334a45a8ff 902 /**
bogdanm 0:9b334a45a8ff 903 * @brief NAND memory read status
bogdanm 0:9b334a45a8ff 904 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 905 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 906 * @retval NAND status
bogdanm 0:9b334a45a8ff 907 */
bogdanm 0:9b334a45a8ff 908 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 909 {
bogdanm 0:9b334a45a8ff 910 uint32_t data = 0;
bogdanm 0:9b334a45a8ff 911 uint32_t deviceaddress = 0;
bogdanm 0:9b334a45a8ff 912
bogdanm 0:9b334a45a8ff 913 /* Identify the device address */
bogdanm 0:9b334a45a8ff 914 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 915 {
bogdanm 0:9b334a45a8ff 916 deviceaddress = NAND_DEVICE1;
bogdanm 0:9b334a45a8ff 917 }
bogdanm 0:9b334a45a8ff 918 else
bogdanm 0:9b334a45a8ff 919 {
bogdanm 0:9b334a45a8ff 920 deviceaddress = NAND_DEVICE2;
bogdanm 0:9b334a45a8ff 921 }
bogdanm 0:9b334a45a8ff 922
bogdanm 0:9b334a45a8ff 923 /* Send Read status operation command */
bogdanm 0:9b334a45a8ff 924 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
bogdanm 0:9b334a45a8ff 925
bogdanm 0:9b334a45a8ff 926 /* Read status register data */
bogdanm 0:9b334a45a8ff 927 data = *(__IO uint8_t *)deviceaddress;
bogdanm 0:9b334a45a8ff 928
bogdanm 0:9b334a45a8ff 929 /* Return the status */
bogdanm 0:9b334a45a8ff 930 if((data & NAND_ERROR) == NAND_ERROR)
bogdanm 0:9b334a45a8ff 931 {
bogdanm 0:9b334a45a8ff 932 return NAND_ERROR;
bogdanm 0:9b334a45a8ff 933 }
bogdanm 0:9b334a45a8ff 934 else if((data & NAND_READY) == NAND_READY)
bogdanm 0:9b334a45a8ff 935 {
bogdanm 0:9b334a45a8ff 936 return NAND_READY;
bogdanm 0:9b334a45a8ff 937 }
bogdanm 0:9b334a45a8ff 938
bogdanm 0:9b334a45a8ff 939 return NAND_BUSY;
bogdanm 0:9b334a45a8ff 940 }
bogdanm 0:9b334a45a8ff 941
bogdanm 0:9b334a45a8ff 942 /**
bogdanm 0:9b334a45a8ff 943 * @brief Increment the NAND memory address
bogdanm 0:9b334a45a8ff 944 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 945 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 946 * @param pAddress: pointer to NAND address structure
bogdanm 0:9b334a45a8ff 947 * @retval The new status of the increment address operation. It can be:
bogdanm 0:9b334a45a8ff 948 * - NAND_VALID_ADDRESS: When the new address is valid address
bogdanm 0:9b334a45a8ff 949 * - NAND_INVALID_ADDRESS: When the new address is invalid address
bogdanm 0:9b334a45a8ff 950 */
bogdanm 0:9b334a45a8ff 951 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
bogdanm 0:9b334a45a8ff 952 {
bogdanm 0:9b334a45a8ff 953 uint32_t status = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 954
bogdanm 0:9b334a45a8ff 955 /* Increment page address */
bogdanm 0:9b334a45a8ff 956 pAddress->Page++;
bogdanm 0:9b334a45a8ff 957
bogdanm 0:9b334a45a8ff 958 /* Check NAND address is valid */
bogdanm 0:9b334a45a8ff 959 if(pAddress->Page == hnand->Info.BlockSize)
bogdanm 0:9b334a45a8ff 960 {
bogdanm 0:9b334a45a8ff 961 pAddress->Page = 0;
bogdanm 0:9b334a45a8ff 962 pAddress->Block++;
bogdanm 0:9b334a45a8ff 963
bogdanm 0:9b334a45a8ff 964 if(pAddress->Block == hnand->Info.ZoneSize)
bogdanm 0:9b334a45a8ff 965 {
bogdanm 0:9b334a45a8ff 966 pAddress->Block = 0;
bogdanm 0:9b334a45a8ff 967 pAddress->Zone++;
bogdanm 0:9b334a45a8ff 968
bogdanm 0:9b334a45a8ff 969 if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
bogdanm 0:9b334a45a8ff 970 {
bogdanm 0:9b334a45a8ff 971 status = NAND_INVALID_ADDRESS;
bogdanm 0:9b334a45a8ff 972 }
bogdanm 0:9b334a45a8ff 973 }
bogdanm 0:9b334a45a8ff 974 }
bogdanm 0:9b334a45a8ff 975
bogdanm 0:9b334a45a8ff 976 return (status);
bogdanm 0:9b334a45a8ff 977 }
bogdanm 0:9b334a45a8ff 978 /**
bogdanm 0:9b334a45a8ff 979 * @}
bogdanm 0:9b334a45a8ff 980 */
bogdanm 0:9b334a45a8ff 981
bogdanm 0:9b334a45a8ff 982 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
bogdanm 0:9b334a45a8ff 983 * @brief management functions
bogdanm 0:9b334a45a8ff 984 *
bogdanm 0:9b334a45a8ff 985 @verbatim
bogdanm 0:9b334a45a8ff 986 ==============================================================================
bogdanm 0:9b334a45a8ff 987 ##### NAND Control functions #####
bogdanm 0:9b334a45a8ff 988 ==============================================================================
bogdanm 0:9b334a45a8ff 989 [..]
bogdanm 0:9b334a45a8ff 990 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 991 the NAND interface.
bogdanm 0:9b334a45a8ff 992
bogdanm 0:9b334a45a8ff 993 @endverbatim
bogdanm 0:9b334a45a8ff 994 * @{
bogdanm 0:9b334a45a8ff 995 */
bogdanm 0:9b334a45a8ff 996
bogdanm 0:9b334a45a8ff 997
bogdanm 0:9b334a45a8ff 998 /**
bogdanm 0:9b334a45a8ff 999 * @brief Enables dynamically NAND ECC feature.
bogdanm 0:9b334a45a8ff 1000 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1001 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 1002 * @retval HAL status
bogdanm 0:9b334a45a8ff 1003 */
bogdanm 0:9b334a45a8ff 1004 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 1005 {
bogdanm 0:9b334a45a8ff 1006 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 1007 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 1008 {
bogdanm 0:9b334a45a8ff 1009 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1010 }
bogdanm 0:9b334a45a8ff 1011
bogdanm 0:9b334a45a8ff 1012 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 1013 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1014
bogdanm 0:9b334a45a8ff 1015 /* Enable ECC feature */
bogdanm 0:9b334a45a8ff 1016 FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 1017
bogdanm 0:9b334a45a8ff 1018 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 1019 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 1020
bogdanm 0:9b334a45a8ff 1021 return HAL_OK;
bogdanm 0:9b334a45a8ff 1022 }
bogdanm 0:9b334a45a8ff 1023
bogdanm 0:9b334a45a8ff 1024 /**
bogdanm 0:9b334a45a8ff 1025 * @brief Disables dynamically FSMC_NAND ECC feature.
bogdanm 0:9b334a45a8ff 1026 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1027 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 1028 * @retval HAL status
bogdanm 0:9b334a45a8ff 1029 */
bogdanm 0:9b334a45a8ff 1030 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 1031 {
bogdanm 0:9b334a45a8ff 1032 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 1033 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 1034 {
bogdanm 0:9b334a45a8ff 1035 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1036 }
bogdanm 0:9b334a45a8ff 1037
bogdanm 0:9b334a45a8ff 1038 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 1039 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1040
bogdanm 0:9b334a45a8ff 1041 /* Disable ECC feature */
bogdanm 0:9b334a45a8ff 1042 FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
bogdanm 0:9b334a45a8ff 1043
bogdanm 0:9b334a45a8ff 1044 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 1045 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 1046
bogdanm 0:9b334a45a8ff 1047 return HAL_OK;
bogdanm 0:9b334a45a8ff 1048 }
bogdanm 0:9b334a45a8ff 1049
bogdanm 0:9b334a45a8ff 1050 /**
bogdanm 0:9b334a45a8ff 1051 * @brief Disables dynamically NAND ECC feature.
bogdanm 0:9b334a45a8ff 1052 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1053 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 1054 * @param ECCval: pointer to ECC value
bogdanm 0:9b334a45a8ff 1055 * @param Timeout: maximum timeout to wait
bogdanm 0:9b334a45a8ff 1056 * @retval HAL status
bogdanm 0:9b334a45a8ff 1057 */
bogdanm 0:9b334a45a8ff 1058 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 1059 {
bogdanm 0:9b334a45a8ff 1060 HAL_StatusTypeDef status = HAL_OK;
bogdanm 0:9b334a45a8ff 1061
bogdanm 0:9b334a45a8ff 1062 /* Check the NAND controller state */
bogdanm 0:9b334a45a8ff 1063 if(hnand->State == HAL_NAND_STATE_BUSY)
bogdanm 0:9b334a45a8ff 1064 {
bogdanm 0:9b334a45a8ff 1065 return HAL_BUSY;
bogdanm 0:9b334a45a8ff 1066 }
bogdanm 0:9b334a45a8ff 1067
bogdanm 0:9b334a45a8ff 1068 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 1069 hnand->State = HAL_NAND_STATE_BUSY;
bogdanm 0:9b334a45a8ff 1070
bogdanm 0:9b334a45a8ff 1071 /* Get NAND ECC value */
bogdanm 0:9b334a45a8ff 1072 status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
bogdanm 0:9b334a45a8ff 1073
bogdanm 0:9b334a45a8ff 1074 /* Update the NAND state */
bogdanm 0:9b334a45a8ff 1075 hnand->State = HAL_NAND_STATE_READY;
bogdanm 0:9b334a45a8ff 1076
bogdanm 0:9b334a45a8ff 1077 return status;
bogdanm 0:9b334a45a8ff 1078 }
bogdanm 0:9b334a45a8ff 1079
bogdanm 0:9b334a45a8ff 1080 /**
bogdanm 0:9b334a45a8ff 1081 * @}
bogdanm 0:9b334a45a8ff 1082 */
bogdanm 0:9b334a45a8ff 1083
bogdanm 0:9b334a45a8ff 1084
bogdanm 0:9b334a45a8ff 1085 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
bogdanm 0:9b334a45a8ff 1086 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 1087 *
bogdanm 0:9b334a45a8ff 1088 @verbatim
bogdanm 0:9b334a45a8ff 1089 ==============================================================================
bogdanm 0:9b334a45a8ff 1090 ##### NAND State functions #####
bogdanm 0:9b334a45a8ff 1091 ==============================================================================
bogdanm 0:9b334a45a8ff 1092 [..]
bogdanm 0:9b334a45a8ff 1093 This subsection permits to get in run-time the status of the NAND controller
bogdanm 0:9b334a45a8ff 1094 and the data flow.
bogdanm 0:9b334a45a8ff 1095
bogdanm 0:9b334a45a8ff 1096 @endverbatim
bogdanm 0:9b334a45a8ff 1097 * @{
bogdanm 0:9b334a45a8ff 1098 */
bogdanm 0:9b334a45a8ff 1099
bogdanm 0:9b334a45a8ff 1100 /**
bogdanm 0:9b334a45a8ff 1101 * @brief return the NAND state
bogdanm 0:9b334a45a8ff 1102 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1103 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 1104 * @retval HAL state
bogdanm 0:9b334a45a8ff 1105 */
bogdanm 0:9b334a45a8ff 1106 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
bogdanm 0:9b334a45a8ff 1107 {
bogdanm 0:9b334a45a8ff 1108 return hnand->State;
bogdanm 0:9b334a45a8ff 1109 }
bogdanm 0:9b334a45a8ff 1110
bogdanm 0:9b334a45a8ff 1111 /**
bogdanm 0:9b334a45a8ff 1112 * @}
bogdanm 0:9b334a45a8ff 1113 */
bogdanm 0:9b334a45a8ff 1114
bogdanm 0:9b334a45a8ff 1115 /**
bogdanm 0:9b334a45a8ff 1116 * @}
bogdanm 0:9b334a45a8ff 1117 */
bogdanm 0:9b334a45a8ff 1118
bogdanm 0:9b334a45a8ff 1119 /** @addtogroup NAND_Private_Functions
bogdanm 0:9b334a45a8ff 1120 * @{
bogdanm 0:9b334a45a8ff 1121 */
bogdanm 0:9b334a45a8ff 1122
bogdanm 0:9b334a45a8ff 1123 /**
bogdanm 0:9b334a45a8ff 1124 * @brief Increment the NAND memory address.
bogdanm 0:9b334a45a8ff 1125 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
bogdanm 0:9b334a45a8ff 1126 * the configuration information for NAND module.
bogdanm 0:9b334a45a8ff 1127 * @param Address: address to be incremented.
bogdanm 0:9b334a45a8ff 1128 * @retval The new status of the increment address operation. It can be:
bogdanm 0:9b334a45a8ff 1129 * - NAND_VALID_ADDRESS: When the new address is valid address
bogdanm 0:9b334a45a8ff 1130 * - NAND_INVALID_ADDRESS: When the new address is invalid address
bogdanm 0:9b334a45a8ff 1131 */
bogdanm 0:9b334a45a8ff 1132 static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address)
bogdanm 0:9b334a45a8ff 1133 {
bogdanm 0:9b334a45a8ff 1134 uint32_t status = NAND_VALID_ADDRESS;
bogdanm 0:9b334a45a8ff 1135
bogdanm 0:9b334a45a8ff 1136 Address->Page++;
bogdanm 0:9b334a45a8ff 1137
bogdanm 0:9b334a45a8ff 1138 if(Address->Page == hnand->Info.BlockSize)
bogdanm 0:9b334a45a8ff 1139 {
bogdanm 0:9b334a45a8ff 1140 Address->Page = 0;
bogdanm 0:9b334a45a8ff 1141 Address->Block++;
bogdanm 0:9b334a45a8ff 1142
bogdanm 0:9b334a45a8ff 1143 if(Address->Block == hnand->Info.ZoneSize)
bogdanm 0:9b334a45a8ff 1144 {
bogdanm 0:9b334a45a8ff 1145 Address->Block = 0;
bogdanm 0:9b334a45a8ff 1146 Address->Zone++;
bogdanm 0:9b334a45a8ff 1147
bogdanm 0:9b334a45a8ff 1148 if(Address->Zone == hnand->Info.BlockNbr)
bogdanm 0:9b334a45a8ff 1149 {
bogdanm 0:9b334a45a8ff 1150 status = NAND_INVALID_ADDRESS;
bogdanm 0:9b334a45a8ff 1151 }
bogdanm 0:9b334a45a8ff 1152 }
bogdanm 0:9b334a45a8ff 1153 }
bogdanm 0:9b334a45a8ff 1154
bogdanm 0:9b334a45a8ff 1155 return (status);
bogdanm 0:9b334a45a8ff 1156 }
bogdanm 0:9b334a45a8ff 1157
bogdanm 0:9b334a45a8ff 1158 /**
bogdanm 0:9b334a45a8ff 1159 * @}
bogdanm 0:9b334a45a8ff 1160 */
bogdanm 0:9b334a45a8ff 1161
bogdanm 0:9b334a45a8ff 1162 /**
bogdanm 0:9b334a45a8ff 1163 * @}
bogdanm 0:9b334a45a8ff 1164 */
bogdanm 0:9b334a45a8ff 1165
bogdanm 0:9b334a45a8ff 1166 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
bogdanm 0:9b334a45a8ff 1167 #endif /* HAL_NAND_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1168
bogdanm 0:9b334a45a8ff 1169 /**
bogdanm 0:9b334a45a8ff 1170 * @}
bogdanm 0:9b334a45a8ff 1171 */
bogdanm 0:9b334a45a8ff 1172
bogdanm 0:9b334a45a8ff 1173 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/