Frank Vannieuwkerke
/
SPI_TFT_ILI9320
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Dependents: KL25Z_ILI9320_Demo Mini-DK
Revision 4:2519f2e680af, committed 2014-05-30
- Comitter:
- frankvnk
- Date:
- Fri May 30 13:35:24 2014 +0000
- Parent:
- 3:a016fe71ed72
- Commit message:
- Added ILI9325 and ILI9328 initialization
Changed in this revision
| SPI_TFT_ILI9320.cpp | Show annotated file Show diff for this revision Revisions of this file |
--- a/SPI_TFT_ILI9320.cpp Tue Mar 18 18:59:54 2014 +0000
+++ b/SPI_TFT_ILI9320.cpp Fri May 30 13:35:24 2014 +0000
@@ -148,60 +148,143 @@
void SPI_TFT::tft_reset()
{
+ uint16_t DeviceID;
_spi.format(8,3); // 8 bit spi mode 3
+ DeviceID = Read_ID();
_spi.frequency(SPI_F_HI); // 48 Mhz SPI clock
+ if(DeviceID == 0x9320 || DeviceID == 0x9300)
+ {
+ wr_reg(0x00,0x0000);
+ wr_reg(0x01,0x0100); // Driver Output Control
+ wr_reg(0x02,0x0700); // LCD Driver Waveform Control
+ wr_reg(0x03,0x1030); // Set the scan mode
+ wr_reg(0x04,0x0000); // Scaling Control
+ wr_reg(0x08,0x0202); // Display Control 2
+ wr_reg(0x09,0x0000); // Display Control 3
+ wr_reg(0x0a,0x0000); // Frame Cycle Contal
+ wr_reg(0x0c,(1<<0)); // Extern Display Interface Control 1
+ wr_reg(0x0d,0x0000); // Frame Maker Position
+ wr_reg(0x0f,0x0000); // Extern Display Interface Control 2
+
+ wait_ms(50);
+
+ wr_reg(0x07,0x0101); // Display Control
+
+ wait_ms(50);
- wr_reg(0x00,0x0000);
- wr_reg(0x01,0x0100); // Driver Output Control
- wr_reg(0x02,0x0700); // LCD Driver Waveform Control
- wr_reg(0x03,0x1030); // Set the scan mode
- wr_reg(0x04,0x0000); // Scaling Control
- wr_reg(0x08,0x0202); // Display Control 2
- wr_reg(0x09,0x0000); // Display Control 3
- wr_reg(0x0a,0x0000); // Frame Cycle Contal
- wr_reg(0x0c,(1<<0)); // Extern Display Interface Control 1
- wr_reg(0x0d,0x0000); // Frame Maker Position
- wr_reg(0x0f,0x0000); // Extern Display Interface Control 2
+ wr_reg(0x10,(1<<12)|(0<<8)|(1<<7)|(1<<6)|(0<<4)); // Power Control 1
+ wr_reg(0x11,0x0007); // Power Control 2
+ wr_reg(0x12,(1<<8)|(1<<4)|(0<<0)); // Power Control 3
+ wr_reg(0x13,0x0b00); // Power Control 4
+ wr_reg(0x29,0x0000); // Power Control 7
+ wr_reg(0x2b,(1<<14)|(1<<4));
+
+ wr_reg(0x50,0); // Set X Start
+ wr_reg(0x51,239); // Set X End
+ wr_reg(0x52,0); // Set Y Start
+ wr_reg(0x53,319); // Set Y End
- wait_ms(50);
+ wait_ms(50);
+
+ wr_reg(0x60,0x2700); // Driver Output Control
+ wr_reg(0x61,0x0001); // Driver Output Control
+ wr_reg(0x6a,0x0000); // Vertical Srcoll Control
- wr_reg(0x07,0x0101); // Display Control
-
- wait_ms(50);
+ wr_reg(0x80,0x0000); // Display Position Partial Display 1
+ wr_reg(0x81,0x0000); // RAM Address Start Partial Display 1
+ wr_reg(0x82,0x0000); // RAM Address End-Partial Display 1
+ wr_reg(0x83,0x0000); // Displsy Position Partial Display 2
+ wr_reg(0x84,0x0000); // RAM Address Start Partial Display 2
+ wr_reg(0x85,0x0000); // RAM Address End Partial Display 2
- wr_reg(0x10,(1<<12)|(0<<8)|(1<<7)|(1<<6)|(0<<4)); // Power Control 1
- wr_reg(0x11,0x0007); // Power Control 2
- wr_reg(0x12,(1<<8)|(1<<4)|(0<<0)); // Power Control 3
- wr_reg(0x13,0x0b00); // Power Control 4
- wr_reg(0x29,0x0000); // Power Control 7
- wr_reg(0x2b,(1<<14)|(1<<4));
+ wr_reg(0x90,(0<<7)|(16<<0)); // Frame Cycle Control
+ wr_reg(0x92,0x0000); // Panel Interface Control 2
+ wr_reg(0x93,0x0001); // Panel Interface Control 3
+ wr_reg(0x95,0x0110); // Frame Cycle Control
+ wr_reg(0x97,(0<<8));
+ wr_reg(0x98,0x0000); // Frame Cycle Control
+ wr_reg(0x07,0x0133);
+ }
+ if(DeviceID == 0x9325 || DeviceID == 0x9328)
+ {
+ wr_reg(0xe7,0x0010);
+ wr_reg(0x00,0x0001); // start internal osc
+ wr_reg(0x01,0x0100);
+ wr_reg(0x02,0x0700); // power on sequence
+ wr_reg(0x03,(1<<12)|(1<<5)|(1<<4)|(0<<3) ); // importance
+ wr_reg(0x04,0x0000);
+ wr_reg(0x08,0x0207);
+ wr_reg(0x09,0x0000);
+ wr_reg(0x0a,0x0000); // display setting
+ wr_reg(0x0c,0x0001); // display setting
+ wr_reg(0x0d,0x0000);
+ wr_reg(0x0f,0x0000);
+ wr_reg(0x10,0x0000); // Power On sequence
+ wr_reg(0x11,0x0007);
+ wr_reg(0x12,0x0000);
+ wr_reg(0x13,0x0000);
- wr_reg(0x50,0); // Set X Start
- wr_reg(0x51,239); // Set X End
- wr_reg(0x52,0); // Set Y Start
- wr_reg(0x53,319); // Set Y End
+ wait_ms(50);
+
+ wr_reg(0x10,0x1590);
+ wr_reg(0x11,0x0227);
+
+ wait_ms(50);
- wait_ms(50);
+ wr_reg(0x12,0x009c);
+
+ wait_ms(50);
+
+ wr_reg(0x13,0x1900);
+ wr_reg(0x29,0x0023);
+ wr_reg(0x2b,0x000e);
+
+ wait_ms(50);
- wr_reg(0x60,0x2700); // Driver Output Control
- wr_reg(0x61,0x0001); // Driver Output Control
- wr_reg(0x6a,0x0000); // Vertical Srcoll Control
+ wr_reg(0x20,0x0000);
+ wr_reg(0x21,0x0000);
+
+ wait_ms(50);
+
+ wr_reg(0x30,0x0007);
+ wr_reg(0x31,0x0707);
+ wr_reg(0x32,0x0006);
+ wr_reg(0x35,0x0704);
+ wr_reg(0x36,0x1f04);
+ wr_reg(0x37,0x0004);
+ wr_reg(0x38,0x0000);
+ wr_reg(0x39,0x0706);
+ wr_reg(0x3c,0x0701);
+ wr_reg(0x3d,0x000f);
+
+ wait_ms(50);
- wr_reg(0x80,0x0000); // Display Position Partial Display 1
- wr_reg(0x81,0x0000); // RAM Address Start Partial Display 1
- wr_reg(0x82,0x0000); // RAM Address End-Partial Display 1
- wr_reg(0x83,0x0000); // Displsy Position Partial Display 2
- wr_reg(0x84,0x0000); // RAM Address Start Partial Display 2
- wr_reg(0x85,0x0000); // RAM Address End Partial Display 2
-
- wr_reg(0x90,(0<<7)|(16<<0)); // Frame Cycle Control
- wr_reg(0x92,0x0000); // Panel Interface Control 2
- wr_reg(0x93,0x0001); // Panel Interface Control 3
- wr_reg(0x95,0x0110); // Frame Cycle Control
- wr_reg(0x97,(0<<8));
- wr_reg(0x98,0x0000); // Frame Cycle Control
- wr_reg(0x07,0x0133);
-
+ wr_reg(0x50,0x0000);
+ wr_reg(0x51,0x00ef);
+ wr_reg(0x52,0x0000);
+ wr_reg(0x53,0x013f);
+ wr_reg(0x60,0xa700);
+ wr_reg(0x61,0x0001);
+ wr_reg(0x6a,0x0000);
+ wr_reg(0x80,0x0000);
+ wr_reg(0x81,0x0000);
+ wr_reg(0x82,0x0000);
+ wr_reg(0x83,0x0000);
+ wr_reg(0x84,0x0000);
+ wr_reg(0x85,0x0000);
+
+ wr_reg(0x90,0x0010);
+ wr_reg(0x92,0x0000);
+ wr_reg(0x93,0x0003);
+ wr_reg(0x95,0x0110);
+ wr_reg(0x97,0x0000);
+ wr_reg(0x98,0x0000);
+
+ wr_reg(0x07,0x0133); // display on sequence
+
+ wr_reg(0x20,0x0000);
+ wr_reg(0x21,0x0000);
+ }
wait_ms(100);
WindowMax();
}
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